CSSE 332 Operating Systems: Virtual Memory Exercise

Name:_______________________________________ Grade:________________ How to convert a logical address to a physical address in a paging system In a paging system, the process space is divided into consecutive pages of fixed length: Page 0, Page 1, Page 2, etc. As such, a logical address (also called a virtual address) consists of: Virtual address A page number An offset within that page Page # Offset In a paging system, main memory is divided into consecutive frames of fixed length (same length as the pages): Frame 0, Frame 1, Frame 2, etc. Some of the logical pages are placed in the physical frames. For example, pages 3, 8 and 10 might be placed in frames 104, 87 and 378, respectively, with the other pages of the process in virtual memory, i.e., on disk (or other form of secondary memory). The goal of this exercise is to help you understand 4 approaches to converting a logical address (page number + offset) to a physical address (frame number + offset, or a page fault if the page is not in main memory): Simple indexing Multi-level indexing Hashing into an inverted page table Associative lookup in a cache called the translation lookaside buffer (TLB) Real operating systems will often use a combination of these 4 approaches. In addition, there is an interaction with the main memory cache (see Figure 8.10 in your text). Throughout this exercise, logical addresses and physical addresses are written as pairs of numbers (page number offset for logical addresses, frame number/offset for physical addresses). These are physically manifested as the high and low bits of a binary number.

1. (7 points) Paging with simple indexing: Connect the pieces of hardware below to show how each logical address is translated to a physical address or a page fault is detected.
Main memory

Virtual address Page # Offset

Address 0 1 2 3 4 256

Present bit

Frame number 104 334 45 891 115

0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 1

333 228 610 200 324 900 1005 820 20 5 1005 220 4 303 689 446 848 666 111 229

257 258 259 260 261 262 263

Physical address Frame # Offset

Register Page table pointer

264 265 266 267 268 269 270 271 272 273 274 275

Register Interrupt indicator

Assumptions: Assume the value in the register for the page table pointer is 256. Answer the following questions based on the above (completed) diagram.
Logical 2 105 causes a page fault? Yes or No (circle one). If no, converts to physical: ________ Logical 5 640 causes a page fault? Yes or No (circle one). If no, converts to physical: ________ Logical 12 320 causes a page fault? Yes or No (circle one). If no, converts to physical: ________ Consider a 32-bit addressing scheme with 18 bits for the page number and 14 for the offset. How many entries in the page table? ___________ What is the size of each page? _________

2. (7 points) Multi-level indexing: Connect the pieces of hardware below to show how each

logical address is translated to a physical address or a page fault is detected.

Virtual address Page # Offset

Address 0 1 2 3 4 5 6

Present bit 1 1 0 1 1 1 1 0 . Present bit

Pointer to page table block 104 334 45 1 115 713 2 228 . Frame # 900 1005 820 20 5 1005 220 . 303 689 446 848 666 111 229

256 257 258

1 1 0 1 0 0 0 1 1 0 1 0 1 1

Physical address Frame # Offset

Register Root page table ptr

259 260 261 262 512 513

Assumptions: Assume the value in the register for the root page table pointer is 0. Suppose that the page # is divided into 4 bits + 8 bits for a two-level page table. The page number for this exercise is written in binary. Also, assume that each page (or page table block) has 256 bytes.

Register Interrupt indicator

514 515 516 517 518

Answer the following questions based on the above (completed) diagram.

Consider a 32-bit addressing scheme with 6 + 12 bits for the page number and 14 for the offset. Assume a page table entry is 4 bytes. Assume byte-addressing : # of entries in the root page table? ____Total entries in the page table? ________ Page size in bytes? ______ What is the primary advantage of using layers in an indexing scheme? Primary disadvantage?

3. (7 points) Hashing into an inverted page table: Connect the pieces of hardware below to show

how each logical address is translated to a physical address or a page fault is detected. In this example, the hash function generates the index to the frame table i.e. the frame number.
Address Main memory Page #/Frame # Present bit 0 256 257 33 / 0 81 / 1 807 / 2 19 / 3 41 / 4 26 / 5 803 / 6 404 / 7 0 1 1 1 1 0 1 0 0 0 0 0 -3 0 -3 0 Relative Pointer

Virtual address Page # Offset

Physical address Frame # Register

258 259 260 261 262 263 264

Offset

Register Interrupt indicator

Hash table entry

Hash function Assumptions: Assume the hashing function is h(x) = 3 + (x % 8) and the inverted page table pointer value is 256. Answer the following questions based on the above (completed) diagram. Logical 81 105 causes a page fault? Yes or No (circle one). If no, converts to physical: __1, 105_ Logical 41 640 causes a page fault? Yes or No (circle one). If no, converts to physical: ________ Logical 25 320 causes a page fault? Yes or No (circle one). If no, converts to physical: ________ Logical 28 204 causes a page fault? Yes or No (circle one). If no, converts to physical: ________ Logical 19 880 causes a page fault? Yes or No (circle one). If no, converts to physical: ________ In the above table, what is the longest chain? ____ Shortest chain? ______

4. (7 points) Associative lookup in a cache called the translation lookaside buffer(TLB): Connect the pieces of hardware below to show how each logical address is translated to a physical address or a page fault is detected.
Address Main memory Present bit 0 1 2 3 4 256 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 1 Frame # 104 334 45 891 115 333 228 610 200 324 900 1005 820 20 5 1005 220 4 303 689 446 848 666 111 229 Translation lookaside buffer (TLB) 16 53 4 80 5 848 100 324 226 900

Virtual address Page # Offset

257 258 259 260 261 262

Physical address Frame # Offset

Register Page table pointer

263 264 265 266 267 268 269

Register Interrupt indicator

Assumptions: Assume the value in the register for the page table pointer is 256. Answer the following questions based on the above (completed) diagram.

270 271 272 273 274 275

Logical 4 105 is in TLB? Yes or No? Causes a page fault? Yes or No (circle one). If no, converts to physical: ______________ Logical 18 640 is in TLB? Yes or No? Causes a page fault? Yes or No (circle one). If no, converts to physical: ______________ Logical 16 105 is in TLB? Yes or No? Causes a page fault? Yes or No (circle one). If no, converts to physical: ______________ If there are n items in the TLB, is the TLB lookup time O(n) or O(1)? How much silicon is needed? What is the primary advantage of this scheme?

5. (8 points) Summary (after doing the exercises on the following pages):

Advantages Indexing Indexing with layers Hashing into an inverted page table Associative lookup in a cache called the translation lookaside buffer (TLB)

Disadvantages