Scribd
Upload
366 views

Addition and Subtraction With Signed 2s Complement

Addition and subtraction of signed 2's complement numbers can be performed using the same hardware and process as unsigned binary numbers. For addition, the numbers are added together including their sign bits and overflow is detected from the carry out of the sign bit position. For subtraction, the number to be subtracted has its 2's complement taken first before addition. This allows subtraction to be performed using the same addition process. Overflow can occur for both addition and subtraction of signed numbers.

Uploaded by

Moses Dian
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
366 views

Addition and Subtraction With Signed 2s Complement

Addition and subtraction of signed 2's complement numbers can be performed using the same hardware and process as unsigned binary numbers. For addition, the numbers are added together including their sign bits and overflow is detected from the carry out of the sign bit position. For subtraction, the number to be subtracted has its 2's complement taken first before addition. This allows subtraction to be performed using the same addition process. Overflow can occur for both addition and subtraction of signed numbers.

Uploaded by

Moses Dian
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Addition and Subtraction with Signed-2's Complement Data

Addition with Signed-2's Complement Data:


• Addition rule can be stated as follows: Add the two numbers, including their sign
bits, and discard any carry out of the sign (leftmost) bit position.
• Adding numbers in the signed-2's complement system require only addition and
complementation.
• Numerical examples for addition are shown below:

• Note that negative numbers must initially be in 2' s complement.


• If the sum obtained after the addition is negative, it is in 2's complement form.
• For example, the signed binary number 1111 1001 is negative because the leftmost
bit is 1.
• Its 2' s complement is 00000111, which is the binary equivalent of +7.
• We therefore recognize the original negative number to be equal to - 7.

Subtraction with Signed-2's Complement Data:


• Subtraction rule can be stated as follows: Take the 2's complement of the
subtrahend (including the sign bit) and add it to the minuend (including the sign bit).
A carry out of the sign bit position is discarded.
• Subtraction operation can be changed to an addition operation if the sign of the
subtrahend is changed. This
is demonstrated by the following relationship:

(±A) - (+B) = (±A) + (- B)


(±A) - (- B) = (±A) + (+B)
• Example: Consider the subtraction of (-6) - (- 13) = +7.
• In binary with eight bits, this is written as
11111010 - 11110011
• The subtraction is changed to addition by taking the 2's complement of the
subtrahend (- 13) to give (+ 13).
• In binary this is 11111010 + 00001101 = 100000111
• Removing the end carry, we obtain the correct answer 00000111 (+ 7).
• Note: Therefore, computers need only one common hardware circuit to handle both
types of arithmetic because binary numbers in the signed-2's complement system
are added and subtracted by the same basic addition and subtraction rules as
unsigned numbers.

Overflow
• When two numbers of n digits each are added and the sum occupies n + 1 digits, we say
that an overflow occurred.
• An overflow is a problem in digital computers because the width of registers is finite.
• A result that contains n + 1 bits cannot be accommodated in a register with a standard
length of n bits.
• For this reason, many computers detect the occurrence of an overflow, by setting a flip-
flop which can then be checked by the user.
• When two unsigned numbers are added, an overflow is detected from the end carry out
of the most significant position.
• In the case of signed numbers, the leftmost bit always represents the sign.
• When two signed numbers are added, the sign bit is treated as part of the number and
the end carry does not indicate an overflow.
• An overflow may occur only if the two numbers added are both positive or both
negative.
• Example: Two signed binary numbers, + 70 and + 80, are stored in two 8-bit registers

• Each register can accommodate values from binary + 127 to binary - I28.
• Since the sum of the two numbers is + I50, it exceeds the capacity of the 8-bit register.
• 8-bit result that should have been positive has a negative sign bit and the 8-bit result
that should have been negative has a positive sign bit.
• If, however, the carry out of the sign bit position is taken as the sign bit of the result, the
9-bit answer so obtained will be correct.
• Since the answer cannot be accommodated within 8 bits, we say that an overflow
occurred.
• An overflow can be detected by applying the last two carries out of the addition in the
above example to an exclusive-OR gate.
• The overflow is detected when the output of the gate is equal to 1.
Hardware Implementation:
• The hardware implementation for signed 2's complement addition and subtraction is
shown in the below figure.
• Let AC(accumulator) and BR be two registers that hold the two numbers for addition
or subtraction.
• The leftmost bit in AC and BR represent the sign bits of the numbers.
• The two sign bits are added or subtracted together with the other bits in the
complementer and parallel adder.
• The sum is obtained by adding the contents of AC and BR (including their sign bits).
• The overflow bit V is set to 1 if the exclusive-OR of the last two carries is 1, and it
is cleared to 0 otherwise.
• If an overflow occurs, there will be an erroneous result in the AC register
• The subtraction operation is accomplished by adding the content of AC to the 2's
complement of BR.
• The algorithm for adding and subtracting two binary numbers in signed-2' s
complement representation is shown in the following flowchart.

You might also like