5 4 3 2 1

01
ZAJ/Z8P/Z8PA SYSTEM BLOCK DIAGRAM
BOM
D TPM@ : TPM D

Dual Channel DDR3L GS@ : G-SENSOR

DDR3L-2GB CB@ : Cloud book SKU
1867 MHz MAX Apollo Lake - 6W
Memory down CHA
P10 (BROXTON-P) eDP
EDP EJ@ : EJ sereies SKU
eDP Conn. P12 KBL@ : keyboard backlight
MCP 1296 pins NVL@ : none LED panel boost
DDR3L-2GB
Memory down CHB VL@ : LED panel boost
P11 EC@ : EMMC
DDI0
SATA0 DP HDMI Conn. TPC@ : Type C function
P13
SATA - HDD w/o GS@: stuff with none GS sku
P16 SATA SSD@ : SATA interface SSD
SATA1
PSD@ : PCIE interfance SSD
SATA SSD M.2 P16 SMB
G-sensor P28 ODD@ : ODD function

USB3-0 + USB2-0
USB3.0 Port P19
C EMMC EMMC5.0
C
32GB/64GB P12

USB2-2 USB3.0/2.0 USB3-1 + USB3-2

USB2.0 Port 1 P19 USB2.0
USB2-1
Type C port
USB2-3 P20
USB2.0 Port 2 P19

USB2-4 PCIE-3
Blue Tooth PCIE-0/1
PCI-E M.2 NGFF
P17
WLAN+BT
P17
USB2-5
Touch Screen
P12 RTL8411B-CG
X'TAL PCIE-2
USB2-6
32.768KHz 10/100/1G RJ45
CCD(Camera) P15 P15
P12 Integrated PCH
X'TAL 19.2MHz
B USB2-7 B

ODD bridge X'TAL 25MHz

Cardreader
ASM1153 P16 P15
P6 BATTERY RTC
Azalia P2~P8 I2C_0
IHDA
SPI
LPC
SPI ROM 8M
P3
BQ24737RGRR RT8231BGQW
Batery Charger P22 +1.35VSUS P25

EC SY8286 & SY8288 G5719CTB1U

D-MIC AUDIO CODEC TPM(NPCT650) +3VPCU/+5VPCU P23 G5719CTB1U
P14 IT8987 G9661MF11U
ALC255 P16
P14 P20
M5671RE1U +1.8V_S5 / +1.24VSUS/+1.5V
+1.05V P24 P28

ISL95859HRTZ-T Thermal Protection

A A
+VCCGI / +VNN P26~27 Discharger P29

HP JACK Speaker K/B Con. SPI ROM 1M Touch PAD Fan module
(PWM signal)
P14 P14 P18 P20 P18 P18 Quanta Computer Inc.
PROJECT : ZAJ
Size Document Number Rev
3A
Block Diagram
Date: Tuesday, March 21, 2017 Sheet 1 of 34
5 4 3 2 1
 5 4 3 2 1

APL ULT (DDR3L) 02

U21A APL_BGA_1296P
M_A_A0 BG50 AY62 M_A_DQ0 U21B APL_BGA_1296P
[10] M_A_A0 DDR3L_CH0_MA0_LPDDR3_CH0_CAB7 DDR3L_CH0_DQ0_LPDDR3_CH0_DQA0 M_A_DQ0 [10]
D M_A_A1 BG51 AY61 M_A_DQ1 M_B_A0 BG9 BJ26 M_B_DQ0 D
[10] M_A_A1 M_A_A2 BH51 DDR3L_CH0_MA1_LPDDR3_CH0_CAB9 DDR3L_CH0_DQ1_LPDDR3_CH0_DQA1 M_A_DQ1 [10] [11] M_B_A0 DDR3L_CH1_MA0_LPDDR3_CH1_CAB7 DDR3L_CH1_DQ0_LPDDR3_CH1_DQA0 M_B_DQ0 [11]
[10] M_A_A2 BE62 M_A_DQ2 M_A_DQ2 [10] [11] M_B_A1
M_B_A1 BG10 BG30 M_B_DQ1 M_B_DQ1 [11]
M_A_A3 BD41 DDR3L_CH0_MA2_LPDDR3_CH0_CAB5 DDR3L_CH0_DQ2_LPDDR3_CH0_DQA2 BG62 M_A_DQ3 M_B_A2 BH9 DDR3L_CH1_MA1_LPDDR3_CH1_CAB9 DDR3L_CH1_DQ1_LPDDR3_CH1_DQA1 BH31 M_B_DQ2
[10] M_A_A3 DDR3L_CH0_MA3_LPDDR3_NC DDR3L_CH0_DQ3_LPDDR3_CH0_DQA3 M_A_DQ3 [10] [11] M_B_A2 DDR3L_CH1_MA2_LPDDR3_CH1_CAB5 DDR3L_CH1_DQ2_LPDDR3_CH1_DQA2 M_B_DQ2 [11]
M_A_A4 BE41 BD63 M_A_DQ4 M_B_A3 BD16 BG31 M_B_DQ3
[10] M_A_A4 M_A_A5 BJ52 DDR3L_CH0_MA4_LPDDR3_NC DDR3L_CH0_DQ4_LPDDR3_CH0_DQA4 M_A_DQ4 [10] [11] M_B_A3 DDR3L_CH1_MA3_LPDDR3_NC DDR3L_CH1_DQ3_LPDDR3_CH1_DQA3 M_B_DQ3 [11]
[10] M_A_A5
AW62M_A_DQ5 M_A_DQ5 [10] [11] M_B_A4
M_B_A4 BB16 BH27 M_B_DQ4 M_B_DQ4 [11]
M_A_A6 BG53 DDR3L_CH0_MA5_LPDDR3_CH0_CAA2 DDR3L_CH0_DQ5_LPDDR3_CH0_DQA5 AW63M_A_DQ6 M_B_A5 BG11 DDR3L_CH1_MA4_LPDDR3_NC DDR3L_CH1_DQ4_LPDDR3_CH1_DQA4 BG27 M_B_DQ5
[10] M_A_A6 M_A_A7 BG55 DDR3L_CH0_MA6_LPDDR3_CH0_CAA0 DDR3L_CH0_DQ6_LPDDR3_CH0_DQA6 M_A_DQ6 [10] [11] M_B_A5 DDR3L_CH1_MA5_LPDDR3_CH1_CAA2 DDR3L_CH1_DQ5_LPDDR3_CH1_DQA5 M_B_DQ5 [11]
[10] M_A_A7
BD62 M_A_DQ7 M_A_DQ7 [10] [11] M_B_A6
M_B_A6 BJ12 BG26 M_B_DQ6 M_B_DQ6 [11]
M_A_A8 BH53 DDR3L_CH0_MA7_LPDDR3_CH0_CAA3 DDR3L_CH0_DQ7_LPDDR3_CH0_DQA7 AV59 M_A_DQ8 M_B_A7 BG14 DDR3L_CH1_MA6_LPDDR3_CH1_CAA0 DDR3L_CH1_DQ6_LPDDR3_CH1_DQA6 BJ30 M_B_DQ7
[10] M_A_A8 M_A_A9 BG52 DDR3L_CH0_MA8_LPDDR3_CH0_CAA1 DDR3L_CH0_DQ8_LPDDR3_CH0_DQA8 M_A_DQ8 [10] [11] M_B_A7 DDR3L_CH1_MA7_LPDDR3_CH1_CAA3 DDR3L_CH1_DQ7_LPDDR3_CH1_DQA7 M_B_DQ7 [11]
[10] M_A_A9 AU63 M_A_DQ9 M_A_DQ9 [10] [11] M_B_A8
M_B_A8 BG12 BA30 M_B_DQ8 M_B_DQ8 [11]
M_A_A10 BH49 DDR3L_CH0_MA9_LPDDR3_CH0_CAA4 DDR3L_CH0_DQ9_LPDDR3_CH0_DQA9 AU62 M_A_DQ10 M_B_A9 BH11 DDR3L_CH1_MA8_LPDDR3_CH1_CAA1 DDR3L_CH1_DQ8_LPDDR3_CH1_DQA8 BB30 M_B_DQ9
[10] M_A_A10 M_A_A11 BH55 DDR3L_CH0_MA10_LPDDR3_CH0_CAB6 DDR3L_CH0_DQ10_LPDDR3_CH0_DQA10 M_A_DQ10 [10] [11] M_B_A9 DDR3L_CH1_MA9_LPDDR3_CH1_CAA4 DDR3L_CH1_DQ9_LPDDR3_CH1_DQA9 M_B_DQ9 [11]
[10] M_A_A11
AV58 M_A_DQ11 M_A_DQ11 [10] [11] M_B_A10
M_B_A10 BG7 BE30 M_B_DQ10 M_B_DQ10 [11]
M_A_A12 BG54 DDR3L_CH0_MA11_LPDDR3_CH0_CAA6 DDR3L_CH0_DQ11_LPDDR3_CH0_DQA11 AV57 M_A_DQ12 M_B_A11 BH13 DDR3L_CH1_MA10_LPDDR3_CH1_CAB6 DDR3L_CH1_DQ10_LPDDR3_CH1_DQA10 BD30 M_B_DQ11
[10] M_A_A12 M_A_A13 BG46 DDR3L_CH0_MA12_LPDDR3_CH0_CAA5 DDR3L_CH0_DQ12_LPDDR3_CH0_DQA12 M_A_DQ12 [10] [11] M_B_A11 DDR3L_CH1_MA11_LPDDR3_CH1_CAA6 DDR3L_CH1_DQ11_LPDDR3_CH1_DQA11 M_B_DQ11 [11]
[10] M_A_A13 AT55 M_A_DQ13 M_A_DQ13 [10] [11] M_B_A12
M_B_A12 BG13 BE25 M_B_DQ12 M_B_DQ12 [11]
M_A_A14 BG56 DDR3L_CH0_MA13_LPDDR3_CH0_CAB0 DDR3L_CH0_DQ13_LPDDR3_CH0_DQA13 AT54 M_A_DQ14 M_B_A13 BH3 DDR3L_CH1_MA12_LPDDR3_CH1_CAA5 DDR3L_CH1_DQ12_LPDDR3_CH1_DQA12 BB27 M_B_DQ13
[10] M_A_A14 DDR3L_CH0_MA14_LPDDR3_CH0_CAA8 DDR3L_CH0_DQ14_LPDDR3_CH0_DQA14 M_A_DQ14 [10] [11] M_B_A13 DDR3L_CH1_MA13_LPDDR3_CH1_CAB0 DDR3L_CH1_DQ13_LPDDR3_CH1_DQA13 M_B_DQ13 [11]
M_A_A15 BG57 AY59 M_A_DQ15 M_B_A14 BG15 BD25 M_B_DQ14
[10] M_A_A15 DDR3L_CH0_MA15_LPDDR3_CH0_CAA9 DDR3L_CH0_DQ15_LPDDR3_CH0_DQA15 M_A_DQ15 [10] [11] M_B_A14 DDR3L_CH1_MA14_LPDDR3_CH1_CAA8 DDR3L_CH1_DQ14_LPDDR3_CH1_DQA14 M_B_DQ14 [11]
AY57 M_A_DQ16 M_A_DQ16 [10] [11] M_B_A15
M_B_A15 BG16 BD27 M_B_DQ15 M_B_DQ15 [11]
BJ48 DDR3L_CH0_DQ16_LPDDR3_CH0_DQA16 BB57 M_A_DQ17 DDR3L_CH1_MA15_LPDDR3_CH1_CAA9 DDR3L_CH1_DQ15_LPDDR3_CH1_DQA15 BG24 M_B_DQ16
[10] M_A_BS#0 DDR3L_CH0_BA0_LPDDR3_CH0_CAB2 DDR3L_CH0_DQ17_LPDDR3_CH0_DQA17 M_A_DQ17 [10] DDR3L_CH1_DQ16_LPDDR3_CH1_DQA16 M_B_DQ16 [11]
[10] M_A_BS#1
BG49 BD59 M_A_DQ18 M_A_DQ18 [10] [11] M_B_BS#0
BH6 BJ20 M_B_DQ17 M_B_DQ17 [11]
BH57 DDR3L_CH0_BA1_LPDDR3_CH0_CAB8 DDR3L_CH0_DQ18_LPDDR3_CH0_DQA18 BF59 M_A_DQ19 BG8 DDR3L_CH1_BA0_LPDDR3_CH1_CAB2 DDR3L_CH1_DQ17_LPDDR3_CH1_DQA17 BH23 M_B_DQ18
[10] M_A_BS#2 DDR3L_CH0_BA2_LPDDR3_CH0_CAA7 DDR3L_CH0_DQ19_LPDDR3_CH0_DQA19 M_A_DQ19 [10] [11] M_B_BS#1 DDR3L_CH1_BA1_LPDDR3_CH1_CAB8 DDR3L_CH1_DQ18_LPDDR3_CH1_DQA18 M_B_DQ18 [11]
AV54 M_A_DQ20 M_A_DQ20 [10] [11] M_B_BS#2
BH15 BJ24 M_B_DQ19 M_B_DQ19 [11]
BH47 DDR3L_CH0_DQ20_LPDDR3_CH0_DQA20 AY55 M_A_DQ21 DDR3L_CH1_BA2_LPDDR3_CH1_CAA7 DDR3L_CH1_DQ19_LPDDR3_CH1_DQA19 BG20 M_B_DQ20
[10] M_A_CAS# DDR3L_CH0_CAS_N_LPDDR3_CH0_CAB1 DDR3L_CH0_DQ21_LPDDR3_CH0_DQA21 M_A_DQ21 [10] DDR3L_CH1_DQ20_LPDDR3_CH1_DQA20 M_B_DQ20 [11]
[10] M_A_RAS# BG47 AV52 M_A_DQ22 M_A_DQ22 [10] [11] M_B_CAS# BH4 BG21 M_B_DQ21 M_B_DQ21 [11]
BG48 DDR3L_CH0_RAS_N_LPDDR3_CH0_CAB3 DDR3L_CH0_DQ22_LPDDR3_CH0_DQA22 BD58 M_A_DQ23 BJ6 DDR3L_CH1_CAS_N_LPDDR3_CH1_CAB1 DDR3L_CH1_DQ21_LPDDR3_CH1_DQA21 BH19 M_B_DQ22
[10] M_A_WE# DDR3L_CH0_WE_N_LPDDR3_CH0_CAB4 DDR3L_CH0_DQ23_LPDDR3_CH0_DQA23 M_A_DQ23 [10] [11] M_B_RAS# DDR3L_CH1_RAS_N_LPDDR3_CH1_CAB3 DDR3L_CH1_DQ22_LPDDR3_CH1_DQA22 M_B_DQ22 [11]
BE56 M_A_DQ24 M_A_DQ24 [10] [11] M_B_WE#
BH7 BG25 M_B_DQ23 M_B_DQ23 [11]
AR43 DDR3L_CH0_DQ24_LPDDR3_CH0_DQA24 BD54 M_A_DQ25 DDR3L_CH1_WE_N_LPDDR3_CH1_CAB4 DDR3L_CH1_DQ23_LPDDR3_CH1_DQA23 AT27 M_B_DQ24
[10] M_A_CS#0 DDR3L_CH0_CS0_N_LPDDR3_CH0_CS0A_N DDR3L_CH0_DQ25_LPDDR3_CH0_DQA25 M_A_DQ25 [10] DDR3L_CH1_DQ24_LPDDR3_CH1_DQA24 M_B_DQ24 [11]
AT43 BF58 M_A_DQ26 M_A_DQ26 [10] [11] M_B_CS#0 BD17 AW29M_B_DQ25 M_B_DQ25 [11]
BB41 DDR3L_NC_LPDDR3_CH0_CS1A_N DDR3L_CH0_DQ26_LPDDR3_CH0_DQA26 BE50 M_A_DQ27 BB17 DDR3L_CH1_CS0_N_LPDDR3_CH1_CS0A_N DDR3L_CH1_DQ25_LPDDR3_CH1_DQA25 AR27 M_B_DQ26
DDR3L_NC_LPDDR3_CH0_CS0B_N DDR3L_CH0_DQ27_LPDDR3_CH0_DQA27 M_A_DQ27 [10] DDR3L_NC_LPDDR3_CH1_CS1A_N DDR3L_CH1_DQ26_LPDDR3_CH1_DQA26 M_B_DQ26 [11]
BA41 BD50 M_A_DQ28 M_A_DQ28 [10] AV17 AT23 M_B_DQ27 M_B_DQ27 [11]
DDR3L_CH0_CS1_N_LPDDR3_CH0_CS1B_N DDR3L_CH0_DQ28_LPDDR3_CH0_DQA28 BB50 M_A_DQ29 AW17 DDR3L_NC_LPDDR3_CH1_CS0B_N DDR3L_CH1_DQ27_LPDDR3_CH1_DQA27 AV27 M_B_DQ28
DDR3L_CH0_DQ29_LPDDR3_CH0_DQA29 M_A_DQ29 [10] DDR3L_CH1_CS1_N_LPDDR3_CH1_CS1B_N DDR3L_CH1_DQ28_LPDDR3_CH1_DQA28 M_B_DQ28 [11]
[10] M_A_CKE0 BH61 BA50 M_A_DQ30 M_A_DQ30 [10] AR25 M_B_DQ29 M_B_DQ29 [11]
BH60 DDR3L_CH0_CKE0_LPDDR3_CH0_CKE0A DDR3L_CH0_DQ30_LPDDR3_CH0_DQA30 BB54 M_A_DQ31 BG18 DDR3L_CH1_DQ29_LPDDR3_CH1_DQA29 AR23 M_B_DQ30
DDR3L_CH0_CKE1_LPDDR3_CH0_CKE1A DDR3L_CH0_DQ31_LPDDR3_CH0_DQA31 M_A_DQ31 [10] [11] M_B_CKE0 DDR3L_CH1_CKE0_LPDDR3_CH1_CKE0A DDR3L_CH1_DQ30_LPDDR3_CH1_DQA30 M_B_DQ30 [11]
BH58 AR39 M_A_DQ32 M_A_DQ32 [10]
BG17 AW27M_B_DQ31 M_B_DQ31 [11]
C BJ58 DDR3L_NC_LPDDR3_CH0_CKE0B DDR3L_CH0_DQ32_LPDDR3_CH0_DQB0 AV37 M_A_DQ33 BH17 DDR3L_CH1_CKE1_LPDDR3_CH1_CKE1A DDR3L_CH1_DQ31_LPDDR3_CH1_DQA31 BF6 M_B_DQ32 C
DDR3L_NC_LPDDR3_CH0_CKE1B DDR3L_CH0_DQ33_LPDDR3_CH0_DQB1 M_A_DQ33 [10] DDR3L_NC_LPDDR3_CH1_CKE0B DDR3L_CH1_DQ32_LPDDR3_CH1_DQB0 M_B_DQ32 [11]
AW37M_A_DQ34 M_A_DQ34 [10]
BJ16 BD10 M_B_DQ33 M_B_DQ33 [11]
AW43 DDR3L_CH0_DQ34_LPDDR3_CH0_DQB2 AR37 M_A_DQ35 DDR3L_NC_LPDDR3_CH1_CKE1B DDR3L_CH1_DQ33_LPDDR3_CH1_DQB1 BE14 M_B_DQ34
DDR3L_CH0_ODT0_LPDDR3_CH0_ODTA DDR3L_CH0_DQ35_LPDDR3_CH0_DQB3 M_A_DQ35 [10] DDR3L_CH1_DQ34_LPDDR3_CH1_DQB2 M_B_DQ34 [11]
AW41 AT37 M_A_DQ36 M_A_DQ36 [10] AW16 BB10 M_B_DQ35 M_B_DQ35 [11]
DDR3L_CH0_ODT1_LPDDR3_CH0_ODTB DDR3L_CH0_DQ36_LPDDR3_CH0_DQB4 AT41 M_A_DQ37 AV16 DDR3L_CH1_ODT0_LPDDR3_CH1_ODTA DDR3L_CH1_DQ35_LPDDR3_CH1_DQB3 BA14 M_B_DQ36
DDR3L_CH0_DQ37_LPDDR3_CH0_DQB5 M_A_DQ37 [10] DDR3L_CH1_ODT1_LPDDR3_CH1_ODTB DDR3L_CH1_DQ36_LPDDR3_CH1_DQB4 M_B_DQ36 [11]
AT34 AR41 M_A_DQ38 M_A_DQ38 [10]
BB14 M_B_DQ37 M_B_DQ37 [11]
AR35 MEM_CH0_VREFDQ DDR3L_CH0_DQ38_LPDDR3_CH0_DQB6 AW35M_A_DQ39 AT30 DDR3L_CH1_DQ37_LPDDR3_CH1_DQB5 BD14 M_B_DQ38
MEM_CH0_VREFCA DDR3L_CH0_DQ39_LPDDR3_CH0_DQB7 M_A_DQ39 [10] MEM_CH1_VREFDQ DDR3L_CH1_DQ38_LPDDR3_CH1_DQB6 M_B_DQ38 [11]
BJ44 M_A_DQ40 M_A_DQ40 [10]
AR29 BE8 M_B_DQ39 M_B_DQ39 [11]
DDR3L_CH0_DQ40_LPDDR3_CH0_DQB8 BG39 M_A_DQ41 MEM_CH1_VREFCA DDR3L_CH1_DQ39_LPDDR3_CH1_DQB7 AV12 M_B_DQ40
MEM_CH0_RCOMPAV34 DDR3L_CH0_DQ41_LPDDR3_CH0_DQB9 M_A_DQ41 [10] DDR3L_CH1_DQ40_LPDDR3_CH1_DQB8 M_B_DQ40 [11]
R89 105_1%_4 BG40 M_A_DQ42 M_A_DQ42 [10]
BD6 M_B_DQ41 M_B_DQ41 [11]
MEM_CH0_RCOMP DDR3L_CH0_DQ42_LPDDR3_CH0_DQB10 BJ40 M_A_DQ43 R91 105_1%_4 MEM_CH1_RCOMP AV30 DDR3L_CH1_DQ41_LPDDR3_CH1_DQB9 BD5 M_B_DQ42
DDR3L_CH0_DQ43_LPDDR3_CH0_DQB11 M_A_DQ43 [10] MEM_CH1_RCOMP DDR3L_CH1_DQ42_LPDDR3_CH1_DQB10 M_B_DQ42 [11]
[10] M_A_CLK0 BD45 BG43 M_A_DQ44 M_A_DQ44 [10] BB7 M_B_DQ43 M_B_DQ43 [11]
BE45 DDR3L_CH0_CLKP0_LPDDR3_CH0_CLKP_B DDR3L_CH0_DQ44_LPDDR3_CH0_DQB12 BG44 M_A_DQ45 BD19 DDR3L_CH1_DQ43_LPDDR3_CH1_DQB11 AV10 M_B_DQ44
[10] M_A_CLK0# DDR3L_CH0_CLKN0_LPDDR3_CH0_CLKN_B DDR3L_CH0_DQ45_LPDDR3_CH0_DQB13 M_A_DQ45 [10] [11] M_B_CLK0 DDR3L_CH1_CLKP0_LPDDR3_CH1_CLKP_B DDR3L_CH1_DQ44_LPDDR3_CH1_DQB12 M_B_DQ44 [11]
BH45 M_A_DQ46 M_A_DQ46 [10] [11] M_B_CLK0#
BE19 AY9 M_B_DQ45 M_B_DQ45 [11]
BB48 DDR3L_CH0_DQ46_LPDDR3_CH0_DQB14 BH41 M_A_DQ47 DDR3L_CH1_CLKN0_LPDDR3_CH1_CLKN_B DDR3L_CH1_DQ45_LPDDR3_CH1_DQB13 AY7 M_B_DQ46
DDR3L_CH0_CLKP1_LPDDR3_CH0_CLKP_A DDR3L_CH0_DQ47_LPDDR3_CH0_DQB15 M_A_DQ47 [10] DDR3L_CH1_DQ46_LPDDR3_CH1_DQB14 M_B_DQ46 [11]
BD48 BA34 M_A_DQ48 M_A_DQ48 [10]
BB21 BF5 M_B_DQ47 M_B_DQ47 [11]
DDR3L_CH0_CLKN1_LPDDR3_CH0_CLKN_A DDR3L_CH0_DQ48_LPDDR3_CH0_DQB16 BE34 M_A_DQ49 BD21 DDR3L_CH1_CLKP1_LPDDR3_CH1_CLKP_A DDR3L_CH1_DQ47_LPDDR3_CH1_DQB15 AU2 M_B_DQ48
DDR3L_CH0_DQ49_LPDDR3_CH0_DQB17 M_A_DQ49 [10] DDR3L_CH1_CLKN1_LPDDR3_CH1_CLKN_A DDR3L_CH1_DQ48_LPDDR3_CH1_DQB16 M_B_DQ48 [11]
MA_DRAMRST# AR34 BD34 M_A_DQ50 AT10 M_B_DQ49
DDR3L_CH0_RESET_N_LPDDR3_NC DDR3L_CH0_DQ50_LPDDR3_CH0_DQB18 M_A_DQ50 [10] DDR3L_CH1_DQ49_LPDDR3_CH1_DQB17 M_B_DQ49 [11]
BD37 M_A_DQ51 M_A_DQ51 [10]
MB_DRAMRST# AR30 AT9 M_B_DQ50 M_B_DQ50 [11]
DDR3L_CH0_DQ51_LPDDR3_CH0_DQB19 BB37 M_A_DQ52 DDR3L_CH1_RESET_N_LPDDR3_NC DDR3L_CH1_DQ50_LPDDR3_CH1_DQB18 AU1 M_B_DQ51
DDR3L_CH0_DQ52_LPDDR3_CH0_DQB20 M_A_DQ52 [10] DDR3L_CH1_DQ51_LPDDR3_CH1_DQB19 M_B_DQ51 [11]
BE39 M_A_DQ53 M_A_DQ53 [10] AY5 M_B_DQ52 M_B_DQ52 [11]
C102 DDR3L_CH0_DQ53_LPDDR3_CH0_DQB21 BD39 M_A_DQ54 DDR3L_CH1_DQ52_LPDDR3_CH1_DQB20 AV5 M_B_DQ53
DDR3L_CH0_DQ54_LPDDR3_CH0_DQB22 M_A_DQ54 [10] DDR3L_CH1_DQ53_LPDDR3_CH1_DQB21 M_B_DQ53 [11]
BB34 M_A_DQ55 M_A_DQ55 [10] C97 AV6 M_B_DQ54 M_B_DQ54 [11]
0.1u/16V_4 DDR3L_CH0_DQ55_LPDDR3_CH0_DQB23 BJ38 M_A_DQ56 DDR3L_CH1_DQ54_LPDDR3_CH1_DQB22 AV7 M_B_DQ55
DDR3L_CH0_DQ56_LPDDR3_CH0_DQB24 M_A_DQ56 [10] DDR3L_CH1_DQ55_LPDDR3_CH1_DQB23 M_B_DQ55 [11]
colsed to CPU pin within 100 mils BG34 M_A_DQ57 M_A_DQ57 [10] 0.1u/16V_4 AY2 M_B_DQ56 M_B_DQ56 [11]
DDR3L_CH0_DQ57_LPDDR3_CH0_DQB25 BG33 M_A_DQ58 DDR3L_CH1_DQ56_LPDDR3_CH1_DQB24 BD2 M_B_DQ57
DDR3L_CH0_DQ58_LPDDR3_CH0_DQB26 M_A_DQ58 [10] colsed to CPU pin within 100 mils DDR3L_CH1_DQ57_LPDDR3_CH1_DQB25 M_B_DQ57 [11]
R102 BH33 M_A_DQ59 M_A_DQ59 [10]
BD1 M_B_DQ58 M_B_DQ58 [11]
DDR3L_CH0_DQ59_LPDDR3_CH0_DQB27 BG38 M_A_DQ60 R101 DDR3L_CH1_DQ58_LPDDR3_CH1_DQB26 BE2 M_B_DQ59
DDR3L_CH0_DQ60_LPDDR3_CH0_DQB28 M_A_DQ60 [10] DDR3L_CH1_DQ59_LPDDR3_CH1_DQB27 M_B_DQ59 [11]
10_5%_4 BH37 M_A_DQ61 M_A_DQ61 [10]
AW1 M_B_DQ60 M_B_DQ60 [11]
DDR3L_CH0_DQ61_LPDDR3_CH0_DQB29 BG37 M_A_DQ62 10_5%_4 DDR3L_CH1_DQ60_LPDDR3_CH1_DQB28 AW2 M_B_DQ61
DDR3L_CH0_DQ62_LPDDR3_CH0_DQB30 M_A_DQ62 [10] DDR3L_CH1_DQ61_LPDDR3_CH1_DQB29 M_B_DQ61 [11]
BJ34 M_A_DQ63 M_A_DQ63 [10]
AY3 M_B_DQ62 M_B_DQ62 [11]
DDR3L_CH0_DQ63_LPDDR3_CH0_DQB31 DDR3L_CH1_DQ62_LPDDR3_CH1_DQB30 BG2 M_B_DQ63
DDR3L_CH1_DQ63_LPDDR3_CH1_DQB31 M_B_DQ63 [11]
B BB63 M_A_DQS0 M_A_DQS0 [10]
B
DDR3L_CH0_DQSP0_LPDDR3_CH0_DQSPA0 BC62 M_A_DQS#0 BG28 M_B_DQS0
DDR3L_CH0_DQSN0_LPDDR3_CH0_DQSNA0 M_A_DQS#0 [10] DDR3L_CH1_DQSP0_LPDDR3_CH1_DQSPA0 M_B_DQS0 [11]
Section 1 of 12 AT59 M_A_DQS1 M_A_DQS1 [10]
BH29 M_B_DQS#0 M_B_DQS#0 [11]
DDR3L_CH0_DQSP1_LPDDR3_CH0_DQSPA1 AT58 M_A_DQS#1 DDR3L_CH1_DQSN0_LPDDR3_CH1_DQSNA0 BD29 M_B_DQS1
DDR3L_CH0_DQSN1_LPDDR3_CH0_DQSNA1 M_A_DQS#1 [10] DDR3L_CH1_DQSP1_LPDDR3_CH1_DQSPA1 M_B_DQS1 [11]
AW48 BB59 M_A_DQS2 M_A_DQS2 [10]
Section 2 of 12 BB29 M_B_DQS#1 M_B_DQS#1 [11]
AW47 DDR3L_CH0_CB0_LPDDR3_NC DDR3L_CH0_DQSP2_LPDDR3_CH0_DQSPA2 BB58 M_A_DQS#2 DDR3L_CH1_DQSN1_LPDDR3_CH1_DQSNA1 BJ22 M_B_DQS2
DDR3L_CH0_CB1_LPDDR3_NC DDR3L_CH0_DQSN2_LPDDR3_CH0_DQSNA2 M_A_DQS#2 [10] DDR3L_CH1_DQSP2_LPDDR3_CH1_DQSPA2 M_B_DQS2 [11]
BB43 BD52 M_A_DQS3 M_A_DQS3 [10] AR21 BG22 M_B_DQS#2 M_B_DQS#2 [11]
AW45 DDR3L_CH0_CB2_LPDDR3_NC DDR3L_CH0_DQSP3_LPDDR3_CH0_DQSPA3 BB52 M_A_DQS#3 AT21 DDR3L_CH1_CB0_LPDDR3_NC DDR3L_CH1_DQSN2_LPDDR3_CH1_DQSNA2 AV25 M_B_DQS3
DDR3L_CH0_CB3_LPDDR3_NC DDR3L_CH0_DQSN3_LPDDR3_CH0_DQSNA3 M_A_DQS#3 [10] DDR3L_CH1_CB1_LPDDR3_NC DDR3L_CH1_DQSP3_LPDDR3_CH1_DQSPA3 M_B_DQS3 [11]
AV48 AV39 M_A_DQS4 M_A_DQS4 [10] AW23 AW25 M_B_DQS#3 M_B_DQS#3 [11]
AV47 DDR3L_CH0_CB4_LPDDR3_NC DDR3L_CH0_DQSP4_LPDDR3_CH0_DQSPB0 AW39 M_A_DQS#4 AW21 DDR3L_CH1_CB2_LPDDR3_NC DDR3L_CH1_DQSN3_LPDDR3_CH1_DQSNA3 BB12 M_B_DQS4
DDR3L_CH0_CB5_LPDDR3_NC DDR3L_CH0_DQSN4_LPDDR3_CH0_DQSNB0 M_A_DQS#4 [10] DDR3L_CH1_CB3_LPDDR3_NC DDR3L_CH1_DQSP4_LPDDR3_CH1_DQSPB0 M_B_DQS4 [11]
BD43 BJ42 M_A_DQS5 M_A_DQS5 [10]
BA19 BD12 M_B_DQS#4 M_B_DQS#4 [11]
BA45 DDR3L_CH0_CB6_LPDDR3_NC DDR3L_CH0_DQSP5_LPDDR3_CH0_DQSPB1 BG42 M_A_DQS#5 AW19 DDR3L_CH1_CB4_LPDDR3_NC DDR3L_CH1_DQSN4_LPDDR3_CH1_DQSNB0 BB5 M_B_DQS5
DDR3L_CH0_CB7_LPDDR3_NC DDR3L_CH0_DQSN5_LPDDR3_CH0_DQSNB1 M_A_DQS#5 [10] DDR3L_CH1_CB5_LPDDR3_NC DDR3L_CH1_DQSP5_LPDDR3_CH1_DQSPB1 M_B_DQS5 [11]
BB35 M_A_DQS6 M_A_DQS6 [10] BA23 BB6 M_B_DQS#5 M_B_DQS#5 [11]
BD47 DDR3L_CH0_DQSP6_LPDDR3_CH0_DQSPB2 BD35 M_A_DQS#6 BB23 DDR3L_CH1_CB6_LPDDR3_NC DDR3L_CH1_DQSN5_LPDDR3_CH1_DQSNB1 AT5 M_B_DQS6
DDR3L_CH0_DQSP8_LPDDR3_NC DDR3L_CH0_DQSN6_LPDDR3_CH0_DQSNB2 M_A_DQS#6 [10] DDR3L_CH1_CB7_LPDDR3_NC DDR3L_CH1_DQSP6_LPDDR3_CH1_DQSPB2 M_B_DQS6 [11]
BB47 BG36 M_A_DQS7 M_A_DQS7 [10]
AT6 M_B_DQS#6 M_B_DQS#6 [11]
DDR3L_CH0_DQSN8_LPDDR3_NC DDR3L_CH0_DQSP7_LPDDR3_CH0_DQSPB3 BH35 M_A_DQS#7 BD23 DDR3L_CH1_DQSN6_LPDDR3_CH1_DQSNB2 BC2 M_B_DQS7
DDR3L_CH0_DQSN7_LPDDR3_CH0_DQSNB3 M_A_DQS#7 [10] DDR3L_CH1_DQSP8_LPDDR3_NC DDR3L_CH1_DQSP7_LPDDR3_CH1_DQSPB3 M_B_DQS7 [11]
BE23 BB1 M_B_DQS#7 M_B_DQS#7 [11]
DDR3L_CH1_DQSN8_LPDDR3_NC DDR3L_CH1_DQSN7_LPDDR3_CH1_DQSNB3

DRAMRST-MA DRAMRST-MB

+1.35VSUS +1.35VSUS

R106 R105

A A
CPU CPU
1K_1%_4 1K_1%_4

MA_DRAMRST# MB_DRAMRST#
MA_DRAMRST# [10] MB_DRAMRST# [11]
C103 C101

0.1u/16V_4 0.1u/16V_4 Quanta Computer Inc.

PROJECT : ZAJ
Size Document Number Rev
3A
BXTP (MEMORY)
Date: Tuesday, March 21, 2017 Sheet 2 of 34
5 4 3 2 1
 5 4 3 2 1

Apollo lake (SATA , ODD, CLK ,USB,PCIE)

03
+1.8V_S5

R366
D D
10K_5%_4

U21C APL_BGA_1296P
[19] USB3_0_TXP J1 N62
J2 USB3_P0_TXP PCIE_W AKE3_N P61 PCIE_LAN_WAKE#
[19] USB3_0_TXN USB3_P0_TXN PCIE_W AKE2_N PCIE_LAN_WAKE# [15]
MB USB3.0 [19] USB3_0_RXP K9 P62
K10 USB3_P0_RXP PCIE_W AKE1_N R62
[19] USB3_0_RXN USB3_P0_RXN PCIE_W AKE0_N
[20] USB3_1_TXP K3
K2 USB3_P1_TXP F6 PCIE_RCOMPP
[20] USB3_1_TXN USB3_P1_TXN PCIE2_USB3_SATA3_RCOMP_P
MB TYPE C [20] USB3_1_RXP F2 R37
G2 USB3_P1_RXP 402_1%_4
[20] USB3_1_RXN USB3_P1_RXN F5 PCIE_RCOMPN
AC16 PCIE2_USB3_SATA3_RCOMP_N
USB2_VBUS_SNS P3 PCIE_TX3+ 0.1u/16V_4 C332
PCIE_P3_USB3_P4_TXP PCIE_TX3+_WLAN [17]
R64 137_1%_4 USB_SSIC_RCOMP AB15 P2 PCIE_TX3- 0.1u/16V_4 C333
USB_SSIC_RCOMP PCIE_P3_USB3_P4_TXN PCIE_TX3-_WLAN [17]
P12 PCIE_RX3+_WLAN [17] WIFI
R75 113_1%_4 USBCOMP Y15 PCIE_P3_USB3_P4_RXP P10
USB2_RCOMP PCIE_P3_USB3_P4_RXN PCIE_RX3-_WLAN [17]
USB2COMP： 4-8mils trace width with <1000 mils
R382 *0_5%_4 USB_OTG_ID AC15 N2
USB2_OTG_ID PCIE_P4_USB3_P3_TXP M2
AH13 PCIE_P4_USB3_P3_TXN H5
R377 *10K_5%_4 AH12 USB_SSIC_0_TX_P PCIE_P4_USB3_P3_RXP H6
+1.8V_S5 USB_SSIC_0_TX_N PCIE_P4_USB3_P3_RXN
AG16
R328 10K_5%_4 AG15 USB_SSIC_0_RX_P L2
USB_SSIC_0_RX_N PCIE_P5_USB3_P2_TXP USB3_2_TXP [20]
R327 10K_5%_4 L1 USB3_2_TXN [20]
B55 PCIE_P5_USB3_P2_TXN K7
[20] USB_OC0#
C55 USB2_OC0_N PCIE_P5_USB3_P2_RXP M7
USB3_2_RXP [20] MB TYPE C
[19] USB_OC1# USB2_OC1_N PCIE_P5_USB3_P2_RXN USB3_2_RXN [20]
V3 PCIE_TX0+_SSD [16]
V12 PCIE_P0_TXP V2
C [19] USBP0+ PCIE_TX0-_SSD [16] C
V10 USB2_DP0 PCIE_P0_TXN P7
MB USB3.0 CONN [19] USBP0-
V16 USB2_DN0 PCIE_P0_RXP P6
PCIE_RX0+_SSD [16]
[20] USBP1+ USB2_DP1 PCIE_P0_RXN PCIE_RX0-_SSD [16]
MB TYPE C [20] USBP1- V15 M.2 SSD
Y13 USB2_DN1 R1
[19] USBP2+ USB2_DP2 PCIE_P1_TXP PCIE_TX1+_SSD [16]
USB 2.0 [19] USBP2-
V13 R2 PCIE_TX1-_SSD [16]
V9 USB2_DN2 PCIE_P1_TXN T10
[19] USBP3+ USB2_DP3 PCIE_P1_RXP PCIE_RX1+_SSD [16]
USB 2.0 V7 T12 PCIE_RX1-_SSD [16]
[19] USBP3- USB2_DN3 PCIE_P1_RXN
Y9 T2 PCIE_TX2+ 0.1u/16V_4 C335
[17] USBP4+ USB2_DP4 PCIE_P2_TXP PCIE_TX2+_LAN [15]
Y10 T3 PCIE_TX2- 0.1u/16V_4 C334
BT [17] USBP4-
AB6 USB2_DN4 PCIE_P2_TXN M5
PCIE_TX2-_LAN [15]
[12] USBP5+
AB7 USB2_DP5 PCIE_P2_RXP M6
PCIE_RX2+_LAN [15] LAN
Touch Screen [12] USBP5-
AC12 USB2_DN5 PCIE_P2_RXN R398 10K_5%_4
PCIE_RX2-_LAN [15]
[12] USBP6+ USB2_DP6
CCD AC10 AK62 CLK_PCIE_SSD_REQ# [16]
[12] USBP6- USB2_DN6 PCIE_CLKREQ0_N
[16] USBP7+ V5 AH62 R391 10K_5%_4
V6 USB2_DP7 PCIE_CLKREQ1_N AH61
ODD bridge [16] USBP7- USB2_DN7 PCIE_CLKREQ2_N AJ62
CLK_PCIE_LAN_REQ# [15]
PCIE_CLKREQ3_N PCIE_CLKREQ_WLAN# [17]
R397 10K_5%_4
W1 C11 R392 *10K_5%_4 +1.8V_S5
[16] SATA_TXP1 SATA_P1_USB3_P5_TXP PCIE_CLKOUT0P
W2 B11
[16] SATA_TXN1 SATA_P1_USB3_P5_TXN PCIE_CLKOUT0N
M.2 SATA T5 C10 CLK_PCIE_SSDP [16]
[16] SATA_RXP1 SATA_P1_USB3_P5_RXP PCIE_CLKOUT1P
[16] SATA_RXN1
T6
SATA_P1_USB3_P5_RXN PCIE_CLKOUT1N
A10 CLK_PCIE_SSDN [16] M.2 SSD
Y3 A7 CLK_PCIE_LANP [15]
[16] SATA_TXP0 SATA_P0_TXP PCIE_CLKOUT2P
[16] SATA_TXN0
Y2
SATA_P0_TXN PCIE_CLKOUT2N
B8 CLK_PCIE_LANN [15] LAN
HDD T9 B7 CLK_PCIE_WLANP [17]
[16] SATA_RXP0 SATA_P0_RXP PCIE_CLKOUT3P
[16] SATA_RXN0
T7
SATA_P0_RXN PCIE_CLKOUT3N
B5 CLK_PCIE_WLANN [17] WIFI

PCH_SPI_SI A58 C1
B PCH_SPI_SO B58 FST_SPI_MOSI_IO0 RSVD_C1 F1 B
PCH_SPI_IO3 B61 FST_SPI_MISO_IO1 RSVD_F1 B4
PCH_SPI_IO2 B60 FST_SPI_IO3 RSVD_B4 A4
C57 FST_SPI_IO2 RSVD_A4 CLK_PCIE_LAN_REQ# R485 *0_5%_4
PCH_SPI_CS0# B57 FST_SPI_CS1_N A18
PCH_SPI_CLK C56 FST_SPI_CS0_N RSVD_A18 C19 PCIE_CLKREQ_WLAN# R486 *0_5%_4
FST_SPI_CLK Section 3 of 12 RSVD_C19

VSTBY_FSPI

VSTBY_FSPI

R352 R326
C5
3.3K_5%_4 *3.3K_5%_4 R354
0.1u/16V_4
U1
3.3K_5%_4
PCH_SPI_CS0# 1 8
PCH_SPI_CLK R302 33_5%_4 SPI_CLK_A 6 CE# VCC
PCH_SPI_SI 5 SCLK
PCH_SPI_SO 2 SI 7 PCH_SPI_IO3
SO IO3
PCH_SPI_IO2 3 4
IO2 VSS

GD25LB64CSIGR
A A

SP@ socket P/N: DFHS08FS023 only for A-TEST

SPI ROM Vender Size Quanta P/N Vender P/N Quanta Computer Inc.
WND 8M AKE5EZN0N01 W25Q64FWSSIQ
1.8V
PROJECT : ZAJ
GGD 8M AKE5EG-0Q01 GD25LB64CSIGR Size Document Number Rev
3A
BXTP (PCIE/USB/SATA/SPI)
Date: Tuesday, March 21, 2017 Sheet 3 of 34
5 4 3 2 1
 5 4 3 2 1

Apollolake (DISPLAY,eDP)
04
U21D APL_BGA_1296P
AF2 AP7 MDSI_RCOMP R87 150_1%_4 +3V
AF3 DDI1_TXP_0 MDSI_RCOMP
AD3 DDI1_TXN_0
D
AD2 DDI1_TXP_1 AK7 D
AC1 DDI1_TXN_1 MDSI_C_DP_0 AK6
AC2 DDI1_TXP_2 MDSI_C_DN_0 AM5
AB3 DDI1_TXN_2 MDSI_C_DP_1 AM6 R297 R336
AB2 DDI1_TXP_3 MDSI_C_DN_1 AM12
DDI1_TXN_3 MDSI_C_DP_2 AM10 10K_5%_4 10K_5%_4
AK16 MDSI_C_DN_2 AK13
AK15 DDI1_AUXP MDSI_C_DP_3 AM13
DDI1_AUXN MDSI_C_DN_3 EDP_VDD_EN [12]
AM9
MDSI_C_CLKP +3V

6
AK3 AM7
[13] INT_HDMITX2P DDI0_TXP_0 MDSI_C_CLKN
AK2
[13] INT_HDMITX2N DDI0_TXN_0 PCH_VDDEN
HDMI

AM3 AP12 5 2
[13] INT_HDMITX1P DDI0_TXP_1 MDSI_A_DP_0
AM2 AP10 SSM6N43FU
[13] INT_HDMITX1N DDI0_TXN_1 MDSI_A_DN_0
AH3 AR2
[13] INT_HDMITX0P DDI0_TXP_2 MDSI_A_DP_1
AH2 AR1
[13] INT_HDMITX0N

1
AL2 DDI0_TXN_2 MDSI_A_DN_1 AP15 Q27A Q27B
[13] INT_HDMICLK+ DDI0_TXP_3 MDSI_A_DP_2
AL1 AP13 R299 R332
[13] INT_HDMICLK- DDI0_TXN_3 MDSI_A_DN_2 AP6
AM16 MDSI_A_DP_3 AP5 10K_5%_4 10K_5%_4
AM15 DDI0_AUXP MDSI_A_DN_3
DDI0_AUXN AP2
MDSI_A_CLKP PCH_BLON [12]
B51 AP3
C51 MIPI_I2C_SDA MDSI_A_CLKN
MIPI_I2C_SCL F27MCSI_DPHY1.2_RCOMP R40 150_1%_4
MCSI_DPHY1.2_RCOMP

6
R385 402_1%_4 DDI0_RCOMP_P AG1
DDI0_RCOMP_N AG2 DDI0_RCOMP_P M23
DDI0_RCOMP_N MCSI_RX_DATA0_P P23 PCH_BKLTEN 5 2
INT_HDMI_HPD# C50 MCSI_RX_DATA0_N L23 SSM6N43FU
[13] INT_HDMI_HPD# GPIO_200 MCSI_RX_CLK0_P
C A50 J23 C
[20] TypeC_HPD# GPIO_199 MCSI_RX_CLK0_N +3V
J21

1
EDP_TXP0 AG7 MCSI_RX_DATA1_P H21 Q26A Q26B
[12] EDP_TXP0 EDP_TXN0 EDP_TXP_0 MCSI_RX_DATA1_N
AG9 M25
[12] EDP_TXN0 EDP_TXP1 EDP_TXN_0 MCSI_RX_DATA2_P
AG12 L25
[12] EDP_TXP1 EDP_TXN1 EDP_TXP_1 MCSI_RX_DATA2_N
AG10 F25
[12] EDP_TXN1 EDP_TXP2 EDP_TXN_1 MCSI_RX_CLK1_P
AC6 E25
eDP Panel [12]
[12]
EDP_TXP2
EDP_TXN2
EDP_TXN2 AC5 EDP_TXP_2 MCSI_RX_CLK1_N H25 R298 R337
EDP_TXP3 AC7 EDP_TXN_2 MCSI_RX_DATA3_P J25
[12] EDP_TXP3 EDP_TXP_3 MCSI_RX_DATA3_N
EDP_TXN3 AC9 10K_5%_4 10K_5%_4
[12] EDP_TXN3 EDP_TXN_3 H27MCSI_DPHY1.1_RCOMP R44 150_1%_4
R74 402_1%_4 EDP_RCOMP_P AG6 MCSI_DPHY1.1_RCOMP
EDP_RCOMP_N AG5 EDP_RCOMP_P PCH_BRIGHT [12]
P17
EDP_RCOMP_N MCSI_DP_0 M17
MCSI_DN_0

6
EDP_AUXP AH10 P21
[12] EDP_AUXP EDP_AUXN EDP_AUXP MCSI_DP_1
AH9 R21
[12] EDP_AUXN EDP_AUXN MCSI_DN_1 PCH_BKLTCTL
L17 5 2
C54 MCSI_DP_2 J17 SSM6N43FU
A54 DDI1_DDC_SDA MCSI_DN_2 F17
DDI1_DDC_SCL MCSI_DP_3 E17

1
HDMI_DDCDATA_SW C49 MCSI_DN_3 Q28A Q28B
[13] HDMI_DDCDATA_SW HDMI_DDCCLK_SW B49 DDI0_DDC_SDA M19
[13] HDMI_DDCCLK_SW DDI0_DDC_SCL MCSI_CLKP_0 L19
C52 MCSI_CLKN_0 H19
B53 PNL1_VDDEN MCSI_CLKP_2 F19
C53 PNL1_BKLTEN MCSI_CLKN_2
PNL1_BKLTCTL L37
PCH_VDDEN C47 GP_CAMERASB0 P34
PCH_BKLTEN B47 PNL0_VDDEN GP_CAMERASB1 J34
PCH_BKLTCTL C46 PNL0_BKLTEN GP_CAMERASB2 H30
B PNL0_BKLTCTL GP_CAMERASB3 M37 B
AG62 GP_CAMERASB4 F30
AF61 OSC_CLK_OUT_0 GP_CAMERASB5 R35
AG63 OSC_CLK_OUT_1 GP_CAMERASB6 L34
AE60 OSC_CLK_OUT_2 GP_CAMERASB7 M34
AF62 OSC_CLK_OUT_3 GP_CAMERASB8 M35
OSC_CLK_OUT_4 GP_CAMERASB9 R34
GP_CAMERASB10 E30
C309 15p/50V_4 XTAL192_OUT P29 GP_CAMERASB11
R27 OSCOUT M45
OSCIN MDSI_A_TE M43
Section 4 of 12 MDSI_C_TE
4
3

Y3 R301

19.2MHZ/20ppm 200K_1%_4
2
1

C310 15p/50V_4 XTAL192_IN

A A

Quanta Computer Inc.

PROJECT : ZAJ
Size Document Number Rev
BXTP (HDMI/eDP) 3A

Date: Tuesday, March 21, 2017 Sheet 4 of 34

5 4 3 2 1
 5 4 3 2 1

Apollolake (EMMC/LPC/I2C) +1.8V_S5

05
U21E APL_BGA_1296P ACCEL_INTA R321 *GS@10K_5%_4

V58 V49 SIO_EXT_SCI# R308 *10K_5%_4

[12] EMMC_DATA_0 EMMC_D0 RSVD_V49
[12] EMMC_DATA_1 T58
T59 EMMC_D1 E34 GPIO_RCOMP R34 200_1%_4
[12] EMMC_DATA_2 EMMC_D2 GPIO_RCOMP
[12] EMMC_DATA_3 V51
V52 EMMC_D3 V59 EMMC_RCOMP R58 200_1%_4 PCH_TPD_INT# R25 10K_5%_4
[12] EMMC_DATA_4 EMMC_D4 EMMC_RCOMP
D [12] EMMC_DATA_5 Y49 D
V55 EMMC_D5
[12] EMMC_DATA_6 EMMC_D6 +3V
V57 A38 Board_ID0
[12] EMMC_DATA_7 EMMC_D7 GPIO_0
V54 B33 Board_ID1
[12] EMMC_RCLK EMMC_RCLK GPIO_1
Y51 C39 Board_ID2
[12] EMMC_CMD EMMC_CMD GPIO_2
Y58 B39 Board_ID3
[12] EMMC_CLK EMMC_CLK GPIO_3 B35 Board_ID4
GPIO_4 A34 Board_ID5 R22 R21
GPIO_104 F54 GPIO_5 B31
[9] GPIO_104 SIO_SPI_0_CLK GPIO_6 ACCEL_INTA [18]
GPIO_105 F52 H39 Board_ID6 10K_5%_4 10K_5%_4
[9] GPIO_105 SIO_SPI_0_FS0 GPIO_7
GPIO_106 H52 B29 Board_ID8
[9] GPIO_106 SIO_SPI_0_FS1 GPIO_8
H54 A30 Board_ID7 GPIO_23
GPIO_110 SIO_SPI_0_RXD GPIO_9 NGFF_SATA_DET# [16]
[9] GPIO_110 J52 L39
SIO_SPI_0_TXD GPIO_10 C34
GPIO_11 SIO_EXT_SCI# [21]

3
GPIO_111 F58 E39
[9] GPIO_111 SIO_SPI_1_CLK GPIO_12
GPIO_112 K55 C30
[9] GPIO_112 SIO_SPI_1_FS0 GPIO_13
GPIO_113 F61 C38 2 5
[9] GPIO_113 SIO_SPI_1_FS1 GPIO_14
H57 F39
GPIO_117 H58 SIO_SPI_1_RXD GPIO_15 C36 Q4B Q4A +3V
[9] GPIO_117 SIO_SPI_1_TXD GPIO_16 C35

4
SOC_OVRIDE F62 GPIO_17 J39 2N7002KDW
SIO_SPI_2_CLK GPIO_18 PCH_TPD_INT# [18]
D61 C33
GPIO_120 E56 SIO_SPI_2_FS0 GPIO_19 B27
EMI [9]
[9]
GPIO_120
GPIO_121
GPIO_121 D59 SIO_SPI_2_FS1
SIO_SPI_2_FS2
GPIO_20
GPIO_21
C26 R487 R289
C62 A26
LPC_CLKOUT1 GPIO_123 SIO_SPI_2_RXD GPIO_22 GPIO_23 TP32
[9] GPIO_123 E62 B25 *10K_5%_4 *10K_5%_4
SIO_SPI_2_TXD GPIO_23 C25 GPIO_24
GPIO_24 C27 GPIO_25
LPC_LAD0_R GPIO_25 RAM_ID0 SATA_DEVSLP0 [16]
R374 20_1%_4 Y61 C31
[16,17,21] LPC_LAD0 LPC_AD0 GPIO_26

6
C336 R375 20_1%_4 LPC_LAD1_R Y62 C29 RAM_ID1
[16,17,21] LPC_LAD1 LPC_LAD2_R LPC_AD1 GPIO_27 RAM_ID2
R370 20_1%_4 W62 B37
[16,17,21] LPC_LAD2 LPC_LAD3_R LPC_AD2 GPIO_28 RAM_ID3 GPIO_24
*10p/50V_4 R372 20_1%_4 W63 H35 5 2
[16,17,21] LPC_LAD3 LPC_AD3 GPIO_29 RAM_ID4
C37
R379 20_1%_4 LPC_CLKOUT0 AB61 GPIO_30 H34 eMMC_ID0
[21] CLK_PCI_EC LPC_CLKOUT0 GPIO_31
[16] PCLK_TPM R376 TPM@20_1%_4 LPC_CLKOUT1AA62 F35 eMMC_ID1 Q25A Q25B

1
C
R380 *DBG@20_1%_4 LPC_CLKOUT1 GPIO_32 F34 RAM_ID5 C
[17] CLK_PCI_LPC GPIO_33
R371 20_1%_4 CLKRUN#_R V62
[16,21] CLKRUN#
[16,17,21] LPC_LFRAME# R369 20_1%_4 LPC_LFRAME#_R V61 LPC_CLKRUN_N HDA *SSM6N43FU
R386 20_1%_4 SOC_SERIRQ_R AB62 LPC_FRAME_N AM48 HDA_BCLK_R R98 33_5%_4
[16] SOC_SERIRQ LPC_SERIRQ ISH_GPIO_0 AZ_CODEC_BITCLK [14] +3V
AK58 HDA_SYNC_R R399 33_5%_4 AZ_CODEC_SYNC [14]
Section 5 of 12 ISH_GPIO_1 AK51
ISH_GPIO_2 AZ_CODEC_SDIN0 [14]
GPIO_39 B45 AM54 HDA_SDO_R R95 33_5%_4
[9] GPIO_39 LPSS_UART0_TXD ISH_GPIO_3 AZ_CODEC_SDOUT [14]
C45 AM51
GPIO_40 LPSS_UART0_RXD ISH_GPIO_4 TP9
A46 AM49
[9] GPIO_40
C44 LPSS_UART0_RTS_N
LPSS_UART0_CTS_N
ISH_GPIO_5
ISH_GPIO_6
AM57
TP7
TP8
EMI R488 R300
AM55 C245 *10p/50V_4
GPIO_43 ISH_GPIO_7 TP10
[9] GPIO_43 B43 AM52 *10K_5%_4 *10K_5%_4
C43 LPSS_UART1_TXD ISH_GPIO_8 AK57
GPIO_44 LPSS_UART1_RXD ISH_GPIO_9 SPKR [14]
[9] GPIO_44 A42
LPSS_UART1_RTS_N SATA_DEVSLP1 [16]
C42
LPSS_UART1_CTS_N

6
AR62
GPIO_47 H41 LPSS_I2C0_SDA AR63
[9] GPIO_47 LPSS_UART2_TXD LPSS_I2C0_SCL
J41 GPIO_25 5 2
TP1 GPIO_48 LPSS_UART2_RXD
[9] GPIO_48 L41 AN62
M41 LPSS_UART2_RTS_N LPSS_I2C1_SDA AM61
TP2 LPSS_UART2_CTS_N LPSS_I2C1_SCL Q24A Q24B

1
AP59
P51 LPSS_I2C2_SDA AP58
T52 SDIO_PWR_DWN_N LPSS_I2C2_SCL *SSM6N43FU +1.8V_S5
P57 SDIO_D0 AM62
T54 SDIO_D1 LPSS_I2C3_SDA AL62
T55 SDIO_D2 LPSS_I2C3_SCL
T57 SDIO_D3 AP52 I2C4_SDA
SDIO_CMD LPSS_I2C4_SDA I2C4_SDA [18]
P58 AP54 I2C4_SCL I2C4_SDA R90 2K_1%_4
SDIO_CLK LPSS_I2C4_SCL I2C4_SCL [18] Touch PAD I2C4_SCL R92 2K_1%_4
AB55 AP49
AC49 SDCARD_LVL_WP LPSS_I2C5_SDA AP51
SDCARD_D0 LPSS_I2C5_SCL
I2C standard/fast mode：
AC48 I2C total lenght is about 4500 mils = 4.5inchs
AC51 SDCARD_D1 AL63
B AB51 SDCARD_D2 LPSS_I2C6_SDA AK61
Cb = 4.5*5pF +7pF = 29.5pF B
AC52 SDCARD_D3 LPSS_I2C6_SCL PU resistor = 2K ohm
AB58 SDCARD_CMD AP62 +1.8V_S5
SDCARD_CLK LPSS_I2C7_SDA
SERIRQ is 1.8V_S5 at EC side but AB54
SDCARD_CD_N LPSS_I2C7_SCL
AP61

3V_S5 at CPU/TPM side R339

R341
10K_5%_4
10K_5%_4
Board_ID0
Board_ID1
R316
R320
*10K_5%_4
*10K_5%_4
R348 10K_5%_4 Board_ID2 R315 *10K_5%_4
HW strap ID Strap pin Description R347 10K_5%_4 Board_ID3 R314 *10K_5%_4
0 = w/o type C R349 10K_5%_4 Board_ID4 R319 *10K_5%_4 Board ID
Board_ID0 1 = w/ type C R342 10K_5%_4 Board_ID5 R309 *10K_5%_4
R288 10K_5%_4 Board_ID6 R296 *10K_5%_4
+1.8V_S5 +3V_S5 0 = with EMMC R282 10K_5%_4 Board_ID7 R290 *10K_5%_4
Board_ID1 R491 10K_5%_4 Board_ID8 R492 *10K_5%_4
1 = without EMMC <HDD only>
U22 0 = SATA SSD
1 6 Board_ID2
VCCA VCCB 1 = PCIE SSD R350 *10K_5%_4 RAM_ID0 R330 10K_5%_4
0 = none G sensor R285 10K_5%_4 RAM_ID1 R293 *10K_5%_4
2 5 R390 10K_5%_4 Board_ID3 R340 10K_5%_4 RAM_ID2 R317 *10K_5%_4
GND EO +1.8V_S5 1 = G sensor R284 10K_5%_4 RAM_ID3 R292 *10K_5%_4 RAM ID
0 = none TPM R338 *10K_5%_4 RAM_ID4 R318 10K_5%_4
[21] IRQ_SERIRQ 3 4 SOC_SERIRQ Board_ID4 1 = TPM R286 10K_5%_4 RAM_ID5 R294 *10K_5%_4
A B
G2129TL1U 0 = EJ HDD R287 *10K_5%_4 eMMC_ID0 R295 10K_5%_4
Board_ID5 1 = Cloud book SSD R283 10K_5%_4 eMMC_ID1 R291 *10K_5%_4 eMMC ID
0 = EJ SSD
Board_ID6 1 = Cloud book N/A
RAM_ID5 RAM_ID4 RAM_ID3 Vender Quanta PN Description
+1.8V_S5 0 = EJ series
Board_ID7 1 = Cloud book 0 0 0 Miron-2GB AKD5JGSTL08 IC SDRAM(96P)MT41K256M16HA-125:E STNBSQ

R381
0 = UMA 0 0 1 Miron-2GB AKD59GSTL12 IC SDRAM(96P)MT41K256M16TW-107:P STNBSQ
A Board_ID8 1 = GPU A

2.2K_5%_4
0 1 0 Hynix-2GB AKD5PGSTW29 IC SDRAM(96P)H5TC4G63EFR-PBA(FBGA)STNBSQ
0 = Single channel (A only)
RAM_ID0 1 = Dual channel (A & B) 0 1 1 Samsung-2GB AKD5JG0T504 IC SDRAM(96P)K4B4G1646E-BYK0(FBGA)STNBSQ
SOC_OVRIDE
0 = Channel A 2GB
RAM_ID1 1 = Channel A 4GB
3

2 Q30
0 = Channel B 2GB
RAM_ID2
[21] ME_WR# 1 = Channel B 4GB eMMC_ID1 eMMC_ID0 Vender
Quanta Computer Inc.
2N7002K 0 0 Samsung 32/64GB
PROJECT : ZAJ
1

Flash Descriptor Override (SOC_OVRIDE) 0 1 Hynix 32/64GB

0 = Normal Override(Normal operation) Size Document Number Rev
3A
1 = Override 1 0 Kingston 32/64GB BXTP (EMMC/LPC/SMB/ISH)
Date: Tuesday, March 21, 2017 Sheet 5 of 34
5 4 3 2 1
 5 4 3 2 1

Apollolake (PMU/PMIC/HDA)
colsed to CPU pin within 100 mils
06
C50 0.1u/16V_4 R61 10_5%_4
U21F APL_BGA_1296P
RTC_TEST# AH49 AC55 RTC_RST#
AC57 RTC_TEST_N RTC_RST_N AC63 PCH_SUSPWRDNACK
[21] RSMRST# RSM_RST_N SUSPWRDNACK PCH_SUSPWRDNACK [21]
[21,22,26] H_PROCHOT# E47 AG58
PMU_WAKE# PROCHOT_N SUS_STAT_N TP6
AG55
PMU_SUSCLK AE62 PMU_WAKE_N J62
TP37 PMU_SUSCLK AVS_I2S1_WS_SYNC GPIO_78
[21] SUSC# AK54 K62 GPIO_78 [9]
AC62 PMU_SLP_S4_N AVS_I2S1_SDO K61
[21] SUSB# PMU_SLP_S0# AD61 PMU_SLP_S3_N AVS_I2S1_SDI G62
D TP38 PMU_RSTBTN# AD62 PMU_SLP_S0_N AVS_I2S1_MCLK D

PMU Block
H63
TP36 PMU_RSTBTN_N AVS_I2S1_BCLK
R73 200_1%_4 PMU_RCOMP AG59
AK55 PMU_RCOMP M58 GPIO_88
[21] DNBSWON# PCI_PLTRST# PMU_PWRBTN_N AVS_I2S2_SDO GPIO_88 [9]
AG57 K59
PCH_BATLOW# AH51 PMU_PLTRST_N AVS_I2S2_SDI K58 HDA_RST#_R R52 33_5%_4
PMU_BATLOW_N AVS_I2S2_MCLK AZ_CODEC_RST# [14]
ACPRESENT AK49 H59
+1.8V_S5 PMU_AC_PRESENT AVS_I2S2_BCLK M57
AG49 AVS_I2S2_WS_SYNC
[21] EC_PWROK SOC_PWROK M61
THERMTRIP#_SOC J47 AVS_I2S3_WS_SYNC L63 GPIO_92
PMIC_THERMTRIP_N AVS_I2S3_SDO GPIO_92 [9]
C79 J45 L62
R384 *10K_5%_4 PCH_SUSPWRDNACK M47 PMIC_STDBY AVS_I2S3_SDI M62
R17 1K_1%_4 H_PROCHOT# 0.1u/16V_4 F48 PMIC_SDWN_B_GPIO_213 AVS_I2S3_BCLK
R23 *10K_5%_4 THERMTRIP#_SOC H48 PMIC_RESET_N M52
F47 PMIC_PWRGOOD AVS_DMIC_DATA_2 M54
R83 H45 PMIC_I2C_SDA AVS_DMIC_DATA_1 P52
+3V_S5 PMIC_I2C_SCL AVS_DMIC_CLK_B1 GPIO_82
10_5%_4
L47
P47 GPIO_214 AVS_DMIC_CLK_AB2
M55
P54
GPIO_82 [9] Folllow APL MOW31：
GPIO_215 AVS_DMIC_CLK_A1
R82
R71
*100K_5%_4
1K_1%_4
PCH_BATLOW#
PMU_WAKE# H50 AG51 C58 0.1u/16V_4
un-stuff 51 ohm pull down resistor on
colsed to CPU pin within 100 mils PMC_SPI_TXD VCC_RTC_EXTPAD
R85
R389
10K_5%_4
10K_5%_4
ACPRESENT
PMU_RSTBTN#
J50
M48 PMC_SPI_RXD RTC_X2
AC58
AC59
RTC_X2
RTC_X1
+1.8V_S5 TRST_N pin
R67 *100K_5%_4 RSMRST# INT_EDP_HPD# P48 PMC_SPI_FS2 RTC_X1
EC_PWROK [12] INT_EDP_HPD# PMC_SPI_FS1 XDP_PREQ#
R81 20K_1%_4 L48 C20 R307 100_1%_4
E52 PMC_SPI_FS0 JTAG_PREQ_N C21 XDP_PRDY# R306 100_1%_4
PMC_SPI_CLK JTAG_PRDY_N B19 +1.05V
GPIO_34 B41 JTAG_PMODE C24 XDP_TRST# R322 *51_5%_4
[9] GPIO_34 GPIO_35 PWM0 JTAG_TRST_N XDP_TMS
[9] GPIO_35 C41 C23 R303 51_5%_4
GPIO_36 F41 PWM1 JTAG_TMS A22 XDP_TDO R304 100_1%_4
[9] GPIO_36 PWM2 JTAG_TDO XDP_TDI
E41 C22 R305 51_5%_4
PWM3 JTAG_TDI B23 XDP_TCK R335 51_5%_4 R323 R324 C313
B21 JTAG_TCK
R62 330K_5%_4 INTRUDER# AC54 JTAGX L30 169_1%_4 68_1%_4 1000p/50V_4
+3V_RTC INTRUDER GPIO_219 M30
PCH_MBDAT0_R T61 GPIO_218 M29 H_CPU_SVIDDAT
PCH_MBCLK0_R T62 SMB_DATA GPIO_217 P30 VR_SVID_ALERT#_VCORE
R63 SMB_CLK GPIO_216
SMB_ALERT_N E21 CLKDRV_RCOMP R42 60.4_1%_4
C
PLTRST# Buffer H43 PCIE_REF_CLK_RCOMP
C

+3V AG52 RSVD_H43 C18

RSVD_AG52 SVID0_DATA H_CPU_SVIDDAT [26]
J43 C17
RSVD_J43 SVID0_CLK H_CPU_SVIDCLK [26]
AG54 B17SVID_ALERT#_R R329 220_5%_4
RSVD_AG54 SVID0_ALERT_N VR_SVID_ALERT#_VCORE [26]
Section 6 of 12
R66

Q5 10K_5%_4
2

PCI_PLTRST# 3 1 PLTRST# [12,15,16,17,21]

2N7002K THERMALTRIP#
C70

0.1u/16V_4 THERMTRIP#_SOC R24 *S_4 THERMTRIP# [21]

colsed to CPU pin within 100 mils
R72

10_5%_4

RTC Clock 32.768KHz (CPU) CH01006JB08 -> 10p

CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p
C47 15p/50V_4 RTC_X1

1
SMBus(PCH) Trace length < 1000 mils Y1 R60

10M_5%_4
+3V_S5 +3V 32.768KHZ/20ppm
C34 15p/50V_4 RTC_X2

2
B B

R368 R365 R45 R38

RTC Circuitry (RTC)
5

1K_1%_4 1K_1%_4 4.7K_5%_4 4.7K_5%_4 +3VPCU

Q29A +3V_RTC
PCH_MBDAT0_R 3 4 +3V_RTC
CLK_SDATA [18]
D26
Trace width = 20 mils
CN7 2 R245
3
2

3 RTC_RST#
Q29B R463 1K_1%_4 +3V_RTC_1 1
1

1
PCH_MBCLK0_R 6 1 20K_1%_4
CLK_SCLK [18] 2
Trace width = 20 mils C253
2N7002KDW BAT54CW J1
DDR_GS/S0
4

CB@cable RTC 1u/6.3V_4 *JUMP

APL S5

2
R246
RTC_TEST#

20K_1%_4
C254

1u/6.3V_4
+5V_S5
20MIL
VCCRTC_2 1 3 VCCRTC_3 VCCRTC_4 R474 [email protected]_5%_4
[21,22] SB_ACDC R88 *S_4 ACPRESENT R475 [email protected]_5%_4
1

CN13 Q34 EJ@PMST3904

R468
2
+

3 4
[email protected]_1%_4
-

EJ@53014-00201-V09
2

A A
R469

RTC_TEST# ML1220 Coin type EJ@150K_1%_4

EC reset RTC RTC_RST#
AHL03001031 [VDE] 17mAH
AHL03001057 [DBV] 17mAH
3

5 2
[21] CLR_CMOS
Q11A Q11B
Quanta Computer Inc.
PROJECT : ZAJ
4

2N7002KDW
Size Document Number Rev
3A
BXTP (PMU/PMIC/HDA/RTC)
Date: Tuesday, March 21, 2017 Sheet 6 of 34
5 4 3 2 1
 5 4 3 2 1

Apollolake (POWER)
+VCC_VCCGI
07
+VNN U21H APL_BGA_1296P
AJ44 AA36
RSVD_AJ44 VCC_VCGI_1 AA37
AJ37 VCC_VCGI_2 AA39 + C3
AJ39 VNN_SVID_1 VCC_VCGI_3 AC36 C4 C296 C300
AJ41 VNN_SVID_2 VCC_VCGI_4 AC37 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 330u/2V_7343H1.9
D C65 C87 C85 C64 C304 C302 C293 C297 C301 C292 C298 AJ42 VNN_SVID_3 VCC_VCGI_5 AE36 D
22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 47u/6.3V_8 AJ46 VNN_SVID_4 VCC_VCGI_6 AE37
AK37 VNN_SVID_5 4.8A VCC_VCGI_7 AG36
AK39 VNN_SVID_6 VCC_VCGI_8 E43
AK41 VNN_SVID_7 VCC_VCGI_9 E45
AK42 VNN_SVID_8 VCC_VCGI_10 E48
AK44 VNN_SVID_9 VCC_VCGI_11 E50 C8 C33 C41 C66 C81 C46 C7 C6
C73 C78 C76 AK46 VNN_SVID_10 VCC_VCGI_12 R45 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 AM44 VNN_SVID_11 VCC_VCGI_13 R47
+3V_S5 VNN_SVID_12 VCC_VCGI_14 U36
AG48 VCC_VCGI_15 U37
[26] VNN_SENSE VNN_SENSE VCC_VCGI_16 U39
BG63
RSVD_BG63
21A VCC_VCGI_17
VCC_VCGI_18
U41
U42
R84 *S_6 +VCC_3.3V AC41 VCC_VCGI_19 U44 C24 C14 C13 C27 C23 C12 C39 C31 C16 C15 C11 C29
AA42 VCC_3P3V_A_1 VCC_VCGI_20 U46 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
Y44 VCC_3P3V_A_2 VCC_VCGI_21 U47
C38 C77 C37 C48 C92 V44 VCC_3P3V_A_3 0.15A VCC_VCGI_22 U48
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 V46 VCC_3P3V_A_4 VCC_VCGI_23 V36
AJ25 VCC_3P3V_A_5 VCC_VCGI_24 V37
+1.24V_S5 AK25 VCC_3P3V_A_USB_1 VCC_VCGI_25 V39
VCC_3P3V_A_USB_2 VCC_VCGI_26 V41
R395 *S_4 +VCC_1.24V_USB2 AC22 VCC_VCGI_27 Y36
RSVD_AC22 VCC_VCGI_28 Y37
R394 *S_6 +VCC_1.24V_AUD_ISH_PLL C67 AC20 VCC_VCGI_29 Y39
1u/6.3V_4 RSVD_AC20 VCC_VCGI_30 Y41
C72 C74 C348 AG20 VCC_VCGI_31 AA28
1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 VCC_1P24V_1P35V_A_USB2 VCC_VCGI_32 AA30
AJ20 VCC_VCGI_33 AA32
AJ22 VCC_1P24V_1P35V_A_PLL_1 VCC_VCGI_34 AC28
R387 *S_6 +VCC_1.24V_MPHY VCC_1P24V_1P35V_A_PLL_2 VCC_VCGI_35 AC30
AE18 VCC_VCGI_36 AC32
C AE20 VCC_1P24V_1P35V_A_MPHY_1 1.3A VCC_VCGI_37 AE28 C
C56 C71 C49 C68 AE22 VCC_1P24V_1P35V_A_MPHY_2 VCC_VCGI_38 AE30
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 AG22 VCC_1P24V_1P35V_A_MPHY_3 VCC_VCGI_39 AE32
VCC_1P24V_1P35V_A_MPHY_4 VCC_VCGI_40 AG28
AM20 VCC_VCGI_41 AG30
R396 *S_6 +VCC_1.24V_GLM AM28 VCC_1P24V_1P35V_A_GLML2LDO_1 VCC_VCGI_42 AG32
AM37 VCC_1P24V_1P35V_A_GLML2LDO_2 VCC_VCGI_43 AJ28
AK20 VCC_1P24V_1P35V_A_GLML2LDO_3 VCC_VCGI_44 AJ30
C86 C82 C83 C80 C351 VCC_1P24V_1P35V_A_GLML2 VCC_VCGI_45 AJ32
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 AA18 VCC_VCGI_46 AK28
AA20 VDD2_1P24_DSI_CSI#1 VCC_VCGI_47 AK30
R388 *0_5%_6 +VCC_1.24V_DSI_CSI VDD2_1P24_DSI_CSI#2 VCC_VCGI_48 AK32
+VCC_1.24V_AUD_ISH_PLL AK22 VCC_VCGI_49 AK34
VCC_1P24V_1P35V_A_AUD_ISH VCC_VCGI_50 AM30
C57 C60 C69 V48 VCC_VCGI_51 E29
*1u/6.3V_4 *1u/6.3V_4 *22u/6.3V_6 RSVD_V48 VCC_VCGI_52 E35
+1.8V_S5 VCC_VCGI_53 E37
AA46 VCC_VCGI_54 F29
AC46 VCC_1P8V_A_1 VCC_VCGI_55 U28
AE44 VCC_1P8V_A_2 VCC_VCGI_56 U30
R86 *S_6 +VCC_1.8V AE42 VCC_1P8V_A_3 VCC_VCGI_57 U32
AC42 VCC_1P8V_A_4 0.4A VCC_VCGI_58 V28
AC44 VCC_1P8V_A_5 VCC_VCGI_59 V30
C62 C59 C63 C61 C91 AE46 VCC_1P8V_A_6 VCC_VCGI_60 V32
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 AG25 VCC_1P8V_A_7 VCC_VCGI_61 Y28
VCC_1P8V_A_8 VCC_VCGI_62 Y30
VCC_VCGI_63 Y32
BJ3 VCC_VCGI_64 +VCC_1.05V_IO
BJ61 RSVD_BJ3
RSVD_BJ61

+3V_RTC AA44 AA25

VCCRTC_3P3V VCC_1P05V_1 AC25
B C45 1u/6.3V_4 VCC_1P05V_2 AE25 B
+1.05V D1 VCC_1P05V_3 U22 C35 C32 C25 C19 C30 C26
RSVD_D1 VCC_1P05V_4 U23 22u/6.3V_6 22u/6.3V_6 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4
VCC_1P05V_5 V22
R373 *S_8 +VCC_1.05V_IO AA22 VCC_1P05V_6 V23
R378 *S_8 AC23 VCC_1P05V_IO_1 VCC_1P05V_7 V25
V18 VCC_1P05V_IO_2 VCC_1P05V_8 Y23
C21 C17 C44 C20 C40 Y18 VCC_1P05V_IO_3 2.7A VCC_1P05V_9 Y25
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 22u/6.3V_6 Y20 VCC_1P05V_IO_4 VCC_1P05V_10 U25
VCC_1P05V_IO_5 VCC_1P05V_11 U20
AA23 VCC_1P05V_12
VCC_1P05V_3PHASEIO
+VCC_1.05V_INT P16
+1.05V VCC_1P05V_FUSE
R383 *S_6 T15
T13 VCC_1P05V_FHV1
VCC_1P05V_FHV0

Section 8 of 12

+1.35VSUS

U21I APL_BGA_1296P
BJ62
AN18 RSVD_BJ62
AN20 VDDQ_1 R41
VDDQ_2 VCC_VCGI_SENSE_P VCCGI_SENSE [26]
AN22
C84 C99 C88 C94 C95 C89 C98 C100 AN23 VDDQ_3 R43
VDDQ_4 VCC_VCGI_SENSE_N VCCGISS_SENSE [26]
22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 22u/6.3V_6 AN41
AN42 VDDQ_5
AN44 VDDQ_6
AN46 VDDQ_7
A AR17 VDDQ_8 2.8A A
AR47 VDDQ_9
C104 C96 AT13 VDDQ_10 +VNN
1u/6.3V_4 1u/6.3V_4 AT17 VDDQ_11
AT47 VDDQ_12 AM23
AT51 VDDQ_13 VCCIOA_1 AM25
AV14 VDDQ_14 VCCIOA_2 AM41
AV50 VDDQ_15 VCCIOA_3 AM42 C305 C303 C93 C90

AM32
VDDQ_16 VCCIOA_4
AN32
22u/6.3V_6 22u/6.3V_6 1u/6.3V_4 1u/6.3V_4 Quanta Computer Inc.
RSVD_AM32 Section 9 of 12 RSVD_AN32
PROJECT : ZAJ
Size Document Number Rev
3A
BXTP (POWER)
Date: Tuesday, March 21, 2017 Sheet 7 of 34
5 4 3 2 1
 5 4 3 2 1

Apollolake ULT (GND)

R29
A12
U21J
VSS_1
APL_BGA_1296P
AH58
VSS_82 AH59
AV19
AV2
U21K
VSS_163
APL_BGA_1296P
BG29
VSS_244 BG32 L43
U21L APL_BGA_1296P
U2 U21G APL_BGA_1296P
08
A16 VSS_2 VSS_83 AH6 AV21 VSS_164 VSS_245 BG35 L45 VSS_325 VSS_361 U27 B13 M12
A20 VSS_3 VSS_84 AH7 AV23 VSS_165 VSS_246 BG41 L50 VSS_326 VSS_362 U34 C13 SPARE_9 NOCONNECT_16 C15
A24 VSS_4 VSS_85 AJ1 AV29 VSS_166 VSS_247 BG45 M14 VSS_327 VSS_363 U5 L16 SPARE_8 NOCONNECT_17 F16
D A28 VSS_5 VSS_86 AJ18 AV3 VSS_167 VSS_248 BH1 M21 VSS_328 VSS_364 U50 M16 SPARE_7 NOCONNECT_18 J16 D
A32 VSS_6 VSS_87 AJ2 AV32 VSS_168 VSS_249 BH2 M27 VSS_329 VSS_365 U51 E23 SPARE_6 NOCONNECT_19 D8
A36 VSS_7 VSS_88 AJ23 AV35 VSS_169 VSS_250 BH21 M3 VSS_330 VSS_366 U53 F23 SPARE_5 NOCONNECT_20 E8
A40 VSS_8 VSS_89 AJ27 AV41 VSS_170 VSS_251 BH25 M32 VSS_331 VSS_367 U54 R25 SPARE_4 NOCONNECT_21 H16
A44 VSS_9 VSS_90 AJ34 AV43 VSS_171 VSS_252 BH39 M50 VSS_332 VSS_368 U56 AB49 SPARE_3 NOCONNECT_22 C9
A48 VSS_10 VSS_91 AJ36 AV45 VSS_172 VSS_253 BH43 M59 VSS_333 VSS_369 U57 AC13 SPARE_2 NOCONNECT_23 F8
A5 VSS_11 VSS_92 AJ63 AV55 VSS_173 VSS_254 BH62 M9 VSS_334 VSS_370 U59 AB13 SPARE_11 NOCONNECT_24 E10
A52 VSS_12 VSS_93 AK10 AV61 VSS_174 VSS_255 BH63 N1 VSS_335 VSS_371 U62 AM59 SPARE_10 NOCONNECT_25 E16
A56 VSS_13 VSS_94 AK12 AV62 VSS_175 VSS_256 BJ10 N32 VSS_336 VSS_372 U63 AM58 SPARE_1 NOCONNECT_26 F14
A62 VSS_14 VSS_95 AK18 AV9 VSS_176 VSS_257 BJ14 N63 VSS_337 VSS_373 U7 SPARE_0 NOCONNECT_27 F12
A9 VSS_15 VSS_96 AK23 AW14 VSS_177 VSS_258 BJ18 P13 VSS_338 VSS_374 U8 T51 NOCONNECT_28 H10
AA1 VSS_16 VSS_97 AK27 AW30 VSS_178 VSS_259 BJ28 P19 VSS_339 VSS_375 V20 L14 NOCONNECT_1 NOCONNECT_29 H14
AA2 VSS_17 VSS_98 AK36 AW34 VSS_179 VSS_260 BJ32 P35 VSS_340 VSS_376 V27 R19 NOCONNECT_2 NOCONNECT_30 H12
AA27 VSS_18 VSS_99 AK48 AW50 VSS_180 VSS_261 BJ36 P37 VSS_341 VSS_377 V34 E6 NOCONNECT_3 NOCONNECT_31 A14
AA34 VSS_19 VSS_100 AK5 AY10 VSS_181 VSS_262 BJ4 P41 VSS_342 VSS_378 V42 R17 NOCONNECT_4 NOCONNECT_32 C14
AA41 VSS_20 VSS_101 AK52 AY32 VSS_182 VSS_263 BJ46 P43 VSS_343 VSS_379 Y12 E3 NOCONNECT_5 NOCONNECT_33 M39
AA63 VSS_21 VSS_102 AK59 AY54 VSS_183 VSS_264 BJ50 P45 VSS_344 VSS_380 Y16 D4 NOCONNECT_6 NOCONNECT_34 P39
AB10 VSS_22 VSS_103 AK9 AY58 VSS_184 VSS_265 BJ54 P5 VSS_345 VSS_381 Y22 A60 NOCONNECT_7 NOCONNECT_35 R39
AB12 VSS_23 VSS_104 AM18 AY6 VSS_185 VSS_266 BJ56 P55 VSS_346 VSS_382 Y27 A61 NOCONNECT_8 NOCONNECT_36 R37
AB16 VSS_24 VSS_105 AM22 B2 VSS_186 VSS_267 BJ60 P59 VSS_347 VSS_383 Y34 BJ2 NOCONNECT_9 NOCONNECT_37 C2
AB48 VSS_25 VSS_106 AM27 B3 VSS_187 VSS_268 BJ8 P9 VSS_348 VSS_384 Y42 BG1 NOCONNECT_10 NOCONNECT_38 J29
AB5 VSS_26 VSS_107 AM34 B62 VSS_188 VSS_269 C12 R23 VSS_349 VSS_385 Y46 P27 NOCONNECT_11 NOCONNECT_39 P25
AB52 VSS_27 VSS_108 AM36 B63 VSS_189 VSS_270 C16 R32 VSS_350 VSS_386 Y48 A3 NOCONNECT_12 NOCONNECT_40 R30
AB57 VSS_28 VSS_109 AM39 B9 VSS_190 VSS_271 C28 T49 VSS_351 VSS_387 Y5 M10 NOCONNECT_13 NOCONNECT_41 C63
C VSS_29 VSS_110 AM46 VSS_191 VSS_272 C32 VSS_352 VSS_388 Y52 NOCONNECT_14 NOCONNECT_42 C
AB59 BA1 U1 B15 E63
AB9 VSS_30 VSS_111 AN1 BA12 VSS_192 VSS_273 C40 U10 VSS_353 VSS_389 Y54 NOCONNECT_15 NOCONNECT_43 D2
AC18 VSS_31 VSS_112 AN10 BA16 VSS_193 VSS_274 C48 U11 VSS_354 VSS_390 Y55 NOCONNECT_44 AP57
AC27 VSS_32 VSS_113 AN11 BA17 VSS_194 VSS_275 D32 U13 VSS_355 VSS_391 Y57 Section 7 of 12 NOCONNECT_45
AC34 VSS_33 VSS_114 AN13 BA2 VSS_195 VSS_276 D58 U14 VSS_356 VSS_392 Y59
AC39 VSS_34 VSS_115 AN14 BA21 VSS_196 VSS_277 D6 U16 VSS_357 VSS_393 Y6
AE1 VSS_35 VSS_116 AN16 BA25 VSS_197 VSS_278 E12 U17 VSS_358 VSS_394 Y7
AE10 VSS_36 VSS_117 AN17 BA27 VSS_198 VSS_279 E14 U18 VSS_359 VSS_395
AE11 VSS_37 VSS_118 AN2 BA29 VSS_199 VSS_280 E19 VSS_360 Sect 12/12
AE13 VSS_38 VSS_119 AN25 BA32 VSS_200 VSS_281 E27
AE14 VSS_39 VSS_120 AN27 BA35 VSS_201 VSS_282 E4
AE16 VSS_40 VSS_121 AN28 BA37 VSS_202 VSS_283 E54
AE17 VSS_41 VSS_122 AN30 BA39 VSS_203 VSS_284 F10
AE2 VSS_42 VSS_123 AN34 BA43 VSS_204 VSS_285 F21
AE23 VSS_43 VSS_124 AN36 BA47 VSS_205 VSS_286 F3
AE27 VSS_44 VSS_125 AN37 BA48 VSS_206 VSS_287 F32
AE34 VSS_45 VSS_126 AN39 BA52 VSS_207 VSS_288 F37
AE39 VSS_46 VSS_127 AN47 BA62 VSS_208 VSS_289 F43
AE4 VSS_47 VSS_128 AN48 BA63 VSS_209 VSS_290 F45
AE41 VSS_48 VSS_129 AN5 BB19 VSS_210 VSS_291 F50
AE47 VSS_49 VSS_130 AN50 BB25 VSS_211 VSS_292 F56
AE48 VSS_50 VSS_131 AN51 BB3 VSS_212 VSS_293 F59
AE5 VSS_51 VSS_132 AN53 BB39 VSS_213 VSS_294 F63
AE50 VSS_52 VSS_133 AN54 BB45 VSS_214 VSS_295 G1
B B
AE51 VSS_53 VSS_134 AN56 BB61 VSS_215 VSS_296 G32
AE53 VSS_54 VSS_135 AN57 BC32 VSS_216 VSS_297 H17
AE54 VSS_55 VSS_136 AN59 BD3 VSS_217 VSS_298 H23
AE56 VSS_56 VSS_137 AN63 BD32 VSS_218 VSS_299 H29
AE57 VSS_57 VSS_138 AN7 BD56 VSS_219 VSS_300 H3
AE59 VSS_58 VSS_139 AN8 BD61 VSS_220 VSS_301 H37
AE63 VSS_59 VSS_140 AP55 BD8 VSS_221 VSS_302 H47
AE7 VSS_60 VSS_141 AP9 BE1 VSS_222 VSS_303 H61
AE8 VSS_61 VSS_142 AR19 BE10 VSS_223 VSS_304 H7
AG13 VSS_62 VSS_143 AR32 BE12 VSS_224 VSS_305 J12
AG18 VSS_63 VSS_144 AR45 BE16 VSS_225 VSS_306 J14
AG23 VSS_64 VSS_145 AT12 BE17 VSS_226 VSS_307 J19
AG27 VSS_65 VSS_146 AT16 BE21 VSS_227 VSS_308 J27
AG34 VSS_66 VSS_147 AT19 BE27 VSS_228 VSS_309 J30
AG37 VSS_67 VSS_148 AT2 BE29 VSS_229 VSS_310 J32
AG39 VSS_68 VSS_149 AT25 BE35 VSS_230 VSS_311 J35
AG41 VSS_69 VSS_150 AT29 BE37 VSS_231 VSS_312 J37
AG42 VSS_70 VSS_151 AT3 BE43 VSS_232 VSS_313 J48
AG44 VSS_71 VSS_152 AT35 BE47 VSS_233 VSS_314 J63
AG46 VSS_72 VSS_153 AT39 BE48 VSS_234 VSS_315 K32
AH15 VSS_73 VSS_154 AT45 BE52 VSS_235 VSS_316 K5
AH16 VSS_74 VSS_155 AT48 BE54 VSS_236 VSS_317 K54
AH48 VSS_75 VSS_156 AT52 BE63 VSS_237 VSS_318 K57
A AH5 VSS_76 VSS_157 AT57 BF3 VSS_238 VSS_319 K6 A
AH52 VSS_77 VSS_158 AT61 BF32 VSS_239 VSS_320 L21
AH54 VSS_78 VSS_159 AT62 BF61 VSS_240 VSS_321 L27
AH55 VSS_79 VSS_160 AT7 BG19 VSS_241 VSS_322 L29
AH57 VSS_80
VSS_81
VSS_161 AU32
VSS_162
BG23 VSS_242
VSS_243
VSS_323 L35
VSS_324
Quanta Computer Inc.
Section 10 of 12 Section 11 of 12
PROJECT : ZAJ
Size Document Number Rev
3A
BXTP (GND)
Date: Tuesday, March 21, 2017 Sheet 8 of 34
5 4 3 2 1
 5 4 3 2 1

HARDWARE STRAPS

+1.8V_S5
Folllow APL WoW36：
Enable boot from SPI
Hardware Strap

GPIO_36
Strap Description
VCC_1P24V_1P35V_A voltage select
0 = 1.24V
1 = 1.35V
09
GPIO_43=0;GPIO_44=1
Enable CSE(TXE3.0) ROM Bypass
D D
GPIO_39 0 = Disable bypass
1 = Enable Bypass
Allow eMMC as a boot source
R27 R310 R311 R312 R28 R360 R19 R363 R16 R26 R18 GPIO_43 0 = Disable
1 = Enable
*4.7K_5%_4 *4.7K_5%_4 *4.7K_5%_4 4.7K_5%_4 *4.7K_5%_4 *10K_5%_4 *10K_5%_4 *4.7K_5%_4 *4.7K_5%_4 *10K_5%_4 *4.7K_5%_4
Allow SPI as a boot source
GPIO_44 0 = Disable
GPIO_36 1 = Enable
GPIO_36 [6]
GPIO_39 Force DNX FW Load
GPIO_39 [5]
GPIO_47 0 = Do not force
GPIO_43 1 = Force
GPIO_43 [5]
GPIO_44 SMBus 1.8V/3.3V mode select
GPIO_44 [5]
GPIO_78 0=buffers set to 3.3V
GPIO_47 1=buffers set to 1.8V
GPIO_47 [5]
GPIO_78 PMU 1.8V/3.3V mode select
GPIO_78 [6]
GPIO_88 0=buffers set to 3.3V mode
GPIO_88 1=buffers set to 1.8V mode
C
GPIO_88 [6] C
GPIO_92 SMBus No Re-Boot
GPIO_92 [6]
GPIO_92 0 = Disable (default)
GPIO_110 1 = Enable
GPIO_110 [5]
GPIO_111 LPC 1.8V/3.3V mode select
GPIO_111 [5]
GPIO_110 0=buffers set to 3.3V mode
1=buffers set to 1.8V mode
GPIO_120 Boot BIOS Strap
GPIO_120 [5]
GPIO_111 0 = Boot from SPI
1 = Do not boot from SPI
R33 R343 R344 R345 R32 R364 R31 R367 R36 R29 R30

10K_5%_4 10K_5%_4 10K_5%_4 *10K_5%_4 10K_5%_4 10K_5%_4 10K_5%_4 10K_5%_4 4.7K_5%_4 4.7K_5%_4 10K_5%_4

Top swap override

GPIO_120 0 = Disable
1 = Enable

B B

+1.8V_S5

GPIO_34 R346 10K_5%_4

[6] GPIO_34
[5] GPIO_106 R20 4.7K_5%_4
GPIO_35 R313 10K_5%_4
[6] GPIO_35
[5] GPIO_123 R356 10K_5%_4
GPIO_40 R334 4.7K_5%_4
[5] GPIO_40
GPIO_48 R54 10K_5%_4
[5] GPIO_48
GPIO_82 R59 10K_5%_4
[6] GPIO_82
GPIO_104 R41 10K_5%_4
[5] GPIO_104
GPIO_105 R43 10K_5%_4
[5] GPIO_105
GPIO_117 R55 10K_5%_4
[5] GPIO_117
GPIO_112 R57 4.7K_5%_4
[5] GPIO_112
A GPIO_113 R39 4.7K_5%_4 A
[5] GPIO_113
GPIO_121 R35 10K_5%_4
[5] GPIO_121
Quanta Computer Inc.
PROJECT : ZAJ
Size Document Number Rev
3A
HARDWARE STRAPS
Date: Tuesday, March 21, 2017 Sheet 9 of 34
5 4 3 2 1
 5 4 3 2 1

DDR3L MEMORY CHANNEL A

On board memory(OBM)
BYTE0_0-7 BYTE2_16-23 BYTE7_56-63 BYTE4_32-39
10
BYTE1_8-15
U24 U8 BYTE3_24-31 U25 BYTE5_40-47 U9 BYTE6_48-55
+SMDDR_VREF_CA_A M8 E3 +SMDDR_VREF_CA_A M8 E3 +SMDDR_VREF_CA_A M8 E3 +SMDDR_VREF_CA_A M8 E3
+SMDDR_VREF_DQ_A VREFCA DQL0/DQ0 M_A_DQ7 [2] +SMDDR_VREF_DQ_A VREFCA DQL0/DQ0 M_A_DQ19 [2] +SMDDR_VREF_DQ_A VREFCA DQL0/DQ0 M_A_DQ62 [2] +SMDDR_VREF_DQ_A VREFCA DQL0/DQ0 M_A_DQ38 [2]
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1/DQ1 M_A_DQ3 [2] VREFDQ DQL1/DQ1 M_A_DQ18 [2] VREFDQ DQL1/DQ1 M_A_DQ60 [2] VREFDQ DQL1/DQ1 M_A_DQ35 [2]
F2 F2 F2 F2
[2] M_A_A[15:0] M_A_A0 DQL2/DQ2 M_A_DQ2 [2] M_A_A0 DQL2/DQ2 M_A_DQ23 [2] M_A_A0 DQL2/DQ2 M_A_DQ56 [2] M_A_A0 DQL2/DQ2 M_A_DQ37 [2]
N3 F8 N3 F8 N3 F8 N3 F8
M_A_A1 A0 DQL3/DQ3 M_A_DQ4 [2] M_A_A1 A0 DQL3/DQ3 M_A_DQ17 [2] M_A_A1 A0 DQL3/DQ3 M_A_DQ61 [2] M_A_A1 A0 DQL3/DQ3 M_A_DQ32 [2]
P7 H3 P7 H3 P7 H3 P7 H3
M_A_A2 A1 DQL4/DQ4 M_A_DQ6 [2] M_A_A2 A1 DQL4/DQ4 M_A_DQ21 [2] M_A_A2 A1 DQL4/DQ4 M_A_DQ57 [2] M_A_A2 A1 DQL4/DQ4 M_A_DQ39 [2]
P3 H8 P3 H8 P3 H8 P3 H8
M_A_A3 A2 DQL5/DQ5 M_A_DQ0 [2] M_A_A3 A2 DQL5/DQ5 M_A_DQ20 [2] M_A_A3 A2 DQL5/DQ5 M_A_DQ59 [2] M_A_A3 A2 DQL5/DQ5 M_A_DQ33 [2]
N2 G2 N2 G2 N2 G2 N2 G2
D
M_A_A4 A3 DQL6/DQ6 M_A_DQ1 [2] M_A_A4 A3 DQL6/DQ6 M_A_DQ22 [2] M_A_A4 A3 DQL6/DQ6 M_A_DQ58 [2] M_A_A4 A3 DQL6/DQ6 M_A_DQ36 [2] D
P8 H7 P8 H7 P8 H7 P8 H7
M_A_A5 A4 DQL7/DQ7 M_A_DQ5 [2] M_A_A5 A4 DQL7/DQ7 M_A_DQ16 [2] M_A_A5 A4 DQL7/DQ7 M_A_DQ63 [2] M_A_A5 A4 DQL7/DQ7 M_A_DQ34 [2]
P2 P2 P2 P2
M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5 M_A_A6 R8 A5
M_A_A7 R2 A6 D7 M_A_A7 R2 A6 D7 M_A_A7 R2 A6 D7 M_A_A7 R2 A6 D7
M_A_A8 A7 DQU0/DQ8 M_A_DQ10 [2] M_A_A8 A7 DQU0/DQ8 M_A_DQ28 [2] M_A_A8 A7 DQU0/DQ8 M_A_DQ40 [2] M_A_A8 A7 DQU0/DQ8 M_A_DQ55 [2]
T8 C3 T8 C3 T8 C3 T8 C3
M_A_A9 A8 DQU1/DQ9 M_A_DQ12 [2] M_A_A9 A8 DQU1/DQ9 M_A_DQ31 [2] M_A_A9 A8 DQU1/DQ9 M_A_DQ43 [2] M_A_A9 A8 DQU1/DQ9 M_A_DQ51 [2]
R3 C8 R3 C8 R3 C8 R3 C8
M_A_A10 A9 DQU2/DQ10 M_A_DQ9 [2] M_A_A10 A9 DQU2/DQ10 M_A_DQ30 [2] M_A_A10 A9 DQU2/DQ10 M_A_DQ46 [2] M_A_A10 A9 DQU2/DQ10 M_A_DQ50 [2]
L7 C2 L7 C2 L7 C2 L7 C2
M_A_A11 A10/AP DQU3/DQ11 M_A_DQ8 [2] M_A_A11 A10/AP DQU3/DQ11 M_A_DQ24 [2] M_A_A11 A10/AP DQU3/DQ11 M_A_DQ41 [2] M_A_A11 A10/AP DQU3/DQ11 M_A_DQ52 [2]
R7 A7 R7 A7 R7 A7 R7 A7
M_A_A12 A11 DQU4/DQ12 M_A_DQ13 [2] M_A_A12 A11 DQU4/DQ12 M_A_DQ27 [2] M_A_A12 A11 DQU4/DQ12 M_A_DQ44 [2] M_A_A12 A11 DQU4/DQ12 M_A_DQ48 [2]
N7 A2 N7 A2 N7 A2 N7 A2
M_A_A13 A12/BC DQU5/DQ13 M_A_DQ11 [2] M_A_A13 A12/BC DQU5/DQ13 M_A_DQ26 [2] M_A_A13 A12/BC DQU5/DQ13 M_A_DQ47 [2] M_A_A13 A12/BC DQU5/DQ13 M_A_DQ54 [2]
T3 B8 T3 B8 T3 B8 T3 B8
M_A_A14 A13 DQU6/DQ14 M_A_DQ14 [2] M_A_A14 A13 DQU6/DQ14 M_A_DQ29 [2] M_A_A14 A13 DQU6/DQ14 M_A_DQ45 [2] M_A_A14 A13 DQU6/DQ14 M_A_DQ49 [2]
T7 A3 T7 A3 T7 A3 T7 A3
M_A_A15 A14 DQU7/DQ15 M_A_DQ15 [2] M_A_A15 A14 DQU7/DQ15 M_A_DQ25 [2] M_A_A15 A14 DQU7/DQ15 M_A_DQ42 [2] M_A_A15 A14 DQU7/DQ15 M_A_DQ53 [2]
M7 M7 M7 M7
A15/NC +1.35VSUS A15/NC +1.35VSUS A15/NC +1.35VSUS A15/NC +1.35VSUS
[2] M_A_BS#[2:0] M_A_BS#0 M_A_BS#0 M_A_BS#0 M_A_BS#0
M2 B2 M2 B2 M2 B2 M2 B2
M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9 M_A_BS#1 N8 BA0 VDD#B2 D9
M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7 M_A_BS#2 M3 BA1 VDD#D9 G7
BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
M_A_CLK0 J7 VDD#N1 N9 M_A_CLK0 J7 VDD#N1 N9 M_A_CLK0 J7 VDD#N1 N9 M_A_CLK0 J7 VDD#N1 N9
[2] M_A_CLK0 M_A_CLK0# CK VDD#N9 M_A_CLK0# CK VDD#N9 M_A_CLK0# CK VDD#N9 M_A_CLK0# CK VDD#N9
K7 R1 K7 R1 K7 R1 K7 R1
[2] M_A_CLK0# M_A_CKE0 CK VDD#R1 M_A_CKE0 CK VDD#R1 M_A_CKE0 CK VDD#R1 M_A_CKE0 CK VDD#R1
K9 R9 K9 R9 K9 R9 K9 R9
[2] M_A_CKE0 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9

M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1 M_A_ODT0 K1 A1

M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8 M_A_CS#0 L2 ODT VDDQ#A1 A8
[2] M_A_CS#0 M_A_RAS# J3 CS VDDQ#A8 C1 M_A_RAS# J3 CS VDDQ#A8 C1 M_A_RAS# J3 CS VDDQ#A8 C1 M_A_RAS# J3 CS VDDQ#A8 C1
[2] M_A_RAS# M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9 M_A_CAS# K3 RAS VDDQ#C1 C9
[2] M_A_CAS# M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2 M_A_WE# L3 CAS VDDQ#C9 D2
[2] M_A_WE# WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
M_A_DQS0 F3 VDDQ#F1 H2 M_A_DQS2 F3 VDDQ#F1 H2 M_A_DQS7 F3 VDDQ#F1 H2 M_A_DQS4 F3 VDDQ#F1 H2
[2] M_A_DQS0 M_A_DQS1 DQSL VDDQ#H2 [2] M_A_DQS2 M_A_DQS3 DQSL VDDQ#H2 [2] M_A_DQS7 M_A_DQS5 DQSL VDDQ#H2 [2] M_A_DQS4 M_A_DQS6 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
[2] M_A_DQS1 DQSU VDDQ#H9 [2] M_A_DQS3 DQSU VDDQ#H9 [2] M_A_DQS5 DQSU VDDQ#H9 [2] M_A_DQS6 DQSU VDDQ#H9

C
E7 A9 E7 A9 E7 A9 E7 A9 C
D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
M_A_DQS#0 G3 VSS#G8 J2 M_A_DQS#2 G3 VSS#G8 J2 M_A_DQS#7 G3 VSS#G8 J2 M_A_DQS#4 G3 VSS#G8 J2
[2] M_A_DQS#0 M_A_DQS#1 DQSL VSS#J2 [2] M_A_DQS#2 M_A_DQS#3 DQSL VSS#J2 [2] M_A_DQS#7 M_A_DQS#5 DQSL VSS#J2 [2] M_A_DQS#4 M_A_DQS#6 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
[2] M_A_DQS#1 DQSU VSS#J8 [2] M_A_DQS#3 DQSU VSS#J8 [2] M_A_DQS#5 DQSU VSS#J8 [2] M_A_DQS#6 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
MA_DRAMRST# T2 VSS#P1 P9 MA_DRAMRST# T2 VSS#P1 P9 MA_DRAMRST# T2 VSS#P1 P9 MA_DRAMRST# T2 VSS#P1 P9
[2] MA_DRAMRST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
M_A_ZQ1 L8 VSS#T1 T9 M_A_ZQ2 L8 VSS#T1 T9 M_A_ZQ3 L8 VSS#T1 T9 M_A_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R414 VSSQ#B9 D1 R149 VSSQ#B9 D1 R412 VSSQ#B9 D1 R162 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
240_1%_4 VSSQ#D8 E2 240_1%_4 VSSQ#D8 E2 240_1%_4 VSSQ#D8 E2 240_1%_4 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L
H5TC4G63EFR-PBA H5TC4G63EFR-PBA H5TC4G63EFR-PBA H5TC4G63EFR-PBA

DE-CAPS FOR MEMORY CHANNEL A VTT TERMINATIONS VREF_CA-DQ CIRCUIT

B B

M_A_RAS# R423 80.6_1%_4

M_A_CAS# +VDDQ_VTT +1.35VSUS
R426 80.6_1%_4
M_A_WE# R429 80.6_1%_4
M_A_BS#0 R428 80.6_1%_4
+1.35VSUS M_A_BS#1 R187 80.6_1%_4 VREF_CA trace at least 20mils wide and space
M_A_BS#2 R422 80.6_1%_4 R144
Distributed around all DRAM devices (CHA) M_A_CKE0 R419 80.6_1%_4 +SMDDR_VREF_CA_A
M_A_CS#0 R420 80.6_1%_4 3.65K_1%_4
M_A_A0 R427 80.6_1%_4
C362 C160 C162 C134 C120 C133 M_A_A1 R188 80.6_1%_4
M_A_A2 R189 80.6_1%_4
10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 M_A_A3 R425 80.6_1%_4
M_A_A4 R185 80.6_1%_4 R146
M_A_A5 R184 80.6_1%_4 C139 C141 C146
M_A_A6 R183 80.6_1%_4 3.65K_1%_4 470p/50V_4 0.1u/16V_4 2.2u/10V_4
M_A_A7 R182 80.6_1%_4
M_A_A8 R424 80.6_1%_4
Place these Caps near each X16 Memory Down M_A_A9 R180 80.6_1%_4
M_A_A10 R430 80.6_1%_4
M_A_A11 R179 80.6_1%_4
C148 C366 C377 C157 C143 C153 M_A_A12 R178 80.6_1%_4
M_A_A13 R186 80.6_1%_4
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 M_A_A14 R181 80.6_1%_4
M_A_A15 R421 80.6_1%_4
+1.35VSUS
VREF_DQ trace at least 20mils wide and space
C365 C361 C356 C357 C354 C369 M_A_CLK0 R154 80.6_1%_4 M_A_CLK0# R145
+SMDDR_VREF_DQ_A
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 3.65K_1%_4

A R147 A
C367 C373 C360 C379 C140 C142 C147
M_A_ODT0 R152 1K_1%_4 3.65K_1%_4 470p/50V_4 0.1u/16V_4 2.2u/10V_4
+1.35VSUS
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4

Folllow APL WoW37：Memory Down

ODT single on DRAM side is pulled up to VDDQ
Quanta Computer Inc.
PROJECT :ZAJ
Size Document Number Rev
3A
DDR3L SODIMM-STD CHA
Date: Tuesday, March 21, 2017 Sheet 10 of 34
5 4 3 2 1
 5 4 3 2 1

DDR3L MEMORY CHANNEL B

On board memory(OBM)
BYTE0_0-7 BYTE1_8-15 BYTE5_40-47 BYTE6_48-55
11
U26 BYTE2_16-23 U10 BYTE3_24-31 U11 BYTE7_56-63 U27 BYTE4_32-39
+SMDDR_VREF_CA_B M8 E3 M_B_DQ0 +SMDDR_VREF_CA_B M8 E3 M_B_DQ12 +SMDDR_VREF_CA_B M8 E3 M_B_DQ47 +SMDDR_VREF_CA_B M8 E3 M_B_DQ53
+SMDDR_VREF_DQ_B VREFCA DQL0/DQ0 M_B_DQ4 M_B_DQ0 [2] +SMDDR_VREF_DQ_B VREFCA DQL0/DQ0 M_B_DQ15 M_B_DQ12 [2] +SMDDR_VREF_DQ_B VREFCA DQL0/DQ0 M_B_DQ43 M_B_DQ47 [2] +SMDDR_VREF_DQ_B VREFCA DQL0/DQ0 M_B_DQ48 M_B_DQ53 [2]
H1 F7 H1 F7 H1 F7 H1 F7
VREFDQ DQL1/DQ1 M_B_DQ5 M_B_DQ4 [2] VREFDQ DQL1/DQ1 M_B_DQ13 M_B_DQ15 [2] VREFDQ DQL1/DQ1 M_B_DQ42 M_B_DQ43 [2] VREFDQ DQL1/DQ1 M_B_DQ51 M_B_DQ48 [2]
F2 F2 F2 F2
[2] M_B_A[15:0] M_B_A0 DQL2/DQ2 M_B_DQ6 M_B_DQ5 [2] M_B_A0 DQL2/DQ2 M_B_DQ14 M_B_DQ13 [2] M_B_A0 DQL2/DQ2 M_B_DQ41 M_B_DQ42 [2] M_B_A0 DQL2/DQ2 M_B_DQ52 M_B_DQ51 [2]
N3 F8 N3 F8 N3 F8 N3 F8
M_B_A1 A0 DQL3/DQ3 M_B_DQ1 M_B_DQ6 [2] M_B_A1 A0 DQL3/DQ3 M_B_DQ9 M_B_DQ14 [2] M_B_A1 A0 DQL3/DQ3 M_B_DQ40 M_B_DQ41 [2] M_B_A1 A0 DQL3/DQ3 M_B_DQ50 M_B_DQ52 [2]
P7 H3 P7 H3 P7 H3 P7 H3
M_B_A2 A1 DQL4/DQ4 M_B_DQ3 M_B_DQ1 [2] M_B_A2 A1 DQL4/DQ4 M_B_DQ11 M_B_DQ9 [2] M_B_A2 A1 DQL4/DQ4 M_B_DQ44 M_B_DQ40 [2] M_B_A2 A1 DQL4/DQ4 M_B_DQ55 M_B_DQ50 [2]
P3 H8 P3 H8 P3 H8 P3 H8
M_B_A3 A2 DQL5/DQ5 M_B_DQ2 M_B_DQ3 [2] M_B_A3 A2 DQL5/DQ5 M_B_DQ10 M_B_DQ11 [2] M_B_A3 A2 DQL5/DQ5 M_B_DQ46 M_B_DQ44 [2] M_B_A3 A2 DQL5/DQ5 M_B_DQ54 M_B_DQ55 [2]
N2 G2 N2 G2 N2 G2 N2 G2
D
M_B_A4 A3 DQL6/DQ6 M_B_DQ7 M_B_DQ2 [2] M_B_A4 A3 DQL6/DQ6 M_B_DQ8 M_B_DQ10 [2] M_B_A4 A3 DQL6/DQ6 M_B_DQ45 M_B_DQ46 [2] M_B_A4 A3 DQL6/DQ6 M_B_DQ49 M_B_DQ54 [2] D
P8 H7 P8 H7 P8 H7 P8 H7
M_B_A5 A4 DQL7/DQ7 M_B_DQ7 [2] M_B_A5 A4 DQL7/DQ7 M_B_DQ8 [2] M_B_A5 A4 DQL7/DQ7 M_B_DQ45 [2] M_B_A5 A4 DQL7/DQ7 M_B_DQ49 [2]
P2 P2 P2 P2
M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5 M_B_A6 R8 A5
M_B_A7 R2 A6 D7 M_B_DQ16 M_B_A7 R2 A6 D7 M_B_DQ27 M_B_A7 R2 A6 D7 M_B_DQ56 M_B_A7 R2 A6 D7 M_B_DQ34
M_B_A8 A7 DQU0/DQ8 M_B_DQ22 M_B_DQ16 [2] M_B_A8 A7 DQU0/DQ8 M_B_DQ28 M_B_DQ27 [2] M_B_A8 A7 DQU0/DQ8 M_B_DQ58 M_B_DQ56 [2] M_B_A8 A7 DQU0/DQ8 M_B_DQ39 M_B_DQ34 [2]
T8 C3 T8 C3 T8 C3 T8 C3
M_B_A9 A8 DQU1/DQ9 M_B_DQ23 M_B_DQ22 [2] M_B_A9 A8 DQU1/DQ9 M_B_DQ30 M_B_DQ28 [2] M_B_A9 A8 DQU1/DQ9 M_B_DQ60 M_B_DQ58 [2] M_B_A9 A8 DQU1/DQ9 M_B_DQ36 M_B_DQ39 [2]
R3 C8 R3 C8 R3 C8 R3 C8
M_B_A10 A9 DQU2/DQ10 M_B_DQ21 M_B_DQ23 [2] M_B_A10 A9 DQU2/DQ10 M_B_DQ25 M_B_DQ30 [2] M_B_A10 A9 DQU2/DQ10 M_B_DQ63 M_B_DQ60 [2] M_B_A10 A9 DQU2/DQ10 M_B_DQ33 M_B_DQ36 [2]
L7 C2 L7 C2 L7 C2 L7 C2
M_B_A11 A10/AP DQU3/DQ11 M_B_DQ18 M_B_DQ21 [2] M_B_A11 A10/AP DQU3/DQ11 M_B_DQ26 M_B_DQ25 [2] M_B_A11 A10/AP DQU3/DQ11 M_B_DQ62 M_B_DQ63 [2] M_B_A11 A10/AP DQU3/DQ11 M_B_DQ38 M_B_DQ33 [2]
R7 A7 R7 A7 R7 A7 R7 A7
M_B_A12 A11 DQU4/DQ12 M_B_DQ17 M_B_DQ18 [2] M_B_A12 A11 DQU4/DQ12 M_B_DQ31 M_B_DQ26 [2] M_B_A12 A11 DQU4/DQ12 M_B_DQ59 M_B_DQ62 [2] M_B_A12 A11 DQU4/DQ12 M_B_DQ32 M_B_DQ38 [2]
N7 A2 N7 A2 N7 A2 N7 A2
M_B_A13 A12/BC DQU5/DQ13 M_B_DQ19 M_B_DQ17 [2] M_B_A13 A12/BC DQU5/DQ13 M_B_DQ29 M_B_DQ31 [2] M_B_A13 A12/BC DQU5/DQ13 M_B_DQ61 M_B_DQ59 [2] M_B_A13 A12/BC DQU5/DQ13 M_B_DQ37 M_B_DQ32 [2]
T3 B8 T3 B8 T3 B8 T3 B8
M_B_A14 A13 DQU6/DQ14 M_B_DQ20 M_B_DQ19 [2] M_B_A14 A13 DQU6/DQ14 M_B_DQ24 M_B_DQ29 [2] M_B_A14 A13 DQU6/DQ14 M_B_DQ57 M_B_DQ61 [2] M_B_A14 A13 DQU6/DQ14 M_B_DQ35 M_B_DQ37 [2]
T7 A3 T7 A3 T7 A3 T7 A3
M_B_A15 A14 DQU7/DQ15 M_B_DQ20 [2] M_B_A15 A14 DQU7/DQ15 M_B_DQ24 [2] M_B_A15 A14 DQU7/DQ15 M_B_DQ57 [2] M_B_A15 A14 DQU7/DQ15 M_B_DQ35 [2]
M7 M7 M7 M7
A15/NC +1.35VSUS A15/NC +1.35VSUS A15/NC +1.35VSUS A15/NC +1.35VSUS
[2] M_B_BS#[2:0] M_B_BS#0 M_B_BS#0 M_B_BS#0 M_B_BS#0
M2 B2 M2 B2 M2 B2 M2 B2
M_B_BS#1 N8 BA0 VDD#B2 D9 M_B_BS#1 N8 BA0 VDD#B2 D9 M_B_BS#1 N8 BA0 VDD#B2 D9 M_B_BS#1 N8 BA0 VDD#B2 D9
M_B_BS#2 M3 BA1 VDD#D9 G7 M_B_BS#2 M3 BA1 VDD#D9 G7 M_B_BS#2 M3 BA1 VDD#D9 G7 M_B_BS#2 M3 BA1 VDD#D9 G7
BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2 BA2 VDD#G7 K2
VDD#K2 K8 VDD#K2 K8 VDD#K2 K8 VDD#K2 K8
VDD#K8 N1 VDD#K8 N1 VDD#K8 N1 VDD#K8 N1
M_B_CLK0 J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9 M_B_CLK0 J7 VDD#N1 N9
[2] M_B_CLK0 M_B_CLK0# CK VDD#N9 M_B_CLK0# CK VDD#N9 M_B_CLK0# CK VDD#N9 M_B_CLK0# CK VDD#N9
K7 R1 K7 R1 K7 R1 K7 R1
[2] M_B_CLK0# M_B_CKE0 CK VDD#R1 M_B_CKE0 CK VDD#R1 M_B_CKE0 CK VDD#R1 M_B_CKE0 CK VDD#R1
K9 R9 K9 R9 K9 R9 K9 R9
[2] M_B_CKE0 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9 CKE VDD#R9

M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1 M_B_ODT0 K1 A1

M_B_CS#0 L2 ODT VDDQ#A1 A8 M_B_CS#0 L2 ODT VDDQ#A1 A8 M_B_CS#0 L2 ODT VDDQ#A1 A8 M_B_CS#0 L2 ODT VDDQ#A1 A8
[2] M_B_CS#0 M_B_RAS# J3 CS VDDQ#A8 C1 M_B_RAS# J3 CS VDDQ#A8 C1 M_B_RAS# J3 CS VDDQ#A8 C1 M_B_RAS# J3 CS VDDQ#A8 C1
[2] M_B_RAS# M_B_CAS# K3 RAS VDDQ#C1 C9 M_B_CAS# K3 RAS VDDQ#C1 C9 M_B_CAS# K3 RAS VDDQ#C1 C9 M_B_CAS# K3 RAS VDDQ#C1 C9
[2] M_B_CAS# M_B_WE# L3 CAS VDDQ#C9 D2 M_B_WE# L3 CAS VDDQ#C9 D2 M_B_WE# L3 CAS VDDQ#C9 D2 M_B_WE# L3 CAS VDDQ#C9 D2
[2] M_B_WE# WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9 WE VDDQ#D2 E9
VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1 VDDQ#E9 F1
M_B_DQS0 F3 VDDQ#F1 H2 M_B_DQS1 F3 VDDQ#F1 H2 M_B_DQS5 F3 VDDQ#F1 H2 M_B_DQS6 F3 VDDQ#F1 H2
[2] M_B_DQS0 M_B_DQS2 DQSL VDDQ#H2 [2] M_B_DQS1 M_B_DQS3 DQSL VDDQ#H2 [2] M_B_DQS5 M_B_DQS7 DQSL VDDQ#H2 [2] M_B_DQS6 M_B_DQS4 DQSL VDDQ#H2
C7 H9 C7 H9 C7 H9 C7 H9
[2] M_B_DQS2 DQSU VDDQ#H9 [2] M_B_DQS3 DQSU VDDQ#H9 [2] M_B_DQS7 DQSU VDDQ#H9 [2] M_B_DQS4 DQSU VDDQ#H9

C
E7 A9 E7 A9 E7 A9 E7 A9 C
D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3 D3 DML VSS#A9 B3
DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1 DMU VSS#B3 E1
VSS#E1 G8 VSS#E1 G8 VSS#E1 G8 VSS#E1 G8
M_B_DQS#0 G3 VSS#G8 J2 M_B_DQS#1 G3 VSS#G8 J2 M_B_DQS#5 G3 VSS#G8 J2 M_B_DQS#6 G3 VSS#G8 J2
[2] M_B_DQS#0 M_B_DQS#2 DQSL VSS#J2 [2] M_B_DQS#1 M_B_DQS#3 DQSL VSS#J2 [2] M_B_DQS#5 M_B_DQS#7 DQSL VSS#J2 [2] M_B_DQS#6 M_B_DQS#4 DQSL VSS#J2
B7 J8 B7 J8 B7 J8 B7 J8
[2] M_B_DQS#2 DQSU VSS#J8 [2] M_B_DQS#3 DQSU VSS#J8 [2] M_B_DQS#7 DQSU VSS#J8 [2] M_B_DQS#4 DQSU VSS#J8
M1 M1 M1 M1
VSS#M1 M9 VSS#M1 M9 VSS#M1 M9 VSS#M1 M9
VSS#M9 P1 VSS#M9 P1 VSS#M9 P1 VSS#M9 P1
MB_DRAMRST# T2 VSS#P1 P9 MB_DRAMRST# T2 VSS#P1 P9 MB_DRAMRST# T2 VSS#P1 P9 MB_DRAMRST# T2 VSS#P1 P9
[2] MB_DRAMRST# RESET VSS#P9 RESET VSS#P9 RESET VSS#P9 RESET VSS#P9
T1 T1 T1 T1
M_B_ZQ1 L8 VSS#T1 T9 M_B_ZQ2 L8 VSS#T1 T9 M_B_ZQ3 L8 VSS#T1 T9 M_B_ZQ4 L8 VSS#T1 T9
ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9 ZQ VSS#T9

B1 B1 B1 B1
VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9 VSSQ#B1 B9
R413 VSSQ#B9 D1 R155 VSSQ#B9 D1 R159 VSSQ#B9 D1 R411 VSSQ#B9 D1
VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8 VSSQ#D1 D8
240_1%_4 VSSQ#D8 E2 240_1%_4 VSSQ#D8 E2 240_1%_4 VSSQ#D8 E2 240_1%_4 VSSQ#D8 E2
J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8 J1 VSSQ#E2 E8
L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9 L1 NC#J1 VSSQ#E8 F9
J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1 J9 NC#L1 VSSQ#F9 G1
L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9 L9 NC#J9 VSSQ#G1 G9
NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9 NC#L9 VSSQ#G9
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L SDRAM DDR3L
H5TC4G63EFR-PBA H5TC4G63EFR-PBA H5TC4G63EFR-PBA H5TC4G63EFR-PBA

DE-CAPS FOR MEMORY CHANNEL B VTT TERMINATIONS VREF_CA-DQ CIRCUIT

B B

M_B_RAS# R435 80.6_1%_4

M_B_CAS# +VDDQ_VTT +1.35VSUS
R438 80.6_1%_4
M_B_WE# R441 80.6_1%_4
M_B_BS#0 R440 80.6_1%_4
+1.35VSUS M_B_BS#1 R199 80.6_1%_4 VREF_CA trace at least 20mils wide and space
M_B_BS#2 R434 80.6_1%_4 R166
Distributed around all DRAM devices (CHB) M_B_CKE0 R431 80.6_1%_4 +SMDDR_VREF_CA_B
M_B_CS#0 R432 80.6_1%_4 3.65K_1%_4
M_B_A0 R439 80.6_1%_4
C164 C371 C150 C132 C158 C151 M_B_A1 R200 80.6_1%_4
M_B_A2 R201 80.6_1%_4
10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 10u/6.3V_4 M_B_A3 R436 80.6_1%_4
M_B_A4 R197 80.6_1%_4 R164
M_B_A5 R196 80.6_1%_4 C167 C165 C163
M_B_A6 R195 80.6_1%_4 3.65K_1%_4 470p/50V_4 0.1u/16V_4 2.2u/10V_4
M_B_A7 R194 80.6_1%_4
M_B_A8 R437 80.6_1%_4
Place these Caps near each X16 Memory Down M_B_A9 R192 80.6_1%_4
M_B_A10 R442 80.6_1%_4
M_B_A11 R191 80.6_1%_4
C374 C166 C355 C372 C368 C364 M_B_A12 R190 80.6_1%_4
M_B_A13 R198 80.6_1%_4
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 M_B_A14 R193 80.6_1%_4
M_B_A15 R433 80.6_1%_4
+1.35VSUS
VREF_DQ trace at least 20mils wide and space
C376 C175 C171 C136 C121 C168 M_B_CLK0 R156 80.6_1%_4 M_B_CLK0# R148
+SMDDR_VREF_DQ_B
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 3.65K_1%_4

A R150 A
C358 C363 C378 C375 C149 C152 C156
M_B_ODT0 R160 1K_1%_4 3.65K_1%_4 470p/50V_4 0.1u/16V_4 2.2u/10V_4
+1.35VSUS
1u/6.3V_4 1u/6.3V_4 1u/6.3V_4 1u/6.3V_4

Folllow APL WoW37：Memory Down

ODT single on DRAM side is pulled up to VDDQ
Quanta Computer Inc.
PROJECT : ZAJ
Size Document Number Rev
3A
DDR3L MEMORY DOWNx16 CHB
Date: Tuesday, March 21, 2017 Sheet 11 of 34
5 4 3 2 1
 5 4 3 2 1

eMMC (MMC)
12
+1.8V

R325 *S_4 15 mils +1.8V_EMMC

C331 C321 C317 C319 C316

EC@1u/6.3V_4 [email protected]/16V_4 EC@1u/6.3V_4 [email protected]/16V_4 [email protected]/16V_4
U2 R355 *EC@20K_1%_4
K6 W6 EMMC_CLK_R R331 *S_4
VCCQ_1 CLK EMMC_CLK [5]
AA5 W5
VCCQ_2 CMD EMMC_CMD [5]
W4
VCCQ_3 EMMC_DATA_0 TP5
Y4 H3 [5] C318
+3V AA3 VCCQ_4 DAT0 H4 EMMC_DATA_1 EMMC_DATA_0
[5] *[email protected]/50V_4
VCCQ_5 DAT1 H5 EMMC_DATA_2 EMMC_DATA_1
D
R353 *S_4 15 mils +3V_EMMC T10 DAT2 J2 EMMC_DATA_3 EMMC_DATA_2 [5] D

C322 C320 C328 C329 C327

U9
M6
N5
VCC_1
VCC_2
VCC_3
Power Signals DAT3
DAT4
DAT5
J3
J4
J5
EMMC_DATA_4
EMMC_DATA_5
EMMC_DATA_6
EMMC_DATA_3
EMMC_DATA_4
EMMC_DATA_5
[5]
[5]
[5] EMI request
VCC_4 DAT6 EMMC_DATA_7 EMMC_DATA_6 [5]
[email protected]/16V_4 EC@1u/6.3V_4 EC@1u/6.3V_4 [email protected]/16V_4 [email protected]/16V_4 J6 [5]
+VDDI_EMMC DAT7 EMMC_DATA_7
K2 +1.8V
VDDI U5
RESET
C330 R10 AA6
[email protected]/16V_4 U8 VSS_1 VSSQ_1 Y5 R63
M7
P5
VSS_2
VSS_3
VSS_4
GND VSSQ_2
VSSQ_3
VSSQ_4
K4
AA4
Y2
EC@20K_1%_4
VSSQ_5
D2
L4 R1 EMMC_RST# 2 1
A4 NC#L4 NC_70 R2 PLTRST# [6,15,16,17,21]
A6 NC_1 NC_71 R3
A9 NC_2 NC_72 R5 EMMC_RCLK EC@RB500V-40
NC_3 NC_73 EMMC_RCLK [5]
A11 R12
B2 NC_4 NC_74 R13
B13 NC_5 NC_75 R14 R357
D1 NC_6 NC_76 T1
D14 NC_7 NC_77 T2 EC@100K_5%_4
H1 NC_8 NC_78 T3
H2 NC_9 NC_79 T5
H6 NC_10 NC_80 T12
H7 NC_11 NC_81 T13
H8 NC_12 NC_82 T14
H9 NC_13 NC_83 U1
H10 NC_14 NC_84 U2
H11 NC_15 NC_85 U3
H12 NC_16 NC_86
H13 NC_17 U6
H14 NC_18 NC_87 U7
J1 NC_19 NC_88 U10
J7 NC_20 RFU#7 U12
J8 NC_21 NC_90 U13
J9 NC_22 NC_91 U14
J10 NC_23 NC_92 V1
J11 NC_24 NC_93 V2
J12 NC_25 NC_94 V3
J13 NC_26 NC_95 V12
J14 NC_27 NC_96 V13
K1 NC_28 NC_97 V14
K3 NC_29 NC_98 W1
K5
K7
K8
NC_30
NC_31
NC_32
NC NC_99
NC_100
NC_101
W2
W3
W7
C K9 NC_33 NC_102 W8 C
K10 NC_34 NC_103 W9
K11 NC_35 NC_104 W10
K12 NC_36 NC_105 W11
K13 NC_37 NC_106 W12
K14 NC_38 NC_107 W13
L1 NC_39 NC_108 W14
L2 NC_40 NC_109 Y1
L3 NC_41 NC_110 Y3
L12 NC_42 NC_111 Y6
L13 NC_43 NC_112 Y7
L14 NC_44 NC_113 Y8
M1 NC_45 NC_114 Y9
M2 NC_46 NC_115 Y10
M3 NC_47 NC_116 Y11
M5 NC_48 NC_117 Y12
M8 NC_49 NC_118 Y13
M9 RFU#3 NC_119 Y14
M10 RFU#4 NC_120 AA1
M12 RFU#2 NC_121 AA2
M13 NC_53 NC_122 AA7
M14 NC_54 NC_123 AA8
N1 NC_55 NC_124 AA9
N2 NC_56 NC_125 AA10
N3 NC_57 RFU#1 AA11
N10 NC_58 NC_127 AA12
N12 RFU#5 NC_128 AA13
N13 NC_60 NC_129 AA14
N14 NC_61 NC_130 AE1
P1 NC_62 NC_131 AE14
P2 NC_63 NC_132 AG2
P3 NC_64 NC_133 AG13
P10 NC_65 NC_134 AH4
P12 RFU#6 NC_135 AH6
P13 NC_67 NC_136 AH9
P14 NC_68 NC_137 AH11
NC_69 NC_138

EC@Hynix 32GB

eDP CONNECTOR (LDS) eDP Power (LDS)

B B
co-layout +3V
VOUT_BACKLIGHT TP_PWR CCD+DMIC_PWR

+3V R3 0_5%_4 DualDMIC_PWR

U19
+1.8V R4 *0_5%_4 C315 LCDVCC

C9 C2 C284 C283 C282 C281 1u/6.3V_4 5 1

100p/50V_4 0.1u/25V_4 0.1u/16V_4 1000p/50V_4 0.1u/16V_4 1000p/50V_4 IN#2 OUT
4 2
IN#1 GND C306 C308 C311
3 0.1u/16V_4 0.01u/50V_4 22u/6.3V_6
[4] EDP_VDD_EN EN
co-layout
G5245AT11U
R5 NVL@0_5%_6 MAX 1.5A CN3 R281 Enable: High Active /2A
42

+VIN
[6] INT_EDP_HPD#
R6 VL@0_5%_6 VOUT_BACKLIGHT 100K_5%_4 GMT:AL005245000
+12V_Panel 40 NVT:AL003522001
39
Reserve for 4K2K panel 38
3

R274 *0_5%_6
Q1 2 EDP_HPD R1 33_5%_4 EDP_HPD_R R275 *S_6 LCDVCC_R 37
LCDVCC 36
35
PJA138K R2 R276 *S_4 CCD+DMIC_PWR 34
1

+3V 33
C1
100K_5%_4 180p/50V_4 32
+5V R277 *S_4 TP_PWR
DualDMIC_PWR
31
30
29
eDP Backlight (LDS)
Prevent ESD/EOS Layout near connector [21] TS_EN 28
[4] PCH_BRIGHT BL_ON 27
EDP_HPD_R 26
R278 *100K_5%_4 25
EDP_AUXP C285 0.1u/16V_4 EDP_AUXP_C 24
[4] EDP_AUXP EDP_AUXN EDP_AUXN_C 23
C286 0.1u/16V_4
[4] EDP_AUXN 22
EDP_TXP0 +3V EDP_TXP0_C 21 +3V
[4] EDP_TXP0 C287 0.1u/16V_4 R279 *100K_5%_4 +3VPCU
EDP_TXN0 C288 0.1u/16V_4 EDP_TXN0_C 20
[4] EDP_TXN0 19
EDP_TXP1 C289 0.1u/16V_4 EDP_TXP1_C 18
eDP FHD [4] EDP_TXP1 EDP_TXN1 C290 0.1u/16V_4 EDP_TXN1_C 17 R11 R7
LID# [13,21]
[4] EDP_TXN1 16

1
EDP_TXP2 EDP_TXP2_C 15 LID591#,EC intrnal PU
C291 0.1u/16V_4 10K_5%_4 10K_5%_4 D1
[4] EDP_TXP2 EDP_TXN2 EDP_TXN2_C 14
C294 0.1u/16V_4
[4] EDP_TXN2 13 BL# 1N4148WS
EDP_TXP3 C295 0.1u/16V_4 EDP_TXP3_C 12
[4] EDP_TXP3

2
EDP_TXN3 C299 0.1u/16V_4 EDP_TXN3_C 11 BL_ON
[4] EDP_TXN3 10 PCH_BLON_R
R10 *S_4
9 [4] PCH_BLON
A A
[3] USBP6+ 8
3

R9 *S_4
CCD-USB [3] USBP6- 7 [21] PCH_BLON_EC
R8
6
3

2
[3] USBP5+ 5 EC_FPBACK# [21]
Touch Panel-USB [3] USBP5- 100K_5%_4
4 5 2 Q2
3 DDTC144EUA-7-F
[14] DMIC_DAT
1

R280 *S_4 DMIC_CLK_C 2 Q3A Q3B

[14] DMIC_CLK 1
4

1
41

196538-40041-3 2N7002KDW
2

D14 D13
*AZ5725-01F.R7G *AZ5725-01F.R7G
1

D12 D11
*AZ5725-01F.R7G *AZ5725-01F.R7G Quanta Computer Inc.
1

PROJECT : ZAJ
Size Document Number Rev
3A
eDP/ CCD/eMMC
Date: Tuesday, March 21, 2017 Sheet 12 of 34
5 4 3 2 1
 5 4 3 2 1

HDMI (HDM)

HDMI_EQ1 R118 *10K_5%_4

+3V

HDMI_EQ0 R119 *10K_5%_4

+3V
13
R109 *0_5%_4 R111 *0_5%_4

+3V

D D
HDMI_HPD_ROUT
DDCDATA_ROUT
DDCCLK_ROUT
+3V
+3V
C105
*0.1u/16V_4 C109
*0.1u/16V_4
C131 C129 C127 C126 C128 C137 C130
*0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4

20

22
CN6

24
23
22
21
20
19
18
17
U6 INT_HDMITX2P_C 1 D2+
2

NC#3
NC#2

VDD#2
DDC_EN

OE_N
HPD_SINK
SDA_SINK
SCL_SINK
D2_shield
INT_HDMITX2N_C 3
D2-
INT_HDMITX1P_C 4
D1+
5
D1_shield
INT_HDMITX1N_C 6
D1-
INT_HDMITX0P C124 *0.1u/16V_4 INT_HDMITX0P_C_RIN 25 16 INT_HDMITX0P_C_ROUT R142 *0_5%_4 INT_HDMITX0P_C INT_HDMITX0P_C 7
IN_D1- OUT_D1- D0+
INT_HDMITX0N C122 *0.1u/16V_4 INT_HDMITX0N_C_RIN 26 15 INT_HDMITX0N_C_ROUT R140 *0_5%_4 INT_HDMITX0N_C 8
INT_HDMITX1P C118 *0.1u/16V_4 INT_HDMITX1P_C_RIN 27 IN_D1+ OUT_D1+ 14 INT_HDMITX1P_C_ROUT R137 *0_5%_4 INT_HDMITX1P_C INT_HDMITX0N_C 9
D0_shield

INT_HDMITX1N C116 *0.1u/16V_4 INT_HDMITX1N_C_RIN 28 IN_D2- OUT_D2- 13 INT_HDMITX1N_C_ROUT R135 *0_5%_4 INT_HDMITX1N_C INT_HDMICLK+_C 10
D0-

INT_HDMITX2P C114 *0.1u/16V_4 INT_HDMITX2P_C_RIN 29 IN_D2+ OUT_D2+ 12 INT_HDMITX2P_C_ROUT R132 *0_5%_4 INT_HDMITX2P_C 11
CLK+
IN_D3- OUT_D3- CLK_shield
INT_HDMITX2N C112 *0.1u/16V_4 INT_HDMITX2N_C_RIN 30 11 INT_HDMITX2N_C_ROUT R130 *0_5%_4 INT_HDMITX2N_C INT_HDMICLK-_C 12
IN_D3+ OUT_D3+ CLK-
INT_HDMICLK+ C110 *0.1u/16V_4 INT_HDMICLK+_C_RIN 31 10 INT_HDMICLK+_C_ROUT R125 *0_5%_4 INT_HDMICLK+_C 13
INT_HDMICLK- INT_HDMICLK-_C_RIN IN_D4- OUT_D4- INT_HDMICLK-_C_ROUT INT_HDMICLK-_C +5V CEC

HPD_SOURCE
SDA_SOURCE
C107 *0.1u/16V_4 32 9 R123 *0_5%_4 14

SCL_SOURCE
IN_D4+ OUT_D4+ HDMI_DDCCLK 15
NC
DDC CLK
33 37 U5 HDMI_DDCDATA 16
GND#1 GND#5 36 17
DDC DATA

VDD#1
GND#4 35 GND

REXT
1 HDMI_5V 18

NC#1
EQ1

EQ0
GND#3 34 OUT HDMI_HPD 19
+5V
C GND#2 3
HP DET C

*PTN3366BS IN C353 D30 HMRBL-AK120C

1
2
3
4
5
6
7
8
2 *220p/50V_4

21

23
+3V GND *VARISTOR

co-layout co-layout G5250Q1T73U

HDMI_HPD_RIN
DDCDATA_RIN
DDCCLK_RIN
*12.4K_1%_4
HDMI_EQ1
GMT:AL005250003

HDMI_EQ0
BCD:AL002802002
C106 ESD7
*0.1u/16V_4 INT_HDMITX0P_C 1 10 INT_HDMITX0P_C
Line-1 NC#4
INT_HDMITX0N_C 2 9 INT_HDMITX0N_C

R117
Line-2 NC#3
3
GND#1
INT_HDMITX1P_C 4 7 INT_HDMITX1P_C
INT_HDMITX0P C125 0.1u/16V_4 INT_HDMITX0P_NOR R410 *S_4 INT_HDMITX0P_C Line-3 NC#2
[4] INT_HDMITX0P INT_HDMITX0N INT_HDMITX0N_NOR INT_HDMITX0N_C INT_HDMITX1N_C INT_HDMITX1N_C
C123 0.1u/16V_4 R409 *S_4 5 6
[4] INT_HDMITX0N Line-4 NC#1
INT_HDMITX1P C119 0.1u/16V_4 INT_HDMITX1P_NOR R408 *S_4 INT_HDMITX1P_C *AZ1045-04F.R7G
[4] INT_HDMITX1P INT_HDMITX1N INT_HDMITX1N_NOR INT_HDMITX1N_C
C117 0.1u/16V_4 R407 *S_4
[4] INT_HDMITX1N
INT_HDMITX2P C115 0.1u/16V_4 INT_HDMITX2P_NOR R406 *S_4 INT_HDMITX2P_C
[4] INT_HDMITX2P INT_HDMITX2N INT_HDMITX2N_NOR INT_HDMITX2N_C ESD6
C113 0.1u/16V_4 R405 *S_4
[4] INT_HDMITX2N INT_HDMITX2P_C 1 10 INT_HDMITX2P_C
INT_HDMICLK+ C111 0.1u/16V_4 INT_HDMICLK+_NOR R404 *S_4 INT_HDMICLK+_C Line-1 NC#4
[4] INT_HDMICLK+ INT_HDMICLK- INT_HDMICLK-_NOR INT_HDMICLK-_C INT_HDMITX2N_C INT_HDMITX2N_C
C108 0.1u/16V_4 R403 *S_4 2 9
[4] INT_HDMICLK- HDMI_HPD_RIN Line-2 NC#3
3
GND#1
INT_HDMICLK+_C 4 7 INT_HDMICLK+_C
Q12 Line-3 NC#2

2
B B
R122 R126 R129 R133 R134 R138 R139 R143 INT_HDMICLK-_C 5 6 INT_HDMICLK-_C
R100 *0_5%_4 HDMI_HPD_RIN_Q 3 1 Line-4 NC#1
470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4 470_1%_4 *AZ1045-04F.R7G
*PJA138K

R99 *S_4 HDMI_HPD_NOR

[4] INT_HDMI_HPD#
3

2
co-layout HDMI_HPD_ROUT

3
+3V R401 *0_5%_4
Q13 Q9 2 HDMI_HPD_NOR-1 R402 *S_4 HDMI_HPD
2N7002K
1

PJA138K co-layout EMI

1
+1.8V R400 D29

+1.8V HDMI_5V 100K_5%_4 *VARISTOR

R103 R110
5

*2.2K_5%_4 2.2K_5%_4
R120 *0_5%_4 DDCCLK_RIN DDCCLK_ROUT R107 *0_5%_4
Hall Sensor (HSR) [4] HDMI_DDCCLK_SW
R104 *S_4 DDCCLK_NOR 4 3 DDCCLK_NOR-1 R108 *S_4 HDMI_DDCCLK

1st:AL008251000 -- YBT Q10A

+3VPCU R112 R116
2nd:AL008132004 -- ANC co-layout co-layout
2

*2.2K_5%_4 Q10B 2.2K_5%_4

R121 *0_5%_4 DDCDATA_RIN DDCDATA_ROUT R114 *0_5%_4
R151 R113 *S_4 DDCDATA_NOR 1 6 DDCDATA_NOR-1 R115 *S_4 HDMI_DDCDATA
A [4] HDMI_DDCDATA_SW A

2.2_5%_6 SSM6N43FU

2
D4 D5
LID# [12,21]
*AZ5725-01F.R7G *AZ5725-01F.R7G

1
2

Q14
S VCC

OUTPUT

Quanta Computer Inc.

GND
N

C138
4.7u/6.3V_4 YB8251ST23 PROJECT : ZAJ
3

Size Document Number Rev

3A
HDMI/Hall sensor
Date: Tuesday, March 21, 2017 Sheet 13 of 34
5 4 3 2 1
 5 4 3 2 1

Codec(ADO)
HP-R2

HP-L2
14
LINE1-VREFO-L

LINE1-VREFO-R

MIC2-VREFO

CODEC_VREF C249 2.2u/10V_4 ADOGND

INT_AMIC-VREFO C255 10u/6.3V_4
D +5VA D

C228

C231

C237
R251 100K_5%_4

10u/6.3V_4

2.2u/10V_4

2.2u/10V_4
C259 C428
0.1u/16V_4 10u/6.3V_4

+AZA_VDD
Place next to pin 26

36

35

34

33

32

31

30

29

28

27

26

25
+1.5VA
U15
ADOGND

CPVEE

HP-OUT-L

LINE1-VREFO-L

MIC2-VREFO

LDO1-CAP

AVDD1

AVSS1
CPVDD

CBN

HP-OUT-R

LINE1-VREFO-R

VREF
C401 C220
10u/6.3V_4 0.1u/16V_4
ADOGND 37 24
CBP LINE2-L
38 23
ADOGND AVSS2 LINE2-R
Place next to pin 40 C223 10u/6.3V_4 39 22 LINE1-L
LDO2-CAP LINE1-L
Analog 40 21 LINE1-R
L9 AVDD2 LINE1-R
Digital 1 2 +5V_PVDD 41 20
+5V PVDD1 VD33 STB +3VPCU
PBY160808T-600Y-N
L_SPK+ 42 19 C443 10u/6.3V_4
SPK-L+ MIC-CAP ADOGND
C412 C213 L_SPK- 43 18 SLEEVE
SPK-L- MIC2-R/SLEEVE trace width of SLEEVE & RING2
10u/6.3V_4 0.1u/16V_4
R_SPK- 44 17 RING2 are required at least 40mil and
SPK-R- MIC2-L/RING2 its length should be asshort as possible
R_SPK+ 45 16
Low is power down SPK-R+ MONO-OUT
amplifier output 46 15
PVDD2 SPDIFO/FRONT JD/GPIO3
GPIO0/DMIC-DATA

PD# 47 14 Placement near Audio Codec

GPIO1/DMIC-CLK

C
PDB MIC2/LIN2 JD C
C411 C214 48 13 SENSEA R257 200K_1%_4
TP19 SPDIF-OUT SDATA-OUT HP/LINE1 JD HP_JD# [19]

LDO3-CAP
10u/6.3V_4 0.1u/16V_4

SDATA-IN

DVDD-IO

PCBEEP
RESETB
DC DET

R256 100K_1%_4 +3V

DVDD

SYNC
49 BCLK
DGND
Analog
Digital
1

10

11

12
ALC255-CG
10u/6.3V_4

1.6Vrms
R238 *S_4 +AZA_VDD
+3V
PCBEEP C264 0.1u/16V_4 BEEP_1 R255 20K_1%_4 1 2
[5]
SPKR
DMIC_DAT_R

DMIC_CLK_R

D25 1N4148WS
C250

R262 1 2
PCBEEP_EC [21]
C229 C230 C268 D23 1N4148WS
0.1u/16V_4 10u/6.3V_4 100p/50V_4 10K_5%_4

+1.5V

[12] DMIC_DAT
DMIC_DAT R240 *S_4
AZ_CODEC_RST#

AZ_CODEC_SYNC [5]
[6]
Universal Audio Jack HEADPHONE/MIC/LINE combo (ADO)
Tied at one point only under DMIC_CLK R243 22_5%_4 DVDD_IO
[12] DMIC_CLK
the codec or near the codec MIC2-VREFO R478 2.2K_5%_4

R479 *S_4 AZ_SDIN0_R R249 33_5%_4 R477 2.2K_5%_4

AZ_CODEC_SDIN0 [5]
R473 *S_4 C241 C257 C261 D10 1 2 *AZ5725-01F.R7G
R460 *S_4 10p/50V_4 0.1u/16V_4 10u/6.3V_4 SLEEVE
AZ_CODEC_BITCLK [5] SLEEVE [19]
R227 *S_4 D9 1 2 *AZ5725-01F.R7G
R239 *S_4 C247 *22p/50V_4 RING2
RING2 [19]
R235 *S_4
C436 *1000p/50V_4 Place next to pin 9 HP-L2 R466 62_1%_4 HP-L3

C260 *0.1u/16V_4
Close to Codec AZ_CODEC_SDOUT [5]
HP-R2 R244 62_1%_4 HP-R3
HP-L3 [19]

HP-R3 [19]
B B

ADOGND

Cap need near AVDD1 and AVDD2 LINE1-L C423 4.7u/6.3V_4

power source input C442 C441 C417 C243
LINE1-VREFO-L R465 4.7K_5%_4 100p/50V_4 100p/50V_4 100p/50V_4 100p/50V_4

LINE1-VREFO-R R476 4.7K_5%_4

LINE1-R C444 4.7u/6.3V_4 ADOGND

Codec PWR 5V(ADO) Mute(ADO)

+AZA_VDD +1.5V

R232

1K_1%_4
2

D21 Q32
PD# 2 1 3 1 AZ_CODEC_RST#
DIGITAL ANALOG
+5V +5VA R228 *PJA138K

1
L11
2 *10K_5%_4
C219
*1u/6.3V_4
*RB500V-40
Codec PWR 1.5V(ADO)
D22
PBY160808T-600Y-N 2 1
AMP_MUTE# [21]

40mil RB500V-40 +1.5VA

DIGITAL ANALOG
A A

Internal Speaker +1.5V

2
L8
1

PBY160808T-600Y-N
40mil for each signal CN19 C397
5

1u/6.3V_4
R_SPK+
R_SPK- 1
L_SPK- 2
L_SPK+ 3
4
Quanta Computer Inc.
6

C435 C434 C432 C433 50278-00401-V01

1000p/50V_4 1000p/50V_4 1000p/50V_4 1000p/50V_4
PROJECT : ZAJ
Size Document Number Rev
3A
Audio Codec/HP/SPK/AMIC
Date: Tuesday, March 21, 2017 Sheet 14 of 34
5 4 3 2 1
 5 4 3 2 1

LAN & Card reader Combo (LAN)

C180 10p/50V_4 LAN_XTALI

Card Reader (CRD)
15

2
1
Y2 SP8=SD_CD#
25MHZ/30ppm
SP1=SD_D1 C232 *10p/50V_4

4
3
SP2=SD_D0=MS_D1 C238 *10p/50V_4
C179 10p/50V_4 LAN_XTAL2
D PCIE_LAN_WAKE#_R SP4=SD_CMD=MS_D2 C445 *10p/50V_4 D

SP5=SD_D3=MS_D3 C446 *10p/50V_4

TP40

TP11
TP13
VDD10 TP12 SP6=SD_D2=MS_CLK C447 *10p/50V_4

14

13

15
TP14
R173 2.49K_1%_4 RSET CN2

GND#2
10 mils

Hole#2

Hole#1
LANVCC
VCC_XD

48
47
46
45
44
43
42
41
40
39
38
37
U13

LED1/GPO
RSET

LED_CR
AVDD33

AVDD10
CKXTAL2
CKXTAL1
MS_CD#
SD_CD#
LED0

LED3
LANWAKEB
49 SP5=SD_D3=MS_D3 1
E_PAD CD/DAT3
SP4=SD_CMD=MS_D2 2
CMD
+3V C262 C263 3
4.7u/6.3V_4 0.1u/16V_4 VSS
VCC_XD 4
MDI_0+ 1 36 VDD
MDIP0 REGOUT REGOUT
MDI_0- 2 35 R224 SP3=SD_CLK=MS_D0 R247 *S_4 SD_CLK_R 5
MDIN0 VDDREG LANVCC
VDD10 3 34 ENSWREG reserve for EMI CLK
MDI_1+ 4 AVDD10#1 ENSWREG_H 33 1K_1%_4 6
VDD10
MDI_1-
MDI_2+
5
6
MDIP1
MDIN1
DVDD10
DVDD33
32
31 ISOLATEB
LANVCC
SP2=SD_D0=MS_D1 7
VSS#2
TAI - SOL
MDI_2- 7 MDIP2 ISOLATEB 30 DAT0
MDIN2 PERSTB PLTRST# [6,12,16,17,21]
8 29 CLK_LAN_REQ# SP1=SD_D1 8
VDD10 AVDD10#2 CLKREQB
MDI_3+ 9 28 SP7=SD_WP=MS_BS C212 1000p/50V_4 R225 DAT1
MDI_3- 10 MDIP3 SD_WP/MS_BS 27 VDD33/18 SP6=SD_D2=MS_CLK 9
11 MDIN3 VDD33/18 26 PCIE_RX2-_LAN_C C225 0.1u/16V_4 15K_1%_4 DAT2
LANVCC AVDD33#1 HSON PCIE_RX2-_LAN [3]
R234 *S_6 +3V_CR 12 25 PCIE_RX2+_LAN_C C224 0.1u/16V_4 SP8=SD_CD# 10
+3V DVDD33_CR HSOP PCIE_RX2+_LAN [3]
CD
SP7=SD_WP=MS_BS 11

SD_CMD/MS_D2
SD_CLK/MS_D0

SD_D2/MS_CLK
C C
WP
SD_D0/MS_D1

SD_D3/MS_D3

REFCLK_N
CARD_3V3

REFCLK_P
EMI
EVDD10
SD_D1

HSIN
HSIP

GND#1
SP3=SD_CLK=MS_D0
RTL8411B-CG
13
14
15
16
17
18
19
20
21
22
23
24
C246 156-1001902602

12
VCC_XD
10p/50V_4
C448 0.1u/16V_4

SP1=SD_D1
SP2=SD_D0=MS_D1
SP3=SD_CLK=MS_D0 CLK_PCIE_LANN [3]
SP4=SD_CMD=MS_D2 CLK_PCIE_LANP [3]
SP5=SD_D3=MS_D3 PCIE_TX2-_LAN [3]
SP6=SD_D2=MS_CLK PCIE_TX2+_LAN [3]
VDD10

WAKE#/REQ# circuit(LAN) Tramsformer

B B
+1.8V_S5 LANVCC LANVCC
10 mils
60 mils Layout:All termination

25
signal should have 30 10

9
VDD33/18 U20
mil trace CN4

GND
R168 C215 C176 C202 C200 C186 1 24 LAN_MCT0
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 4.7u/6.3V_4 0.1u/16V_4 C226 C227 MDI_0+ 2 TCT1 NC #4 23 LAN_MX0+
TD1+ MX1+
5

Q15A 10K_5%_4 *4.7u/6.3V_4 0.1u/16V_4 MDI_0- 3 22 LAN_MX0- LAN_MX0+ 1

4 TD1- MX1- 21 LAN_MCT1 LAN_MX0- 2
4 3 PCIE_LAN_WAKE#_R MDI_1+ 5 TCT2 NC #3 20 LAN_MX1+ LAN_MX1+ 3
[3] PCIE_LAN_WAKE# MDI_1- TD2+ MX2+ LAN_MX1- LAN_MX2+
For RTL8411B 6 19 4
7 TD2- MX2- 18 LAN_MCT2 LAN_MX2- 5
Place 0.1uF,CAP close to each VDD33 pin -- 11,32,48 Closed to Pin35 Place close to pin 27 TCT3 NC #2
R226 MDI_2+ 8 17 LAN_MX2+ LAN_MX1- 6
MDI_2- 9 TD3+ MX3+ 16 LAN_MX2- LAN_MX3+ 7
TD3- MX3-
2

Q15B 10K_5%_4 10 15 LAN_MCT3 LAN_MX3- 8

MDI_3+ 11 TCT4 NC #1 14 LAN_MX3+
1 6 CLK_LAN_REQ# MDI_3- 12 TD4+ MX4+ 13 LAN_MX3-
[3] CLK_PCIE_LAN_REQ# TD4- MX4-

EJ@75_1%_8

EJ@75_1%_8

EJ@75_1%_8

EJ@75_1%_8
JMP1H01-R3401-7H
SSM6N43FU RTL8411B (LDO mode) close to each VDD10 pin-- 3, 8, 33, 46 Close to Pin20

11

12
NS892407
REGOUT C10
VDD10 0.01u/50V_4
40 mils (Iout=1A) 40 mils (Iout=1A)
R174 *S_6 TF height limit = 4mm
EJ series Vender Descripiton

R12

R13

R14

R15
C178 C210 C189 C177 C386 C403 C407
DB0LL1LAN00 FCE TRANSFORMER LL1 LAN 24P(NS892407)
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 1u/6.3V_4 0.1u/16V_4
DB0X81LAN01 PSK TRANSFORMER X81 GIGA LAN (A-8300G)

TERM9
DB0Z06LAN00 BOT TRANSFORMER Z06 LAN 24P(GST5009B LF)

A A
TF height limit = 2.4mm
Descripiton C307
Cloudbook Vender EJ@1000p/3KV_1808
LANVCC 60 mils +3V_S5
DB0Z8PLAN00 PSK TRANSFORMER Z8P LAN (A-8300G-SLIM)
R209 *S_6

C188 C203 C204 C187

10u/6.3V_4 0.1u/16V_4 *0.1u/16V_4 *0.1u/16V_4 Quanta Computer Inc.
PROJECT : ZAJ
Size Document Number Rev
3A
LAN/CRD COMBO - RTL8411B
Date: Tuesday, March 21, 2017 Sheet 15 of 34
5 4 3 2 1
 5 4 3 2 1

2.5" SATA HDD (HDD) USB ODD Bridge (ODD)

16

20
CN12
25
co-layout CN16
23

18
21
R252 CB@0_5%_8 17
1 SATA_DEVSLP0 [5] +3V
16
2 HDD+M2_PWR 60mil R260 EJ@0_5%_8 15 +5V_ODD 60mil R461 *S_8
3 +5V +5V
14
4 13
5 C409 C244 C239 C235 C248 C399 12 C439 C430 C438 C429 C418
6 0.01u/50V_4 0.01u/50V_4 0.1u/16V_4 0.1u/16V_4 10u/6.3V_4 *100u/6.3V_12 11 [email protected]/50V_4 [email protected]/50V_4 [email protected]/16V_4 ODD@10u/6.3V_4 *ODD@100u/6.3V_12
7 10
D 8 9 D
9 8
10 7
11 R242 w/o GS@0_5%_4 6 ODD_RXP_C C424 [email protected]/50V_4 ODD_RXP
12 5 ODD_RXN_C C427 [email protected]/50V_4 ODD_RXN
13 ACCEL_INT2 [18]
4
14 SATA_RXP0_CN C199 [email protected]/50V_4 SATA_RXP0_RD 3 ODD_TXN_C C431 [email protected]/50V_4 ODD_TXN
15 SATA_RXN0_CN C191 [email protected]/50V_4 SATA_RXN0_RD 2 ODD_TXP_C C437 [email protected]/50V_4 ODD_TXP
16 1
17 SATA_TXN0_CN C184 [email protected]/50V_4 SATA_TXN0_RD
18 SATA_TXP0_CN C181 [email protected]/50V_4 SATA_TXP0_RD
19 ODD@18 pin conn
20 +3V_ASM

19
Close to ASM1153
26 24
22

R241
VCC1.2O
GS12201-1011-7H co-layout Internal 1.2V voltage (Switching) *S_4
>40mil R472

TP41
TP42
1 2
+1.2V_ASM
CN11 L10 [email protected]_3.2x2.5x1.55

+1.2V_ASM
ODD@100K_5%_4
12

PGND
C426 ODD@1u/6.3V_4
10 SATA_TXP0_M2 R175 CB@0_5%_4 SATA_TXP0_RD C421
9 SATA_TXN0_M2 R203 CB@0_5%_4 SATA_TXN0_RD ODD@10u/6.3V_4 R470 [email protected]_5%_4
8 PGND
7 SATA_RXN0_M2 SATA_RXN0_RD +3V_ASM
6
C192 [email protected]/50V_4 Close to ASM1153
SATA_RXP0_M2 C198 [email protected]/50V_4 SATA_RXP0_RD

49
48
47
46
45
44
43
42
41
40
39
38
37
5 U32
4 SATA_DEVSLP0 C391 [email protected]/16V_4

VDD#3

GPIO1
GPIO0

UART_TX
UART_RX
VCC#2
RST#
GPIO6
EPAD
LXI
PGND

HDDPC

TEST_EN
3 C419 [email protected]/16V_4
2 HDD+M2_PWR
1 C389 [email protected]/16V_4
C398 [email protected]/16V_4 PGND C413 [email protected]/6.3V_4
C414 [email protected]/16V_4
11

CB@132F10-000000-A2-R +3V_ASM 1 36 +1.2V_ASM

SPI_DI 2 VCCIN VDD#2 35 R471 [email protected]_5%_4
+1.2V_ASM SPI_CLK 3 I2C_DATA GPIO7 34 +3V_ASM
+601_VCC +3V_ASM 4 I2C_CLK VCCS 33 ODD_TXP
C388 [email protected]/16V_4 SPI_DO 5 VCC#1 STXP 32 ODD_TXN
C406 [email protected]/16V_4 SPI_CS0 6 GPIO5 STXN 31
+3V +601_VCC +1.2V_ASM 7 GPIO4 GNDA#2 30 ODD_RXN
C Close to pin10/20 of IC R172 4.7K_5%_4 EQ2 R171 *4.7K_5%_4 C404 [email protected]/16V_4
VDD#1 SRXN
C
R169 *4.7K_5%_4 EQ1 R170 *4.7K_5%_4 C422 [email protected]/16V_4 R458 [email protected]_5%_4 8 29 ODD_RXP
R444 4.7K_5%_4 DEW1 R447 *4.7K_5%_4 C387 [email protected]/16V_4 9 GPIO3 SRXP 28 +1.2V_ASM
R416 *S_4 C392 [email protected]/16V_4 R456 [email protected]_5%_4 10 GPIO2 VDDS 27 +3V_ASM
11 VBUS VCCTXL 26 ASM_XOUT
+5V_ODD +3V_ASM VBUS_LDO XO ASM_XIN
R220 *4.7K_5%_4 DE1 R452 *4.7K_5%_4 12 25
C381 C383 C382 C211 C182 R219 *4.7K_5%_4 DE2 R453 *4.7K_5%_4 VCCO XI +3V_ASM
10u/6.3V_4 1u/6.3V_4 1u/6.3V_4 0.1u/16V_4 0.1u/16V_4 R217 4.7K_5%_4 DEW2 R218 *4.7K_5%_4
U31

GNDA#1
VDDU#1
VCCU#1

VCCU#2

VDDU#2
C405 C390
SPI_CS0

URXN
URXP
UTXN
1 8

UTXP
REXT
[email protected]/10V_4 ODD@1u/6.3V_4

UDM
UDP
R216 *4.7K_5%_4 EN R451 4.7K_5%_4 SPI_CLK 6 CS VCC
SPI_DO 5 CLK
SPI_DI 2 DI 7
DEW1

ODD@ASM1153 C385

13
14
15
16
17
18
19
20
21
22
23
24
DO HOLD
EQ2

EQ1

[email protected]/16V_4
EQ2 DE1 3 4
H - 14dB H - -2dB +3V_ASM +3V_ASM WP GND
+601_VCC X - 0dB X - -4dB ASM_XIN ODD@W25X10CLSNIG
L - 7dB L - 0dB

+1.2V_ASM
2
1
C400
20
19
18
17
16

U12 Y4 [email protected]/16V_4
EQ1 DE2 C395 R449
VCC#2
EQ2
GND#3
EQ1
DEW1

21 H - 14dB H - -2dB ODD@25MHZ/30ppm ODD@10p/50V_4

C183 0.01u/50V_4 SATA_TXP0_C 1 PPAD X - 0dB X - -4dB [email protected]_1%_4
[3] SATA_TXP0

4
3
C185 0.01u/50V_4 SATA_TXN0_C 2 RX1P 15 SATA_TXP0_RD L - 7dB L - 0dB
[3] SATA_TXN0 RX1N TX1P
3 14 SATA_TXN0_RD ASM_XOUT
SATA_RXN0_C GND#1 TX1N

[3] USBP7-
[3] USBP7+
C193 0.01u/50V_4 4 13
[3] SATA_RXN0 SATA_RXP0_C 5 TX2N GND#2 12 SATA_RXN0_RD DEW2
C197 0.01u/50V_4
[3] SATA_RXP0 TX2P RX2N 11 SATA_RXP0_RD H - Long Duration
DEW2 6 RX2P X - NC (Long)
EN 7 DEW2 22 L - Short Duration
DE2 8 EN GND#4 23
DE1 9 DE2 GND#5 24
10 DE1 GND#6 25 DEW1 SW7 - EN
+601_VCC VCC#1 GND#7 H - Long Duration H - Enabled
26
GND#8 X - NC (Long)
L - Short Duration
L - Standby Mode
M.2 PCPIE & SATA SSD (NGF)
SN75LVCP601RTJR

B B

+3V +3V_M2
TPM NPCT650 (TPM) 20mil
R393 *S_4 C339 10u/6.3V_4
C337 0.1u/16V_4
C338 0.1u/16V_4 +1.8V_S5 +3V_M2
R236 *S_4 +3V_S5 C345 0.1u/16V_4
C346 0.1u/16V_4
U4
C217 TPM@10u/6.3V_4 CN5 1 6

76

78
C234 [email protected]/16V_4 C190 TPM@10u/6.3V_4 VCCA VCCB
C201 [email protected]/16V_4 C196 [email protected]/16V_4 1 2
C222 [email protected]/16V_4 3 4 2 5 R93 PSD@10K_5%_4
5 6 GND EO +1.8V_S5
7 8
9 10 TP35 3 4 CLKREQ_SSD#
22
14

11 12 [3] CLK_PCIE_SSD_REQ# A B
8

U14
13 14 PSD@NTS0101GW
VHIO#2
VHIO#1
VDD1

VSB

15 16
17
19
18
20
S5 S0
LPC_LAD3 15 4 TPM_PP 21 22 +3V_M2
[5,17,21] LPC_LAD3 LPC_LAD2 LAD3 PP TP16 23 24
18 3
[5,17,21] LPC_LAD2 LPC_LAD1 LAD2/SPI_IRQ GPX/GPIO2 25 26
21 30
[5,17,21] LPC_LAD1 LPC_LAD0 LAD1/MOSI GPIO1/SCL PCIE_RX1-_SSD_R 27 28
24 R351 PSD@0_5%_4
[5,17,21] LPC_LAD0 LPC_LFRAME# LAD0/MISO [3] PCIE_RX1-_SSD PCIE_RX1+_SSD_R 29 30
20 29 R333 PSD@0_5%_4 R70 *10K_5%_4
[5,17,21] LPC_LFRAME# SOC_SERIRQ LFRAME/SCS SDA/GPIO0 TPM_BADD [3] PCIE_RX1+_SSD 31 32
27 6 R221 *10K_5%_4
[5] SOC_SERIRQ PCLK_TPM SERIRQ GPIO3/BADD PCIE_TX1-_SSD_C 33 34
19 5 [3] PCIE_TX1-_SSD C314 [email protected]/50V_4 R490 R484
[5] PCLK_TPM LCLK/SCLK TEST PCIE_TX1+_SSD_C 35 36
[3] PCIE_TX1+_SSD C312 [email protected]/50V_4 SATA_DEVSLP1 [5]
13 2 37 38 *PSD@10K_5%_4 *PSD@10K_5%_4
[5,21] CLKRUN# CLKRUN/GPIO04/SINT NC1 SATA_RXP1_R 39 40
17 7 R361 SSD@0_5%_4
[6,12,15,16,17,21] PLTRST# LRESET/SPI_RST/SRESET NC2 [3] SATA_RXP1 SATA_RXN1_R 41 42 CLK_PCIE_SSD_REQ#
28 10 R362 SSD@0_5%_4
LPCPD NC3 11 [3] SATA_RXN1 43 44
NC4 45 46

3
26 12 C325 [email protected]/50V_4 SATA_TXN1_C
NC7 Reserved [3] SATA_TXN1 47 48
31 25 C326 [email protected]/50V_4 SATA_TXP1_C
NC8 NC6 [3] SATA_TXP1 49 50 PLTRST# [6,12,15,16,17,21]
CLKREQ_SSD# CLKREQ_SSD#
GND1
GND2
GND3
GND4

2 5
EPAD

A BADD SELECTION A
0 EEh - EFh R358 PSD@0_5%_4 51 52
[3] PCIE_RX0-_SSD [3] CLK_PCIE_SSDN 53 54
1 7Eh - 7Fh R359 PSD@0_5%_4
[3] PCIE_RX0+_SSD [3] CLK_PCIE_SSDP 55 56 TP34
TPM@NPCT650ABBYX Q36B Q36A
33

9
16
23
32

4
57 58 TP33
[3] PCIE_TX0-_SSD C323 [email protected]/50V_4
3/4 EMI request add 33p near TPM IC '1' - pin is left open. [3] PCIE_TX0+_SSD C324 [email protected]/50V_4 *PSD@SSM6N43FU
'0' - pin is pulled down.
co-layout +3V_M2
CLKRUN#
C233 TPM@33p/50V_4 67 68
[5] NGFF_SATA_DET# 69 70
71 72
R47 73
75
74 Quanta Computer Inc.
77

79

*0_5%_4 NASM0-S6701-TS40
PROJECT : ZAJ
Size Document Number Rev
3A
HDD/ODD/TPM NPCT650/Hole
Date: Tuesday, March 21, 2017 Sheet 16 of 34
5 4 3 2 1
 5 4 3 2 1

+1.8V_S5 +WL_VDD

NGFF_M.2 WiFi & BT (NGF)

1

2
VCCA
U29

VCCB
6

5 R418 10K_5%_4 +1.8V_S5

17
GND EO
D D
+WL_VDD PCIE_CLKREQ_WLAN# 3 4 CLKREQ_WLAN#
A B

76

78
CN9 NTS0101GW

76

78
1 2 +WL_VDD
USBP4+ 3 1 2 4
[3] USBP4+ USBP4- 5 3 4 6
[3] USBP4- 7 5 6 8
9 7 8 10
11 9 10 12
13 11 12 14 R489 R483
15 13 14 16
17 15 16 18 *10K_5%_4 *10K_5%_4
19 17 18 20
21 19 20 22
23 21
23
22 [3] PCIE_CLKREQ_WLAN#
S0

3
C
32
S5 2 5 CLKREQ_WLAN# C

33 32 34
PCIE_TX3+_WLAN 35 33 34 36 Q35B Q35A
[3] PCIE_TX3+_WLAN

4
PCIE_TX3-_WLAN 37 35 36 38
[3] PCIE_TX3-_WLAN 39 37 38 40 *SSM6N43FU
PCIE_RX3+_WLAN 41 39 40 42
[3] PCIE_RX3+_WLAN PCIE_RX3-_WLAN 43 41 42 44
[3] PCIE_RX3-_WLAN 45 43 44 46 C221 180p/50V_4
CLK_PCIE_WLANP 47 45 46 48
[3] CLK_PCIE_WLANP CLK_PCIE_WLANN 47 48
49 50
[3] CLK_PCIE_WLANN 49 50
51 52
CLKREQ_WLAN# 53 51 52 54 BT_EN PLTRST# [6,12,15,16,21]
53 54 BT_EN [21]
55 56 RF_EN
55 56 RF_EN [21]
57 58
59 57 58 60
61 59 60 62
63 61 62 64
65 63 64 66 LPC_LAD0 [5,16,21]
67 65 66 68 LPC_LAD1 [5,16,21]
B
69 67 68 70 LPC_LAD2 [5,16,21] B
CLK_PCI_LPC 71 69 70 72 LPC_LAD3 [5,16,21]
[5] CLK_PCI_LPC 71 72
[5,16,21] LPC_LFRAME# R464 *DBG@0_5%_4 LPC_LFRAME#_C 73 74
+WL_VDD
75 73 74
75
77

79
APCI0076-P001A
77

79

+WL_VDD 30mil +3V

R163 *S_6

C172 C173 C174 C236 C240

A 10u/6.3V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 A

Quanta Computer Inc.

PROJECT : ZAJ
Size Document Number Rev
3A
NGFF WiFi & BT
Date: Tuesday, March 21, 2017 Sheet 17 of 34
5 4 3 2 1
 5 4 3 2 1

KEYBOARD (KBC) TOUCHPAD (TPD I2C/PS2 co-lay)

CN14
TPD->100kHz,TS=400Khz
Intel design guide suggestion
MCP PIN 10u.
Per inch 3u TS=3x5inch
18
29
+3V_S5 R263 *S_4
400kHz10~100u =2.4~0.4k. +3V_S5
MX0
1 MX1
MX0 [21] 100Khz 10~100u=9k~1k.
2 MX1 [21]
MX2 C266 C270 C269
3 MX2 [21]
MX3 0.1u/16V_4 0.22u/10V_4 0.1u/16V_4
4 MX3 [21]
MX4
5 MX4 [21]
MX5 R258 R259
D 6 MX6
MX5 [21] 10 mils CN15
D

9
7 MX6 [21]
MX7 10K_5%_4 10K_5%_4
8 MX7 [21]
MY17 +TPVDD
9 MY17 [21] 1
MY16 TPCLK
10 MY16 [21] [21] TPCLK 2
MY15 TPDATA
11 MY15 [21] [21] TPDATA 3 ESD4
MY14
12 MY14 [21] I2C4_SDA_C 4 I2C4_SDA_C I2C4_SCL_C
MY13 1 6
13 MY13 [21] 5 1 6

2
MY12 I2C4_SCL_C 2 5 +TPVDD
14 MY12 [21] 6 TPD_INT# GND VDD TPD_EN
MY11 D28 D27 3 4
15 MY11 [21] [21] TPD_INT# 7 3 4
MY10 *AZ5725-01F.R7G *AZ5725-01F.R7G
16 MY10 [21] [21] TPD_EN 8
MY9 *TVL ST23 04 AD0
MY9 [21]

1
17 MY8

10
18 MY8 [21]
MY7 51653-0080N-001
19 MY7 [21]
MY6
20 MY5
MY6 [21] Touch PAD level shift I2C(TPD)
21 MY5 [21]
MY4
22 MY4 [21] +3V_S5
MY3
23 MY3 [21]
MY2 +3V_S5
24 MY2 [21]
MY1 +1.8V_S5
25 MY1 [21]
MY0
26 MY0 [21]
27 R267 R261
28 R253 33_5%_4
NBSWON# [21]
R268 R264 10K_5%_4 10K_5%_4
30

50584-0280N-V02

5
Q21A 2K_1%_4 2K_1%_4 TPD_INT#
[5] PCH_TPD_INT#
C258

3
180p/50V_4 4 3 I2C4_SCL_C
[5] I2C4_SCL
C Prevent ESD/EOS Layout near connector 2 5 C

2
Q21B Q20B Q20A

4
1 6 I2C4_SDA_C 2N7002KDW
[5] I2C4_SDA
SSM6N43FU

CPU Thermal sensor(THM) +3V

CPU FAN (THM)
+3V +5V
+3V +5V

20mil
C352 R222 R229
[email protected]/50V_4 R223 R230
EJ@1K_1%_4 EJ@10K_5%_4
EJ@10K_5%_4 *S_4
4 CN10

5
U23 [21] FAN1_RPM

2
+Vs Q16 +5V_FAN1
1
1 3 FAN_PWM_Q 2
2ND_MBDATA [21] FAN_PWM 3
5
[21] 2ND_MBDATA 4
SMBDATA 3 ALERT# EJ@METR3904-G
2ND_MBCLK ALERT# TP39
1
[21] 2ND_MBCLK

6
SMBCLK EJ@50278-00401-V01
C218 C216
B For EMI *EJ@220p/50V_4 *EJ@220p/50V_4
B

GND
CB@G753T11U
2

Keyboard backlight (KBL) G-sensor(ACS)

+3V +3V
U17
C280 C277 1 2
+5V +5V [email protected]/16V_4 GS@10u/6.3V_4 14 Vdd_IO NC#1 3
R231 VDD NC#2
C265 [email protected]/10V_4
R266 GS@10K_5%_4
1

KBL@10K_5%_4 ACCEL_INT1 10
[5] ACCEL_INTA RES
Q22 to CPU ACCEL_INT1 D7 1 2
GS@RB500V-40 ACCEL_INT1_R 11 15
2 1 2 ACCEL_INT2_R 9 INT1 ADC2
to SATA HDD [16] ACCEL_INT2 INT2
KBL@PJA3413 C242 D8 GS@RB500V-40
6

*GS@22p/50V_4 7
3

CN18 6 SDO/SA0 5
20mil
6

[6] CLK_SDATA
3

Q23 2 5 4 SDA/SDI/SDO GND#1 12

[6] CLK_SCLK SCL/SPC GND#2
A 2 +5V_KB 13 A
[21] KB_BL_LED 4 ADC3
Q19B Q19A +3V 8 16
KBL@DDTC144EUA-7-F 3 CS ADC1
1

C273 C279 2 GS@2N7002KDW

1

[email protected]/6.3V_4 [email protected]/50V_4 1 GS@LIS3DHTR

5

KBL@50591-00401-001
Quanta Computer Inc.
PROJECT : ZAJ
Size Document Number Rev
KB/TP/FAN/G-sensor 3A

Date: Tuesday, March 21, 2017 Sheet 18 of 34

5 4 3 2 1
 5 4 3 2 1

USB 3.0 (UB3)

19
R167 *S_4
C170 *1.6p/50V_4
L3
3 4 USB3_0_RXN_R
[3] USB3_0_RXN USB3_0_RXP_R
2 1
[3] USB3_0_RXP
C169 *1.6p/50V_4 *MCM2012B900GBE

11

12
R165 *S_4 CN8

5 Shield Shield USBPWR1

StdA_SSRX-
R161 0_5%_4 4
GND
6 ESD3
+5V_S5 L2 3
StdA_SSRX+ USB3_0_TXP_R 1
3 4 USBP0+_R 7 D+ I/O-1 10USB3_0_TXN_R
[3] USBP0+ 2 1 USBP0-_R 2 GND_Drain 2 I/O-6
[3] USBP0- D- VDD
D 8 9 D

C135
trace midth：100 mils *MCM2012B900GBE
R158 0_5%_4
USBPWR1
1
9
StdA_SSTX-
VBUS
C370
3
NC#1
GND#1
8
StdA_SSTX+ USBP0-_R NC#2
1u/6.3V_4 U7 0.1u/16V_4 4
5 3 Shield Shield I/O-2 7 USBP0+_R
IN OCB USB_OC1# [3] USB3_0_RXP_R I/O-5
R157 *S_4 2UB4008-390101F 5

GND#2
10

13
USBPWR1 I/O-3 6 USB3_0_RXN_R
L1 I/O-4
USBON# 4 1 C159 0.1u/16V_4 USB3_0_TXN_C 3 4 USB3_0_TXN_R
[21] USBON# EN GND OUT [3] USB3_0_TXN
C154 0.1u/16V_4 USB3_0_TXP_C 2 1 USB3_0_TXP_R
[3] USB3_0_TXP

11
2 G524B2T11U
*MCM2012B900GBE AZ1065-06F.R7G
C145 C144 C359 R153 *S_4 C161 C155
470p/50V_4 0.1u/16V_4 100u/6.3V_12 *1.6p/50V_4 *1.6p/50V_4
USB protection diodes for ESD.
as close as possible to USB connector pins.
Enable: Low Active /2.5A
GMT:AL000524007
EMS:AL005203001

USB 2.0 (UB2) Stitch cap (EMC)

R270 *S_4
C L6 C
2 1 USBP3+_R
+5V_S5 [3] USBP3+ USBP3-_R
3 4
[3] USBP3-
trace midth：100 mils *MCM2012B900GBE
R271 *S_4

C278 U18
1u/6.3V_4 5 3 USB_OC1#
IN OCB USBPWR2 ESD5 USBPWR2
1 6
2 1 6 5
USBON# 4 1 3 GND VDD 4
EN GND OUT 3 4
2 G524B2T11U *TVL ST23 04 AD0
C275 C274 C271
470p/50V_4 0.1u/16V_4 *100u/6.3V_12
R272 *S_4
Enable: Low Active /2.5A L7
GMT:AL000524007 2 1 USBP2+_R
[3] USBP2+
EMS:AL005203001 [3] USBP2-
3 4 USBP2-_R

*MCM2012B900GBE
R273 *S_4

B
USB 2.0/LED/AUDIO JACK DB (UB2) HOLE(OTH)
B

USBPWR2
HOLE2 HOLE12 HOLE11 HOLE8 HOLE5 HOLE15 HOLE14 HOLE13
*HG-EJ-AP-1 *HG-C354D220P2 *HG-C354D220P2 *HG-C315D165P2 *HG-Z8P-1 *HG-C354D126P2 *HG-C315D165P2 *HG-TC315BC236D95P2
CN17 7 6 7 6 7 6 7 6 7 6 7 6 7 6 7 6
35

8 5 8 5 8 5 8 5 8 5 8 5 8 5 8 5
9 4 9 4 9 4 9 4 9 4 9 4 9 4 9 4
1
2
1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3

1
2
3
3
4
5
6
7 +3VPCU
8 PWRLED# [21]
9 SUSLED# [21] HOLE1
[21] SPAD1 SPAD3 SPAD2 SPAD4 SPAD5 SPAD6 HOLE6 HOLE10
10 BATLED0# *H-C236D94P2
[21] *SPAD-C315NP *SPAD-C236NP *SPAD-C236NP *SPAD-C236NP *SPAD-C177NP *SPAD-C177NP
11 BATLED1# *O-EJ-KBL-1 *H-C122D122N
12
13 USBP3+_R
14 USBP3-_R
15
1

1
16

1
17 USBP2+_R
18 USBP2-_R
19
20
21 HOLE9 HOLE3 HOLE7 HOLE4
22 HP_JD# [14] WLAN nut CPU nut CPU nut CPU nut
23
24
25 SLEEVE [14]
26
A 27 A
RING2 [14]
1

28
29
30
31 HP-L3 [14]
32
33 HP-R3 [14]
34

Quanta Computer Inc.

36

196332-34041-3

ADOGND
PROJECT : ZAJ
Size Document Number Rev
3A
USB/CARDREADER/LED
Date: Tuesday, March 21, 2017 Sheet 19 of 34
5 4 3 2 1
 5 4 3 2 1

USB TYPE-C (UB3)

trace midth：150 mils
+5V_S5
Vendor suggest input cap 120u +TYPEC_VBUS_C
U3
C394 TPC@100u/6.3V_12
D D
C53 TPC@10u/6.3V_4 2 15 C42 TPC@10u/6.3V_4
C52 TPC@10u/6.3V_4 3 IN1#1 OUT#2 14 +3V_S5
4 IN1#2 OUT#1 C54 TPC@100p/50V_4
5 IN2 11 25810_CC1 C43 TPC@1000p/50V_4 25810_FAULT# R69 *TPC@100K_5%_4
AUX CC1 13 25810_CC2 25810_LD_DET# R80 TPC@100K_5%_4
6 CC2 EMI 25810_UFP# R79 *TPC@100K_5%_4
[21] EC_TypeC_EN EN 25810_FAULT# 25810_POL#
1 R68 *S_4 R77 TPC@100K_5%_4
TYPEC_CHG FAULT 25810_LD_DET# USB_OC0# [3] 25810_AUO#
7 20 R76 TPC@100K_5%_4
R49 *S_4 TYPEC_CHG_HI 8 CHG LD_DET 19 25810_UFP# R78 *S_4 25810_DBG# R65 TPC@100K_5%_4
[21] EC_TypeC_CHG_HI CHG_HI UFP TypeC_HPD# [4]
18 25810_POL# TYPEC_CHG R51 TPC@100K_5%_4
25810_REF 10 POL 17 25810_AUO# TYPEC_CHG_HI R50 TPC@100K_5%_4
REF AUDIO 16 25810_DBG# EC_TypeC_EN R56 TPC@10K_5%_4
25810_REF_RTN 9 DEBUG
REF_RTN
R48 TPC@100K_1%_4 12 21
GND#1 PwPd

TPC@TPS25810RVCR

C C

+TYPEC_VBUS
trace midth：150 mils +TYPEC_VBUS C343 [email protected]/25V_4
C344 [email protected]/25V_4

1
+TYPEC_VBUS_C Q7 +TYPEC_VBUS
D3 C350 TPC@100p/50V_4
3 C342 TPC@1000p/50V_4
D

5 2 [email protected]

2
1
+5V_S5 EMI
G

TPC@AON7401 R97
4

TPC@10K_5%_4
R96 25810_UFP#_G2R94 TPC@100K_5%_4
CN1
TPC@10K_5%_4
C75 Close to connector
3

[email protected]/25V_4
25810_UFP#_G1 2
Q8 C28 [email protected]/16V_4 USB3_1_TXP_CN A2
[3] USB3_1_TXP USB3_1_TXN_CN SSTXp1 +TYPEC_VBUS
B C36 [email protected]/16V_4 A3 A4 C340 [email protected]/25V_6 B
[3] USB3_1_TXN USB3_1_RXP SSTXn1 VBUS#1
3

TPC@PJA138K B11 B4 C349 [email protected]/25V_6

1

[3] USB3_1_RXP SSRXp1 VBUS#3

25810_UFP# 2 USB3_1_RXN B10 A9 C347 [email protected]/25V_6
[3] USB3_1_RXN SSRXn1 VBUS#2
Q6 B9 C341 [email protected]/25V_6
VBUS#4
TPC@PJA138K C55 [email protected]/16V_4 USB3_2_TXP_CN B2
1

[3] USB3_2_TXP USB3_2_TXN_CN SSTXp2

C51 [email protected]/16V_4 B3
[3] USB3_2_TXN USB3_2_RXP SSTXn2
[3] USB3_2_RXP A11
USB3_2_RXN A10 SSRXp2
[3] USB3_2_RXN SSRXn2 A1
GND#1 A12
GND#2 B1
USBP1+ A6 GND#3 B12
[3] USBP1+ Dp1 GND#4
[3] USBP1- USBP1- A7 1
USBP1+ B6 Dn1 GND#5 2
USBP1- B7 Dp2 GND#6 3
Dn2 GND#7 4
GND#8 5
25810_CC1 A5 NC#1 6
ESD2 25810_CC2 CC1 NC#2
B5
USB3_1_TXP_CN 1 9 USB3_1_TXN_CN CC2
USB3_1_RXN LINE-1 LINE-2 USB3_1_RXP ESD1
2 8
LINE-3 LINE-4 USBP1+ 1 6 USBP1- A8
1 6 TP4 SBU1
3 2 5 +5V_S5 B8
GND 25810_CC1 GND VDD 25810_CC2 TP3 SBU2
3 4
USB3_2_TXP_CN 4 7 USB3_2_TXN_CN 3 4
USB3_2_RXN 5 LINE-6 LINE-5 6 USB3_2_RXP TPC@TVL ST23 04 AD0
LINE-8 LINE-7
A A
[email protected]

Amazing：BC104508Z00 *TPC@AUSB0181-P101A
PJT ：BC605S8QZ00 Quanta Computer Inc.
INPAQ ：BC38109LZ00
PROJECT :ZAJ
Size Document Number Rev
3A
USB_Type C_25810
Date: Tuesday, March 21, 2017 Sheet 20 of 34
5 4 3 2 1
 5 4 3 2 1

PU/PD (KBC)
EC(KBC)
21
+3V_LDO_EC
1 2 +A3VPCU
L12 BLM15AG121SN1D +3VPCU_ECPLL 1 2
+3VPCU_EC SPIVCC_ON
L4 BLM15AG121SN1D R213 10K_5%_4
C267 (For PLL Power)
+3VPCU_EC and +3V_RTC 0.1u/16V_4 VSTBY_FSPI_R C208 NBSWON# R212 10K_5%_4
VSTBY_FSPI
ECAGND R205 2.2_5%_6 0.1u/16V_4
minimum trace width 12mils. MBCLK R206 4.7K_5%_4
12 mils MBDATA R211 4.7K_5%_4
+3VPCU_EC SB_ACDC [6,22]
R459 2.2_5%_6 VccDSW GPC6 R202 *10K_5%_4
+3V_LDO_EC BT_EN TP23
BT_EN [17]
R207 CB@10K_5%_4
C410 C209 C440 C415 C408 C205 C206 PCH_SLP_SUS#
TP25
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 MAINON R480 100K_5%_4
D/C# [22] Prevent ESD/EOS Layout near EC
SUSON R215 100K_5%_4
USBON# [19]
R214 33_5%_4
+3V_EC TPD_EN [18]
D +3V_S5 R248 2.2_5%_6 RSMRST# R210 100K_5%_4 D
EC_TypeC_CHG_HI [20]
C194 EC_PWROK R481 100K_5%_4
CLKRUN# [5,16]
C251 180p/50V_4
[5,16,17] LPC_LAD0 CLR_CMOS
0.1u/16V_4 R254 100K_5%_4
[5,16,17] LPC_LAD1

114
121

106

127
11
26
50
92

74

84
83
82

19
20

99
98
97
96
93
[5,16,17] LPC_LAD2

3
U16 S5_ON R265 10K_5%_4
[5,16,17] LPC_LAD3 10 110 MBCLK

VSTBY#1
VSTBY#2
VSTBY#3
VSTBY#4
VSTBY#5

VSTBY(PLL)

EGCLK/GPE3
EGCS#/GPE2
EGAD/GPE1

L80HLAT/BAO/GPE0
L80LLAT/GPE7

GPH7
ID6/GPH6
ID5/GPH5
ID4/GPH4
ID3/GPH3
CLKRUN#/ID0/GPH0
VCC

VSTBY_FSPI
AVCC
+3V_LDO_EC LAD0/GPM0(3) SMCLK0/GPB3 MBCLK [22]
9 111 MBDATA
LAD1/GPM1(3) SMDAT0/GPB4 2ND_MBCLK MBDATA [22]
C425 180p/50V_4 8 SM BUS 115 +3V
LAD2/GPM2(3) SMCLK1/GPC1 2ND_MBDATA 2ND_MBCLK [18]
7 116
LAD3/GPM3(3) SMDAT1/GPC2 SLP_S0IX# 2ND_MBDATA [18]
22 117
[6,12,15,16,17] PLTRST# 13 LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) 118 TP15
R204 33_5%_4
[5] CLK_PCI_EC LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) LID# [12,13] 2ND_MBCLK
6 R177 [email protected]_5%_4
[5,16,17] LPC_LFRAME# LFRAME#/GPM5(3) 2ND_MBDATA
C195 180p/50V_4 Prevent ESD/EOS Layout near EC R176 [email protected]_5%_4
PROCHOT_EC 17
LPCPD#/GPE6
1

R462 126 PS/2 D6 VARISTOR

TP17 GA20/GPB5(3)
D24 5 85
[5] IRQ_SERIRQ SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0 TP21
100K_5%_4 RB500V-40 [6] 15 LPC 86
PCH_SUSPWRDNACK ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 EC_FPBACK# [12]
23 89
[5] SIO_EXT_SCI# TPCLK [18] H_PROCHOT# [6,22,26]
2

WRST# 14 ECSCI#/GPD3 PS2CLK2/GPF4 90

WRST# GPIO PS2DAT2/GPF5 TPDATA [18]
KBRST# 4
TP20 KBRST#/GPB6(3)
16
TP24 PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
IT8987E/CX

3
C416
1u/6.3V_4 24 PROCHOT_EC 2
PWM0/GPA0 PWRLED# [19]
25 Q17
PWM1/GPA1 BATLED1# [19]
113
LQFP PWM2/GPA2
28
29
SUSLED# [19]
R233 2N7002K

1
[18] KB_BL_LED CRX0/GPC0 PWM3/GPA3 BATLED0# [19]
123 CIR 30
[6] DNBSWON# CTX0/TMA0/GPB2(3) PWM4/GPA4 MAINON [23,24,25,28,29]
31 100K_5%_4
CLK_PCI_EC PWM5/GPA5
Output for type-c Apling ridge
reset timming"Low " Active PWM
80
[20] EC_TypeC_EN DAC4/DCD0#/GPJ4(3)
119 47
[6] SUSB# DSR0#/GPG6 TACH0A/GPD6(3) FAN1_RPM [18]
R467 33 48
[6] EC_PWROK GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) TP28
88
[12] PCH_BLON_EC TS_EN_C 81 PS2DAT1/RTS0#/GPF3 120
*22_5%_4
DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) SUSON [25]
87 124 GPC6
TP22 PS2CLK1/DTR0#/GPF2 TMRI1/GPC6(3)
C 109 C
[5] ME_WR# TXD/SOUT0/GPB1
108 Pin124 is a board ID for Cloud book (PD) , EC has internal PU for EJ series
C420
*10p/50V_4
[14] AMP_MUTE#

TP26
71
RXD/SIN0/GPB0

ADC5/DCD1#/GPI5(3) PWRSW/GPE4
107 NBSWON#
NBSWON# [18]
Battery Disable (FSW)
72 UART port 18
[22] ACIN ADC6/DSR1#/GPI6(3) RI1#/GPD0(3) SUSC# [6]
73 WAKE UP 21 HWPG
[22] TEMP_MBAT# ADC7/CTS1#/GPI7(3) RI2#/GPD1
35
TP43 RTS1#/GPE5
34
[14] PCBEEP_EC 122 PWM7/RIG1#/GPA7 112
[6] THERMTRIP# AC_Protect DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 RSMRST# [6] +3V_RTC +3VPCU
95
[22] AC_Protect CTX1/SOUT1/GPH2/SMDAT3/ID2
94 C449 0.1u/16V_4 R493 10_5%_4 Prevent ESD/EOS Layout near EC
TP18 CRX1/SIN1/SMCLK3/GPH1/ID1
R250 33_5%_4 TS_EN_C PCH_SPI_CLK_EC 105 colsed to EC pin within 100 mils R269 33_5%_4 [22] BI#
[12] TS_EN SPI_CS0#_UR_ME 101 FSCK/GPG7 RF_EN [17]
FSCE#/GPG3

2
1
C256 180p/50V_4 PCH_SPI_SI_EC 102 EXTERNAL SERIAL FLASH ICMNT
PCH_SPI_SO_EC FMOSI/GPG4 ICMNT [22]
103 66 C276 6 R455 R454
FMISO/GPG5 ADC0/GPI0(3) 67 C272 10u/6.3V_4 ECAGND 180p/50V_4 SW2
Prevent ESD/EOS Layout near EC ADC1/GPI1(3)
56 68 *0_5%_4 *0_5%_4
[18] MY16 57 KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) 69
[18] MY17 KSO17/SMISO/GPC5(3) ADC3/GPI3(3) S5_ON [23,28]
32 70 5
[18] FAN_PWM PWM6/SSCK/GPA6 ADC4/GPI4(3) TP27
SPIVCC_ON 100 JTE1CQR +3V_RTC
A/D D/A

3
4
125 SSCE0#/GPG2 R457
SSCE1#/GPG0 SPI ENABLE
76
TACH2/GPJ0(3) VNN_ON [26]
36 77 *10K_5%_4
[18] MY0 KSO0/PD0 GPJ1(3) SYS_HWPG [23]
37 78 R446
[18] MY1 KSO1/PD1 DAC2/TACH0B/GPJ2(3) PANEL_LED_EN [30]
38 79 C402 *0.1u/16V_4 WRST#
[18] MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(3) CLR_CMOS [6]
39 100K_5%_4
[18] MY3 40 KSO3/PD3

3
[18] MY4 KSO4/PD4 2 BI_GATE
41 Q31
[18] MY5 KSO5/PD5
42 KBMX
[18] MY6 KSO6/PD6
43
[18] MY7 KSO7/PD7

3
4

6
44 PJA138K

1
[18] MY8 45 KSO8/ACK# 5
[18] MY9 KSO9/BUSY
46 C384 5 2
[18] MY10 KSO10/PE SYS_SHDN#_R R237
51 2 *S_4 *0.1u/16V_4
[18] MY11 KSO11/ERR# GPJ7 SYS_SHDN# [23,29]
KSI3/SLIN#
KSI1/AFD#

52 128
KSI0/STB#

KSI2/INIT#

CLOCK R208 33_5%_4 SW1 Q33A Q33B

[18] MY12 KSO12/SLCT GPJ6 TPD_INT# [18]
53 6 *SSM6N43FU
VCORE

[18] MY13

1
KSO13
VSS#1

VSS#2
VSS#3
VSS#4
VSS#5

54 TME-532W-Q-T/R
AVSS

Prevent ESD/EOS Layout near device

KSI4
KSI5
KSI6
KSI7

B [18] MY14 KSO14 B

55 C207
[18] MY15

2
1
KSO15 180p/50V_4
IT8987E/CX
SM BUS ARRANGEMENT TABLE
58
59
60
61
62
63
64
65

27
49
91
104

ECAGND 75

12

SM Bus 1 Battery
[18] MX0
[18] MX1
C252 SM Bus 2 Thermal sensor
[18] MX2
0.1u/16V_4
[18] MX3
[18] MX4
2 1 SM Bus 3
[18] MX5
L5 BLM15AG121SN1D
[18] MX6
[18] MX7
SM Bus 4

SPI ROM(KBC) Power_Auto_Recovery

VSTBY_FSPI
+3V_LDO_EC VSTBY_FSPI
HWPG(KBC) +3V

VSTBY_FSPI
15 mils 20 mils
R443
R450 *S_4 R448 *S_4
Reserve power on switch for test R445 R415
680_LDO 1.8V_LDO
10K_5%_4
(MP remove)
3.3K_5%_4 3.3K_5%_4 R417 1 2 HWPG
[28] HWPG_1.5V
C380 D20 RB500V-40
U28
3.3K_5%_4 0.1u/16V_4 1 2
SPI_CS0#_UR_ME [28] HWPG_1.8V_S5
SW3 1 8 D18 *RB500V-40
PCH_SPI_CLK_EC 6 CS VCC 680_LDO 1.8V_LDO 1 2
PCH_SPI_SI_EC CLK [25] HWPG_1.35VSUS
5 D15 *RB500V-40
NBSWON# 3 2 PCH_SPI_SO_EC 2 SI 7 SPI_HOLD# U30 1 2
4 1 DO HOLD 20 mils [24] HWPG_1.05V
20 mils D17 *RB500V-40
SPI_WP# 3 4 1 5 1 2
WP GND VIN VOUT [26] IMVP_PWRGD
D16 *RB500V-40
5

A A
*TME-532W-Q-T/R W25Q80BWSSIG 2 1 2
GND [28] HWPG_1.24V_S5
D19 *RB500V-40
SPIVCC_ON 3 4
EN NC

G9090-180T11U C393
C396 1u/6.3V_4
2.2u/10V_4
SP@ socket P/N: DFHS08FS023 only for A-TEST
SPI ROM Vender Size Quanta P/N Vender P/N Quanta Computer Inc.
WND 1M AKE5GGN0N00 W25Q80EWSSIG PROJECT : ZAJ
Size Document Number Rev
1.8V GGD 1M AKE5GZN0Q00 GD25LQ80BSIGR 3A
KBC IT8987E_CX
Date: Tuesday, March 21, 2017 Sheet 21 of 34
5 4 3 2 1
 5 4 3 2 1

Double Check ADP-IN Connector

22
with ME PQ6 VA2 PQ17
VA1 TPCA8109 PD3 PR44 TPCA8109
PJ1 SV1040 0.02_1%_0612 +VIN

D
3 1 3
4 2 5 3 2 5
3 1 2 1
2 PR45

G
D 1 D

1
*S_4
EJ@CI2504P1H02-RB-NH PC190 PR187 24737_ACN PC206 PC49 PR49

4
PC55 PD2 0.1u/50V_6 220K_1%_4 0.1u/50V_6 2200p/50V_4 33K_1%_4
0.1u/50V_6 P4SMAFJ20A
24737_ACP

2
PC37 PC38 PR46
0.1u/50V_6 2200p/50V_6 3 4 *S_4 PC213

2
PR188 PR51 *10u/25V_8
220K_1%_4 2 5 10K_5%_4
D/C# [21]
PD4
VA1 1N4148WS 1 6 PR189
PJ2 *S_4
8

1
recommend 200mA at least. PQ16
IMD2AT108
6
5

3
4 2
3 24737_ACP PQ7
2 2N7002K
1

1
24737_ACN
7

CB@50278-006T1-001
PR71
*S_6 PC46 PC50 PC45
0.1u/50V_6 0.1u/50V_6 0.1u/50V_6
PR67
63.4K_1%_4
+3VPCU

1
+VIN
PR68 PC59

ACP

ACN
11K_1%_4 1u/16V_6
C 24737_ACDET 6 24737_REGN C
100K_5%_4

100K_5%_4

16
*10K_5%_4

0.1u/25V_4
ACDET REGN
PC42

2
PR56

PR63

PR60

24737_VCC 20 PD7 PC48 PC209

VCC PR72 RB500V-40 2200p/50V_4 10u/25V_8
PR58 *S_6

1
20_5%_12 PC51 17 24737_BST PQ20
[21] ACIN BTST
0.47u/25V_6 AON7410

5
PC54 D
[6,21] SB_ACDC
0.047u/50V_6 G
PR57 18 24737_DH 4
*0_5%_4 5 HIDRV S
ACOK
6

1
2
3
PU2 19 24707_LX
2 5 PR70 BQ24737RGRR PHASE
*S_4 PR78
MBDATA 8 PL10 0.01_1%_0612
PQ9B PQ9A SDA 6.8uH_7x7x3
1

2N7002KDW 2N7002KDW 15 24737_DL 1 2 BAT-V

LODRV
PC200 MBCLK 9
0.1u/50V_6 SCL PQ21

5
+3VPCU PR76 AON7410 PR69
PR81 *S_4 14 D *4.7_5%_6
PC43 10K_5%_4 GND#1
G
*100p/50V_4 24737_BM# 11 4 PR83 PR82
BM S *S_4 *S_4
PR62 PC61

1
2
3
10K_5%_4 24737_CMPOUT 3 0.1u/25V_4
BAT-V CMPOUT 13 24737_SRP PC52 24737_SRP PC44 PC204 PC201 PC214
SRP PR202 10_5%_6 *680p/50V_6 2200p/50V_4 10u/25V_8 10u/25V_8 *10u/25V_8
B PJ5 24737_ILIM 10 24737_SRN B
10

BI# [21] ILIM PC60

PR77 *0_5%_4 PR80 0.1u/25V_4
8 316K_1%_4 24737_CMPIN 4 12 24737_SRN
7 CMPIN SRN PR203 7.5_5%_6

GND#2
GND#3
GND#4
GND#5
GND#6
6 PR73 100_1%_4 TEMP_MBAT# PC62
5 TEMP_MBAT# [21] IOUT 0.1u/25V_4
4
3 PR201 PR61 SRP／SRN
+3VPCU
7

21
22
23
24
25
2 PR79 1M_5%_4 *100K_5%_4 100K_5%_4
1
Check PU High with HW side
4-Cells Others
9

R2 +1.8V_S5
PR75 PR74
PR200 PC58 bq24707A 0／0 10／7.5
100_1%_4 100_1%_4 100K_1%_4 0.01u/50V_4
50458-00801-V02 PR50
*100K_5%_4
bq24737 10／7.5 10／7.5
3

PR54
24737_BM# 2 51K_1%_4 PR66
MBCLK [21] R1 *0_5%_4 H_PROCHOT# [6,21,26]
PQ10
1

[21] ICMNT
MBDATA [21] *2N7002K
REGN MAX voltage 6.5V

3
1

24737_CMPOUT 2
PQ8
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
PC57 PC56 PC53 2N7002K
*47p/50V_4 *47p/50V_4 100p/50V_4
1
=0.793V for 3.965A current limit
2

PR55
Pin10 ILIM=0.793V
A PD6 PD5 *S_4 Rsr = 0.01ohm A
PDZ5.6B PDZ5.6B
R1 R2
UMA-45W 51K 100K [21] AC_Protect For BATT Only

Quanta Computer Inc.

PROJECT : ZAJ
Size Document Number Rev
3A
Charger(BQ24737RGRR)
Date: Tuesday, March 21, 2017 Sheet 22 of 36
5 4 3 2 1
 5 4 3 2 1

Do Not add test pad on LDO pin

[12,22,25,26,27,29,30]
[6,12,13,14,19,21,22,24,28]
[28]
[29]
+VIN
+3VPCU
+5VPCU
VL
[12,13,14,16,18,29]
[6,19,20,25,26,27,30]
[4,5,6,12,13,14,15,16,17,18,21,24,25,26,28,29]
[5,6,7,15,16,18,20,21,28]
+5V
+5V_S5
+3V
+3V_S5 23
+3VPCU
PC85
4.7u/6.3V_4 JP1
+VIN 3.3 Volt +/- 5%
*S_3720 TDC : 5.73A
PU5
2 3VPCU_VIN PEAK : 7.64A
D IN#1 D
SYS_SHDN# PR109 10K_1%_4 17
SY8286BLDO
LDO IN#2
3 Width : 240mil

PC63
4

10u/25V_8

10u/25V_8
0.1u/25V_4

2200p/50V_4

0.1u/25V_4
IN#3 +5VPCU +5VPCU

PC64

PC69

PC65

PC68
LDO=3.3V/100mA 5
IN#4 +3VPCU
7
PR88 10K_1%_4 GND#1
+3VPCU
SYS_HWPG PR87 *S_4 SY8286BPG 9
[21] SYS_HWPG PG JP4 TDC : 5.25A TDC : 2.25A
PR3 100K_1%_4
1 SY8286BBST
PR102 PC88
SY8286BBST_S
*S_3720 PEAK : 7A PEAK : 3A
+VIN
11
EN2
BS PL3 Width : 220mil Width : 100mil
Vih=0.8V *S_6 0.1u/25V_4 2.2uH_7x7x3
PR93 6 SY8286BSW 1 2 +3VPCU_SRC PC177 PC178
499K_1%_4 PR98 LX#1 19 1u/25V_4 1u/25V_4
LX#2

7
20

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

0.1u/16V_4
*22u/6.3V_8

*22u/6.3V_8
150K_1%_4
LX#3 +5V_S5 +5V

PC107

PC123

PC112

PC122

PC121

PC102
PR17

VIN1#1

VIN1#2

VIN2#1

VIN2#2
*4.7_5%_6 Idc=8A
10 PR125
SYS_SHDN# SY8286BEN 12 NC#1 16 *S_4 13
[21,29] SYS_SHDN# EN1 NC#3 14 VOUT1#1 8
PC179 PC181 PC182 PC180
PR4 PC13 10u/6.3V_6 0.1u/16V_4 VOUT1#2 OUT2#1 9 0.1u/16V_4 10u/6.3V_6
*S_4 PC2 *680p/50V_6 OUT2#2
*0.1u/16V_4 PU13
PR173 4 AOZ1331DI 11
+5VPCU VBIAS GND#1
14 SY8286BVOUT *S_4 PC174
OUT 15
15 GND#2 PR174
C
NC#2 0.1u/16V_4 *S_4 C
13 SY8286BFB S5_ON 3 5 MAINON MAINON [21,24,25,28,29]
GND#2
GND#3
GND#4
FF [21,28] S5_ON ON1 ON2

CT1

CT2
PR99 PC84 PR172
1K_1%_4 470p/50V_4 *S_4 PC176 PC175

12

10
SY8286BRAC *0.1u/16V_4 *0.1u/16V_4
8
18
21

Freq=600KHZ
PC183 PC184
1000p/50V_4 1000p/50V_4

680_LDO
PR15 Soft-Start
*S_6
680_LDO SY8286BLDO
+3VPCU +3VPCU

[21] 680_LDO

+5VPCU
+VIN 5 Volt +/- 5% TDC : 0.28A TDC : 3.345A
LDO=5V/100mA PU11
JP7
*S_3720 TDC : 7.5A PEAK : 0.21A PEAK : 4.46A
VL SY8288CRAC
PEAK : 10A Width : 20mil Width : 140mil
2 5VPCU_VIN PC116 PC136
B IN#1 B
VL 15 3 Width : 300mil 1u/25V_4 1u/25V_4

*33u/25V_D6.3H4.5
LDO IN#2

7
4
10u/25V_8

10u/25V_8

2200p/50V_4
0.1u/25V_4

0.1u/25V_4
IN#3 +3V_S5 +3V
PC151

PC152

PC157

PC155

PC154

PC165
5 +

VIN1#1

VIN1#2

VIN2#1

VIN2#2
PC162 IN#4 +5VPCU
4.7u/6.3V_4 7
GND#1
13
SYS_HWPG SY8288CPG 9 PC111 PC115 14 VOUT1#1 8 PC135 PC139
PR157 *S_4 PG JP8 10u/6.3V_6 0.1u/16V_4 VOUT1#2 OUT2#1 9 0.1u/16V_4 10u/6.3V_6
PR169 PC164 *S_3720 OUT2#2
1 SY8288CBST SY8288CBST_S PU7
Vih=0.8V 11 BS 4 11
+VIN PL8 +5VPCU AOZ1331DI
EN2 *S_6 0.1u/25V_4 1.5uH_7x7x3 PR137 *S_4 PC120 VBIAS GND#1
PR158 6 SY8288CSW 1 2 +5VPCU_SRC 15
499K_1%_4 PR162 LX#1 19 GND#2 PR138
LX#2 20

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

0.1u/16V_4
*22u/6.3V_8

*22u/6.3V_8
150K_1%_4 0.1u/16V_4 *S_4
LX#3 S5_ON

PC170

PC169

PC168

PC172

PC173

PC171
PR40 3 5 MAINON
ON1 ON2

CT1

CT2
*4.7_5%_6 Idc=9A
PR136
10 PR171 *S_4 PC117 PC125

12

10
SYS_SHDN# SY8288CEN 12 NC#1 16 *S_4 *0.1u/16V_4 *0.1u/16V_4
EN1 NC#2
PR164 PC33
*S_4 *680p/50V_6
PC32
*0.1u/16V_4 PC119 PC124
14 SY8288CVOUT 1000p/50V_4 1000p/50V_4
OUT
17
A
VCC A
13 SY8288CFB
Soft-Start
GND#2
GND#3
GND#4

FF PR168 PC34
PC163 1K_1%_4 470p/50V_4
2.2u/10V_4
8 1821

Freq=600KHZ Quanta Computer Inc.

VCC=3.3V
PROJECT : ZAJ
Size Document Number Rev
3A
SYSTEM 5V/3V (NB680 & NB679)
Do Not add test pad on VCC & LDO pin Date: Tuesday, March 21, 2017 Sheet 23 of 34
5 4 3 2 1
 5 4 3 2 1

24
D [6,12,13,14,19,21,22,23,28] +3VPCU D
[6,7,26] +1.05V
[4,5,6,12,13,14,15,16,17,18,21,23,25,26,28,29] +3V +1.05V
1.05Volt +/- 5%
TDC : 2.025A
PEAK : 2.7A
Width : 100mil
+3V

+1.05V

Z
H
P
C
h
a
n
g
e
+
1
.
0
5
V
_
S
5
t
o
+
1
.
0
5
V
PR144
100K_1%_4 PC148 PR148
C C
PR145 JP5
*S_4 *2200p/50V_4 *2.2_5%_6 *S_3720
8068PG_1.05V PU8 PL5
[21] HWPG_1.05V 1uH_7x7x3
4 1 8068LX_1.05V1 2
POK NC#1 8068FB_1.05V_S

0.1u/25V_4

22u/6.3V_6
+3VPCU 9 2 PR146 *S_4
VIN#1 SW#1

PC147

PC143
PC137
10 3 *22p/50V_4 PR141
JP6 VIN#2 SW#2 7.5K_1%_4
*S_3720 PR147 7 8068NC_1.05V
PC141
R1
10_5%_6 NC#2 *68p/50V_4
8068SVIN_1.05V 8 6 8068FB_1.05V
VCC FB
8068EN_1.05V
0.01u/50V_4

11 5 PR142
GND EN Vo=0.6*(R1+R2)/R2
PC144

*S_4 PR143
PC149 PC142 R2 10K_1%_4
B
10u/6.3V_6 1u/6.3V_4 M5671RE1U PC140 =1.05V B

*0.1u/16V_4

MAINON [21,23,25,28,29]

A A
Quanta Computer Inc.
PROJECT :
Size Document Number Rev
3A
+1.05V (M5671RE1U)
Date: Tuesday, March 21, 2017 Sheet 24 of 34
5 4 3 2 1
 1 2 3 4 5

+3V
+VIN
+1.35VSUS
+VDDQ_VTT
+5V_S5
[12,22,23,26,27,29,30]
[2,7,10,11]
[10,11]
[6,19,20,23,26,27,30]
25
PR197 +3V [4,5,6,12,13,14,15,16,17,18,21,23,24,26,28,29]
100K_1%_4
PR196
A *S_4 A
[21] HW PG_1.35VSUS

[21] SUSON
PR59
*S_4 PC47 Ilimit=13A
*0.1u/16V_4
+1.35VSUS
PR193
*S_4
PR199
340K_1%_4 +VIN
1.35 Volt +/- 5%
TDC : 7.875A

1P35V_PGOOD
[21,23,24,28,29] MAINON Fsw=500KHz JP9
PEAK : 10.5A

1P35V_CS
1P35V_S3

1P35V_S5
*S_3720
PC41
1P35V_TON
PR194
1.35VSUS_VIN
OCP : 13A
*0.1u/16V_4
Width : 320mil

10u/25V_8

10u/25V_8
0.1u/25V_4

2200p/50V_4

0.1u/25V_4
499K_1%_4

PC192

PC193

PC196

PC191

PC199
10

13
7

9
PQ18 +1.35VSUS
TDC : 0.75A AON7410

S3

S5

PGOOD

TON
CS

5
PEAK : 1A +VDDQ_VTT
D
B
Width : 40mil 20
VTT G B
17 1P35V_UGATE 4
2 UGATE S JP10
PC197 VTTSNS PR195 PC207 *S_3720

1
2
3
10u/6.3V_6 18 1P35V_BOOT
1 BOOT PL9
+VDDQ VTTGND 2.2_5%_6 0.1u/50V_6 1uH_7x7x3
PR48 PU15 16 1P35V_PHASE 1 2 +1.35VSUS_SRC
100_1%_4 RT8231BGQW PHASE
TDC : 0.375A 4 15 1P35V_LGATE

0.1u/16V_4

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8
*22u/6.3V_8

*22u/6.3V_8
VTTREF LGATE

5
PEAK : 0.5A PR52

PC208

PC198

PC212

PC211

PC205

PC203

PC194
19 12 1P35V_VDD D *4.7_5%_6 PR190
Width : 20mil PC39 PC195 VLDOIN VDD PR64
+5V_S5
G *S_4
*10u/6.3V_6

0.1u/16V_4 0.033u/16V_4 *S_4 4

PC202

S
PC210

1
2
3
VDDQ
PGND

1u/6.3V_4 PQ19 PC40

GND

PAD
VID

AON7752 *680p/50V_6
FB

+1.35VSUS
3

11

14

21

PR47
*S_4
1P35V_VID

1P35V_FB

PR53 PR65 Rds(on)=14.5mohm

C *0_5%_4 *S_4 C
1P35V_S3 1P35V_S5 1P35V_VDDQ
+5V_S5

PR198 *0_5%_4
R1
PR191
10K_1%_4
VID Ref. Voltage R2 PR192
10K_1%_4
High 0.675V

Low 0.75V
S3 S5 VDDQ VTTREF VTT
OCP=13A
L ripple current S0 1 1 ON ON ON
=(19-1.35)*1.35/(1u*500k*19)
=2.508A S3 (mainon off) 0 1 ON ON OFF
Vtrip=13-(2.508/2)*14.5mohm DDR=1.35V
=170.317mV R1=10K/F_4
D S4/S5 0 0 OFF OFF OFF D
Rlimit=170.317mV/5uA*10=340.63Kohm R2=10K/F_4

Quanta Computer Inc.

PROJECT :
Size Document Number Rev
3A
DDR3L (RT8231BGQW)
Date: Tuesday, March 21, 2017 Sheet 25 of 34
1 2 3 4 5
 5 4 3 2 1

SVID_CLK : UP:85 ohm

SVID_ALERT : UP:68 ohm
SVID_DATA : UP:170 ohm
Series:95 ohm
Series:220 ohm
Series:20 ohm
+1.05V

+5V_S5
IMVP8 VR Controller
26
PR122 PR27 +VIN
86.6_1%_4 169_1%_4
Rail A（1 phase）：+VCCGI

1_1%_6

*S_6
PR24 20_1%_4 ISL95857_SDA
[6] H_CPU_SVIDDAT

D
[6] VR_SVID_ALERT#_VCORE
95.3_1%_4 ISL95857_SCLK
Rail C（1 phase）：+VNN D

PR117

PR114
[6] PR123
H_CPU_SVIDCLK

+3V
Check PU High with HW

PR129
10K_1%_4

PR127 *S_4 ISL95857_VR_HOT PC87 PR101

[6,21,22] H_PROCHOT#

1u/25V_4

1u/25V_4
63.4K_1%_4

63.4K_1%_4
*S_4 ISL95857_VR_READY

PR18

PR20

PC92

PC95
[21] IMVP_PWRGD PR130
2200p/50V_4 1K_1%_4

ISL95857_PROG1

ISL95857_PROG2
ISL95857_VCC

ISL95857_VIN
Close to
ISL95857_VR_EN
[21] VNN_ON VNN Choke
PR133 *S_4 PR14 332_1%_4 ISUMN_C [27]
PR33
*S_4

2
PR131
Check VR Sequence *10K_1%_4
PR110

41

40

39

38

37

36

35

34

33

32

31
10K_NTC_4_1%
+3V

0.1u/25V_4

0.01u/50V_4
Rail C

VR_HOT#

ALERT#

PROG1

PROG2
VCC

VIN
EP

VR_ENABLE

VR_READY

SCLK

SDA

1
PC6

PC11
PC86 PR100
ISL95857_PSYS 1 30 ISL95857_PWM_C PR112 *S_4 0.047u/16V_4 11K_1%_4
TP30 PSYS PWM_C PWM_C [27]
29 ISL95857_FCCM_C PR108 *S_4
2 FCCM_C FCCM_C [27] PR6
IMON_B 2.61K_1%_4
28 ISL95857_ISUMN_C
C ISUMN_C C
3
NTC_B
4 27
COMP_B ISUMP_C ISUMP_C [27]
PU6
Double Check Rail B Non-Usage Pin ISL95859AHRTZ-T
RTN_C
26 ISL95857_RTN_C

5 25 ISL95857_FB_C
FB_B FB_C
6

301_1%_4
+5V_S5 RTN_B ISL95857_COMP_C

PR107
24

*2K_1%_4
7 COMP_C

402_1%_4
ISUMP_B

4.02K_1%_4
ISL95857_IMON_C

PR105

PR106
8 23

68p/50V_4
PR132 *S_4
ISUMN_B IMON_C +VNN

127K_1%_4

330p/50V_4
9
ISEN1_B 22 ISL95857_PWM_A PC3

2200p/50V_4
PWM_A

PC83
10
ISEN2_B ISL95857_FCCM_A

PR13
21 PR95

8200p/50V_4

*680p/50V_4
ISUMN_A
ISUMP_A
PWM1_B

PWM2_B

COMP_A
FCCM_A
FCCM_B

IMON_A

PC10
NTC_A *0.01u/50V_4 100_1%_4

RTN_A

PC9
FB_A

PR11

PC81

PC82
Rail A
11

12

13

14

15

16

17

18

19

20
PR104 *S_4 PR12 *S_4

ISL95857_ISUMN_A
ISL95857_COMP_A

PWM_A [27] VNN_SENSE [7]

ISL95857_IMON_A

PC4
ISL95857_NTC_A

ISL95857_RTN_A

PR103 *S_4 *0.01u/50V_4 PR97 *S_4

ISL95857_FB_A

FCCM_A [27] TP29

PC91 PR115

B 2200p/50V_4 1K_1%_4 PC5 PR96 B

*S_4
Close to
VCCGI Choke *0.01u/50V_4
PR111 182_1%_4 ISUMN_A [27]

2
0.1u/25V_4
PC89
PR116
10K_NTC_4_1%

0.1u/25V_4

1
PC90
APL VR (1+1 Phase) PC12
0.022u/50V_4
PR19
11K_1%_4
470K_NTC_4_5%

PR22
2.61K_1%_4

+VCCGI +VNN
2K_1%_4

2K_1%_4
27.4K_1%_4

PR113

PR120

PR118

2.55K_1%_4

ISUMP_A [27]
PR23
499_1%_4
Icc Max：21A Icc Max：4.8A
1
330p/50V_4

Icc TDC：18A Icc TDC：N/A +VCC_VCCGI

PR32

PC19
PR26
97.6K_1%_4

Vboot：0V Vboot：1.05V
2
PR128

68p/50V_4

PC15
8200p/50V_4

1200p/50V_4

1000p/50V_4 *0.01u/50V_4 PR30

100_1%_4
OCP：25A OCP：8A
PC100

Close to
VCCGI MOS
10K_1%_4

Fsw：750KHZ Fsw：750KHZ
PR31

A PR124 *S_4 A
VCCGI_SENSE [7]
PC18

PC96

PC94

PC98 PR119 *S_4

*0.01u/50V_4 VCCGISS_SENSE [7]
VCCGI L/L：
R_DC_LL：6mV/A
PC17 PR21
100_1%_4
R_AC_LL：6mV/A Quanta Computer Inc.
0.01u/50V_4
PROJECT :
Size Document Number Rev
3A
CPU_CORE (ISL95859)
Date: Tuesday, March 21, 2017 Sheet 26 of 34
5 4 3 2 1
 5 4 3 2 1

+VIN
+VCC_VCCGI
[12,22,23,25,26,29,30]
[7,26]
30
+VNN [7,26]
+5V_S5 [6,19,20,23,25,26,30]

VCCGI D

JP3
*S_3720
PR1
*S_6
+VCCGI

*33u/25V_D6.3H4.5
+VIN
+5V_S5

10u/25V_8

10u/25V_8

2200p/50V_4
0.1u/50V_6
Icc Max：21A

PC70

PC71

PC73

PC72

PC80
+
4.7u/6.3V_4
PC67

+VCC_VCCGI
Icc TDC：18A

5
PU4 ISL95808HRZ-T PR86 D
*S_6 G PQ13
6
VCC BOOT
2 4
S
AON6414AL Vboot：0V
PC75
Rail A 0.1u/50V_6
OCP：25A

1
2
3
[26] PWM_A PR84 *S_4 3 1
PWM UGATE
PL4 Fsw：750KHZ
0.15uH_7x7x4
[26] FCCM_A PR90 *S_4 7
FCCM PHASE
8 PHASE_A 1 2 DCR=0.66mOhm +VCC_VCCGI

*330u/2V_7343H1.9
VCCGI L/L：

0.1u/16V_4

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8
PR5
GND#2

PC30

PC134

PC105

PC103

PC132

PC108

PC20
4 5 D 2.2_5%_6 +
GND#1 LGATE

PC109

PC129
G PQ14
4
S
AON6752 R_DC_LL：6mV/A
9

R_AC_LL：6mV/A

1
2
3
C PC1 C
1000p/50V_4

+VCC_VCCGI

PR121 3.65K_1%_6
[26] ISUMP_A

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8

*22u/6.3V_8
PC24

PC99

PC22

PC25

PC21
PC114

PC118

PC131

PC128

PC133

PC130

PC126

PC113
[26] ISUMN_A PR126 *S_6

17x22uF for VCCGI

VNN
JP2
*S_3720
B B
+VIN
PR2
10u/25V_8

10u/25V_8

0.1u/50V_6

2200p/50V_4
*S_6
PC77

PC78

PC76

PC74
+5V_S5
4.7u/10V_6
PC66

+VNN
5

D +VNN
PU3 ISL95808HRZ-T PR92 G PQ11
*S_6 4 AON7410
6
VCC BOOT
2 S Icc Max：4.8A
Rail C
1
2
3

PC79
0.1u/50V_6 Icc TDC：N/A
[26] PWM_C PR85 *S_4 3 1
PWM UGATE
PL2 Vboot：1.05V
0.47uH_7x7x3
PR89 *S_4 7 8 PHASE_C 1 2 DCR=4.2mOhm
[26] FCCM_C FCCM PHASE OCP：8A
0.1u/16V_4

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8

22u/6.3V_8
5

PC93

PC26

PC110

PC97

PC23

PC106

PC101

PC104
PR16
Fsw：750KHZ
GND#2

4 5 D 2.2_5%_6
GND#1 LGATE PQ12
G
4 AON7752
S
9

1
2
3

PC14
1000p/50V_4

7x22uF for VNN

A PR91 3.65K_1%_6 A
[26] ISUMP_C

[26] ISUMN_C PR94 *S_6

Quanta Computer Inc.

PROJECT :
Size Document Number Rev
3A
+VCCGI / +VNN (ISL95859)
Date: Tuesday, March 21, 2017 Sheet 27 of 34
5 4 3 2 1
 5 4 3 2 1

[6,12,13,14,19,21,22,23,24]
[3,5,6,7,9,15,16,17,18,22]
[7]
[12,13,29]
+3VPCU
+1.8V_S5
+1.24V_S5
+1.8V
[5,6,7,15,16,18,20,21,23]
[23]
[4,5,6,12,13,14,15,16,17,18,21,23,24,25,26,29]
+3V_S5
+5VPCU
+3V
28
[14] +1.5V

+1.8V_S5
1.8Volt +/- 5%
D TDC : 0.514A D
ZHP change +1.8V_S5 PG pull up to +3V_S5 PEAK : 0.685A
+3V_S5 +3VPCU Width : 40mil +1.8V_S5

PR41
*S_6 PC161 +1.8V_S5
4.7u/6.3V_4
PR160
100K_1%_4

3
JP11

4
PR165 *S_3720
*S_4 PL7 MAIND 2 PQ4

VIN
5 3 G5719LX1.8V 1 2 [29] MAIND AO3404
[21] HWPG_1.8V_S5 PG LX 2.2uH_2.5x2.0x1.2
PU12

1
G5719CTB1U

10u/6.3V_6

0.1u/16V_4
*10u/6.3V_6
1 2
[21,23] S5_ON EN GND

PC35

PC36

PC166
PR161 +1.8V

VFB
PR170 *S_4
100K_5%_4 PC167
0.1u/16V_4
TDC : 0.173A

6
R1 PEAK : 0.23A
Width : 20mil
PR166
Check RC delay time with HW 30K_1%_4
(follow ZHP RC dealy time) R2 PR167
15K_1%_4 Vo=(0.6(R1+R2)/R2)
=1.8V

C C
+1.24V_S5
1.24Volt +/- 5%
TDC : 0.975A
PEAK : 1.3A
+3V_S5 +3VPCU Width : 40mil
PR150
*S_6 PC150 +1.24V_S5
4.7u/6.3V_4
PR149
100K_1%_4
JP12
4

PR152 *S_3720
*S_4 PL6
VIN

[21] 5 3 G5719LX1.24V1 2
HWPG_1.24V_S5 PG LX 2.2uH_2.5x2.0x1.2
PU10
G5719CTB1U
HWPG_1.8V_S5

10u/6.3V_6

0.1u/16V_4
*10u/6.3V_6
1 2
EN GND

PC156

PC153

PC159
PR151
VFB

PR163 *S_4
*S_4 PC158
*0.1u/16V_4
6

R1

PR154
Check RC delay time with HW 16K_1%_4
(follow ZHP RC dealy time) R2 PR155
15K_1%_4 Vo=(0.6(R1+R2)/R2)
B =1.24V B

+3VPCU
10u/6.3V_6

0.1u/50V_6
PC187

PC188

PR180
*S_8
+1.5V
PU14
1.5Volt +/- 5%
G9661MF11U TDC : 0.39A
MAINON 3 5
[21,23,24,25,29] MAINON VIN NC PEAK : 0.52A
Width : 20mil
100K_5%_4

*0.1u/50V_6

PR182
PR184

PC189

*S_4 PR181
*S_8
6 +1.5V
VO
2
VEN

+5VPCU 4 8 PC186
VPP GND#1 10u/6.3V_6
ADJ

PR179 1 9
*S_4 PC185 [21] HWPG_1.5V POK GND#2
1u/25V_4 +3V PR183
7

30K_1%_4
PR186 R1
100K_5%_4
A A
0.8V Vo =0.8(1+R1/R2)
=1.506V
PR185
34K_1%_4
R2
Quanta Computer Inc.
PROJECT :
Size Document Number Rev
3A
+1.8V_S5 / +1.24V_S5 / +1.5V
Date: Tuesday, March 21, 2017 Sheet 28 of 34
5 4 3 2 1
 5 4 3 2 1

[4,5,6,12,13,14,15,16,17,18,21,23,24,25,26,28]
[23]
[12,22,23,25,26,27,30]

[12,13,14,16,18,23]
[12,13,28]
VL
+VIN
+3V
+5V
+1.8V
29
D Thermal Protection D

(1) Need fine tune

for thermal protect point
(2) Note placement position
PR159 150_1%_4
VL TEMP=85C
PC160
0.1u/16V_4

5
VCC
3 SYS_SHDN#
OT SYS_SHDN# [21,23]
PU9 PR156
PR153 TMP708AIDBVR *S_4
24K_1%_4
1
SET

HYST
GND
C C

Rset(Kohm)=0.0012T*T-0.9308T+96.147

4
=25.69 K ohm HYST=VCC for 10
degree Hys.
HYST=GND for 30
degree Hys.

+5V PU High R= 220 ohm for

Bo-Bo sound issue.

+VIN +3V +5V +1.8V +VIN

PR36 PR42 PR43 PR39 PR35

1M_5%_6 22_5%_8 *220_5%_8 22_5%_8 1M_5%_6
B B

MAINON_ON_G MAIND
MAIND [28]
3

3
PR37
2 1M_5%_6 2 2 2 2
[21,23,24,25,28] MAINON PC31
PQ5 PQ15 PQ3 PQ1 *2200p/50V_4
2N7002K *2N7002K 2N7002K 2N7002K
1

1
1

PR38
*100K_1%_6

PQ2
DDTC144EUA-7-F

A A

Quanta Computer Inc.

PROJECT :
Size Document Number Rev
3A
Thermal / Discharge
Date: Tuesday, March 21, 2017 Sheet 29 of 34
5 4 3 2 1
 5 4 3 2 1

30
Panel Spec (TFT-LCD 14'')
D
VLED : 6V~21V (Tpy:12V) D

Power Consumption : 3W (MAX)

+12V_Panel
12 Volt +/- 5%
PEAK : 0.35A
Width : 20mil
PL1
1 2
+12V_Panel
[email protected]_5x5x1.8

+5V_S5
40V, 2A
PR204 PQ22 PU1 VL@TPS61087DRCR
VL@0_5%_8 S VL@AO3415 D PD1
1 3 8 6 61087SW 2 1
IN SW #1

VL@10u/25V_8

VL@10u/25V_8

VL@1u/6.3V_4
C VL@DFLS240-7 C

PC28

PC27

PC29
G
2

PC216 PR205 PR28 *VL@0_5%_4 61087EN 3 7 PR9 R1 PC138 PC127 PC145 PC146
*[email protected]/25V_4 VL@100K_1%_4 EN SW #2 *VL@22u/25V_8 *VL@22u/25V_8 VL@22u/25V_8 VL@22u/25V_8
VL@174K_1%_4

61087FREQ 9 2 61087FB
VFB=1.238V
PR29
FREQ FB
VGS=-4.5V
VL@0_5%_4

PR206 PANEL_LED_EN PR7 VL@0_5%_4 4 1 61087COMP PR8

[21] PANEL_LED_EN AGND COMP
VL@10K_5%_4 R2
VL@20K_1%_4

EPAD#1
EPAD#2
EPAD#3
EPAD#4
EPAD#5
EPAD#6
PR10
PC7 PR25 5 10 61087SS
[email protected]/16V_4 PGND SS VL@100K_5%_4
PR207 *VL@0_5%_4
3

VL@0_5%_4

11
12
13
14
15
16
PANEL_LED_EN 2 PQ23 PC16
VL@2N7002K [email protected]/25V_4
PC8 Vo =1.238*(1+R1/R2)
VL@820p/50V_4 =12V
1

B B

BL Discharge Circuit

+VIN +12V_Panel

PR209 PR210
VL@1M_5%_6 VL@22_5%_8

PQ24
VL@DDTC144EUA-7-F

3
PR208

3
VL@0_5%_4 PR211
PANEL_LED_EN 2 VL@1M_5%_6 2
A PQ25 A
VL@2N7002K

1
1
PR212
*VL@100K_1%_6 Quanta Computer Inc.
PROJECT : ZAJ
Size Document Number Rev
3A
LED Panel (TPS61087)
Date: Tuesday, March 21, 2017 Sheet 30 of 34
5 4 3 2 1
 5 4 3 2 1

Apollo Power Tree 30

+VCC_VCCGI
110mil
840 mil PU4

+VNN
25mil
D D

200 mil
PU3

LAN RTL8411B-CG
55mil +1.35VSUS 40mil U13
RTC
420 mil
PU15 20mil CN13
TPM
5mil U14
105mil +3VPCU LED
310mil 10mil
PU5
Touch Pad
10mil CN15

+3V_S5
EC
70mil PU7
12mil U16

Audio codec
C
10mil U15 C

WIFI
30mil CN9

+3V CRD RTL8411B-CG

190mil PU7 35mil U13
VIN
600mil LCDVCC
60mil U19

M.2 SSD
20mil CN5

eMMC
15mil U2

+1.8V_S5 +1.8V
B B

40mil PU12 20mil PQ4

+1.05V
110mil PU8

+1.24V_S5
55mil PU10

+1.5V
20mil PU14

305mil +5VPCU +5V Codec panel boost +5V_FAN1 HDD+M2_PWR +5V_ODD TP_PWR
590mil 240mil PU13 40mil U15 40mil PU1 20mil CN10 60mil CN12 60mil CN16 10mil CN3
PU11
A A

+5V_S5 USBPWR1 USBPWR2 +TYPEC_VBUS_C

350mil PU13 100mil U7 100mil U18 150mil U3

Quanta Computer Inc.

PROJECT : ZAJ
Size Document Number Rev
3A
POWER TREE
Date: Tuesday, March 21, 2017 Sheet 31 of 34
5 4 3 2 1
 5 4 3 2 1

VCCRTC
RTC_RST#
31
VCC_RTC_3P3V power to RTC_TEST# > 9 ms
RTC_TEST#
D D

Adaptor in +3VPCU/+5VPCU
From PWM to EC SYS_HWPG
POWER BUTTON NBSWON#
S5_ON
+5V_S5/+3V_S5
From EC to PWM VNN_ON
+VNN
C
Delay S5_ON (6.34ms) +1.8V_S5 C

HWPG_1.8V_S5 +1.24V_S5 30ms

From EC to SOC RSMRST# 120ms
From EC to SOC DNBSWON#

10ms
From SOC to EC SUSB#/SUSC#
From EC to PWM SUSON
+1.35VSUS 10ms
MAINON
B B

+1.05V/+1.5V
HWPG_1.5V HWPG >100ms
From PW to MOS MAIND
+1.8V
From EC to SOC EC_PWROK boot up by SVID
+VCC_VCCGI
PLTRST#
A A

Quanta Computer Inc.

PROJECT : ZAJ
Size Document Number Rev
3A
Power on Sequence
Date: Tuesday, March 21, 2017 Sheet 32 of 34
5 4 3 2 1
 1 2 3 4 5 6 7 8

32
A A

B B

C C

D D

Quanta Computer Inc.

PROJECT : ZAJ
Size Document Number Rev
3A
Power status table
Date: Tuesday, March 21, 2017 Sheet 33 of 34
1 2 3 4 5 6 7 8
 5 4 3 2 1

Model Date CHANGE LIST

1.Change 0 ohm to shortpad：
02/10 R403,R404,R405,R406,R407,R408,R409,R410,R104,R113,R108,R115,R99,R402,R167,R165,R161,R158,R157,R153,R270,R271,R272,R273,R247

2.Un-stuff R380/R464 (debug card circuit)

ZAJ REV.D
1.Unstuff SW3
2.Update SW2 FP to "sw-ds-a40e-4p-smt" by SMT request
D
02/18 D
3.Update CN2 FP to "sdcard-156-1001902602-11p-smt" by SMT request
4.Update CN9 FP to "ngff-apci0076-p001a-75p-ke-smt" by SMT request

C C

B B

A A

Quanta Computer Inc.

PROJECT MODEL : ZAJ APPROVED BY: DATE:
PROJECT : ZAJ DOC NO.
Size Document Number Rev
3A
Change list PART NUMBER: DRAWING BY: REVISON:
Date: Tuesday, March 21, 2017 Sheet 34 of 34

5 4 3 2 1