2020 Final
2020 Final
Final Examination
[Total 100 pts. Close book, Close notes]
1. (10 pts.) [ADC and DAC] Please choose the most appropriate answer to the following questions.
(1) The number of clock cycles per A-to-D conversion for an 8-bit flash ADC is
(a) 1 (b) 8 (c) 16 (d) 64 (e) 256
(2) The number of clock cycles per A-to-D conversion in worst case for an 8-bit Dual slope ADC is
(a) 1 (b) 8 (c) 16 (d) 64 (e) 256
(3) The number of clock cycles per A-to-D conversion for an 8-bit SAR ADC is
(a) 1 (b) 8 (c) 16 (d) 64 (e) 256
(4) In an N-bit segmented current-steering DAC, the “segmented architecture” is a combination of
(a) unary and binary weighted current cells
(b) I-2I (similar with R-2R) current cells
(c) 2N equal weighted current cells
(d) binary weighted current cells implemented by resistors and capacitors
(5) What is/are the characteristic(s) of an R-2R DAC?
(a) Easier to build accurately as resistors with only two resistances, i.e. R and 2R, are required
(b) Number of bits can be easily expanded by adding more sections of same R-2R value
(c) The input-to-output response may be non-monotonic
(d) All of above
1
Fig. 2(c)
3. (10 pts.) Consider the bridge-T network of Fig. 3(a) with R3 = R4 = R and C1 = C2 = C, and denote
RC = τ. Find the zeros and poles of the bridge-T network. If the network is placed in the negative-
feedback path of an ideal infinite-gain op amp, as in Fig. 3(b), find the poles of the closed-loop
amplifier.
1 1 1 1
𝑉𝑎 𝑠 2 + 𝑠 (𝐶 + 𝐶 ) 𝑅 + 𝐶 𝐶 𝑅 𝑅
1 2 3 1 2 3 4
𝑡(𝑠) ≡ =
𝑉𝑏 𝑠 2 + 𝑠 ( 1 + 1 + 1 ) + 1
𝐶1 𝑅3 𝐶2 𝑅3 𝐶1 𝑅4 𝐶1 𝐶2 𝑅3 𝑅4
Fig. 3(a)
Fig. 3(b)
2
(e) What filter function is (i) V1/Vi, (ii) V2/Vi?
(f) Follow (d), use this Gm-C circuit to design a BP filter (Gm1, Gm2, Gm3, and Gm4) with a central
frequency of 10 MHz, a 3-dB bandwidth of 1 MHz, and a center-frequency gain of 10. Let
time constants of integrators are equal, and use equal capacitors of 5pF.