ation.

But the Flash market did not take off until this technology
was proven to be reliable and manufacturable. In the
late 1990s, the Flash technology exploded as the right nonvolatile
memory for code and data storage, mainly for mobile
applications. Starting from 2000, the Flash memory can be
considered a really mature technology: more than 800 million
units of 16-Mb equivalent NOR Flash devices were sold
in that year.
In Fig. 6, the Flash market is reported and compared with
the DRAM and SRAM one [10]. It can be seen that the Flash
market became and has stayed bigger than the SRAM one
since 1999. Moreover, the Flash market is forecasted to be
above $20 billion in three or four years from now, reaching
the DRAM market amount, and only smoothly following the
DRAM oscillating trend, driven by the personal computer
market. In fact, portable systems for communications and
consumer markets, which are the drivers of the Flash market,
are forecasted to continuously grow in the coming years.
In the following, we briefly describe the basics of the Flash
cell functionality.
Fig. 7. Schematic cross section of a Flash cell. The floating-gate
structure is common to all the nonvolatile memory cells based on
the floating-gate MOS transistor.
A. Basic Concept
A Flash cell is basically a floating-gate MOS transistor
(see Fig. 7), i.e., a transistor with a gate completely surrounded
by dielectrics, the floating gate (FG), and electrically
governed by a capacitively coupled control gate (CG).
Being electrically isolated, the FG acts as the storing electrode
for the cell device; charge injected in the FG is maintained
there, allowing modulation of the “apparent” threshold
voltage (i.e., seen from the CG) of the cell transistor.
Obviously the quality of the dielectrics guarantees the nonvolatility,
while the thickness allows the possibility to program
or erase the cell by electrical pulses. Usually the gate
dielectric, i.e., the one between the transistor channel and the
FG, is an oxide in the range of 9–10 nm and is called “tunnel
oxide” since FN electron tunneling occurs through it. The
dielectric that separates the FG from the CG is formed by a
triple layer of oxide–nitride–oxide (ONO). The ONO thickness
is in the range of 15–20 nm of equivalent oxide thickness.
The ONO layer as interpoly dielectric has been introduced
in order to improve the tunnel oxide quality. In fact, the
BEZ et al.: INTRODUCTION TO FLASH MEMORY 491
Fig. 8. Schematic energy band diagram (lower part) as referred to a floating gate MOSFET
structure (upper part). The left side of the figure is related to a neutral cell, while the right side to a
negatively charged cell.
Fig. 9. (a) NOR Flash array equivalent circuit. (b) Flash memory cell cross section.
use of thermal oxide over polysilicon implies growth temperature
higher than 1100 C, impacting the underneath tunnel
oxide. High-temperature postannealing is known to damage
the thin oxide quality.
If the tunnel oxide and the ONO behave as ideal dielectrics,
then it is possible to schematically represent the
energy band diagram of the FG MOS transistor as reported
in Fig. 8. It can be seen that the FG acts as a potential well
for the charge. Once the charge is in the FG, the tunnel and
ONO dielectrics form potential barriers.
The neutral (or positively charged) state is associated with
the logical state “1” and the negatively charged state, corresponding
to electrons stored in the FG, is associated with the
logical “0.”
The “NOR” Flash name is related to the way the cells are
arranged in an array, through rows and columns in a NOR-like
structure. Flash cells sharing the same gate constitute the
so-called wordline (WL), while those sharing the same drain
electrode (one contact common to two cells) constitute the
bitline (BL). In this array organization, the source electrode
is common to all of the cells [Fig. 9(a)].
A scanning electron microscope (SEM) cross section
along a bitline of a Flash array is reported in Fig. 9(b), where
three cells can be observed, sharing two by two the drain
contact and the sourceline. This picture can be better understood
considering the layout of a cell (see Fig. 10) and the
two schematic cross sections, along the direction (bitline)
and the direction (wordline). The cell area is given by the
pitch times the pitch. The pitch is given by the active
area width and space, considering also that the FG must
overlap the oxide field. The pitch is constituted by the cell
gate length, the contact-to-gate distance, half contact, and
half sourceline. It is evident, as reported in Fig. 9(b), that
both contact and sourceline are shared between two adjacent
cells.
B. Reading Operation
The data stored in a Flash cell can be determined measuring
the threshold voltage of the FG MOS transistor. The
best and fastest way to do that is by reading the current driven
by the cell at a fixed gate bias. In fact, as schematically reported
in Fig. 11, in the current–voltage plane two cells,
respectively, logic “1” and “0” exhibit the same transconductance
curve but are shifted by a quantity—the threshold
voltage shift ( )—that is proportional to the stored electron
charge .
Hence, once a proper charge amount and a corresponding
is defined, it is possible to fix a reading voltage in such
492 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 4, APRIL 2003
Fig. 10. The NOR Flash cell. (a) Basic layout. (b) Updated Flash
product (64-Mb, 1.8-V Dual bank). (c) and (d) are, respectively,
the schematic cross section along bitline (y pitch) and wordline
(x pitch).
Fig. 11. Floating-gate MOSFET reading operation.
a way that the current of the “1” cell is very high (in the range
of tens of microamperes), while the current of the “0” cell is
zero, in the microampere scale. In this way, it is possible to
define the logical state “1” from a microscopic point of view
as no electron charge (or positive charge) stored in the FG and
from a macroscopic point of view as large reading current.
Vice versa, the logical state “0” is defined, respectively, by
electron charge stored in the FG and zero reading current.
C. Writing Operation
Considering Fig. 8, the problem of writing an FG cell corresponds
to the physical problem of forcing an electron above
or across an energy barrier. The problem can be solved exploiting
different physical effects [11]. In Fig. 12, the three
main physical mechanisms used to write an FG memory cell
are sketched.
– The CHE mechanism, where electrons gain enough
energy to pass the oxide–silicon energy barrier,
thanks to the electric field in the transistor channel
between source and drain. In fact, the electron energy
distribution presents a tail in the high energy
side that can be modulated by the longitudinal
electric field.
Fig. 12. Writing mechanism in floating-gate devices.
Fig. 13. NOR Flash writing mechanism.
– The photoelectric effect, where electrons gain
enough energy to surmount the barrier thanks to
the interaction with a photon with energy larger
than the barrier itself. For silicon–dioxide, this
corresponds to UV radiation. This mechanism is
the one originally used in EPROM’s products to
erase the entire device.
– The Fowler–Nordheim electron tunneling mechanism
is a quantum-mechanical tunnel induced by
an electric field. Applying a strong electric field
(in the range of 8–10 MV/cm) across a thin oxide,
it is possible to force a large electron tunneling
current through it without destroying its dielectric
properties.
A NOR Flash memory cell is programmed by CHE injection
in the FG at the drain side and it is erased by means of
the FN electron tunneling through the tunnel oxide from the
FG to the silicon surface (see Fig. 13).
III. RELIABILITY
Many issues have to be addressed when, from the theoretical
model of a single cell, a Flash product has to be realized,
integrating millions of cells in an array. Nonvolatility
implies at least ten years of charge retention, and the data
must be stored in a cell after many read/program/erase cycles.
The confidence in Fla