ELEG 3230

Microprocessors and Computer

Systems

Part 9
Basic Input & Output Interface
(Hall’s Ch 9; Brey’s Ch 10)

ELEG 3230 - Part 9 1

 Outline
aInput-output Interface
aSerial/Parallel Interface
a8255 Programmable Peripheral Interface
aKeyboard
a8254 Software-Programmable
Timer/Counter

ELEG 3230 - Part 9 2

Introduction to Input-Output

address & Memory

control address
interface MEMORY
data bus
CPU
I/O address
& control I/O interface Outside world
eg. keyboard
printer
CRT display
mass storage

ELEG 3230 - Part 9 3

 I/O interface
a Input-output involves the transfer to (or from) peripheral devices
from (or to) the data bus of the cpu; eg. data transfer to the CRT
display, from the keyboard, to/from a hard-disk drive, to/from a
modem to another computer system.
a Input-output operations fall into one of the following types:
• Programmed I/O - cpu polls peripherals to check if I/O is needed
• Interrupt I/O - peripheral sends an interrupt request to cpu for I/O
• Direct memory access (DMA) - peripheral writes directly to memory
a Considering the address of I/O, 8088 uses Isolated I/O (I/O
addresses are not part of memory address) as distinct from
Memory mapped I/O (peripherals are mapped to locations in the
memory address space).
Q: pros and cons of isolated I/O and memory mapped I/O?
ELEG 3230 - Part 9 4
 Memory and I/O Map
Memory
FFFFF I/O
The Memory and I/O FFFF
maps for the 8086/8088
1M × 8 64K × 8
microprocessor.
(a) Isolated I/O. 00000 0000
(a)
(b) Memory mapped I/O.
Memory + I/O
FFFFF

I/O
Q: In Isolated I/O, an I/O port has the
same address as one of the memory
byte. How does it know it is being
addressed? 00000
(b)

ELEG 3230 - Part 9 5

 I/O interface
cpu side peripheral side

data bus output ports

data buffer registers

address bus status register input ports

control bus I/O protocol unit protocol line

example of an I/O interface

Typically, not all data, address or control lines are needed.

Input and output ports may be the same (shared).
ELEG 3230 - Part 9 6
 I/O interface
a I/O interface functions include
• data storage buffer for sending and receiving data
• low-level communications protocol (handshaking)
• data format conversion (eg. parallel/serial)
• error detection
• addressing of different peripherals

a I/O interface are typically implemented by LSI (large scale

integration) - many different types are available from different
manufacturers.
a Data can be transferred through I/O interface by either
programmed I/O or interrupt I/O. DMA typically needs a separate
controller.
ELEG 3230 - Part 9 7
8088 maximum mode I/O interface

IORC I/O device

IOWC 0
CLK Bus
controller AIOWC
I/O device
8288 ALE 1
S0-S2 DT/ R
I/O
DEN interface
8088
circuitry
AD0-AD7

A8-A19 I/O device

IO/ M N-1

Generalized I/O interface connections to maximum mode 8088

ELEG 3230 - Part 9 8
Parallel and Serial Data Transfer
a Data Transfer between the I/O interface and the peripheral can
involve either parallel or serial data transmission, depending on the
peripheral and the actual implementation of the I/O interface.

a Parallel data transfer involves using at least 8 separate lines for the
8 data bits in a byte. Normally, other lines are needed for the
communications protocol (eg. STB [data strobe] line to indicate
when data is valid, ACK line to acknowledge data has been read).
STB is sent by sender ACK is sent by receiver
a Parallel data transfer is usually faster. Each data bit typically needs
its own ground return line to reduce noise. A popular parallel data
transfer interface standard is the CENTRONICS type interface
which uses a 36-pin connector. The Centronics interface is
commonly used in printers.
ELEG 3230 - Part 9 9
 Parallel and Serial Data Transfer
(cont.)
a Serial data transfer involves sending the data on a single line, bit
by bit. The I/O interface converts the data from parallel to serial or
vice-versa using shift registers.

a Serial connections are commonly used for data transfer over

longer distances (eg over telephone line). A popular standard for
serial data transmission is the RS232C standard.

Q: Why serial data transfer is more commonly used in long distance transmission?

ELEG 3230 - Part 9 10

 Serial I/O
a Serial I/O can be either
(1) Synchronous - data are sent in blocks, with start and end-of-block
markers. Individual characters within a block do not need start and stop
bits since the receiver identifies every 8 bits as one character, eg.

one frame

syn syn stx data field etx bcc pad

syn = sync character (ascii code 16)

stx = start of text (ascii code 02)
etx = end of text (ascii code 03)
bcc = block check characters (error detection)
pad = end of frame pad ( ascii code ff)
ELEG 3230 - Part 9 11
 Serial I/O (contd.)
(2) Asynchronous - no block synchronization bits. Each character is
identified by the start and stop bit(s) (stop bits can be 1, 1.5, 2 bits)
inserted at the start and end of each character.

MSB LSB

Stop Parity Start

bit bit data bit

a Synchronous serial data transfer is more efficient (ie. faster) since

asynchronous transfer “wastes” about 30% of the bits for start and
stop bits in sending a 7-bit ASCII code.

a An example of asynchronous serial data transfer is the RS232

serial port found in most computers.

ELEG 3230 - Part 9 12

 Handshaking for I/O
a Three types of handshaking:
• Simple parallel I/O - no handshaking implemented
• Single handshake I/O - uses STB-ACK handshake
• Double handshake I/O - uses STB-ACK and STB-ACK

simple
data
(no handshake)

ELEG 3230 - Part 9 13

 Handshaking for I/O (cont.)
strobe
Single
ACK Handshake

: means the circle will trigger the

data event pointed by the arrow after
a given time

strobe
Tx

Rx ACK Double
Handshake

Data transferred after the

data first STB and ACK.

ELEG 3230 - Part 9 14

 8255 Programmable Peripheral
Interface (PPI)

a Intel 8255A is a general purpose parallel I/O interface. It

provides three I/O port (A, B and C).
a Intel 8255A provides three modes of operations (mode 0, 1,
and 2).
a 8255A’s mode of operation is determined by the contents of
its control register (see Intel data sheet for further details).
a Port A and Port B can be set to different mode and
input/output independently.

Note:
Mode 2 is a bidirectional transmission mode; not necessary using double
handshaking. ELEG 3230 - Part 9 15
 8255A Programmable Parallel
Port Device
Power +5V
GROUP A I/O
Supply GND GROUP PORTA
PA7-PA0
A (8)
CONTROL

Bi-directional GROUP A I/O

PRRT C
Data Bus UPPER
PC7-PC4
DATA

Internal structure D0-D7 BUS

BUFFER
GROUP B I/O
8 BITS
block diagram INTERNAL
PRRT C
LOWER
PC3-PC0
DATA BUS

RD
WR READ/ GROUP GROU B
WRITE B PORT B
I/O
A1 CONTROL CONTROL PB7-PB0
LOGIC (8)
A0
RESET

CS 8255
ELEG 3230 - Part 9 16
 8255A Mode 0 Operation
a In Mode 0 operation, no handshaking will be used.

a If both port A and port B are initialized as mode 0 operation, port C

can be used together as an additional 8-bit port, or two 4-bit ports.

a When used as an outputs, port C line can be set/reset by sending

special control word to the control register address.

a The two halves of port C are independent and can be set as input
or output port independently.

ELEG 3230 - Part 9 17

 8255A Mode 0 Operation
ADDRESS BUS

CONTROL BUS

DATA BUS

R D, W R D7-D0 A0-A1
CS
8255A

MODE 0 C
B A
NO
HANDSHAKE 8 I/O 4 I/O 4 I/O 8 I/O
SIGNALS
PB7-PB0 PC3-PC0 PC7-PC4 PA7-PA0
ELEG 3230 - Part 9 18
 8255A Mode 1 Operation
a In Mode 1 operation, single handshaking (strobed) is used.

a In this mode, some of the port C pins are used for handshaking
purpose.
`If Port A is set to mode 1 & input port: PC3, PC4, and PC5 pins are used.

`If Port A is set to mode 1 & output port: PC3, PC6, and PC7 pins are used.

`If Port B is set to mode 1 & input port: PC0, PC1, and PC2 pins are used.

`If Port B is set to mode 1 & output port: PC0, PC1, and PC2 pins are used.

ELEG 3230 - Part 9 19

 8255A Mode 1 Operation

MODE 1
B PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 A

8 I/O 8 I/O

PB7-PB0 PA7-PA0

INTRB IBFB STBB INTRA STB A IBFA I/O I/O

INPUT
OR OR OR OR OR OR
HANDSHAKING
SIGNAL INTRB OBF B ACK B INTRA I/O I/O ACK A OBF A

OUTPUT
PORT A, PORT B CONTROL HANDSHAKING
SIGNAL
ELEG 3230 - Part 9 20
 8255A Mode 2 Operation
a Only port A can be initialized in mode 2.
a In mode 2, port A can be used as bi-directional handshake data
transfer.
a In this mode, PC3-PC7 are used for handshake lines.
a PC0-PC2 can be used as I/O pins if port B is set to mode 0.
a PC0-PC2 are used as handshake lines if port B is set to mode 1.
a Note that Mode 2 does not mean that it uses double handshake
I/O. It basically specify the bi-directional transmission of data flow.
Both Mode 1 and Mode 2 require handshaking, but no specification
which type is used.

ELEG 3230 - Part 9 21

Summary of Port C Usage when Port A
is in Mode 2
MODE 2
for port A
B PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 A

8 I/O 8 I/O

PB7-PB0 PA7-PA0

INTRA STB A IBFA ACK A OBF A

Bi- Directional
I/O (or CONTROL) BUS

PORT A CONTROL
PORT B may be MODE 0
(or MODE 1)
ELEG 3230 - Part 9 22
 8255A Control Words
a How to set 8255A? – by control words
a Two control word formats are used:
(1) mode-set control word format : to set the modes of each port
(2) port C bit set/rest control word format : to set the particular bit in
port C. (such that 8255 can send a “1” or “0” via a particular bit to
other devices)
a These two formats can be differentiated by the MSB of the control
word.

a The control words can be sent to the corresponding 8255A’s

address by using I/O instruction.
Ex. Assume 8255A is located at 0FFF8H, control register address
is 0FFFEH, and the control word is to be set to 10001110B
→ MOV AL, 10001110B
MOV DX, 0FFFEH
OUT DX, AL Q: Why there are two address for 8255?
ELEG 3230 - Part 9 23
8255A Control Word Formats
CONTROL WORD

D7 D6 D5 D4 D3 D2 D1 D0 GROUP B

PORT C (LOWER)
1 = INPUT
0 = OUTPUT
PORT B
1 = INPUT
0 = OUTPUT
MODE SELECTION
0 = MODE 0
1 = MODE 1

GROUP A

PORT C (UPPER)
1 = INPUT
0 = OUTPUT
PORT A
1 = INPUT
0 = OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2

MODE SET FLAG (a) Mode-set control word

1 = ACTIVE

ELEG 3230 - Part 9 24

8255A Control Word Formats
CONTROL WORD
BIT SET/RESET
D7 D6 D5 D4 D3 D2 D1 D0
1 = SET
0 = RESET

X X X BIT SELECT
DON’T CARES 0 1 2 3 4 5 6 7
0 1 0 1 0 1 0 1 B0
0 0 1 1 0 0 1 1 B1
0 0 0 0 1 1 1 1 B2

BIT SET/RESET
FLAG 0=FLAG

(b) Port C bit set/reset control word

ELEG 3230 - Part 9 25

Control Word examples for 8255A
Suppose we want to set :
Port A as mode 0 output
Port B as mode 1 input
D7 D6 D5 D4 D3 D2 D1 D0 Port C upper as inputs
Port C bit 3 output and set bit 3
1 0 0 0 1 1 1 0
PORT C Lower (incl. BIT 3 )= OUT
PORT B INPUT
PORT B MODE 1
PORT C UPPER = IN
PORT A OUTPUT
PORT A MODE 0
MODE SET WORD

(a) mode-set control word

ELEG 3230 - Part 9 26
Control Word examples for 8255A
(cont.)

D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 1 1 1

SET BIT

Select BIT # 3

MUST BE 0*
BIT SET/ RESET WORD

*:D6-D4 are set to 0 for simplicity and compatibility with future product.

(b) Port C bit set/reset control word to set bit 3

ELEG 3230 - Part 9 27
 Strobed Output Operation
of 8255A (Mode 1 Port A)
For example when outputting data to printer.
Mode 1 Port A

Port A
CONTROL WORD
INTE A
PC6 ACK
(PC6) D7 D6 D5 D4 D3 D2 D1 D0
PC7 OBF 1 0 1 0 1/0
2 1
PC4+5
1 = INPUT
3
PC3 INTR 0 = OUTPUT

PC4+5 I/O

Internal structure
ELEG 3230 - Part 9 28
 Strobed Output Operation
of 8255A (Mode 1 Port B)
Mode 1 Port B

Port B
INTE B
PC2 ACK
(PC2) CONTROL WORD

5 4
PC1 OBF D7 D6 D5 D4 D3 D2 D1 D0
1 1 0

6
PC0 INTR

Internal structure
ELEG 3230 - Part 9 29
 Signal Definition of Mode 1
Strobed Output
a Whenever data are written to a port programmed as a strobed output
port, the OBF signal becomes a logic 0 to indicate that data are present
in the port latch (buffer) and is ready for external device to access. The
external device strobes the ACK signal to indicate it has received the
data. The ACK returns the OBF to logic 1.

a OBF an output that goes low whenever data are output (using OUT)
from CPU to the port A or port B latch; a strobe signal.
a ACK an Acknowledge signal that causes OBF pin to return to a logic
1. This signal is a response from external device to indicate it
has received data from 8255 port.
a INTR a signal that is often used to interrupts the processor when the
external device receives the data and sends back the ACK signal.
a INTE an internal bit programmed to enable or disable the INTR pin.
INTE A is programmed as PC6 (for output mode) or PC4 (for
input mode) and INTEB is PC2 (for both input/output mode).
(Also check 8255 data sheet in course web site http://course.ie.cuhk.edu.hk/~ieg3810/msm82c55a-2rs-gs-vjs.pdf )
ELEG 3230 - Part 9 30
 Strobed Output Operation
(Mode 1) of 8255A

(Program) OUT DataStrobe

WR

OBF (buffer full)

INTR (Interrupt requested)

ACK

Port

CPU sent data to port data removed from port

Timing diagram Q: who sends what data?
Data flow: CPU → port buffer → external device
ELEG 3230 - Part 9 31
 Example of Strobed Output
Mode of Operation for 8255A

8255A printer

PB0 D0

ASCII

PB7 D7

ACK
PC2 ACK

PC4 DS (Data Strobe)

8255A connected to a parallel printer interface

(Note that PC4, rather than the OBF on PC1 for port B, is used for data
strobe in this example.)
ELEG 3230 - Part 9 32
 Example of Strobed Output Mode of
Operation for 8255A (cont.)
;a procedure that transfers an ASCII-coded character from AH to the printer via port B
PORTC EQU 62H
PORTB EQU 61H
COMMAND EQU 63H ; control word

BIT1 EQU 2
PRINT PROC NEAR
Jump if ;check for printer ready
Z=1 or Check if printer has
IN AL,PORTC ;get OBF
AL AND BIT1=0 or accessed the previous
TEST AL,BIT1 ;test OBF
OBF=0 data in the port buffer
JZ PRINT ;jump if OBF = 0
;send character to printer via port B
MOV AL,AH ;get character
OUT PORTB,AL ;send it
;send DS to printer
MOV AL,8 ;clear DS (data strobe pin on printer)
OUT COMMAND,AL ; 8=00001000B -> reset PC4 Check mode set
MOV AL,9 ;set DS control word format
OUT COMMAND,AL ; 9=00001001B -> set PC4
RET
PRINT ENDP
ELEG 3230 - Part 9 33
 Strobed Input Operation
of 8255A (Mode 1 Port A)
Mode 1 Port A For example when inputting data from keyboard.

Port A
INTE A CONTROL WORD
PC4 STB
(PC4)
D7 D6 D5 D4 D3 D2 D1 D0
PC5 IBF
2 1 1 0 1 1 1/0

For PC6+7
3 1 = INPUT
PC3 INTR
0 = OUTPUT

PC6+7 I/O

Internal Structure
ELEG 3230 - Part 9 34
 Strobed Input Operation
of 8255A (Mode 1 Port B)
Mode 1 Port B

Port B
INTE B
CONTROL WORD
PC2 STB
(PC2)

PC1 D7 D6 D5 D4 D3 D2 D1 D0
5 4 IBF
1 1 1

6
PC0 INTR

Internal Structure
ELEG 3230 - Part 9 35
 Strobed Input Operation
(Mode 1) of 8255A
Level 0 trigger Port Latch

STB

IBF
(buffer full)
INTR
(Interrupt requested)
RD

Port

data strobed into port data read by microprocessor

Timing diagram
Data flow: external device → port buffer → CPU
ELEG 3230 - Part 9 36
 Example Procedure of
keyboard encoder reading
;procedure that reads the keyboard encoder and returns with the ASCII character in AL
=0020 BIT5 EQU 20H
=0022 PORTC EQU 22H
=0020 PORTA EQU 20H

0000 READ PROC NEAR

Junp if Z=1 or
0000 E4 22 AL AND BIT5=0 IN AL,PORTC ;read port C
0002 A8 20 or IBF=0 TEST AL,BIT5 ;test IBF (PC5)
0004 74 FA JZ READ ;jump if IBF = 0

0006 E4 20 IN AL,PORTA ;read ASCII code

0008 C3 RET

0009 READ ENDP

ELEG 3230 - Part 9 37
Mode 2 Operation of 8255A
Bi-directional mode 2
1
3 PC3 INTR
2
3
Port A

1 2 OBF
PC7

3 INTE
1 PC6 ACK

1 2 INTE
PC4 STB
2

PC5 IBF

PC2 - PC0 I/O

Internal Structure
ELEG 3230 - Part 9 38
 Mode 2 Operation of 8255A
WR

OBF

INTR

ACK

STB

IBF

Port A

RD
Data stored in port A
Data read from port A
Data output (OUT) to port A
Data input (IN) from port A
Timing diagram
ELEG 3230 - Part 9 39
 Example Procedure of output
through bidirectional bus data
;procedure that transmits AH through the bi-directional bus of port A
=0080 BIT7 EQU 80H
=0062 PORTC EQU 62H
=0060 PORTA EQU 60H

0000 TRANS PROC NEAR

;test OBF
0000 E4 62 IN AL,PORTC ;get OBF
0002 A8 80 TEST AL,BIT7 ;test OBF
0004 74 FA JZ TRANS ;jump if OBF = 0
;send data
0006 8A C4 MOV AL,AH ;get data
0008 E6 60 OUT PORTA,AL ;output data to port A
000A C3 RET

000B TRANS ENDP

ELEG 3230 - Part 9 40

 Example Procedure of
bidirectional bus data input
;procedure that inputs data from the bi-directional bus and returns with it in AL

=0020 BIT5 EQU 20H

=0062 PORTC EQU 62H
=0060 PORTA EQU 60H

0000 READ PROC NEAR

;test IBF
0000 E4 62 IN AL,PORTC ;get IBF
0002 A8 20 TEST AL,BIT5 ;test IBF
0004 74 FA JZ READ ;jump if IBF = 0
;read data
0006 E4 60 IN AL,PORTA
0008 C3 RET

0009 READ ENDP

ELEG 3230 - Part 9 41

 8255A Status Word Format (Port
C) for Mode 1 Input and Output
PORT C BITS
Set bit value of Port
C for certain signals D7 D6 D5 D4 D3 D2 D1 D0

GROUP A STATUS GROUP B STATUS

INPUT PORT INPUT PORT

D7 D6 D5 D4 D3 D2 D1 D0
I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB
STB STB
OUTPUT PORT OUTPUT PORT

D7 D6 D5 D4 D3 Note: Here STB and ACK D2 D1 D0

are input (not set by the
OBF A INTEA I/O I/O INTRA program) through INTEB OBF B INTRB
particular bit of Port C.
ACK ACK
ELEG 3230 - Part 9 42
Interfacing a Microprocessor to
Keyboard

Keyswitch Types

(a) Membrane

(c) Hall Effect

(100M key strokes)

(b) Capacitive (D. Hall Fig 9-18)

20M key strokes

ELEG 3230 - Part 9 43

 Detecting a Matrix Keyboard
Keypress
+5V

Q:
Assume key “9” is pressed.
+5V
For the following cases,
OUTPUT C D E F
PORT 01 what are the values of D3-
Y D0 D0 at Port 2?
8 9 A B
X
(1). Port 1, D3-D0=0000
D1
4 5 6 7
(2). Port 1, D3-D0=1110
O
row

(3). Port 1, D3-D0=1101

Y D2
0 1 2 3
O open close
high high high (1) Port 2, D3-D0=1011
X (1) D3
low high low INPUT 10 K Ω (2) Port 2, D3-D0=1111
(0) PORT 02
D7
D6 (3) Port 2, D3-D0=1011
X,Y: control
column

D5
O: Output D4
D3
D2 Q: How to detect if no key is pressed?
D1
D0 Q: How to detect which (one) key is
Port connections pressed?
ELEG 3230 - Part 9 44
 Detecting a Matrix Keyboard
Keypress

KEYBRD Read Output

Columns Zero to
One Row
Zero to
DETECT
Read
All Rows N Key
Pressed? Columns

Y
ENCODE
N Key Found?
Read Wait
Columns 20 ms DEBOUNCE
Y
Convert
Read
to HEX
N All Keys Y Columns
Open?
N Key Y RETURN
Pressed?

(D. Hall)
Flowchart for procedure
ELEG 3230 - Part 9 45
 Assembly Program for Keybrd
Detect, Debounce and Encode
1 ;8086 Program F9-20.ASM
2 ;Abstract : Program scans and detect a 16 - switch keypad
3 ; It initializes the ports below and then calls a procedure
4 ; to input an 8 - bit value from a 16 - switch keypad and encode it.
5 ; Ports : SDK-86 board Port P1A (FFF9H) - output, P1B(FFFBH) - input
6 ; Procedures : Calls KEYBRD to scan and decode 16 - switch keypad
7 ; Registers : Uses CS, DS, SS, SP, AX, DX
8 Q: Why, e.g., 7Eh corresponds to “3”?
9 0000 DATA SEGMENT WORD PUBLIC
10 ; 0 1 2 3 4 5 6 7
11 0000 77 7B 7D 7E B7 BB BD BE TABLE DB 77H, 7BH, 7DH, 7EH, 0B7H, 0BBH, 0BDH, 0BEH
12
13 ; 8 9 A B C D E F
14 0008 D7 DB DD DE E7 EB ED + DB 0D7H, 0DBH, 0DDH, 0DEH, 0E7H, 0EBH, 0EDH, 0EEH
15 EE
16 0010 DATA ENDS
17 0000 STACK_SEG SEGMENT
18 0000 1E*(0000) DW 30 DUP(0) ;set up stack of 30 words with value 0
19 TOP_STACK LABEL WORD ;pointer to top of stack
20 003C STACK_SEG ENDS

ELEG 3230 - Part 9 46

 Assembly Program for Keybrd
Detect, Debounce and Encode
21
22 0000 CODE SEGMENT WORD PUBLIC
23 ASSUME CS:CODE, DS:DATA, SS:STACK_SEG
24 0000 B8 0000s START: MOV AX, STACK_SEG ; Initialize stack
25 0003 8E D0 MOV SS, AX ; segment register and
26 0005 BC 003Cr MOV SP, OFFSET TOP_STACK ; top of stack
27 0008 B8 0000s MOV AX, DATA
28 000B 8E D8 MOV DS, AX
29 ; initialize ports, mode 0, Port A for output, Ports B & C for input
30 000D BA FFFF MOV DX, 0FFFFH ; Put port control register address in DX
31 0010 B0 8B MOV AL, 10001011B ; Code: control word 8BH
32 0012 EE OUT DX, AL ; Send control word
33 0013 E8 0001 CALL KEYBRD
34 0016 90 NOP
35 ; Program will continue here with other tasks
36
37 ; 8086 PROCEDURE KEYBRD
38 ; Abstract : Procedure gets a code from a 16 - switch and decodes it.
39 ; It returns the code for the keypress in AL and AH = 00. If there
40 ; is an error in the keypress then it returns AH = 01.

ELEG 3230 - Part 9 47

 Assembly Program for Keybrd
Detect, Debounce and Encode
41 ; Ports : Uses SDK - 86 ports P1A (FFF9H) for output and P1B (FFFBH) for input
42 ; Inputs : Keypress from port
43 ; Outputs : Keypress code or error message in AX
44 ; Procedures : None used
45 ; Registers : Destroys AX
46
47 0017 KEYBRD PROC NEAR
48 0017 9C PUSHF ; Save registers used
49 0018 53 PUSH BX
50 0019 51 PUSH CX
51 001A 52 PUSH DX
52 ; Send 0’s to all rows
53 001B B0 00 MOV AL, 00
54 001D BA FFF9 MOV DX, 0FFF9H ; Load output address
55 0020 EE OUT DX, AL ; Send 0’s
56 ; Read columns to see if all keys are open
57 0021 BA FFFB MOV DX, 0FFFBH ; Load input port address
58 0024 EC WAIT_OPEN: IN AL, DX
59 0025 24 0F AND AL, 0FH ; Mask row bits
60 0027 3C 0F CMP AL, 0FH ; Wait until no keys pressed
ELEG 3230 - Part 9 48
 Assembly Program for Keybrd
Detect, Debounce and Encode
61 0029 75 F9 JNE WAIT_OPEN ; If key pressed, go back
62 ; Read columns to see if a key is pressed
63 002B EC WAIT_PRESS: IN AL, DX ; Read columns
64 002C 24 0F AND AL, 0FH ; Mask row bits Detect
65 002E 3C 0F CMP AL, 0FH ; See if keypressed
66 0030 75 F9 JE WAIT_PRESS
67 ; Debounce keypress
68 0032 B9 16EA MOV CX, 16EAH ; Delay for 20ms
69 0035 E2 FE DELAY: LOOP DELAY
70 ; Read columns to see if key still pressed
71 0037 EC IN AL, DX
72 0038 24 0F AND AL, 0FH
73 003A 3C 0F CMP AL, 0FH
74 003C 74 ED JE WAIT_PRESS Q: Why sends 0FEh on Port A?
75 ; Find the key
76 003E B0 FE MOV AL, 0FEH ; Initialize a row mask with bit-0
77 0040 8A C8 MOV CL, AL ; low and save the mask
78 0042 BA FFF9 NEXT_ROW: MOV DX, 0FFF9H ; Send out a low on one row
79 0045 EE OUT DX, AL
80 0046 BA FFFB MOV DX, 0FFFBH ; Read columns and check for low
ELEG 3230 - Part 9 49
 Assembly Program for Keybrd
Detect, Debounce and Encode
81 0049 EC IN AL, DX
82 004A 24 0F AND AL, OFH ; Mask out row code
83 004C 3C 0F CMP AL, OFH ; If low in a column then
84 004E 75 06 JNE ENCODE ; key column found, so encode it
85 0050 D0 C1 ROL CL, 01 ; else rotate mask
86 0052 8A C1 MOV AL, CL
87 0054 EB EC JMP NEXT_ROW ; and look at next row
88 ; Encode the row/column information
89 0056 BB 000F ENCODE: MOV BX, 000FH ; Set up BX as a counter
90 0059 EC IN AL, DX ; read row and column from port
91 005A 3A 87 0000r TRY_NEXT: CMP AL, TABLE[BX] ; Compare row/column code with table entry
92 005E 74 08 JE DONE ; Hex code in BX
93 0060 4B DEC BX ; Point at next table entry
94 0061 79 F7 JNS TRY_NEXT
95 0063 B4 01 MOV AH, 01 ; Pass an error code in AH
96 0065 EB 05 90 JMP EXIT
97 0068 8A C3 DONE: MOV AL, BL ; Hex code for key in AL
98 006A B4 00 MOV AH, 00 ; Put key-valid code in AH
99 006C 5A EXIT: POP DX ; Restore calling program
100 006D 59 POP CX ; registers

ELEG 3230 - Part 9 50

Assembly Program for Keybrd
Detect, Debounce and Encode
101 006E 5B POP BX
102 006F 9D POPF
103 0070 C3 RET
104 0071 KEYBRD ENDP
105 0071 CODE ENDS
106 END

ELEG 3230 - Part 9 51

Interfacing to Alphanumeric Display

(a) 18-segment (b) 5 by 7 dot matrix

display display format

(c) 5 by 7 dot matrix

circuit connections
(D Hall Fig 9-23)
ELEG 3230 - Part 9 52
Circuit Driving a 7-Segment LED
with 7447

+5V

MAN 7

160 Ω EACH

13 12 11 10 9 15 14 +6V
a b c d e f g
16 5
+5V Vcc BI
4
8 RBI
GND 7447 3
LT

A B C D
7 1 2 6

BCD INPUTS

ELEG 3230 - Part 9 53

Multiplexing 7-segment Displays
with a Microcomputer

Q: Only one 7447 for all 7 digits. → display the same values for all?
A: time-multiplexing
ELEG 3230 - Part 9 54
 8254 Software-Programmable
Timer/Counter
a 8254 is very versatile and can be used in many applications.
a There are several modes of operation for different applications.
a Intel 8253 and 8254 are almost pin-to-pin compatible except
` The maximum input clock frequency for 8253 and 8254 is 2.6 MHz
and 8 MHz, respectively. (10 MHz for 8254-2)
` 8254 has a read-back feature which allows you to latch the count in all
the counters and the status of the counter at any point. 8253 does not
have this feature.
a 8254 contains three 16-bit counters. The counter can be
programmed to load the initial count, start and stop the count.
a 8254 has an 8-bit interface to data bus, and two address input A0
and A1 to address each of the three counters.

ELEG 3230 - Part 9 55

 8254 Block Diagram
CLK 0
DATA COUNTER GATE 0
D7-D0 8 BUS 0 OUT 0
BUFFER

RD

INTERNAL BUS
WR READ/ CLK 1
WRITE COUNTER GATE 1
A0 1
A1 LOGIC OUT 1

CS
CLK 2
CONTROL COUNTER
WORD GATE 2
2
REGISTER OUT 2

ELEG 3230 - Part 9 56

8254 Pin Configuration

D7 1 24 Vcc
D6 2 23 WR
D5 3 22 RD
D4 4 21 CS
D3 5 20 A1
D2 6 19 A0
8254
D1 7 18 CLK2
D0 8 17 OUT2
CLK 0 9 16 GATE2
OUT 0 10 15 CLK1
GATE 0 11 14 GATE1
GND 12 13 OUT1

ELEG 3230 - Part 9 57

Internal Block Diagram of a Counter
INTERNAL BUS

CONTROL STATUS
WORD LATCH
REGISTER
CRM CRL
STATUS
REGISTER

CRM: Count Register MSB

CE
CRL: Count Register LSB
CONTROL
LOGIC CE : Counter Element
OLM: Output Latch MSB
OLL: Output Latch LSB

OL M OL L

GATE n

CLK n OUT n

ELEG 3230 - Part 9 58

 Initializing 8254
a When power on, programmable peripheral devices such as
8254 are usually in undefined state. → need initialization
a Initialization steps: (D. Hall Fig 8-14, 8-15, 8-16)
1. Determine the base address of the device from the address decode
circuitry or the address decoder truth table.
2. Determine the internal address for each 8254 internal device (control
register, port, counters, status register, etc.)
3. “Add” each of the internal address to the system base address to
determine the system address of each device.
4. Look in data sheet for the device for the format of the control word(s)
that you have to send to the device to initialize it.
5. Construct the control word required to initialize the device.
6. Send the control word to the device. (programming part)
7. In case of the 8254, you need to send the starting count to each of the
counter registers. ELEG 3230 - Part 9 59
 8254 Addresses

A1 A0 SELECTS
0 0 COUNTER 0
Internal 0 1 COUNTER 1
1 0 COUNRER 2
1 1 CONTROL WORD REGISTER

SYSTEM ADDRESS 8254 PART

F F 0 1 COUNTER 0 Register
System* F F 0 3 COUNTER 1 Register
F F 0 5 COUNTER 2 Register
F F 0 7 CONTROL Register

*Note : This system address is for the example in D. Hall Fig 8-14, and may vary for
different circuit. In this example, 8254’s A1 and A0 are connected to CPU’s address pin
A2 and A1. Also check 784LS138 connections.
ELEG 3230 - Part 9 60
 Example of 8254 Circuit

74LS138

Q: Find the system port address for the three counters and control register.
ELEG 3230 - Part 9 61
 Address Decoding via LS138
a To activate the output Y4 of LS138 in the previous example, G1 shall be high
and G2(A&B) shall be low.
a From the previous figure, we note that
G1=~A7*~A6*~A5
~G2A=~(A15*…*A8)
~G2B=M/~IO

a Thus LS138 will be selected when M/~IO is low and

the system address is
1111 1111 000X XXXX

a And Y4 is will be selected when CBA=100 or A0=1, A4=A3=0; therefore the

system address for 8254 is
1111 1111 0000 0XX1
a The remaining A2 and A1 pins are connected to A1 and A0 of 8284 for counter
and register selection.
a So the system address for counter 0-3 and control register are 0FF01h, 0FF03h,
0FF05h, 0FF07h, respectively, in the previous example.
ELEG 3230 - Part 9 62
8254 Control Word Format
A1A0 = 11 CS = 0 WR = 0 RD = 1

D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC0 RW1 RW0 M2 M1 M0 BCD

(1) SC - Select Counter

SC1 SC0
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Read-Back Command
(see Read Operations)

ELEG 3230 - Part 9 63

8254 Control Word Format (cont.)
(2) RW - Read/ Write
RW1 RW0
0 0 Counter Latch Command
(see Read Operations)
0 1 Read/Write least significant byte only
1 0 Read/Write most significant byte only
1 1 Read/Write least significant byte first
then most significant byte

(4) BCD
0 Binary Counter 16-bits
1 Binary Coded Decimal (BCD) Counter
(4 Decades)

ELEG 3230 - Part 9 64

8254 Control Word Format (cont.)
(3) M - Mode

M2 M1 M0
0 0 0 Mode 0 - Interrupt on Terminal Count
0 0 1 Mode 1 - Hardware One-Shot
× 1 0 Mode 2 - Pulse Generator
× 1 1 Mode 3 - Square Wave Generator
1 0 0 Mode 4 - Software Triggered Strobe
1 0 1 Mode 5 - Hardware Triggered Strobe

NOTE:
Don’t Care bits (×) should be 0 to insure
compatibility with future Intel products

ELEG 3230 - Part 9 65

 A Few Possible Programming
Sequences to initialize 8254
a The control words and initial counts of each counter can be sent in many
different ways. But for each counter, always send the control word and then
initial count(s).
Example 1 A1 A0 Example 2 A1 A0
Control Word - Counter 0 1 1 Control Word - Counter 2 1 1
LSB of Count - Counter 0 0 0 Control Word - Counter 1 1 1
MSB of Count - Counter 0 0 0 Control Word - Counter 0 1 1
Control Word - Counter 1 1 1 LSB of Count - Counter 2 1 0
LSB of Count - Counter 1 0 1 MSB of Count - Counter 2 1 0
MSB of Count - Counter 1 0 1 LSB of Count - Counter 1 0 1
Control Word - Counter 2 1 1 MSB of Count - Counter 1 0 1
LSB of Count - Counter 2 1 0 LSB of Count - Counter 0 0 0
MSB of Count - Counter 2 1 0 MSB of Count - Counter 0 0 0

Example 3 A1 A0 Example 4 A1 A0
Control Word - Counter 0 1 1 Control Word - Counter 1 1 1
Control Word - Counter 1 1 1 Control Word - Counter 0 1 1
Control Word - Counter 2 1 1 LSB of Count - Counter 1 0 1
LSB of Count - Counter 2 1 0 Control Word - Counter 2 1 1
LSB of Count - Counter 1 0 1 LSB of Count - Counter 0 0 0
LSB of Count - Counter 0 0 0 MSB of Count - Counter 1 0 1
MSB of Count - Counter 0 0 0 LSB of Count - Counter 2 1 0
MSB of Count - Counter 1 0 1 MSB of Count - Counter 0 0 0
MSB of Count - Counter 2 1 0 MSB of Count - Counter 2 1 0

NOTE: (1) In all four examples, all Counters are programmed to read/write two-byte counts.
(2) When programmed in 2-byte, the first ELEG
byte (LSB)
3230will- stop
Partthe
9 count. The second byte (MSB) will 66
start the counter with the new count.
 Example of a control word
Task: Use counter 0 of the 8254 to divide a clock signal at 2.45 MHz to
78.6 kHz (→1/32).

MOV AL, 00010111B ; Control word for counter 0

; Read/write LSB only, mode 3, BCD countdown
; 00 01 011 1
; BCD countdown
; Mode 3
; R/W LSB only
; Select counter 0
MOV DX, 0FF07H ; Point at 8254 control register (see page 54)
OUT DX, AL ; Send control word
MOV AL, 32H ; Load lower byte of count
MOV DX, 0FF01H ; Point to counter 0 count register
OUT DX, AL ; Send count to count register
ELEG 3230 - Part 9 67
Six Modes of Operation for 8254
Programmable Interval Timer

(Brey Fig10-35)

The G input stopsELEG 3230 - Part

the count when 9 0 in modes 2, 3 and 4 68
 8254 Mode Operation
a Mode 0: Allows 8254 counter to be used as an event counter. The
output becomes a logic 0 when the control word is written and remains
until “N” plus the number of programmed counts.

a Mode 1: Causes the counter to function as a retriggerable monostable

multivibrator (one shot). In this mode, the G input triggers the counter so
that it develops a pulse at the OUT pin that becomes a logic 0 for the
duration of the counter. If the count is 10, then the OUT pin goes low for
10 clock period when triggered. If the G input occurs within the duration
of the output pulse, the counter is again reloaded with the count and the
OUT pin continues for the total length of the count.

a Mode 2: Allows the counter to generate a series of continuous pules

that are one clock pulse in width. The separation between pulses is
determined by the count. (periodic pulse generator)
ELEG 3230 - Part 9 69
 8254 Mode Operation (cont.)
a Mode 3: Generates a continuous square-wave at the OUT pin,
provided the G pin is a logic 1. If the count is even, the output is high for
one-half of the count and low for one-half of the count. If the count is odd,
the output is high for one clocking period longer than it is low.

a Mode 4: Allows the counter to produce a single pulse at the output. If

the count is 10, the output is high for 10 clocking period and then low for 1
clocking period. (software-triggered strobe) (Writing the count to the
counter register starts the count.)

a Mode 5: A hardware triggered one-shot that functions as mode 4

except that it is started by a trigger pulse on the G pin instead of by
software. This mode is also similar to mode 1 because it is retriggerable.
(hardware-triggered strobe) (Count will be transferred to counter register
after trigger goes high.) ELEG 3230 - Part 9 70
8254 Example Timing Diagrams
CW=10 H →
counter 0, mode 0,
LSB R/W only,
binary count

MODE 0
ELEG 3230 - Part 9 MODE 1 71
8254 Example Timing Diagrams

New count value will not be reloaded until

end of the current count or until the gate is
re-enable. MODE 3
MODE 2
(periodic pulse generator) ELEG 3230 - Part 9 (square-wave generator) 72
8254 Example Timing Diagrams

MODE 4 MODE 5
(software-triggered strobe) (hardware-triggered strobe)
ELEG 3230 - Part 9 73
 Gate Pin Operations Summary
Signal
Low or Going
Status Rising High
Low
Modes
0 Disables Counting ----------- Enables Counting
1 ----------- 1) Initializes Counting -----------
2) Resets Output after
Next Clock
2 1) Disables Counting Initializes Counting Enables Counting
2) Sets Output
Immediately High
3 1) Disables Counting Initializes Counting Enables Counting
2) Sets Output
Immediately High
4 Disables Counting ----------- Enables Counting
5 ----------- Initializes Counting -----------
ELEG 3230 - Part 9 74
Minimum and Maximum Initial Counts

Mode Min Count Max Count

0 1 0
1 1 0
2 2 0
3 2 0
4 1 0
5 1 0

NOTE:
0 is equivalent to 216 (0FFFFh+1) for binary counting and 104 (9999+1)
for BCD counting

ELEG 3230 - Part 9 75

 Reading a Counter
a Each counter has an internal latch that can be read with the
read counter port operation.
a The latch value usually follows the count.
a When the count is needed, the latch can remember the count
by programming the counter latch control word, which causes
the content of the counter to be held in a latch until it is read.
a When there are more than one counters to be read, we use
the read-back control word.
a If the status register is to be latched, then STATUS=0. (pp76)
a The status register shows the state of the OUT pin: whether
the counter is at its null state, and how the counter is
programmed.
ELEG 3230 - Part 9 76
Counter Latching Command Format
A1A0 = 11; CS = 0; RD = 1; WR = 0
SC1,SC0 - D7 D6 D5 D4 D3 D2 D1 D0
Specify counters SC1 SC0 0 0 × × × ×
to be latched

SC1 SC0 Counter

0 0 0
0 1 1 for latching single
counter only
1 0 2
1 1 Read-Back Command for latching multiple
counters
D5, D4 - 00 designates Counter Latch Command
× - don’t care NOTE: Don’t Care bits (×) should be 0 to insure
compatibility with future intel products

Q: How do we know this is counter latching command?

ELEG 3230 - Part 9 77
Read-Back Command Format
For latching multiple counters:

A1A0 = 11 CS = 0 RD = 1 WR = 0

D7 D6 D5 D4 D3 D2 D1 D0
1 1 COUNT STATUS CNT 2 CNT 1 CNT 0 0

D5: 0 = Latch the count of selected counter(s)

D4: 0 = Latch the status of selected counter(s)
D3: 1 = Select counter 2
D2: 1 = Select counter 1
D1: 1 = Select counter 0
D0: Reserved for future expansion. Must be 0

ELEG 3230 - Part 9 78

 8254 Status Register

D7 D6 D5 D4 D3 D2 D1 D0
OUTPUT NULL COUNT RW1 RW0 M2 M1 M0 BCD

D7 1 = OUT Pin is 1
0 = OUT Pin is 0

D6 1 = NULL Count
0 = Count available for reading

D5-D4 Read/Write operation

D3-D1 Counter mode

D0 Logic 1 for BCD counter

ELEG 3230 - Part 9 79
 An Example of Read-Back Command
Sequence and Its Results
Count
D7 D6 D5 D4 D3 D2 D1 D0 Description Result
Assume these commands are sent sequentially

1 1 0 0 0 0 1 0 To Read back count Count and status latched

and status of counter 0 for counter 0

1 1 1 0 0 1 0 0 To Read back status of Status latched for Counter

counter 1 1

1 1 1 0 1 1 0 0 To Read back status of Status latched for counter 2,

counter 2, 1 but not* counter 1

1 1 0 1 1 0 0 0 To Read back count of Count latched for counter 2

counter 2

1 1 0 0 0 1 0 0 To Read back count Count latched for counter 1,

and status of counter 1 but not* status

1 1 1 0 0 1 0 0 To Read back status of Command ignored, status

counter 1 already latched for counter
1

Status *: already latched

ELEG 3230 - Part 9 80
Read-Back Command Example (cont.)
a If multiple count and/or status read-back commands are issued to the
same counter(s) without intervening reads, all but the first are ignored.

a After the counter register or status register is latched, the content can be
read by instruction
IN AL, counter_n_address
a If both the count and status of a counter are latched, the first read
operation of that counter will return the latched status, regardless of
what was latched first. The next one or two read will return the latched
count.
a Subsequent read will return unlatched count.

ELEG 3230 - Part 9 81

 FAQ
a Q: When does the counter decide whether to continue the count? For example, in mode 0,
the middle case, the G becomes low during the second half cycle of the (03)cycle. (See Fig
8-18 or Lecture note part 10, pp70). Why does the count still go low in the next cycle.
a A: (see Intel data book) The GATE input is always sampled on the rising edge of CLK. In
mode 0,2,3 and 4, the the GATE input is level sensitive, and the logic level is sampled on
the rising edge of CLK. In mode 1,2,3, and 5 the rising edge of GATE (trigger) sets an
edge-sensitive flip-flop in the counter. This flip-flop will then be sampled on the next rising
edge of CLK; the flip-flop is reset immediately after it is sampled. In this way, the G does not
need to be maintained at high until the next rising edge if CLK. Note that mode 2 and 3 are
both edge- and level-sensitive, both the level and the rising edge of G has effect on the
counter output. (see page 72 about gate pin operation summary).

a Q: In mode 4, it generates a low pulse when it reaches 0 and continue to count

down from 0FFFFh. Will it generate another low pulse when it reaches 0 count again?
a A: In mode 4, only one low pulse is generated while zero count is reached and there is no
pulse from the OUT till next write to counter latch operation,i.e. OUT keeps high all the way.
The counter may continue counting.

ELEG 3230 - Part 9 82

 FAQ
a Q: What is the purpose of INTR in the diagram on pp30? Is the INTR sent to
8088? But isn't the 8088 outputting data low? why should 8255 interrupt it?
a A:Yes. 8088 is outputting data to the external device through 8255. Here, the key
is 8255. When 8088 has finished writing data into 8255. The "out dx, al" command
will be finished regardless whether the external device has received the data from
8255 successfully. So, if 8088 needs to output data to the device again, how can it
know if the device is free? Well, two ways: (i) The first one is to loop and check
the state of 8255 OBF pin to determine if the previous output is successful. (ii) the
other method is to ask 8255 to "report" immediately to 8088 when the operation
has been finished. And this is exactly what the INTR in the diagram does. When
the external device acknowledges 8255 that data has been received, 8255 will pull
high the INTR which if 8088 has interrupt flag set, it will be interrupted and then
can proceed on the next operation

ELEG 3230 - Part 9 83