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ARM Assembly Language

Course Objective’s:
Arm, Thumb & Thumb-2 Instruction Set’s

FIFO & LIFO Data Structures in Assembly

Finite State Machine (Moor Machine & Mealy Machine)

Algorithms (Binary Search)

Hardware Drivers to configure Peripherals (GPIO, ADC, UART, TIMER, SSR)

Introduction

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ARM Assembly Language 2
 Assembly code and C language code is compiled using Assembler.
Assembler generates Object code.

All the Object files are combined to create a executable image.

While testing we can run this code in debugger which will use additional registers on
the hardware to view the contents on the registers and set and clear break points.

ELF & DWARF are (executable linkable formats - just a naming convention)

Object file stores addition information i.e name of the variable in the high level code
as a asm comment e.g mov r1, #10 ; int a = 10 this is used while debugging.

Assembly Syntax
Arm Instructions have 4 fields separated by spaces or tabs.

Label opcode operand ;comment

Label is optional. Used to find the position of instruction in the memory.

Opcode specifies operation to perform.

Operand is the source / destination of the data opcode to be processed.

Comment is optional. Used to explain the meaning of the code.

store_routine STR R0, [R1] ; store R0 into address present in R1

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 ARM - RISC
Arm uses Reduced Instruction set, instruction set is like a set of words available in
the language.
RISC philosophy is to execute simple but powerful instructions, one instruction per
cycle at high clock speed.

Instructions are executed in pipelines.

RISC provides large set of general purpose registers.
Except LOAD and STORE no other RISC instructions operate only on memory, but
only on registers.

In RISC Architecture complexity of compiler is more than complexity of processor.

ARM - Not Just

RISC
ARM uses both Littlie & Big Endian
Formats

Typical ARM Processor

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 Made of 4 components

Processor (with ARM Core), Controllers

Peripherals & Bus

controller - yellow
Peripherals - green
Bus - blue

Interrupt controller
AHB arbiter

AHB-APB bridge
Memory controller

AHB - external bridge

AHB Advanced High Performance Bus
APB Advanced Peripheral Bus

ARM Bus Technology & AMBA Bus Protocol

Basically there are 2 kinds of devices connected to bus.

Bus Master - is a logical device capable of initiating data transfer with another
device.

Bus Slave - is only capable to responding to a transfer request from the master.

A Bus has 2 architecture levels

Physical Level - electrical characteristics i.e bus width 16, 32 bit etc.

Protocol Level - ARM use AMBA bus protocol.

AMBA : Advanced Microcontroller Bus Architecture

ASB : ARM System Bus

APB : ARM Peripheral Bus

AHB : ARM High Performance Bus

Memory

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 Memory plays a major role in processor.
There are different types of memory cache, RAM, ROM.
cache memory is closest to core, so its fastest to access(size in KB usually).

RAM is main memory (primary) faster than ROM (size MBs to GBs usually).
ROM is secondary memory far from processor, slowest to access (size GB’s usually)

Apart of the type (where it is located wrt process) there are other properties of
memory.

Memory width - number of bits returned on each memory access. (16, 32, 64
etc. )

Cycles required to fetch an instruction from memories with different memory widths.

Memory type based on manufacturing.

ARM has 32 bit core

Internal register bank has 32 bit registers.

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 Data paths are 32 bit.

Bus interfaces are 32 bit.

As ARM has a it can directly address 2^32 (4 GB) address spaces.

ARM memory space can be divided into 5 sections.

On chip peripherals and IO register section can occupy in any of the empty arrays,
depending on the chip manufacturer.
SFR section is for Special Function Registers.

Peripherals
All ARM peripherals are memory mapped. This means programming interfaces to
this register is a set of memory address registers, accessed with relative offset from
specific peripheral base address.

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 Memory Controller
A memory controller connects different types of memory to the processor.
Say up of reset some memory types need initial sequence to access the memory,
basically memory controller takes care about such things.

Interrupt Controller
An Interrupt controller determines which peripheral can access processor at a
specific time.

30 General Purpose Registers

6 Status Registers

1 PC

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 17 General Purpose Registers

1 Status Register
3 Interrupt Mask Registers

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 These Special Purpose Registers are cab be accessed by special Instructions.

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 r0-r15 or R0-R15

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 a1-a4 or r0 - r3
r13 or sp or SP
r14 or lr or LR

r15 or pc or PC

Assembly Directives
Assist and control assembly process.
Are also called pseudo-ops.

Not apart of instruction set.

They change the way code is assembled.

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 Use space directive to create a variable and check in which
address they are getting created.
If you create a variable using SPACE directive, the address in which it will be created
will depend on assembly file or memory layout of the processor.

Under stand the use of align directive.

The ALIGN directive aligns the current location to a specified boundary by
padding with zeros or NOP instructions
.
ARM must precede any ARM code. Use of ALIGN ensures that your code is
correctly aligned. By default, the ALIGN directive aligns the current location within
the code to a word (4-byte) boundaryv. ALIGN 2 can also be used to align on a
halfword (2-byte) boundary in Thumb code.

SUB vs SUBS

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 SUB will not effect SPSR (carry, zeroflag...), SUBS sets (SPSR)

Write a small c routines to see how SP and LR are maintain.

MOV R0, #0xBABEFACE

LDR R0, =A

LDR R0, =0XBABEFACE

EQU directive is to create alias for numbers

RN directive is to create alias for registers.

For instructions like LDRB the data byte is present in Least indexed bytes

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 There are 2 kinds of addressing modes in assembly.

1. Pre-Indexed Addressing LDR/STR {size} {cond} <Rd>, [<Rn>, <Offset>] {!}

Note : without ! at the end contents in the Rn remains same.

2.

STR r3, [r8]

r3=0x12345678 r8=0x800000 [Before executing instruction]

r3=0x12345678 r8=0x800000 [After executing instruction]
STR r3, [r8], #4

r3=0x12345678 r8=0x800000 [Before executing instruction]

r3=0x12345678 r8=0x800004 [After executing instruction]

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 Fill the memory contents with some value & copy it into some other location

RAM_ADDR_1 EQU 0x4000000

RAM_ADDR_2 EQU 0x6000000

BYTES_COPY EQU 0x20. ; 32 bytes to be copied

AREA fill_copy , CODE, READONLY

ENTRY

EXPORT __main

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 __main

BX COPY

BX FILL

COPY

MOV R0, =RAM_ADDR_1

MOV R1, =0xDEADBEEF

MOV R2, =BYTES_COPY

L1 STR R1, [R0], #4

SUBS R2, #1

BNE L1

BX LR

FILL

MOV R0, =RAM_ADDR_1

MOV R1, =RAM_ADDR_2

MOV R2, =BYTES_COPY

L2 LDR R3, [R0, #1]!

STR R3, [R1, #1]!

SUBS R2, #1

BNE L2

BX LR

END

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 Constants and Literal Pools

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 0xE3A004FF MOV r0, 0xFF, 8

ARM inbuilt barrel shifter performs rotate right operation, thus the (32 - n) for left
shift operation.

Loading constants into registers

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 Now R8 = 0x200000789, in general sudo instructions are not used to move
constants into registers, but occasionally yes.

Loading constants using MOVW and MOVT

ADR <Rd>, labeel/variable

ADRL <Rd>, label/variable

LDR <Rd>, =label/variable

If we load the address of a code (function/ label or variable) into Rd using ADR
then there will be no change in the address that is loaded into register.

eg : ADR R3, __main ; where __main is in code section at location 0x50000 [

R3=0x50000]

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 ADR R3, VAR1 ; where VAR1 DCD 0x1234 . R3=0x20000 location at which
var1 is stored.

If we load the address of a code (function/ label) into Rd using LDR then there
will be an change in the address by 1 that is loaded into register.

where as for variables the address is not incremented.

eg : LDR R3, __main ; where __main is in code section at location 0x50000

[R3=0x50001]
ADR R3, VAR1 ; where VAR1 DCD 0x1234 . R3=0x20000 location at which
var1 is stored.
Note : ADRL has some thing to do with alignment, need further study.

Solving Equation

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 N Flag:
To indicate result is negative

ADD R0, R1 this will not update N flag in xPSR register.

ADDS R0, R1 this will not update N flag in xPSR register. (R0=-1, R1 = -2)

SUBS R0, R1 (R0=1, R1 =

C Flag:
ADDS R0, R1, R2 if R1=0xFFFFFFFF ; R2=0x5
ADC R3, R4, R5 if R3 = R4 + R5 + CARRY

Note : ADC always follows by a ADDS instruction.

V Fag:
To indicate Signed overflow

ADDS R0, R1 if the result is > 2^32 or < -(2^31).

Z Flag:
To indicate if result is equal to 0.

SUBS R0, R1 Z Flag will get set if the result in R0 is equal to 0.

We can detect and jump to a label using BNE <label>

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 Barrel Shifter:
There are 4 kinds of shifts Logical Shift & Arithmetic Shift.

1. Logical Shift by one bit is equal to multiply by 2^1

Logical shift by n bits equal to multiply by 2^n

2. Arithmetic shit

3. Rotate Right

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 4. Rotate with carry

Note : Basically for a unsigned number logical shift is performed where as for a
signed number processor performs Arithmetic shift.

Note : There is no ROL instruction cause ROL (n) = ROR(32-n).

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 BGE label branch if greater than or equal to.

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 This UDIV will take up to 14 cycles.

Division by 0 in Cortex-M is Handel in 2 ways.(exception & …)

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