Microprocessors and Microsystems 75 (2020) 103040

Contents lists available at ScienceDirect

Microprocessors and Microsystems

journal homepage: www.elsevier.com/locate/micpro

Design of BCD adder with five input majority gate for QCA
V.J. Arulkarthick a,∗, Abinaya Rathinaswamy a, K. Srihari b
a
Department of ECE, JCT college of Engineering and Technology, Tamilnadu, India
b
Department of Computer Science and Engineering, SNS College of Engineering, Coimbatore, Tamilnadu, India

a r t i c l e i n f o a b s t r a c t

Article history: In the digital world BCD numbers play a pivotal role in constituting decimal numbers. New different tech-
Received 25 November 2019 nologies are emerging in order to obtain low area/power/delay factors to replace the CMOS technology.
Revised 4 February 2020
One such technology is quantum cellular automata (QCA) realization, through which many arithmetic cir-
Accepted 14 February 2020
cuits can be designed. This paper deals with the implementation of BCD adder with 5 input majority
Available online 24 February 2020
gates for QCA. The 3 input majority gate and an inverter are basic elements of QCA. In this project amal-
Keywords: gamation of majority gates with 3 and 5 inputs are used instead of implementing the entire circuit using
Microprocessor 3 input majority gate in the BCD i.e. mainly comprised by partly consumed gates and entirely consumed
Communications gates. The proposed is designed and functional verification is done by Verilog HDL and Modelsim version
Microsystems 10.4a. The proposed design has been verified and the delay of existing and proposed design is analysed
using Xilinx tool. The numbers of partly consumed and entirely consumed gates are less when compared
to the existing method of implementation. The delay is reduced compared to the existing system which
shows the improvement of 9.84%. The drawback of crossovers that leads the difficulty in implementation
and reduces the efficiency of the circuit is reduced in the proposed implementation.
© 2020 Elsevier B.V. All rights reserved.

1. Introduction is 3 in decimal format, then the output sum S and carry C is 0101
and 0 respectively in both binary sum and BCD sum [7]. But when
In natural philosophy adders are used to perform addition of the value of sum is more than 9, 1 will set to the value of carry
numbers. Adders are used in several computers and different kinds set and again the sum value will start from 0 0 0 0 to 1001 with
of processors not solely to perform operations in ALUs, however carry 1 for 10 to 19 respectively. The obtained value of sum (if it
additionally in different elements of the processor for address cal- exceeds 9) should be summed up to the value 6, for the purpose
culation, signal processing applications and so on [1]. Approximate of obtaining the BCD code with 1 as carry.
adders, High speed adders and error tolerant adders are the differ- As the VLSI were developed, monstrous operations and various
ent adders used for signal processing applications [2]. concepts were proposed in these streams. Even though VLSI tech-
Even though adders are designed for different numerical for- nologies also have the advantages such as reduced delay, area and
mats, the most common adders handles ones and zeros formats. power factors there are some physical limitations in the technology
The half adder adds two single bits to produce its corresponding of CMOS [8]. In future the concept of “BEYOND CMOS” can begin
output sum and carry. In the same way the full adder produces because the scaling of the present CMOS technology can reach the
two outputs as sum and carries by adding three single bit inputs. basic limit. New technologies are needed to solve the drawback.
Likewise a BCD adder produces a BCD sum by adding the BCD in- Emerging device technology will overcome the scaling drawback
puts [3]. within the current CMOS technology.
Assume that the two inputs are labelled A and B with output Some of the “Beyond CMOS” technologies are RTD, SET and
as sum S and carry C. If the value of A is 0010 in binary equivalent QCA. A QCA represents quantum-dot cellular automata which is
that is 2 in decimal format and B is 0011 in binary equivalent that one of the contestant for the fore coming beyond CMOS genera-
tion [9].
∗
Quantum-dot cellular automata (QCA) is a paradigm without
Corresponding author.
transistor computation that replaces some complex physical prob-
E-mail addresses: [email protected] (V.J. Arulkarthick),
[email protected] (A. Rathinaswamy), [email protected] (K. lems caused by the transistors. Quantum dot cellular automata is
Srihari). having cellular arrangements as an array. Quantum dot is a nano

https://doi.org/10.1016/j.micpro.2020.103040
0141-9331/© 2020 Elsevier B.V. All rights reserved.
2 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040

dimensional semiconductor material with distinguishing property

of conductivity depends on the size of the material. The exact nano
dimension will be nano metre in size. A fundamental cell of QCA
has 4 place holders. Place holders are also called as quantum dots.
The quantum dot can either be empty (dot) or filled with electrons.
The filled dot (electrons) can only be accommodated in opposite
direction in the cell.
The existing systems of the design of decimal full adder en-
tirely consist of majority gate with 3 inputs and NOT gate (in-
verter). This project deals with replacing the MGs by amalgamating
the MGs with 5 and 3 inputs depending on operation requirement
which leads to the reduction of crossover complexities, delay and
the number of gates.
Fig. 1. Abstract view of DFA.

2. Review of literature

The DFA in QCA, studies various proposals.

Keivan Naviet al in [5], presented a novel seven input MGs that
was verified by connections physically and QCA Designer. A seven
input MGs includes seven inputs with one output. This seven in-
put MG is used to obtain basic gates such as AND, OR with four
inputs. Accordingly almost all up-to-date planned styles in QCA is
simplified through this majority device so as to scale back quality,
cell count and latency.
Razieh Farazkish et al. in [6], proposed a novel 5-input major-
ity gate. This new 5 input MG can be achieved by a single layer. It
requires solely ten cells of QCA. Similar to the above literature the
MGs was verified by the connections physically (physical relations)
and simulations. A new design of full adder in QCA technology us-
ing MG based on MG with 5 inputs is used for the verification of
correctness. This design needs solely 2 majority gates and 2 invert-
ers that are enforced by means that of diagonal cells.
The new Full-Adder and former Full-Adder styles are compared
in terms of complexness, space and latency. These designs have
been verified in QCA Designer, a QCA simulation and layout ver-
ification tool. All the 32 states of inputs are checked in order to
verify the accuracy. As the verification was done by the simulation,
it shows that the newly designed Full-Adder using the MGs with Fig. 2. Block Diagram of Conventional BCD Full Adder.
5 inputs reflects a simple arrangement. Moreover it requires less
number of cells and area compared to the previous designs. The
new Full Adder has a supreme configuration compared to other
structures so that is the main reason that this design will lead to numbers. BCD may be a category of encryption within which every
survive in advanced operations. digit is portrayed by some fixed range of bits. BCD binary num-
Subhashee Basu in [13] proposed the realization of gates XOR bers represent decimal digits zero to nine. As an illustration [11],
as well as its complementary gate (XNOR)through innate proper- (8429)10 can be depicted as (10 0 0 010 0 0 010 10 01) in the view of
ties of fundamental gates. The implemented technique reveals the the fact that every numeral in decimal range will be encoded to 0 s
fact that the absence of expanding the number of cells of the cir- and 1 s and chained together for making this type of illustration.
cuitry and size can be achieved when implementing the other fun- The abstract view of DFA is as follows,
damental gates efficiently. As it is known that the XNOR gate is the The addition of BCD will be analogous to traditional 0 s and
complement of XOR, an inverter can be used to collect the output 1saddition. Some excluding situations are, once the total for 2 BCD
of XOR as input and produce the complement of the XOR gate as numerals surpasses nine or a Carry is generated [12], the value
output. Yet the above mentioned for complement operation leads six should be summed together with the sum to convert the error
to enhance the area and entanglement. range into a legitimate number. Thus a new carry will be created
Gurmohan Singh, R.K. Sarin et al. in [4] expressed his idea that by summing the number six to the inappropriate BCD number that
the continuous scaling down of feature size has pushed CMOS will be moved ahead in such a way that it will be forwarded to-
technology to approach its practical and theoretical limits. Lot of wards the succeeding digit of the BCD [14].
research efforts at nano scale are in progress to explore alternate A BCD 1-digit adder circuit will sums up 2 BCD numbers (digits)
viable technologies in coming era of advanced integrated circuits concurrently and also generates the output digit in BCD along with
[10]. QCA is emerging as a potential technology that could be used required correction logic. A conventional implementation of BCD
in fore-coming computing circuits/systems replacing existing Sili- full adder is given as follows in Fig. 2.
con technology. With the intention of examining the output adder of BCD em-
ploys a circuitry to check the output of adder placed first. It veri-
3. Existing system fies whether the output surpassed the value nine. In case of some
illegitimate conditions the adder placed next will start its func-
BCD is the abbreviation of Binary Coded Decimal. A BCD adder tion of summing up a six. Appropriate yield will be obtained from
is the combinative circuitry that sums 2 Binary Coded Decimal the adder other than the first one. In case of legitimate conditions
 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040 3

Fig. 3. Implementation of Eqn (8) to (12).

(within nine) 0 can be added so that the yield offered by both the s1 = M (w1 ∨ cout, coutw1, 0 ) (13)
adders are similar.
In existing system, a BCD adder was implemented with com-
pletely used MGs as well as PUMs. The existing implementation s2 = M (M (w1, w2, cout ), cout ∨ w2, w1w2 ) (14)
was verified by QCA Designer. The conventional equations are
The implementation of the above Eqs. (13) and (14) with mod-
given as follows,
ified S1 and S2 is given in Fig. 4.
ci = M (gi, pi, ci − 1 ) (1)

w3 = g3c1 (2) 4. Proposed system

w2 = g3c1 ∨ p3 p2( p1 ∨ c1 ) ∨ g2g1c1 (3)

Using the modified equations in existing method and the con-
w1 = (M (c2,M (g1, p1, c2 ), c1 )) (4) cept MGs with 5 inputs the proposed method was implemented.
The analysis of existing system which uses the MGs with 3 inputs
w0 = M (c1, M (g0, p0, c1 ), cin ) (5) and the proposed system which uses both the MGs with 5-input
as well as 3-input has been done through the model sim and Xil-
w3 = p3 ∨ c3 (6) inx software. Compared to the existing system the union of MGs
with 5 and 3-inputs will reduce the number of partly consumed
cout = M (g3, p3, p2 ) ∨ ( p3 ∨ g2 ) p1 ∨ ( p3 ∨ M (g2, p2g2 ))c1 (7)
gates (PUMs). In existing system the number of consumed gates
cout = M (w4, w3 ∨ w4, M (w1, w2, w3 )) (8) are 9 and the entirely consumed gates are 16. In proposed method
the PUMs are 8 and entirely consumed gates are 11. So the total
s 3 = M ( w2 , w 4 w 1 , w 3 w 1 ) (9) number of gates used in the proposed method also reduces from
25 majority gates to 19. The delay is reduced from 15.582 ns to
s2 = M (w4 ∨ w1, w3w2, w2 ∨ w1 ) (10) 14.049 ns. The proposed implementation is given below,

s1 = M (w1, w4w1, w3w2 ) ∨ w4 ∨ w3w1 (11)

4.1. MGs with five inputs
s0 = w0 (12)
And the modified equations from the conventional one and the Primarily various explorers had consumed MGs with 3 inputs
implementation diagram is given in Fig. 3. towards implementing the circuits of quantum cellular automata.
To improve the utilization of majority gate and to reduce the Subsequently the necessity for efficiency increases to a greater ex-
problem of crossover complexities, the S1 and S2 equations are fur- tent. As a result MGs with 5 inputs were created. It can be arith-
ther improved as metically given as
4 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040

Fig. 4. Implementation of the existing system.

Fig. 5. Implementation of Proposed method.

M(A, B, C, D, E ) = ABC + ABD + ABE + ACD + ACE + ADE ogy that can be given as
+ BCD + BCE + BDE + CDE (15) c0 = M3(x, y, cin ) (18)

The equation given below represents the 1 binary digit full z = M5(x, y, cin, c0 , c0 ) (19)
adder. It consists of three inputs (X, Y and Cin) and 2 outputs (Z or
M3 in the above expression depicts the MG with 3 inputs and
S, C0 ). Each of the yields and ingoing data are one bit.
M5 depicts MG with 5 inputs. With the help of negator binary ad-
c0 = xy + ycin + cinx (16) dition can be performed which is given below in the generalized
equation. MAJ3 and MAJ5 are same as M3 and M5given in the fol-
s = xycin + x y cin + x ycin + xy cin (17) lowing eqn (20) and (21).
si = MAJ5(ai, bi, ci − 1,ci,ci ) (20)
It is necessary to depict the Eqns (16) and (17) with regard to
MGs for the implementation of adder(full adder) in QCA technol- ci = MAJ3(ai, bi, ci − 1 ) (21)
 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040 5

Fig. 7. Inverter symbol and its truth table.

Fig. 6. Diagrammatic representation of adder. 4.3. XOR using MGs

The circuits especially digital can be implemented with the

union of fundamental elements such as logical conjunction (AND),
Full adders are used to implement the BCD adder here. Initially logical disjunction (OR), inverter (NOT) furthermore universal gates
To obtain the binary output full adders are used. Then various negated OR and negated AND. Additionally utilization of exclusive
equation simplifications are done further to obtain binary coded conjunction and exclusive disjunction will provide more benefits to
decimal. The diagrammatic representation depicted in Fig. 6 de- advanced designs. In order to implement the XOR function in QCA
notes the design of full adder by majority circuits. The model be- the XOR output should be obtained using the MGs.
comes simpler through the utilization of majority gate with 5 in- Ex-Or gate is used to reduce the number of majority gates and
puts compared to the model utilizing solely MG with 3 inputs and implement the equations to achieve the output bit S1 from the
negator (inverter). outputs of full adders that is w1,w2,w3 and w4. It is very clear
that the 6- Majority gate from the Fig. 3 are reduced to single 5
bit majority gate and 1 3-bit majority gate. The carry is used for
4.2. Inverter performing the calculation of MSB.
Instead of transistors, majority gates are used here. This BCD
The inverter in QCA performs as same as the NOT gate function- adder is especially for QCA. The QCA supports only the majority
ality in digitalelectronics. It produce the complement of the input. gate and inverters. The input is first added using full adder and
If the input is one, then the output is going to be zero. If the input produces a sum and carry bit. With proper combinations of those
is zero, then the output is going to be one. The inverter symbol sum and carry binary coded decimal formats are obtained as out-
and the truth table is shown in Fig. 7. put. Here the significant bit is required to consider the accuracy of

Fig. 8. RTL schematic of existing method.

6 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040

Fig. 9. BCD output for the existing system.

Fig. 10. Delay of existing method.

Fig. 11. Area of the existing system.

 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040 7

Fig. 12. RTL schematic of proposed system.

Fig. 13. Area of proposed system.

adder output. Each and every bit of the input and output is impor- 4.4.2. Xilinx ise
tant in determining the proper working of the adder. Xilinx ISE provides simulation and synthesis support for re-
In order to perform the XOR functionality of 2 inputs named X, searchers. It helps the explorers to adapt the intelligent and de-
Y with MGs the expression will be veloping world. Various kits and products are provided by Xilinx
which assist them in area, power and delay analysis.
x  y = M5(x, y, z , z , 0 ) (22)

where equation for Z can be given by 5. Result and discussion

z = M3(x, y, 0 ) (23) The aim of the project which was to build the BCD adder using
the combination of majority gate with 5 and 3 inputs is achieved.
Existing methodology deals with the BCD adder which is imple-
4.4. Software requirements mented entirely by the 3 input majority gates and inverter. The
existing system uses the modified equations derived from the con-
4.4.1. MODELSIM ventional BCD adder. In existing system with careful examinations
Modelsim provides simulation environment which supports of the DFA logical equations they achieved a reduced delay. The
multiple hardware description languages like VHDL, Verilog, Sys- Fig. 9 represents the BCD output of existing method.
tem Verilog, and System C etc.… This simulation environment is The RTL schematic of the existing system which shows the
created by Mentor Graphics. Verilog HDL is used to implement the difference in implementation of proposed system is given in the
simulation of majority gates. Fig. 8 and Fig. 13. Fig. 10 represents the delay value of existing
8 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040

Fig. 14. Delay of proposed system.

Fig. 15. Output waveform of proposed system.

system and the Fig. 11 and 14 represents the area of existing and DELAY (ns) TOTAL EQUIVALENT GATECOUNT
proposed method respectively. FOR DESIGN
In proposed system the way of implementation is changed by EXISTING 15.582 87
using the 5 input majority gate. Compared to the existing sys- PROPOSED 14.049 72
tem the crossover complexities is reduced without increase in area
power and delay constraints. The partly used and completely used
MGs are reduced compared to the existing one. The partly used 6. Conclusion
and the completely used MGs were reduced from 9 to 16 to 8 and
11 respectively. MG (majority gate) is the fundamental QCA component when
This paper deals with the 4 bit adder. So the output may vary joins with the negator (inverter) forms the entire logical set, be-
from 0 0 0 0 to 1111 with carry out 0 and 1 depending upon the cause the remaining logical conjunction and logical disjunction
input. The existing system of this paper deals with the delay of gates are defined in terms of partly used MG, where one of the
15.582 ns and the delay of proposed system is 14.049 ns. So there input is 0 or 1(constants), respectively. In this paper, a BCD adder
is a decrease in delay which increase the speed of operation leads is introduced which is implemented with the help of majority gate
to the improvement of efficiency. The end product is a delay ef- with 5 input and 3 input and the negator where existing system
ficient binary coded decimal adder from which we can obtain a consists of BCD implementation using inverters and majority gate
coded input for decimal input. with 3 inputs.
The Figs. 13–15 shows that the output waveform of proposed With this new type of BCD implementation using the amal-
method, Xilinx synthesis area and delay constraints respectively. gamation of majority gates with 3 and 5 inputs, crossover com-
The RTL schematic of the proposed method are also given as fol- plexities can be reduced with reducing the delay and the count of
lows. partly as well as completely used gates. The future work of this
 V.J. Arulkarthick, A. Rathinaswamy and K. Srihari / Microprocessors and Microsystems 75 (2020) 103040 9

paper is to focus in improvement of delay, area, or power factors [11] Sang-Ho Shin, Kee-Young Yoo, Gil-Je Lee, Design of exclusive-or logic gate on
of BCD adder or achieving the BCD adder based on MGs with 5 quantum-dot cellular automata, International Journal of Control and Automa-
tion 8 (2) (2015) 95–104 (2015).
inputs on QCA designer. [12] Shoubhik Gupta, Rohit Kumar, Bahniman Ghosh, Adder design using a 5-in-
put majority gate in a novel multilayer gate design paradigm for quantum dot
Ethical approval cellular automata circuits, Journal of Semiconductors 36 (4) (2015).
[13] Subhashee Basu, Realization of xor and xnor gates using QCA basic gates, Inter-
national Journal of VLSI and Embedded Systems-IJVES 05 (2014) 10473 ISSN:
This article does not contain any studies with human partici- 2249 – 6556.
pants or animals performed by any of the authors. [14] R. Radha Krishna, K. Vijaya Krishna, Design of the best area-delay adders with
QCA majority logic gates by using vhdl, International Journal of Scientific Re-
search Engineering & Technology (IJSRET) 4 (10) (2015) ISSN 2278 – 0882.
Declaration of Competing Interest
Dr. Arulkarthick V J, received his B.E. in Electrical
This paper has not communicated anywhere till this moment, and Electronics Engineering from Bharathiyar University,
Coimbatore; ME in Applied Electronics and Ph.D in Infor-
now only it is communicated to your esteemed journal for the mation and Communication Engineering from Anna Uni-
publication with the knowledge of all co-authors. versity, Chennai, His research interests are Signal and Im-
age processing, VLSI Design, and VLSI signal processing.
He is currently working as Assistant Professor (Selection
References Grade) at JCT college of Engineering, Coimbatore. He is a
member of IEEE, ISTE.

[1] AngomSachindro Singh, V. Sreevani, Area-Delay efficient binary adders in QCA,

International Journal of Advanced Research in Electrical, Electronics and Instru-
mentation Engineering 3 (11) (2014).
[2] Dariush Abedi, Ghassem Jaberipur, Decimal full adders specially designed for
quantum-dot cellular automata, IEEE Transactions on Circuits and System 2 Abinaya Rathinaswamy received her M.E. degree in VLSI
(2018). Design and B.E. degree in Electronics and Communication
[3] Gregory L. Snider, Alexei O. Orlov, Islamshah Amlani, Gary H. Bernstein, Craig Engineering from Anna University, Chennai. Her current
S. Lent, James L. Merz, Wolfgang porod, Quantum – Dot Cellular automata: line research interests include VLSI Design and Signal Process-
and majority logic gate, Jpn J Appl Phys 38 (1999) 7227–7229. ing. She is currently working as Assistant Professor at JCT
[4] Gurmohan Singh, R.K. Sarin and Balwinder Raj (2017) “A review of quantum- college of Engineering, Coimbatore.
dot cellular automata based adders”, Vol. 10, No. 4, pp. 41–58.
[5] Keivan Navi, Amir Mokhtar Chabi, Samira Sayedsalehi, A novel seven input
majority gate in quantum-dot cellular automata, IJCSI International Journal of
Computer Science Issues 9 (1) (2012).
[6] Keivan Navi, Razieh Farazkish, Mostafa Rahimi Azghadi, Samira Sayedsalehi,
Five-Input majority gate a new device for quantum-dot cellular automata, J
Comput Theor Nanosci (2010), doi:10.1166/jctn.2010.1517.
[7] Konrad Walus, Timothy J. Dysart, Graham A. Jullien, Arief R. Budiman, QCA De- Dr. K. Srihari received the M.E. and Ph.D. degree from
signer: a rapid design and simulation tool for quantum-dot cellular automata, Anna University, Chennai. He is currently working as an
IEEE Trans Nanotechnol (2004), doi:10.1109/TNANO.2003.820815. Associate Professor in the Department of Computer Sci-
[8] Maryam Taghizadeh, Mehdi Askari, Khossro Fardad, BCD computing structures ence and Engineering, SNS College of Engineering, affili-
in Quantum- Dot Cellular automata, in: Proceedings of the International Con- ated to Anna University- Chennai, Tamilnadu, India. Dr. K.
ference on Computer and Communication Engineering, May 13-15, 2008, Kuala Srihari published over 50 papers in international journals
Lumpur, Malaysia, 2008. and his research area includes semantic search engines,
[9] Ramanand Jaiswal, Trailokya Nath Sasamal, Efficient design of full adder and Microprocessor, FPGA, big data and cloud computing.
subtractor using 5-input majority gate in QCA, Tenth International Conference
on Contemporary Computing (IC3), 2017.
[10] Rami Akeela, Meghanad D. Wagh, A Five-Input Majority Gate in Quantum Dot
Cellular Automata, 2, NSTI-Nanotech 2011, 2011 ISBN 978-1-4398-7139-3.