DMD NOTES:

==========
NOTE in this description the LEDs are numbered in accordance with their
x & y position coordinates beginning at (0,0) at the top left corner to (31,15)
at the lower right, looking at the front of the DMD.
The version of the DMD Library used is the one available at:
https://github.com/cjd/DMD
which has significant updates and improvements over the earlier versions.
There could be a little confusion regarding some numbering within the DMD
library. For example: the locations of LEDs are zero referenced (0,0) to
(31,15) but the rows of LEDs are numbered from 1 to 16.
I will use 0 to 15 here.

Top left LED (0,0) is bit 7 of byte 0, next LED (1,0) bit 6 of byte 0,
. . . . . . . etc to bit 0 of byte 7 as last LED on top row (31,0).
Second row LED (0,1) is bit 7 of byte 4, LED (1,1) is bit 6 of byte 4,
. . . . . . . etc to bit 0 of byte 7 . . . . . . etc through to the bottom
row of LEDs:
Bottom left LED (0,15) is bit 7 of byte 60, . . . . . .
etc to (31,15) bit 0 of byte 63.

Layout of the RAM buffer versus LEDs for a single DMD:

Total of 64 bytes per DMD.

0 1 2 3 4 5 6 7 8 9 10 15 23 31 column (x)
/---byte 0----\ /---byte 1----\ /---byte 2----\ /---byte 3----\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 0 (y)

/---byte 4----\ /---byte 5----\ /---byte 6----\ /---byte 7----\

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 1

/---byte 8----\ /---byte 9----\ /---byte 10---\ /---byte 11---\

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 2

/---byte 12---\ /---byte 13---\ /---byte 14---\ /---byte 15---\

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 3

/---byte 16---\ /---byte 17---\ /---byte 18---\ /---byte 19---\

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 4
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/---byte 32---\ /---byte 33---\ /---byte 34---\ /---byte 35---\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 8
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/---byte 48---\ /---byte 49---\ /---byte 50---\ /---byte 51---\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 12

/---byte 52---\ /---byte 53---\ /---byte 54---\ /---byte 55---\

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 13

/---byte 56---\ /---byte 57---\ /---byte 58---\ /---byte 59---\

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 14

/---byte 60---\ /---byte 61--\ /---byte 62---\ /---byte 63----\

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Row 15
For 2 DMDs:
===========
Top left LED (0,0) is bit 7 of byte 0, next LED (1,0) bit 6 of byte 0, . . . . .
etc to bit 0 of byte 7 as last LED on top row (63,0) of 2 DMDs wide.
Second row LED (0,1) is bit 7 of byte 8, LED (1,1) is bit 6 of byte 8, . . . . .
etc to bit 0 of byte 15 . . . .
through to the bottom row of LEDs:
bottom left (0,15) is bit 7 of byte 120, . . . .
etc to (63,15) bit 0 of byte 127.

Layout for 2 DMDs (looking at the front):

Total of 128 bytes (64 bytes per DMD).

/-----------------------DMD1--------------------\ /---------------
DMD2------------\
0 1 2 3 4 5 6 7 8 9 10 15 24 31 32 39 56
63 column (x)
/---byte 0----\ /---byte 1----\ . /---byte 3----\ | /---byte 4----\ . /---byte
7----\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row (y) 0

/---byte 8----\ /---byte 9----\ . /---byte 11---\ | /---byte 12---\ . /---byte

15---\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 1

/---byte 16---\ /---byte 17---\ . /---byte 19---\ | /---byte 20---\ . /---byte

23---\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 2

/---byte 24----\ /---byte 25--\ . /---byte 27---\ | /---byte 28---\ . /---byte

31---\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 3

/---byte 32----\ /---byte 33--\ . /---byte 35---\ | /---byte 36---\ . /---byte

39---\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 4
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/---byte 64----\ /---byte 65--\ . /---byte 67---\ | /---byte 68---\ . /---byte
71---\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 8
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/---byte 96----\ /---byte 96--\ . /---byte 99---\ | /---byte 100--\ . /---byte
103--\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 12

/---byte 104--\ /---byte 105--\ . /---byte 107--\ | /---byte 108--\ . /---byte

111--\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 13

/---byte 112--\ /---byte 113--\ . /---byte 115--\ | /---byte 116--\ . /---byte

119--\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 14

/---byte 120--\ /---byte 121--\ . /---byte 123--\ | /---byte 124--\ . /---byte

127--\
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
0 Row 15

For only 1 DMD high (any number wide), the byte for a particular LED is equal to:
(Xcoord / 8) + (Ycoord * NumberOfDMDs * 4)
For multi dimensional DMD arrays, the byte for a particular LED is equal to:
(DisplaysTotal * 4 * (Ycoord % 16)) + (4 * DisplaysAcross * (Ycoord / 16)) +
(Xcoord / 8)
The bit is equal to:
7 - (Xcoord % 8)

The 16 DMD shift registers are cascaded - 74HC595-1, -2, -3 . . . . to 74HC595-16.

There are a total of 128 outputs for the 16 shift registers but there are 512 LEDs.

Each shift register output drives 4 LEDs in a vertical column (the cathode).
QA of 74HC585-1 is connected to LEDs 31,0 31,1 31,2 & 31,3.
QB is connected to LEDs 30,0 30,1 30,2 & 30,3 and so on to
QH connecting to 24,0 24,1 24,2 & 24,3.
So each shift register drives a block of LEDs 8 wide by 4 high.
The overflow QH' from 74HC595-1 is fed into the input of 74HC595-2 which drives
the next block of 32 LEDs (31,4 31,5 31,6 31,7; 30,4 30,5 etc to 24,4 24,5 24,6
24,7. Finally, the overflow QH' of 74HC595-16 is connected to the DMD JP2
connector for input to a following board where the same process occurs.

The 4 LEDs driven by each shift register output have their anodes connected to
1 of 4 switched Vcc supplies feeding 4 blocks of interleaved rows such that all
anodes in rows 0, 4, 8, 12 are connected together, as are all anodes in rows
1, 5, 9, 13 and 2, 6, 10, 14 and 3, 7, 11, 15.
(There are actually 2 switched Vcc supplies for each of these 4 blocks each
driven by a separate MOSFET to prevent overloading the MOSFET, but they are
driven in parallel.)
These groups of rows are selected by means of the DMD lines A & B (D6 & D7 on
the Arduino) which selects 1 of 4 via the 74HC128, the output of which switches
a pair of MOSFETS to supply Vcc to a total of 128 LEDs.
For an individual LED to be ON, its corresponding shift register output must be
LOW and its row must be selected.

The DMD shift registers operate in a serial fashion with each bit of data
entered being promulgated to the next position when the next data bit is
entered. The order in which the data is entered is critical. Because the LED
connected to the last output (QH) of the last shift register (74HC595-16) is
LED 0,15 this must be the first bit entered, followed by 1,15 etc. Similarly,
the last bit entered must be for LED 31,0 connected to the first output (QA)
of the first shift register (74HC595-1). So exactly the correct number of
bits must be applied in the correct sequence of both bits and bytes.
Note that the bit order is the most significant bit (bit 7) first.

Mapping of the DMD hardware shift registers versus LED position:

0 1 2 3 4 5 6 7 8 9 10 15 23 31 column (x)
/- 74HC595-13-\ /- 74HC595-9 -\ /- 74HC595-5 -\ /- 74HC595-1 -\
H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 0 (y)

/- 74HC595-13-\ /- 74HC595-9 -\ /- 74HC595-5 -\ /- 74HC595-1 -\

H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 1

/- 74HC595-13-\ /- 74HC595-9 -\ /- 74HC595-5 -\ /- 74HC595-1 -\

H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 2

/- 74HC595-13-\ /- 74HC595-9 -\ /- 74HC595-5 -\ /- 74HC595-1 -\

H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 3

/- 74HC595-14-\ /- 74HC595-10-\ /- 74HC595-6 -\ /- 74HC595-2 -\

H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 4
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/- 74HC595-15-\ /- 74HC595-11-\ /- 74HC595-7 -\ /- 74HC595-3 -\
H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 8
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/- 74HC595-16-\ /- 74HC595-12-\ /- 74HC595-8 -\ /- 74HC595-4 -\
H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 12

/- 74HC595-16-\ /- 74HC595-12-\ /- 74HC595-8 -\ /- 74HC595-4 -\

H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 13

/- 74HC595-16-\ /- 74HC595-12-\ /- 74HC595-8 -\ /- 74HC595-4 -\

H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 14

/- 74HC595-16-\ /- 74HC595-12-\ /- 74HC595-8 -\ /- 74HC595-4 -\

H G F E D C B A H G F E D C B A H G F E D C B A H G F E D C B A Row 15

NOTES:
1. Only a maximum of 128 LEDs on a DMD can be ON at any one time - not 512.
2. The data bit for an LED must be LOW for that LED to be ON.
3. The DMD has a 1k pullup and 4k7 pulldown resistors on the CLK and SCLK
lines. Why? and why both? When not driven either HIGH or LOW, these lines
will be read as HIGH because the voltage will be greater than the
(0.7 x Vcc) threshold to guaranty a HIGH, so why the pulldown?
4. There is no pullup/pulldown resistor on an any other line. The OE line
should have a pulldown resistor.
5. The nOE line is incorrectly labelled on the DMD connector board and within
the DMD library. This is active HIGH and should be labelled "OE". It is
correctly labelled in the DMD schematic.
6. There is no reset/clear function on powerup of the DMD. The OE line should
be held LOW until the DMD display is explicitly cleared or updated to
prevent any LEDs from lighting before they are set with valid data.
7. There are no current limiting resistors in the LED circuit. They are driven
directly from the shift register output which has a limited current capacity
of around 35mA (depends on manufacturer). While this is a fairly common
practice, it is not good design. There is a limit of around 70mA total
Vcc or ground current per chip (again depends on the manufacturer) which
will be greatly exceeded if more that 2 LEDs on a single shift register
are ON. Again, poor design.
8. DMDs MUST be powered and NOT fed from the USB port via the Arduino. There
is no Vcc connection between the Arduino board and the DMD. This means that
the only way power can be supplied to the DMD (without its own power supply)
 is via the active control lines (D6, D7, D8, D9, D11, D12, & D13). When at
least one of these is in the HIGH state, it will supply current to the bus
tranceiver 74HC245 which feeds its supply line via its input protection
circuitry. This is NOT GOOD for either the Arduino or the DMD. The only
thing saving your Arduino (and possibly the DMD) is the limited current
available on the USB port.
9. There are several hardware versions of the DMD PCB which appear to be
electrically equivalent. I suspect these might be from different supply
contracts for production based on a supplied circuit rather than a
supplied PCB layout.
===========================================================================

How the DMD update process works

================================
On the first call of the scanDisplayBySPI() method a total of 16 bytes per DMD
is sent to the DMD via the SPI buss. This is only 1/4 of the DMD memory, but is
enough to fill the entire DMD shift register chain.
The data written on this first call is bytes 48, 32, 16, 0, 49, 33, 17, 1, 50,
34, 18, 2, 51, 35, 19, 3 within the DMD RAM buffer which is only the
information required for the LEDs with x coordinates of 0, 4, 8 & 12 (or DMD
rows 1, 2, 3, 4). Once the data has been sent to the DMD, the new data must be
promoted to the shift register outputs. This is achieved by toggling the SCLK
line (D8) which latches the data.
To ensure that only the correct block of LEDs for the installed data is
displayed, the required block is selected by setting the A & B (D6 & D7) lines
appropriately.
Note that the DMD's output enable line must be disabled BEFORE the data in
storage in the shift registers is latched to their outputs to prevent incorrect
LEDs from lighting. Once the data has been updated, the output must remain
disabled until after the correct block of rows has been selected.
The next call of scanDisplayBySPI() will install the data from bytes 52, 36,
20, 4, 53, 37, 21, 5, 54, 38, 22, 6, 55, 39, 23, 7 within the DMD RAM buffer,
which is the data for LEDs with x coordinates of 1, 5, 9 & 13 (or DMD
rows 2, 3, 4, 5). The same process is again used to latch the data to the
but with the new configuration for A & B (D6 & D7).
A total of 4 calls is required to update the entire display.

Each call of the scanDisplayBySPI() interrupt routine takes about 84 uSec for
a single DMD, plus 44 uSec for each additional DMD - based on the DMD
library as supplied with 8 mHz SPI clock (SPI.setClockDivider(SPI_CLOCK_DIV2)).