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Embedded Systems 2011 Midsem

This document contains instructions for two embedded systems design projects involving shared memory and IIR filtering. For the shared memory project, students are asked to design a shared memory system using a 32-bit SRAM chip shared between four 8051 microcontrollers. They must provide block diagrams, address/data routes, and a program to read and write memory. For the IIR filtering project, students must design a system to implement a variable IIR filter using stored filter coefficients, an ADC, DAC, and timers to generate sampling clocks. They are to provide a chip diagram, interrupt-driven filtering program, and calculate maximum sampling frequency.

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29 views

Embedded Systems 2011 Midsem

This document contains instructions for two embedded systems design projects involving shared memory and IIR filtering. For the shared memory project, students are asked to design a shared memory system using a 32-bit SRAM chip shared between four 8051 microcontrollers. They must provide block diagrams, address/data routes, and a program to read and write memory. For the IIR filtering project, students must design a system to implement a variable IIR filter using stored filter coefficients, an ADC, DAC, and timers to generate sampling clocks. They are to provide a chip diagram, interrupt-driven filtering program, and calculate maximum sampling frequency.

Uploaded by

brahma2deen2chaudhar
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EE30004/EE60056 Programmable Embedded Systems

Time: 2 hours Marks:30


Department of Electrical Engineering
Indian Institute of Technology Kharagpur
Open Book Examination
MID-TERM EXAMINATION SPRING 2010

Answer all Questions


(1) Design a shared memory system using a single 32-bit SRAM chip such as TC55V2325FF
from Toshiba which is shared by four 8051 controllers.
Hint: The said memory chip can operate in several modes such as: burst mode
and single read/write mode. There are byte write enables BW 1, BW 2,BW 3,BW 4
and over all BW E to write 8-bits information (see the data sheet). There are global
write enables such as GW which needs to be set properly. The burst-mode signals
such as ADV ,ADSP and ADSC also need to be set properly.
(a) Draw the block diagrams. Make a table that clearly states the Address
routes, Data routes and routes for the control signals for each micro-controller to
the bus-control-unit and the memory chip. [4]
(b) Write the step by step operations when the 2nd 8051 from left needs to read
a data from a given memory location say 3A00H to a register, compliment the bits
and store them in the same location. Write programs for the 2nd MCU and the
Bus-Controller MCU to achieve this.[7]
(c) Find the maximum and minimum possible data transfer rates possible for a
single CPU to the memory for read operation. [5]

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Date: 19/02/2011.
1
2 MID-TERM EXAMINATION SPRING 2010

(2) A variable IIR filter with eight given sets of coefficients is to be implemented on an
8051 based system. Design the complete scheme assuming that the Variable Filter
Coefficients(V.F.C.) are to be stored in the form of tables in the EPROM as shown.
The first location of each table specifies the order of the numerator and the second
location specifies the order of the denominator of the IIR filter. Assume the orders
(both denominator as well as numerator) of each to not to exceed 3. The values
are stored as denominator followed by the numerator coefficients. External control
is required to choose the specific filter. Use 0809 ADC and DAC0808.
a) Draw the chip level diagram showing the various connections in a table. Spec-
ify the pin numbers as well as the names of the pins of each chip. [4]
b) Write the program to acquire the data from the ADC, filter it depending on
the switch selection and send it to the DAC. Use interrupt driven data transfer.
The timing for the ADC clock as well as the SOC to the ADC should be generated
from the internal timers of the 8051.[6]
c) Find the maximum achievable sampling frequency. [4]

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