XR872 Datasheet

High Performance Wireless MCU for Artificial Intelligence

and Internet of Things (AIoT) Applications

Revision 1.0

Oct. 28, 2019

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved

Declaration
THIS DOCUMENTATION IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF XRADIO TECHNOLOGY
(“XRADIO”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF XRADIO AND GIVE
CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER.

THE PURCHASED PRODUCTS, SERVICES AND FEATURES ARE STIPULATED BY THE CONTRACT MADE BETWEEN
XRADIO AND THE CUSTOMER. PLEASE READ THE TERMS AND CONDITIONS OF THE CONTRACT AND RELEVANT
INSTRUCTIONS CAREFULLY BEFORE USING, AND FOLLOW THE INSTRUCTIONS IN THIS DOCUMENTATION STRICTLY.
XRADIO ASSUMES NO RESPONSIBILITY FOR THE CONSEQUENCES OF IMPROPER USE (INCLUDING BUT NOT
LIMITED TO OVERVOLTAGE, OVERCLOCK, OR EXCESSIVE TEMPERATURE).

THE INFORMATION FURNISHED BY XRADIO IS PROVIDED JUST AS A REFERENCE OR TYPICAL APPLICATIONS, ALL
STATEMENTS, INFORMATION, AND RECOMMENDATIONS IN THIS DOCUMENT DO NOT CONSTITUTE A WARRANTY
OF ANY KIND, EXPRESS OR IMPLIED. XRADIO RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN
AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE.

NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM
ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF
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Revision History
Version Data Summary of Changes
1.0 2019-10-28 Release complete data information

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Contents
Declaration................................................................................................................................................................... 2

Revision History ........................................................................................................................................................... 3

Contents....................................................................................................................................................................... 4

Tables ........................................................................................................................................................................... 7

Figures ......................................................................................................................................................................... 9

1 Overview ............................................................................................................................................................ 10

1.1 General Description ........................................................................................................................... 10

1.2 Features ............................................................................................................................................. 10

1.3 Application ......................................................................................................................................... 13

1.4 Block Diagram .................................................................................................................................... 14

2 Function Description .......................................................................................................................................... 15

2.1 System Overview................................................................................................................................ 15

2.1.1 Power Management .................................................................................................................. 15

2.1.2 Clock ........................................................................................................................................... 16

2.1.3 Power State and Power Sequence ............................................................................................. 18

2.1.4 Memory Mapping ...................................................................................................................... 20

2.1.5 CPU............................................................................................................................................. 21

2.1.6 DMA ........................................................................................................................................... 22

2.1.7 Cache ......................................................................................................................................... 22

2.1.8 Crypto Engine ............................................................................................................................. 23

2.1.9 Timer.......................................................................................................................................... 23

2.1.10 RTC ............................................................................................................................................. 23

2.2 Peripherals ......................................................................................................................................... 24

2.2.1 GPIO ........................................................................................................................................... 24

2.2.2 UART .......................................................................................................................................... 27

2.2.3 SPI .............................................................................................................................................. 27

2.2.4 TWI ............................................................................................................................................. 27

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 2.2.5 PWM .......................................................................................................................................... 28

2.2.6 SD/MMC/SDIO ........................................................................................................................... 28

2.2.7 CIR .............................................................................................................................................. 29

2.2.8 GPADC ........................................................................................................................................ 29

2.2.9 I2S .............................................................................................................................................. 30

2.3 Video Subsystem................................................................................................................................ 30

2.3.1 CSI .............................................................................................................................................. 30

2.3.2 JPEG............................................................................................................................................ 31

2.4 AUDIO Subsystem .............................................................................................................................. 31

2.4.1 DMIC .......................................................................................................................................... 31

2.4.2 AUDIO CODEC ............................................................................................................................ 31

2.5 Wi-Fi Subsystem ................................................................................................................................ 32

2.5.1 Wi-Fi MAC .................................................................................................................................. 32

2.5.2 Wi-Fi Baseband .......................................................................................................................... 33

2.5.3 Wi-Fi Radio ................................................................................................................................ 33

2.5.4 Front End Module Control ......................................................................................................... 33

3 Electrical Characteristics .................................................................................................................................... 35

3.1 Absolute Maximum Ratings ............................................................................................................... 35

3.2 Recommended Operating Conditions ................................................................................................ 36

3.3 Digital IO Characteristics .................................................................................................................... 36

3.4 Bootstrap Modes and Pins ................................................................................................................. 37

3.5 High Frequency Reference Clock ....................................................................................................... 38

3.6 Low Frequency Reference Clock ........................................................................................................ 38

3.7 Audio Codec Specifications ................................................................................................................ 40

3.8 Wi-Fi 2.4G RF Receiver Specifications ............................................................................................... 42

3.9 Wi-Fi 2.4G RF Transmitter Specifications........................................................................................... 43

3.10 Power Consumption .......................................................................................................................... 46

4 Package Specifications ....................................................................................................................................... 49

4.1 Pin Layout .......................................................................................................................................... 49

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 4.2 Pin Descriptions ................................................................................................................................. 51

4.3 Package Information .......................................................................................................................... 53

4.4 Package Thermal Characteristics ....................................................................................................... 54

5 Carrier Information ............................................................................................................................................ 55

6 Reflow Profile..................................................................................................................................................... 56

7 Application Circuit.............................................................................................................................................. 57

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Tables
Table 1-1 XR872 Features ........................................................................................................................................... 10

Table 2-1 Power Management States ........................................................................................................................ 15

Table 2-2 SRAM Memory Mapping ............................................................................................................................ 20

Table 2-3 XR872AT GPIO Multiplexing ....................................................................................................................... 25

Table 3-1 Absolute Maximum Ratings ....................................................................................................................... 35

Table 3-2 Recommended Operating Conditions ........................................................................................................ 36

Table 3-3 DC Characteristics of VDD_IO=3.3V ........................................................................................................... 36

Table 3-4 DC Characteristics of VDD_IO=1.8V ........................................................................................................... 36

Table 3-5 Bootstrap pins ............................................................................................................................................ 37

Table 3-6 External High Frequency Crystal Characteristics Requirements ................................................................ 38

Table 3-7 External Low Frequency Crystal Characteristics Requirements ................................................................. 38

Table 3-8 ADC Specifications...................................................................................................................................... 40

Table 3-9 Line-in Specifications.................................................................................................................................. 40

Table 3-10 DAC Specifications .................................................................................................................................... 40

Table 3-11 ADC Specifications.................................................................................................................................... 41

Table 3-12 Line-in Specifications................................................................................................................................ 41

Table 3-13 DAC Specifications .................................................................................................................................... 41

Table 3-14 RF Receiver Specifications ........................................................................................................................ 42

Table 3-15 RF Transmitter Specifications 1 ................................................................................................................ 43

Table 3-16 RF Transmitter Specifications 2 ................................................................................................................ 44

Table 3-17 RF Transmitter Specifications 3 ................................................................................................................ 45

Table 3-18 Power Consumption 1 .............................................................................................................................. 46

Table 3-19 Power Consumption 2 .............................................................................................................................. 47

Table 4-1 Pin Description ........................................................................................................................................... 51

Table 4-2 QFN52 Package Thermal Characteristics .................................................................................................... 54

Table 4-3 QFN40 Package Thermal Characteristics .................................................................................................... 54

Table 5-1 Reel Carrier Information ............................................................................................................................ 55

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Table 5-2 Tape Dimension.......................................................................................................................................... 55

Table 5-3 Packing Quantity Information .................................................................................................................... 55

Table 6-1 XR872 Reflow Profile Conditions ................................................................................................................ 56

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Figures
Figure 1-1 XR872 Functional Block Diagram .............................................................................................................. 14

Figure 2-1 Power Architecture ................................................................................................................................... 16

Figure 2-2 Clock Control ............................................................................................................................................ 17

Figure 2-3 Power-on Sequence .................................................................................................................................. 18

Figure 2-4 Wakeup from standby Sequence .............................................................................................................. 18

Figure 2-5 Wakeup from hibernation Sequence ........................................................................................................ 19

Figure 2-6 Shutdown Sequence ................................................................................................................................. 19

Figure 2-7 Memory Mapping ..................................................................................................................................... 20

Figure 2-8 FEM Control Application Diagram ............................................................................................................ 34

Figure 4-1 XR872AT Pin Layout .................................................................................................................................. 49

Figure 4-2 XR872ET Pin Layout .................................................................................................................................. 50

Figure 4-3 QFN52 Package Outline Drawing .............................................................................................................. 53

Figure 4-4 QFN40 Package Outline Drawing .............................................................................................................. 53

Figure 5-1 Tape Dimension Drawing .......................................................................................................................... 55

Figure 6-1 XR872 Typical Reflow Profile .................................................................................................................... 56

Figure 7-1 Reference Design of XR872AT ................................................................................................................... 57

Figure 7-2 Reference Design of XR872ET ................................................................................................................... 57

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1 Overview

1.1 General Description

XR872 delivers a highly integrated high performance Wi-Fi wireless System-on-Chip (SoC) solution designed for
Artificial Intelligence and Internet of Things (AIOT) applications, such as smart audio, face detection and
recognition, Machine-to-Machine (M2M), Smart Home, Cloud Connectivity and Smart Energy.

The XR872 application subsystem is powered by an ARM Cortex-M4F CPU that operates up to 384MHz. It supports
an integrated 416KB SRAM and 160KB ROM, a QSPI interface to SIP up to 16MB Flash, a OPI interface to SIP 4MB
PSRAM. Integrated I-cache enables Execute In Place (XIP) from flash and PSRAM, and integrated D-cache enables
read and write from PSRAM. It also includes many peripherals, including UART, TWI, SPI, DMIC, AUDIO CODEC,
PWM, CIR (T/R), CSI, SDIO and auxiliary ADC.

The Wi-Fi subsystem contains the 802.11b/g/n baseband, MAC and radio with integrated PA, LNA, Switch and
harmonic filter, which is design to meet both the low power, high integration and high performance network
application. A novel digital RF transmitter is design using XRADIOTECH’s MPDTM technology to deliver higher
output power and maintain higher efficiency, and also to keep the chip not sensitive to antenna mismatch but
always have good EVM at different VSWR.

The SoC is optimized for low-power operation by using several low-power state and fast wake-up times from
hardware to software. Multiple power domains and clocks can be shut down individually. The application
subsystem and Wi-Fi subsystem can be put into low-power states independently, supporting a variety of
application use cases. Also an optional external DC-DC regulator can provide voltage from 1.5V to 2.5V for whole
VDD_ANA power domain with on chip DC-DC control signal, without sacrificing standby power consumption even
using high quiescent current DC-DC.

1.2 Features
 General System Features

Table 1-1 XR872 Features

Chi chip List Description XR872AT XR872ET

6x6mm2 5x5mm2
Package Trays and tape-in-reel
QFN52 QFN40

Supply voltage Power supply from system 1.8~5.5V

PMU LDO for external device (EXT LDO) Yes

External Clock Reference High frequency clock 24/26/40

MCU Core Core Type Cortex-M4F

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 Core clock maximum frequency 384MHz 240MHz

Internal ROM 160KB

Internal RAM 416KB 416KB

Internal Flash / /
Memory External Flash with XIP 128Mb

Cache (can be configured to

40KB 40KB
system ram)

PSRAM 4MB /

Backup register Backup register for power save 16B

Secure boot Yes

Crypto Engine AES/DES/3DES/SHA/MD5/CRC Yes

TRNG Provide random number seed Yes

Watchdog reset Protect specified peripherals been

Yes
protection reset by watchdog reset

BOR BOR Detection Yes

Wi-Fi 802.11 b/g/n Yes

GPIO General Purpose 35 27

UART 3 3

SPI Master and slave 2 2

TWI Max.400Kbps 2 2

SDIO Master 1 1

VBAT 1 1
Peripheral GPADC
Normal 7 2

DMA 8Channel 1 1

I2S 1 0

DMIC 1 0

x1 ADC 1 1
CODEC
x1 DAC 1 1

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 x1 Line-in 1 0

CSI+JPEG 1 1

RTC 1 1

Watchdog 1 1

Timer Normal 2 2

Wakeup 1 1

Output 8 8
PWM
Input capture 8 8

Receiver 1 1
CIR
Transmitter 1 1

Internal RCOSC 1 1
32K
External XTAL 1 0

WAKEUP IO From RTC wakeup 9 9

 Audio Subsystem

- 1 Digital Microphone Controller with left and right channel voice input

- 1 24bit audio digital-to-analog(DAC) channel, support sample rates from 8KHz to 192KHz

- 1 24bit audio analog-to-digital(ADC) channel for microphone input, support sample rates from 8KHz to 48KHz

- 1 24bit audio-to-digital(ADC) channel for line-in, support sample rates from 8KHz to 48KHz

- DMA and interrupt support

 Video Subsystem

- a CMOS Sensor Interface Controller(CSIC) which is an image or video input control module to receive image
or video data via digital camera(DC)interface, CCIR656 interface

- Supports JPEG base line

- Supports online encoding mode with CSI

- Supports nv12 input format in offline encoding mode

- Supports configurable picture resolutions

 Minimum picture resolution: 32x32

 Offline maximum picture resolution: 1920x1088

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  Online maximum picture resolution: 1920x1088

- Supports online 640x480@60fps or online 1280x720@40fps

- Supports offline 640x480@30fps or offline 1280x720@20fps

- Supports bitrate control through quantization table

 Wi-Fi Subsystem

- IEEE 802.11b/g/n, 1x1 SISO 2.4GHz

- Integrated MAC, BB, RF and Embedded TCP/IP Stack

- Integrated T/R switch, harmonic filter, PA and LNA

- Antenna diversity

- Station, AP Modes

- Smart-Config Technology for Autonomous and Fast Wi-Fi Connections

- Security support for WEP, WPA/WPA2 personal, WPS2.0

- Industry-Standard BSD Socket Application Programming Interfaces (APIs)

 Power Management

- Integrate highly flexibility power management unit by several LDOs and external DC-DC controller

- Wide range power supply: 1.8-5.5V

 Miscellaneous

- Integrates 1Kbit eFuse to store device specific information and RF calibration data

1.3 Application
 Smart Audio  Smart Home

 Smart Video  Access Control

 Security Systems  Cloud Connectivity

 Smart Energy  Industrial Control

 Internet Gateway  IP Network Sensor Nodes

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1.4 Block Diagram

FLASH
CTRL I/D DEBUG Control
CACHE (SWD/JTAG)
PSRAM (40KB) SWJDP MPU
CTRL
Cortex-M4F AUDIO Subsystem
SPI x2 384MHz x1 ADC
NVIC SYSTICK x1 DAC
SD/MMC x1
x1 LINEIN
CIR(TX/RX)
VIDEO Subsystem
SRAM ROM CSI
GPIOs
416KB 160KB JPEG
UART x3
PSRAM 4MB
TWI x2 WLAN
ADC x8 Subsystem
Hardware Crypto
PWM x8 Embedded
AES128/192/256,
GDMA Protocol Stack
TIMER x4 DES/3DES,
(8ch)
I2S x1 SHA1/SHA256/MD5/ net80211
CRC/TRNG supplicant
DMIC x1 TCP/IP

Always On

PLL MAC
Oscillator Baseband
RTC PMU
24/26/40
RADIO
MHz
RC32K
1.8V~5.5V 1.8V 1.1V 2.8V 3.3V

Figure 1-1 XR872 Functional Block Diagram

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2 Function Description

2.1 System Overview

2.1.1 Power Management

A single 1.8~5.5V power supply is required for the XR872. It could be from an AC-DC converter, USB to supply to
5V or a DC-DC converter to convert higher voltage supply to 3.3V or even lower. It could be from a battery directly
too, no matter it is lithium, single 3V button or 2 serial NI-MH battery.

The Power Management Unit (PMU) contains a DC-DC control interface, several Low Drop-out Regulators (LDOs),
and a reference band-gap circuit. The circuits are optimized for low quiescent current, low drop-out voltage, load
regulation, high ripple rejection, and low output noise. The PMU integrates several LDOs for different circuits: TOP
LDO, RTC LDO, SoC LDO, EXT LDO, as shown in Figure 2-1. They have different operating conditions and features:

 TOP LDO provide programmable voltage from 1.4V to 3.6V with maximum 350mA load current, for
Analog and PSRAM, also SoC LDO input. Normally, make sure VBAT voltage is higher than this
programmable output voltage setting.

 RTC LDO is the main supply only for RTC domain to optimize power consumption at HIBERNATION state.

 SoC LDO is the main supply for whole chip digital circuit with programmable voltage from 0.6V to 1.35V
to let DVFS operate effectively.

 EXT LDO is main power supply for external device in application, and also can be provide to VDDIO,
GPADC and internal CODEC. It has maximum 200mA load current. The output voltage is limited to
3.3/3.1V (by register configure setting), when VBAT is lower than the value, it will automatically switch to
bypass mode to let output voltage follow VBAT.

When using external DC-DC to further reduce power consumption, the connection can be set as figure 2-1. PA23
GPIO pin is specified for external DC-DC pup, the detail software setting and flow is integrated in our SDK. When
external DC-DC is used, the output voltage on VDD18 should be at least 0.1V step higher than TOP LDO setting
voltage to have DC-DC be operating normally.

There are four power domains in the system: RTC domain, OA domain, Digital Core domain and Wi-Fi domain.
They mainly used for different scenario to maintain ultra-low power application. We define XR872 into ACTIVE,
STANDBY, HIBERNATION and SHUTDOWN power management states, is shown in table 2-1.

Table 2-1 Power Management States

POWER EXT RTC TOP SoC DCXO

CM4F Wi-Fi Description
MODE LDO LDO LDO LDO /DPLL

ACTIVE ACTIVE ACTIVE ON ON ON ON ON All CPU active

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 ACTIVE OFF ON ON ON ON ON/OFF APP CPU active

SLEEP ACTIVE ON ON ON ON ON
APP CPU goes to sleep, Wi-Fi DTIMx state
STANDBY SLEEP SLEEP ON ON LP LP OFF

SLEEP OFF ON ON LP LP OFF APP CPU goes to sleep, Wi-Fi power off

Only RTC on, waiting for timer or

HIBERNATE OFF OFF ON/OFF ON OFF/LP OFF OFF
wakeup IO to interrupt

SHUTDOWN OFF OFF OFF OFF OFF OFF OFF CHIP_PWD pin keep low level

VBAT
External 1.8V 1.8~3.3V
DC-DC

VBAT VDD_ANA VDD_PSM VDD_EXT VDDIO

TOP LDO EXT LDO

(1.4~3.6V) (3.3/3.1V)

RTC SoC
LDO LDO

VDD_DIG
0.6~1.35V

PA23
SoC PA RFIP PSRAM GPADC VDDIO CODEC

Figure 2-1 Power Architecture

2.1.2 Clock
The clock management system can source the system clocks from a range of internal or external high and low
frequency oscillators and distribute them to modules based upon module’s individual requirements. The system
generates two different clocks: a high frequency clock HFCLK and a low frequency clock LFCLK.

The system supports two LFCLK clock sources, the 32.768 KHz crystal oscillator and the 32.768 KHz RC oscillator.
The 32.768 KHz crystal oscillator requires an external AT-cut quartz crystal to be connected to the LXTAL1 and
LXTAL2 pins. The LFCLK clock and all of the available LFCLK sources are switched off by default when the system is
powered up. The LFCLK clock can be started by selecting the preferred clock source in PRCM register. It is used for

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each subsystem to achieve lower current consumption for different running mode. In addition, the LFCLK is also
used in RTC circuit to achieve accuracy timing.

There is only one clock source for HFCLK, generated by the 24MHz, 26MHz, or 40MHz crystal oscillator. The HFCLK
is enabled automatically when the system is powered up and can be switched off when all subsystems won’t use it
anymore in some low power modes.

The HFCLK is used to generate the clock source for Digital PLL, which is used to generate the clock sources for
Cortex-M4F core, Wi-Fi and peripherals. There is also an Audio PLL used to generate the clock source for Audio
Subsystem.

The following figure shows the clock control block diagram.

LXTAL1 LXTAL2 HXTAL1 HXTAL2

32K 32.768K
24/26/40
RC Crystal
DCXO
Oscillator Oscillator

src
LFCLK HFCLK enb
enb
Control Control

LFCLK HFCLK

Figure 2-2 Clock Control

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2.1.3 Power State and Power Sequence

2.1.3.1 Power-on Sequences

VBAT

CHIP_PWD

Internal 100us
BG/Analog
100us
RTC LDO

RCOSC(32K)

TOP LDO/EXT 90us

LDO

1ms
SoC LDO
64us

LDO HFCLK
320us

DCXO EN

HFCLK

Tboot-cold
CPU_Boot

Figure 2-3 Power-on Sequence

2.1.3.2 Wakeup from Standby

VBAT
VDD_EXT/VD
D_IO/VDD_A
NA/VDD_DIG

Event Wakeup by GPIO or timer

RCOSC(32K)

64us

LDO HFCLK
320us

DCXO EN

HFCLK

Tboot-hot
CPU_Boot

Figure 2-4 Wakeup from standby Sequence

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2.1.3.3 Wakeup from Hibernation

VBAT

VDD_EXT/VDD_I
O/VDD_ANA/

Event Wakeup by GPIO or timer

RCOSC(32K)

32us

SoC LDO
64us

LDO HFCLK
320us

DCXO EN

HFCLK

Tboot-cold
CPU_Boot

Figure 2-5 Wakeup from hibernation Sequence

2.1.3.4 Shutdown Sequence

VBAT

VDD_EXT/VD
D_IO/VDD_A
NA/VDD_DIG
Vrest
CHIP_PWD

RCOSC(32K)

SoC LDO
Trest_dig

RTC LDO
Trest_rtc

HFCLK

CPU_Rest

Figure 2-6 Shutdown Sequence

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2.1.4 Memory Mapping
GPIO 0x40050000 – 0x400503FF 1KB
0xE00FFFFF reserved 0x40044400 – 0x4004FFFF 1KB*46
Vendor Reserved 0xE00FF000
0xBAFFFFFF
0xB9C00000 WIFI Peripheral FPB 0xE0042000 TRNG 0x40044400 – 0x400447FF 1KB
Private Peripheral Bus External DWT 0xE0041000 AUDIO CODEC 0x40044000 – 0x400443FF 1KB
ITM 0xE0040000
Private Peripheral Bus Internal Security ID 0x40043C00 – 0x40043FFF 1KB
0xE0000000
0xDFFFFFFF 0xE003F000 IRRX 0x40043800 – 0x40043BFF 1KB
Reserved 0xE000F000
External Device 1GB IRTX 0x40043400 – 0x400437FF 1KB
System Control Space 0xE000E000
Reserved
GPADC 0x40043000 – 0x400433FF 1KB
0xE0003000
FPB 0xE0002000 DAUDIO 0x40042C00 – 0x40042FFF 1KB
DWT 0xE0001000 PWM 0x40042800 – 0x40042BFF 1KB
0xB0000000
ITM 0xE0000000 reserved 0x40042400 – 0x400427FF 1KB
TWI1 0x40042000 – 0x400423FF 1KB
0xA0000000 TWI0 0x40041C00 – 0x40041FFF 1KB
External RAM 1GB
RTC 0x40041800 – 0x40041BFF 1KB
UART2 0x40041400 – 0x400417FF 1KB
UART1 0x40041000 – 0x400413FF 1KB

WIFI SRAM 0x6801CFFF

UART0 0x40040C00 – 0x40040FFF 1KB
64KB(WLAN PAS SRAM)
52KB(WLAN AHB SRAM) TIMER 0x40040800 – 0x40040BFF 1KB
0x68000000 0x43FFFFFF
CCM 0x40040400 – 0x400407FF 1KB
32MB Bit Band Alias
GPRCM 0x40040000 – 0x400403FF 1KB
Peripheral 0.5GB 0x42000000
reserved
0x41FFFFFF 0x4000E000 – 0x4003FFFF 4KB*50
31MB
0x40100000 WIFIC 0x4000D000 – 0x4000DFFF 4KB
1MB Bit Band Region 0x40000000 ICache Controller 0x4000C000 – 0x400CFFFF 4KB
0x40000000
0x3FFFFFFF Flash/PSRAM Controller 0x4000B000 – 0x400BFFFF 4KB
SRAM 0.5GB
SYSCTL 0x4000A000 – 0x4000AFFF 4KB
0x23FFFFFF
DCache Controller 0x40009000 – 0x40009FFF 4KB
0x20000000 32MB Bit Band Alias
Code 0.5GB
0x023FFFFF
reserved 0x40008000 – 0x40008FFF 4KB
< = 16MB (PSRAM) 0x22000000
0x01400000 CSI+JPEG ENC 0x40007000 – 0x40007FFF 4KB
< = 16MB (Flash ROM) 0x21FFFFFF
0x00400000 31MB SPI1 0x40006000 – 0x40006FFF 4KB
0x00271FFF 0x20100000
0x00268000
40KB(icache s hare SRAM)
1MB Bit Band Region
SPI0 0x40005000 – 0x40005FFF 4KB
0x20000000
416KB(SRAM)
0x00200000 SS 0x40004000 – 0x40004FFF 4KB
0x00027FFF
0x00008000
128KB (ROM) SDC1 0x40003000 – 0x40003FFF 4KB
32KB (BROM)
0x00000000 SDC0 0x40002000 – 0x40002FFF 4KB
DMA 0x40001000 – 0x40001FFF 4KB
reserved 0x40000000 – 0x40000FFF 4KB

Figure 2-7 Memory Mapping

Table 2-2 SRAM Memory Mapping

RAM Region SIZE AR400A Address WIFI MCU Address

BROM 32KB 0x00000000 – invisible
0x00007FFF
ROM 128KB 0x00008000 – invisible
0x00027FFF
SRAMA0 288KB 0x00200000 – invisible
0x00247FFF
SRAMA1 128KB 0x00248000 – Shared by WIFI and CSI+JPE, CSI+JPE has high
0x00267FFF priority, APP has lowest priority.
WIFI MCU address range is:0x08080000 –
0x0809FFFF
CSI+JPE use parts of this SRAM for work SRAM.
Only one master access the SRAM at the same
time.
CSI_JPE_SHARE_SRAM=1,
CSI+JPE access 32K bytes (0x00260000 –
0x00267FFF)

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 CSI_JPE_SHARE_SRAM=2,
CSI+JPE access 64K bytes (0x00258000 –
0x00267FFF)
WIFI_SEL_SSRAM=1,
WIFI access 32K bytes (0x00260000 – 0x00267FFF)
WIFI_SEL_SSRAM=2,
WIFI access 64K bytes (0x00258000 – 0x00267FFF)
WIFI_SEL_SSRAM=3,
WIFI access 96K bytes (0x00250000 – 0x00267FFF)
WIFI_SEL_SSRAM=4,
WIFI access 128K bytes (0x00248000 –
0x00267FFF)
WIFI_SEL_SSRAM=0 & CSI_JPE_SHARE_SRAM=0,
AR400A access;
SRAMA2 40KB 0x00268000 – invisible
0x00271FFF
FLASH ROM 16MB 0x00400000 – invisible
0x013FFFFF
WIFI Peripheral 0xB9C00000 – 0xXXXXXXX- 0xXXXXXXXX
0xXXXXXXXX
SRAMC 52KB 0x68000000 – 0x08000000 – 0x0800CFFF (AHB RAM)
0x6800CFFF
SRAMD 64KB 0x6800D000 – 0x09000000 – 0x0900FFFF（PAS RAM）
0x6801CFFF
ROM 128KB invisible 0x00000000 – 0x0001FFFF （ITCM）

2.1.5 CPU
XR872 features an ARM Cortex-M4F processor, which is the most energy efficient ARM processor available. It
supports the clock rates from 32KHz up to 384MHz. The processor provides a low-cost platform that meets the
needs of minimal memory implementation, reduced pin count, and low power consumption.

The ARM Cortex-M4 core has low-latency interrupt processing with the following features:

 Thump-2 instruction set for optimal performance and code size

 Handler and thread modes

 Memory Protection Unit (MPU) for memory protection features

 Floating Point Unit (FPU) to support DSP related function

 Nested Vectored Interrupt Controller (NVIC) to achieve low latency interrupt processing

 Three Advanced High-Performance bus AHB-Lite interfaces: ICode, DCode and system bus

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 21
  Bit-band support for memory and select peripheral that include atomic bit-band write and read
operations

 Wake-up Interrupt Controller (WIC) providing ultra-low power sleep mode support

2.1.6 DMA
There are 8 AHB DMA channels for this DMA controller. Only one channel can be active and the sequence is
according to the priority level.

The DMA controller can support 8-bit/16-bit/32-bit data width. The data width of Source and Destination can be
different, but the address should be aligned. Although the increase mode of NDMA should be address aligned, but
its byte counter should not be multiple. The DMA Source Address, Destination Address, Byte Counter Registers can
be modified even if the DMA is started.

2.1.7 Cache
A configurable 40KB cache is implemented to improve the code fetch performance when CPU accesses a non-zero
wait-state memory such as external flash or PSRAM.

The core cache is a small block of memory containing a copy of a small portion of cached data in the external
memory. If CPU reads a cached data, the data will be copied to the core cache. Once CPU requests the same data
again, it can be obtained directly from the core cache (called cache hit) instead of fetching it again from the
external memory to achieve zero wait-state latency.

The cache can be disabled and this block of memory can be turned into high speed system memory. The sizes of
SRAM and cache can be set to one of the following configurations:

 40KB cache, 416KB SRAM

 32KB cache, 424KB SRAM

 24KB cache, 432KB SRAM

 16KB cache, 440KB SRAM

 8KB cache, 448KB SRAM

 0KB cache, 456KB SRAM

Here, the total cache size with each 8KB block can be set to either I-cache or D-cache. I-cache is only used for
external flash or PSRAM read, while D-cache has both read and write functions. I-cache and D-cache can work
simultaneous to maximum the performance. The cache system has following features:

 Configurable 1/2/4-way set associate (8KB/16KB/32KB)

 Each way has 512 cache lines with 4-word link size

 20-bit tag memory: 19-bit high address and 1-bit valid bit

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 22
Both I-cache and D-cache can be configured to 1/2/4-way, how to use it depends on system application
requirement. The detail configures of I-cache and D-cache please refer to user manual.

2.1.8 Crypto Engine

The Crypto Engine (CE) is one encrypt/decrypt algorithms accelerator. It is suitable for a variety of applications.

Features:

 Supports AES, DES, 3DES, SHA-1, MD5, CRC32/16, SHA256, TRNG

 Supports ECB, CBC, CTR modes for AES/DES/3DES

 Supports 128-bits, 192-bits and 256-bit key size for AES

 Supports 160-bits hardware PRNG with 192-bits seed

The TRNG generates random numbers from the 8 free-run ring oscillators (RCO). IRQ will be issued once the
random data is successfully generated.

2.1.9 Timer
Timer 0 and 1 can take their inputs from internal RC oscillator, external 32768Hz crystal or OSC. They provide the
operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even
for systems with long or short response time. They provide 24-bit programmable overflow counter and work in
auto-reload mode or no-reload mode.

The watch-dog is used to resume the controller operation when it had been disturbed by malfunctions such as
noise and system errors. It features a down counter that allows a watchdog period of up to 16 seconds. It can
generate a general reset or an interrupt request.

2.1.10 RTC
The real time clock (RTC) is for calendar usage. It is built around a 30-bit counter and used to count elapsed time in
YY-MM-DD and HH-MM-SS. The unit can be operated by the backup battery while the system power is off. It has a
built-in leap year generator.

The alarm generates an alarm signal at a specified time in the power-off mode or normal operation mode. In
normal operation mode, both the alarm interrupt and the power management wakeup are activated. In power-off
mode, the power management wakeup signal is activated. In this section, there are two kinds of alarm. Alarm 0 is
a general alarm; its counter is based on second. Alarm 1 is a weekly alarm; its counter is based on the real time.

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 23
2.2 Peripherals

2.2.1 GPIO
The XR872 GPIO unit provides as many as 33 GPIO (General Purpose IO) pins. All ports are brought out of the
device using alternate function multiplexing. The GPIO function can be multiplexed on a multi-function I/O pin by
selecting the GPIO alternate function in the GPIO Controller registers.

There are two types of GPIO designs in XR872: GPIO and AGPIO. Each GPIO can be configured with the following
options:

 Input / Output / Floating(Hi-Z) mode

 Input mode: Pull-up or Pull-down

 Output mode: Active driving

 Pull-up/down control: the pull-up and pull-down resistance is 90KΩ with ±30% variation over PVT
condition

 External Interrupt IO with 5 trigger modes: high-level, low-level, rising edge, falling edge, double edge

 9 WAKEUP IOs can be set to wake system by external interrupt at HIBERNATION mode (RTC on only)

 All IOs can be set to wake system by external interrupt in STANDBY mode (RTC and OA domain on)

The digital IO AGPIO function is equivalent to GPIO as shown above. A dedicated internal control signal is used to
select between the digital and analog functions. These IOs are multiplexed with 8 channels ADC (1 is internal
connected to measure VBAT voltage).

GPIO PA23 has a special function which is used to enter test mode when it is high on first power-up. So we need to
keep it from pulling high (floating or tie low) to have whole chip power up correctly.

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 24
 Table 2-3 XR872AT GPIO Multiplexing

GPIO FUNC2 FUNC3 FUNC4 FUNC5 FUNC6

PA00 SPI1_MOSI SD_CMD TWI1_SCL CSI_D0 EINTA0

PA01 SPI1_MISO SD_DATA0 TWI1_SDA CSI_D1 EINTA1
PA02 SPI1_CLK SD_CLK UART0_TX CSI_D2 EINTA2
PA03 SPI1_CS0 SD_DATA1 UART0_RX CSI_D3 EINTA3
PA04/WUPIO0 UART1_RTS SD_DATA2 TWI0_SCL CSI_D4 EINTA4
PA05/WUPIO1 UART1_CTS SD_DATA3 TWI0_SDA CSI_D5 EINTA5
PA06/WUPIO2 UART1_RX SPI1_CS1 TWI0_SCL CSI_D6 EINTA6
PA07/WUPIO3 UART1_TX SPI1_CS2 TWI0_SDA CSI_D7 EINTA7
PA08 FEM_CTRL1 PWM0/ECT0 TWI1_SCL CSI_PCLK EINTA8
PA09 FEM_CTRL2 PWM1/ECT1 TWI1_SDA CSI_MCLK EINTA9
PA10 ADC_CH0 PWM2/ECT2 DMIC_CLK CSI_HSYNC EINTA10
PA11 ADC_CH1 PWM3/ECT3 DMIC_DATA CSI_VSYNC EINTA11
PA12 ADC_CH2 PWM4/ECT4 I2S_MCLK IR_TX EINTA12
PA13 ADC_CH3 PWM5/ECT5 I2S_BCLK UART1_TX EINTA13
PA14 ADC_CH4 PWM6/ECT6 I2S_DI UART1_RX EINTA14
PA15 ADC_CH5 PWM7/ECT7 I2S_DO UART1_CTS EINTA15
PA16 ADC_CH6 IR_RX I2S_LRCLK UART1_RTS EINTA16
PA17 TWI0_SCL IR_RX / FEM_CTRL1 EINTA17
PA18 TWI0_SDA IR_TX FEM_CTRL2 IR_RX EINTA18
PA19/WUPIO5 UART2_RTS TWI0_SCL PWM0/ECT0 SPI1_MOSI EINTA19
PA20/WUPIO6 UART2_CTS TWI0_SDA PWM1/ECT1 SPI1_MISO EINTA20
PA21/WUPIO7 UART2_RX DMIC_CLK PWM2/ECT2 SPI1_CLK EINTA21
PA22/WUPIO8 UART2_TX DMIC_DATA PWM3/ECT3 SPI1_CS0 EINTA22
PA23/WUPIO9/TEST EXT_DCDC_PUP / FEM_CTRL1 FEM_CTRL2 EINTA23
PB00 UART0_TX JTAG_TMS PWM4/ECT4 SWD_TMS EINTB0
PB01 UART0_RX JTAG_TCK PWM5/ECT5 SWD_TCK EINTB1
PB02 SWD_TMS JTAG_TD0 PWM6/ECT6 FLASH_WP/IO2 EINTB2
PB03 SWD_TCK JTAG_TDI PWM7/ECT7 FLASH_HOLD/IO EINTB3
PB04 SPI0_MOSI SD_CMD UART1_TX 3
FLASH_MOSI/IO0 EINTB4
PB05 SPI0_MISO SD_DATA0 UART1_RX FLASH_MISO/IO1 EINTB5
PB06 SPI0_CS0 FEM_CTRL2 UART1_CTS FLASH_CS EINTB6
PB07 SPI0_CLK SD_CLK UART1_RTS FLASH_CLK EINTB7
PB16 / SD_CMD / / EINTB16
PB17 / SD_DATA0 / / EINTB17
PB18 / SD_CLK / / EINTB18

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 25
 Table 2-4 XR872ET GPIO Multiplexing

GPIO FUNC2 FUNC3 FUNC4 FUNC5 FUNC6

PA00 SPI1_MOSI SD_CMD TWI1_SCL CSI_D0 EINTA0

PA01 SPI1_MISO SD_DATA0 TWI1_SDA CSI_D1 EINTA1
PA02 SPI1_CLK SD_CLK UART0_TX CSI_D2 EINTA2
PA03 SPI1_CS0 SD_DATA1 UART0_RX CSI_D3 EINTA3
PA04/WUPIO0 UART1_RTS SD_DATA2 TWI0_SCL CSI_D4 EINTA4
PA05/WUPIO1 UART1_CTS SD_DATA3 TWI0_SDA CSI_D5 EINTA5
PA06/WUPIO2 UART1_RX SPI1_CS1 TWI0_SCL CSI_D6 EINTA6
PA07/WUPIO3 UART1_TX SPI1_CS2 TWI0_SDA CSI_D7 EINTA7
PA08 FEM_CTRL1 PWM0/ECT0 TWI1_SCL CSI_PCLK EINTA8
PA09 FEM_CTRL2 PWM1/ECT1 TWI1_SDA CSI_MCLK EINTA9
PA10 ADC_CH0 PWM2/ECT2 / CSI_HSYNC EINTA10
PA11 ADC_CH1 PWM3/ECT3 / CSI_VSYNC EINTA11
PA17 TWI0_SCL IR_RX / FEM_CTRL1 EINTA17
PA18 TWI0_SDA IR_TX FEM_CTRL2 IR_RX EINTA18
PA19/WUPIO5 UART2_RTS TWI0_SCL PWM0/ECT0 SPI1_MOSI EINTA19
PA20/WUPIO6 UART2_CTS TWI0_SDA PWM1/ECT1 SPI1_MISO EINTA20
PA21/WUPIO7 UART2_RX / PWM2/ECT2 SPI1_CLK EINTA21
PA22/WUPIO8 UART2_TX / PWM3/ECT3 SPI1_CS0 EINTA22
PA23/WUPIO9/T EXT_DCDC_PUP / FEM_CTRL1 FEM_CTRL2 EINTA23
EST
PB00 UART0_TX JTAG_TMS PWM4/ECT4 SWD_TMS EINTB0
PB01 UART0_RX JTAG_TCK PWM5/ECT5 SWD_TCK EINTB1
PB02 SWD_TMS JTAG_TD0 PWM6/ECT6 FLASH_WP/IO2 EINTB2
PB03 SWD_TCK JTAG_TDI PWM7/ECT7 FLASH_HOLD/IO EINTB3
PB04 SPI0_MOSI SD_CMD UART1_TX 3
FLASH_MOSI/IO EINTB4
PB05 SPI0_MISO SD_DATA0 UART1_RX 0
FLASH_MISO/IO EINTB5
PB06 SPI0_CS0 FEM_CTRL2 UART1_CTS 1
FLASH_CS EINTB6
PB07 SPI0_CLK SD_CLK UART1_RTS FLASH_CLK EINTB7

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 26
2.2.2 UART
The XR872 provides 3 UART controllers: one is used for debug and two with auto-flow control are used for
communication with external devices. The UART has 16450 and 16550 modes of operation, which are compatible
with a range of standard software drivers. In 16550 mode, transmit and receive operations are both buffered by
FIFOs. In 16450 mode, these FIFOs are disabled.

Features:

 Compatible with industry-standard 16550 UARTs

 64-Bytes Transmit and receive data FIFOs

 Support DMA controller interface

 Support Software/ Hardware Flow Control

 Support IrDA 1.0 SIR

 Support RS-485 mode

 Support configurable baud rate from 9600, 19200, 38400, 115200 and 921600 etc.

 Support baud rate detection

2.2.3 SPI
The XR872 features two SPI controllers. Each controller can be configured to a SPI master or a SPI slave. The SPI is
a full-duplex, synchronous, serial communication interface used to control the peripheral devices. The SPI
supports 4 different formats for data transfer. Software can select one of the four modes in which the SPI works by
setting the clock polarity (CPOL) and initial clock phase (CPHA) Register.

 Support standard SPI mode

 Master/Slave configurable

 Up to 3 chip selects to support multiple peripherals

 8-bit wide by 64-entry FIFO for both transmit and receive data

 Interrupt and DMA support

2.2.4 TWI
The XR872 features two TWI serial interfaces. They can be configured as master and salve mode. Each TWI
controller supports three IO mapping. The TWI controllers can be operated in standard mode (100K bps) or
fast-mode, supporting data rate up to 400K bps. Multiple Masters and 10-bit addressing Mode are supported for
this specified application. General Call Addressing is also supported in Slave mode.

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 27
Features:

 Compatible with IIC protocol and SCCB protocol

 Software-programmable for Slave or Master

 Supports Repeated START signal

 Multi-master systems supported

 Allows 10-bit addressing with TWI bus

 Performs arbitration and clock synchronization

 Own address and General Call address detection

 Interrupt on address detection

 Supports speeds up to 400Kbits/s (‘fast mode’)

 Allows operation from a wide range of input clock frequencies

2.2.5 PWM
XR872 features 8 PWMs to generate pulse sequences with programmable frequency a duration for LCD, vibrators
and other devices. The PWM controller provides 8 PWM channels, which are divided into four pairs of PWM pair,
each is composed of three parts: a clock controller, two timer modules, and a programmable dead-zone generator.
The PWM channel logic can be configured as input capture function. The capturer detects the rising edge and the
falling edge of the signal and calculates the high-level and the low-level duration with a 16-bit counter.

Features:

 8 PWM channels, divided into 4 PWM pairs

 Supports pulse, period and complementary pair outputs

 Support input capture

 Programmable dead-zone generator

 Configurable output frequency, 0%-100% duty adjustable

2.2.6 SD/MMC/SDIO
XR872 features a SD/MMC controller can be configured either as a Secure Digital Multimedia Card controller,
which simultaneously supports Secure Digital memory (SD Memo), UHS-1 Card, Secure Digital I/O (SDIO),
Multimedia Cards (MMC), eMMC Card and Consumer Electronics Advanced Transport Architecture (CE-ATA).

Features:

 Supports Secure Digital memory protocol commands (compatible with SD3.0)

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 28
  Supports Secure Digital I/O protocol commands

 Supports Multimedia Card protocol commands

 Supports CE-ATA digital protocol commands

 Supports one SD (Verson1.0 to 3.0) or MMC (Verson3.3 to 4.41) or CE-ATA device

 Supports hardware CRC generation and error detection

 Supports SDIO interrupts in 1-bit and 4-bit modes

 Supports block size of 1 to 65535 bytes

 Supports internal DMA controller

2.2.7 CIR
XR872 features an infrared remote transmitter and a receiver controller. Through the process control pulse
waveform, the remote controller can support a variety of infrared protocol.

The IR receiver controller features:

 Full physical layer implementation

 Support IR for remote control

 64x8 bits FIFO for data buffer

The IR transmitter controller features:

 Full physical layer implementation

 128 bytes FIFO for data buffer

 Configurable carrier frequency

 Interrupt and DMA support

2.2.8 GPADC
XR872 features one GPADC function. The ADC function contains a 8-channel analog switch, a single end input
asynchronous 12-bit SAR (Successive Approximation Register) ADC. The channels 0 to 6 are used to detect the
voltage of the external input and the channel 8 is dedicated to detect the voltage of the VBAT. The channel 7 is NC.

Features:

 12-bit Resolution and 10-bit effective SAR type A/D converter

 8-channel multiplexer, 7 normal channel and 1 VBAT voltage detection channel

 64 FIFO depth of data register

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 29
  DMA support

 Power supply 1.62~3.6V，internal Capless LDO provide 1.4V/2.5V/0.4*VDD-EXT to Vref

 Maximum Sampling frequency: 1 MHz

 Support self-calibration

 Support data compare and interrupt

 Support four operation mode: Single conversion mode, Single-cycle conversion mode, Continuous
conversion mode, Outbreak conversion mode

2.2.9 I2S
XR872 features one DAI(Digital Audio Interface) Controller function. The controller supports standard I2S format,
Left-justified Mode format, Right-justified Mode format, PCM Mode format and TDM Mode format.
Features:
 Compliant with standard Philips Inter-IC sound (I2S) bus specification

 Support full-duplex synchronous work mode

 Compliant with Left-justified, Right-justified, PCM mode, and TDM (Time Division Multiplexing) format

 Support Master / Slave mode

 Support adjustable audio sample resolution from 8-bit to 32-bit.

 Support up to 8 slots which has adjustable width from 8-bit to 32-bit.

 Support sample rate from 8KHz to 192KHz

 Support 8-bits u-law and 8-bits A-law companding sample

 One 128 depth x 32-bit width FIFO for data transmit, one 64 depth x 32-bit width FIFO for data receive

 Support programmable PCM frame width: 1 BCLK width (short frame) and 2 BCLKs width (long frame)

2.3 Video Subsystem

2.3.1 CSI
The Camera Serial Interface (CSI) is a parallel image input interface. It includes the following features:

 8 bits input data

 Support digital camera(DC) interface and CCIR656 interface

 Pass raw data direct to memory

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 30
  Pass jpeg data direct to memory

 Pass YUV420 data to JPEG

 Convert YUV422 data to YUV420

 support X/Y scale 1/2 and cropwin

2.3.2 JPEG
 Supports JPEG base line;

 Supports online encoding mode with CSI;

 Supports nv12 input format in offline encoding mode

 Supports configurable picture resolutions

 Minimum picture resolution: 32x32

 Offline maximum picture resolution: 1920x1088

 Online maximum picture resolution: 1920x1088

 Supports online 640x480@60fps and online 1280x720@40fps

 Supports offline 640x480@60fps and offline 1280x720@20fps

 Supports bitrate control through quantization table

2.4 AUDIO Subsystem

2.4.1 DMIC
XR872 features one DMIC Controller which supports a 2-channels digital microphone interface, the DMIC
controller can output 128fs (fs= ADC sample rate).

Features:

 Support up to 2 channels

 Support sample rate from 8KHz to 24KHz

2.4.2 AUDIO CODEC

XR872 Integrated one ADC and one DAC for audio microphone in and playback, another ADC in line-in channel
used for smart audio AEC feature which record audio signal from power amplifier output.

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 31
ADC (Microphone Input)
 Mono ADC with 100dB SNR typically(A-weight)

 –90 dB THD+N @ 0 dB boost and -3dBFS differential input

 Mono Fully-differential analog microphone input with 0dB~33dB boost amplifier gain

 ADC sample rates supported: 8k, 11.025k, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

Line-in (AEC Input)

 Mono ADC with 99dB SNR typically (A-weight)

 –89 dB THD+N @ 0 dB boost and -3dBFS differential input

 Mono Fully-differential analog microphone input with -3dB~24dB boost amplifier gain

 ADC sample rates supported: 8k, 11.025k, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz

DAC
 Mono DAC with 99dB SNR typically (A-weight)

 –87 dB THD+N @ -3dBFS Output

 Mono Fully-differential Line Output with 0.85Vrms maximum output voltage

 DAC sample rates supported: 8k, 11.025k, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 96kHz,
192kHz

Power Supply
Integrated one low noise LDO for Codec with features as bellow:
 LDO input from 1.8~3.6V

 LDO output is programmable from 1.6~3.025V

 The default output voltage of LDO is set to 2.8V to maintain maximum voltage range. When VBAT is
higher than 2.0V, it maintains good PSRR for Codec. While VBAT is lower than 2.0V, it will have some
performance degradation because of power noise to ADC and DAC.

2.5 Wi-Fi Subsystem

2.5.1 Wi-Fi MAC

Supports MAC enhancements including:

 802.11d - Regulatory domain operation

 802.11e - QoS including WMM

 802.11h - Transmit power control dynamic and frequency selection

 802.11i - Security including WPA2 compliance

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 32
  802.11r - Roaming

2.5.2 Wi-Fi Baseband

Features:

 Compatible with IEEE 802.11 b/g/n standard

 802.11n MCS0-7 with data rate up to 72.2Mbps (BPSK, r=1/2 through 64QAM, r=5/6)

 6M~54M data rate for 802.11g

 DSSS, CCK modulation with long and short preamble

 Short Guard Interval

 Long Guard Interval

 RX antenna Diversity

2.5.3 Wi-Fi Radio

Features:

 Integrated 2.4GHz PA, LNA, and T/R switch

 Internal impedance matching network and harmonic filter allow chip to connect to antenna directly

 High Power Amplifier with 1.8~5.5V full range directly support XRADIOTECH’s MPDTM technology ensure
linearity tracking automatically to always keep EVM and mask within specifications

 Special Architecture and Device design to keep the reliability of PA up to 5.5V high voltage and also
deliver high output power (>25dBm)

2.5.4 Front End Module Control

For applications that use external front-end components, the XR872 provides the ability to control them with two
antenna switch control outputs named:

 FEM_CTRL1: TX_EN
 FEM_CTRL2: RX_EN
FEM_CTRL1 and FEM_CTRL2 are used to control TX and RX signal path separately. It is very useful when customer
want to use XR872 to extend range coverage by add addition high output power RF PA. The typical extend
application is below:

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 33
 DAC LPF PA

RF
S/W
VCO LNA

BB LO
PA

RX_EN
TX_EN
FEM
ADC LPF LNA
FEM_CTRL1
FEM_CTRL2

XR872

Figure 2-8 FEM Control Application Diagram

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 34
3 Electrical Characteristics

3.1 Absolute Maximum Ratings

Table 3-1 Absolute Maximum Ratings

Symbol Parameter Maximum rating Unit

I/O In/Out current for input and output -35 to 35 mA

VBAT 1.8-5.5V Power supply -0.3 to 6 V

CHIP_PWD RESET pin for chip -0.3 to 6 V

VDD_ANA Power supply -0.3 to 3 V

VDD_DIG Power supply -0.3 to 1.5 V

VDD_EXT Power supply -0.3 to 4 V

VDD_PSM Power supply -0.2 to 2.45 V

VDD_IO Power supply -0.3 to 4 V

AVDD Power supply -0.3 to 4 V

Topr Operating Temperature -40 to 85 oC

Tjunction Junction Temperature -40 to 125 oC

Tstg Storage Temperature -65 to 150 oC

VESD HBM ±2000 V

VESD CDM ±500 V

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 35
3.2 Recommended Operating Conditions
Table 3-2 Recommended Operating Conditions

Symbol Parameter Min. Typ. Max. Unit

Topr Ambient Operating Temperature -40 - 85 oC

VBAT Power supply of chip input 1.8 5/3.6/1.8 5.5 V

CHIP_PWD RESET 1.8 - 5.5 V

VDD_ANA Power supply of analog/RF input 1.4 1.8 2.5 V

VDD_DIG Power supply of digital input 0.6 1.1 1.35 V

VDD_EXT Power supply of external device output 1.62 3.3 3.5 V

VDD_PSM Power supply of PSRAM input 1.62 1.8 1.98 V

VDD_IO Power supply of GPIO input 1.62 3.3/1.8 3.6 V

AVDD Power supply of Codec output 1.62 2.8/1.8 2.95 V

3.3 Digital IO Characteristics

Table 3-3 DC Characteristics of VDD_IO=3.3V

Symbol Parameter Condition Min. Max. Unit

VIL Input Low Voltage VDD_IO=3.3V -0.3 1.32 V

VIH Input High Voltage VDD_IO=3.3V 2.06 3.6 V

VOL Output Low Voltage |IOL| = 7.5~50 mA -0.3 0.4 V

VOH Output High Voltage |IOH| = 7.5~50 mA 2.9 3.6 V

RPU Input Pull-up Resistance PU=high, PD=low 35 95 KΩ

RPD Input Pull-down Resistance PU=high, PD=low 35 95 KΩ

Table 3-4 DC Characteristics of VDD_IO=1.8V

Symbol Parameter Condition Min. Max. Unit

VIL Input Low Voltage VDD_IO=1.8V -0.3 0.65 V

VIH Input High Voltage VDD_IO=1.8V 1.18 1.98 V

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 36
VOL Output Low Voltage |IOL| = 2.25~15 mA -0.3 0.4 V

VOH Output High Voltage |IOH| = 2.25~15 mA 1.44 2 V

RPU Input Pull-up Resistance PU=high, PD=low 63 190 KΩ

RPD Input Pull-down Resistance PU=high, PD=low 63 190 KΩ

3.4 Bootstrap Modes and Pins

Table 3-5 Bootstrap pins

Symbol Bootstrap Function Name Value Description

0 Normal operation mode

PA23 Test Mode Enter into test/debug mode when releasing
1
CHIP_PWD

00 When releasing CHIP_PWD will cause the system

going to firmware update mode.

PB02, PB03 Boot Mode 01 Internal normal boot

10

11

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 37
3.5 High Frequency Reference Clock
External XTAL and Built-in Oscillator
Table 3-6 External High Frequency Crystal Characteristics Requirements

Parameter Conditions Min. Typ. Max. Unit

Frequency Range 24,26,40, MHz

ESR - - 60 Ohm

Cin_xtal(1) Single-ended 0 - 25.4 pF

Cshunt(1) - 2 - pF

Load Capacitance(1) - 0 27 pF

Crystal Frequency Accuracy at Nominal Temp. 25 °C -10 - +10 ppm

Crystal Drift Due to Temperature -20 to +85 °C -10 - +10 ppm

Crystal Pull Ability 10 - 150 ppm/pF

(1) The load capacitance value (Cload) and shunt capacitance value(Cshunt) depends on XTAL model, XTAL1 and XTAL2
pin have inside capacitance (Cin_xtal), so external added load capacitance value (PCB Welding Capacitance) Cload_ext =
Cload * 2 - Cin_xtal - Cpcb - Cshunt * 2, Cpcb is PCB parasitic capacitance(single-ended). Cin_xtal has tuning range about
25.4pF, which is controlled by software, for details please go to software user manual.

3.6 Low Frequency Reference Clock

XR872 use low frequency reference clock, it can either use an external low frequency crystal and a built-in
oscillator, or internal RCOSC. The external crystal and a built-in oscillator is used during power save modes.

External XTAL and Built-in Oscillator

Table 3-7 External Low Frequency Crystal Characteristics Requirements

Parameter Conditions Min. Typ. Max. Unit

Nominal Frequency - 32.768 - KHz

Load Capacitance(1) - 12.5 - pF

Cshunt(1) - 2 - pf

(1) The load capacitance value (Cload) and shunt capacitance depends on LXTAL model, external added load
capacitance value(PCB Welding Capacitance) Cload_ext = Cload * 2 - Cpcb - Cshunt * 2, Cpcb is PCB parasitic

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 38
capacitance(Single ended) .

Internal RCOSC Reference Clock Source

XR872 have an integrated RC oscillator low frequency reference clock source inside. This clock is calibrated by APB
clock source from high frequency reference. RCOSC takes effect automatically when there is no external crystal.

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 39
3.7 Audio Codec Specifications
Condition: VBAT=5V, AVDD=2.8V, Temperature=25oC

Table 3-8 ADC Specifications

Parameter Description Performance

Min. Typ. Max. Unit

Full-Scale Input Level PGA Gain=0dB@THD<-40dB 1.75 Vrms

SNR (A-weighted) 100 dB

PGA Gain=0dB
THD+N (-3dBFS 1KHz input) -90 dB

SNR (A-weighted) 94 dB
PGA Gain=24dB
THD+N (-3dBFS 1KHz input) -91 dB

SNR (A-weighted) 84 dB
PGA Gain=36dB
THD+N (-3dBFS 1KHz input) -81 dB

Table 3-9 Line-in Specifications

Parameter Description Performance

Min. Typ. Max. Unit

Full-Scale Input Level PGA Gain=0dB@THD<-40dB 1.8 Vrms

SNR (A-weighted) 99 dB
PGA Gain=0dB
THD+N (-3dBFS 1KHz input) -89 dB

SNR (A-weighted) 91 dB
PGA Gain=24dB
THD+N (-3dBFS 1KHz input) -69 dB

Table 3-10 DAC Specifications

Parameter Description Performance

Min. Typ. Max. Unit

Full-Scale Output Level 0.856 Vrms

SNR (A-weighted) RLoad=100K 99 dB

THD+N(-3dBFS 1KHz output) -87 dB

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Condition: VBAT=3.6V, AVDD=1.8V, Temperature=25oC

Table 3-11 ADC Specifications

Parameter Description Performance

Min. Typ. Max. Unit

Full-Scale Input Level PGA Gain=0dB@THD<-40dB 1.13 Vrms

SNR (A-weighted) 99 dB
PGA Gain=0dB
THD+N (-3dBFS 1KHz input) -93 dB

SNR (A-weighted) 91 dB
PGA Gain=24dB
THD+N (-3dBFS 1KHz input) -84 dB

SNR (A-weighted) 80 dB
PGA Gain=36dB
THD+N (-3dBFS 1KHz input) -78 dB

Table 3-12 Line-in Specifications

Parameter Description Performance

Min. Typ. Max. Unit

Full-Scale Input Level PGA Gain=0dB@THD<-40dB 1.15 Vrms

SNR (A-weighted) 98 dB
PGA Gain=0dB
THD+N (-3dBFS 1KHz input) -93 dB

SNR (A-weighted) 90 dB
PGA Gain=24dB
THD+N (-3dBFS 1KHz input) -76 dB

Table 3-13 DAC Specifications

Parameter Description Performance

Min. Typ. Max. Unit

Full-Scale Output Level 0.551 Vrms

SNR (A-weighted) RLoad=100K 99 dB

THD+N(-3dBFS 1KHz output) -86 dB

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 41
3.8 Wi-Fi 2.4G RF Receiver Specifications
Table 3-14 RF Receiver Specifications

Condition: VBAT=3.6V, VDD_ANA=1.8V, XTAL=40MHz, Temperature=25oC

Parameter Description Performance

Min. Typ. Max. Unit

Frequency Range Center channel frequency 2412 2484 MHz

RX Sensitivity (802.11b) 1Mbps DSSS -95.1 -97.1 dBm

2Mbps DSSS -93.0 -95.0 dBm

5.5Mbps CCK -90.6 -92.6 dBm

11Mbps CCK -87.8 -89.8 dBm

RX Sensitivity (802.11g) 6Mbps OFDM -90.1 -92.1 dBm

9Mbps OFDM -89.4 -91.4 dBm

12Mbps OFDM -88.4 -90.4 dBm

18Mbps OFDM -86.2 -88.2 dBm

24Mbps OFDM -83.4 -85.4 dBm

36Mbps OFDM -80.3 -82.3 dBm

48Mbps OFDM -76.2 -78.2 dBm

54Mbps OFDM -74.4 -76.4 dBm

RX Sensitivity (802.11n, MCS 0 -90.0 -92.0 dBm

20MHz)
MCS 1 -87.6 -89.6 dBm

MCS 2 -85.3 -87.3 dBm

MCS 3 -82.6 -84.6 dBm

MCS 4 -79.3 -81.3 dBm

MCS 5 -75.4 -77.4 dBm

MCS 6 -74.0 -76.0 dBm

MCS 7 -72.3 -74.3 dBm

Maximum Receive Level 6 Mbps OFDM -10.0 0.0 dBm

54 Mbps OFDM -10.0 -5.0 dBm

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 MCS0 -10.0 0.0 dBm

MCS7 -20.0 -5.0 dBm

Receive Adjacent Channel 1 Mbps CCK 42.0 dBc

Rejection
11 Mbps CCK 37.5 dBc

BPSK rate 1/2, 6 Mbps OFDM 35.5 dBc

64QAM rate 3/4, 54 Mbps OFDM 19.2 dBc

HT20, MCS 0, BPSK rate 1/2 28.0 dBc

HT20, MCS 7, 64QAM rate 5/6 10.5 dBc

Note: The minimum limit considers the variation of process, voltage and temperature.

3.9 Wi-Fi 2.4G RF Transmitter Specifications

Table 3-15 RF Transmitter Specifications 1

Condition1: VBAT=3.6V, VDD_ANA=1.8V, XTAL=40MHz, Temperature=25oC

Parameter Description Performance

Min. Typ. Max. Unit

Frequency Range Center channel frequency 2412 2484 MHz

TX Power1 1Mbps DSSS mask compliant 18.8 20.3 dBm

11Mbps CCK mask compliant 18.8 20.3 dBm

6Mbps OFDM mask compliant 17.8 19.3 dBm

54Mbps OFDM EVM compliant 14.8 16.3 dBm

HT20, MCS 0 mask compliant 17.0 18.5 dBm

HT20, MCS 7 EVM compliant 14.2 15.7 dBm

EVM 1Mbps DSSS 17dBm -19.7 -21.7 dB

11Mbps CCK 17dBm -19.3 -21.3 dB

6Mbps OFDM 16dBm -28.5 -30.5 dB

54Mbps OFDM EVM 16dBm -28.9 -30.9 dB

HT20, MCS 0 mask 16dBm -27.8 -29.8 dB

HT20, MCS 7 EVM 15dBm -29.2 -31.2 dB

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 43
Carrier Suppression -30.0 dBc

Accuracy of Power Control Closed-loop control across all -1.5 1.5 dB

temperature ranges and channels

Harmonic Output Power 2nd Harmonic 1Mbps DSSS 17dBm -37.8 dBm/MHz

3rd Harmonic 1Mbps DSSS 17dBm -36.3 dBm/MHz

1. Refer to IEEE 802.11 specification for Tx spectrum limits:

- 802.11b mask (18.4.7.3)

- 802.11g mask (19.5.4)

- 802.11g EVM (17.3.9.6.3)

- 802.11n HT20 mask (20.3.21.1)

- 802.11n HT20 EVM (20.3.21.7.3)

Table 3-16 RF Transmitter Specifications 2

Condition2: VBAT=5.0V, VDD_ANA=1.8V, XTAL=40MHz, Temperature=25oC

Parameter Description Performance

Min. Typ. Max. Unit

Frequency Range Center channel frequency 2412 2484 MHz

TX Power1 1Mbps DSSS mask compliant 20.1 21.6 dBm

11Mbps CCK mask compliant 20.2 21.7 dBm

6Mbps OFDM mask compliant 19.3 20.8 dBm

54Mbps OFDM EVM compliant 16.6 18.1 dBm

HT20, MCS 0 mask compliant 18.6 20.1 dBm

HT20, MCS 7 EVM compliant 15.8 17.3 dBm

EVM 1Mbps DSSS 17dBm -19.2 -21.2 dBm

11Mbps CCK 17dBm -19 -21.0 dBm

6Mbps OFDM 16dBm -28.5 -30.5 dBm

54Mbps OFDM EVM 16dBm -28.6 -30.6 dBm

HT20, MCS 0 mask 16dBm -28.0 -30.0 dBm

HT20, MCS 7 EVM 15dBm -29.5 -31.5 dBm

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 44
Carrier Suppression -30.0 dBc

Accuracy of Power Control Closed-loop control across all -1.5 1.5 dB

temperature ranges and channels

Harmonic Output Power 2nd Harmonic 1Mbps DSSS 17dBm -37.9 dBm/MHz

3rd Harmonic 1Mbps DSSS 17dBm -37.8 dBm/MHz

Table 3-17 RF Transmitter Specifications 3

Condition3: VBAT=1.8V, VDD_ANA=1.6V, XTAL=40MHz, Temperature=25oC

Parameter Description Performance

Min. Typ. Max. Unit

Frequency Range Center channel frequency 2412 2484 MHz

TX Power1 1Mbps DSSS mask compliant 12.6 14.1 dBm

11Mbps CCK mask compliant 12.6 14.1 dBm

6Mbps OFDM mask compliant 10.9 12.4 dBm

54Mbps OFDM EVM compliant 9.2 10.7 dBm

HT20, MCS 0 mask compliant 10.6 12.1 dBm

HT20, MCS 7 EVM compliant 8.3 9.8 dBm

EVM 1Mbps DSSS 12.5dBm -20.5 -22.5 dBm

11Mbps CCK 12.5dBm -19.6 -21.6 dBm

6Mbps OFDM 10.5dBm -22.5 -24.5 dBm

54Mbps OFDM EVM 10.5dBm -25.3 -27.3 dBm

HT20, MCS 0 mask 10.5dBm -22.7 -24.7 dBm

HT20, MCS 7 EVM 9.5dBm -27.7 -29.7 dBm

Carrier Suppression -30.0 dBc

Accuracy of Power Control Closed-loop control across all -1.5 1.5 dB

temperature ranges and channels

Harmonic Output Power 2nd Harmonic 1Mbps DSSS 12.5dBm -40.0 dBm/MHz

3rd Harmonic 1Mbps DSSS 12.5dBm -40.0 dBm/MHz

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 45
3.10 Power Consumption
Table 3-18 Power Consumption 1

Temp=25oC, VBAT=3.6V, VDD_ANA=1.8V, external DC-DC 90% efficiency, MCU 240MHz

Power MCU Wi-Fi TX/R Test Condition Current Consumption Unit

State State X
Mode Min. Typ. Max.

ACTIVE ACTIVE Active TX1 1M DSSS 17dBm 217.0 mA

11M CCK 17dBm 226.6 mA

6M OFDM 16dBm 214.0 mA

54M OFDM 16dBm 218.0 mA

HT20, MCS0 16dBm 201.3 mA

HT20, MCS7 15dBm 196.0 mA

RX 1M DSSS - 40.0 mA

11M CCK - 42.0 mA

54M OFDM - 48.5 mA

HT20, MCS0 - 43.3 mA

HT20, MCS7 - 48.0 mA

STANDBY SLEEP Active TX1 1M DSSS, null 17dBm 217.0 mA

frame

RX RX listen - 40.0 mA

1M DSSS - 32.5 mA

PS RX DTIM1 - 1031.0 uA
Mode2,5
DTIM3 - 428.0 uA

DTIM8 - 186.0 uA

DTIM10 - 154.0 uA

OFF5 - - - 43.0 uA

HIBERNATION3 OFF OFF - - - 5.0 uA

SHUTDOWN4 OFF OFF - - - 0.5 uA

1. Data is captured at TX continues mode on the duration of transmitting;

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 46
2. Use XR872 by external 32K XTAL, Beacon length 1.8ms；

3. RTC and wake up timer on only;

4. CHIP_PWD keeps at low level;

5. Only 40K Bytes SRAM retention;

Table 3-19 Power Consumption 2

Temp=25oC, VBAT=3.6V, VDD_ANA=1.8V, Internal TOP LDO supply, MCU 240MHz

Power MCU Wi-Fi TX/R Test Condition Current Consumption Unit

State State X
Mode Min. Typ. Max.

ACTIVE ACTIVE Active TX1 1M DSSS 17dBm 257.0 mA

11M CCK 17dBm 267.2 mA

6M OFDM 16dBm 269.0 mA

54M OFDM 16dBm 272.0 mA

HT20, MCS0 16dBm 252.5 mA

HT20, MCS7 15dBm 246.0 mA

RX 1M DSSS - 72.0 mA

11M CCK - 75.0 mA

54M OFDM - 84.0 mA

HT20, MCS0 - 77.0 mA

HT20, MCS7 - 89.0 mA

STANDBY SLEEP Active TX1 1M DSSS, null 17dBm 257.0 mA

frame

RX RX listen - 68.0 mA

1M DSSS - 55.0 mA

PS RX DTIM1 - 1736.0 uA
Mode2,5
DTIM3 - 716.0 uA

DTIM8 - 303.0 uA

DTIM10 - 237.0 uA

OFF5 - - - 43.0 uA

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 47
HIBERNATION3 OFF OFF - - - 5.0 uA

SHUTDOWN4 OFF OFF - - - 0.5 uA

1. Data is captured at TX continues mode on the duration of transmitting;

2. Use XR872 by external 32K XTAL, Beacon length 1.8ms；

3. RTC and wake up timer on only;

4. CHIP_PWD keeps at low level;

5. Only 40K Bytes SRAM retention;

Copyright @2019 Xradio Technology Co., Ltd. All Rights Reserved Page 48
4 Package Specifications

4.1 Pin Layout

XR872 use 6mm x 6mm QFN and 5mm x 5mm packages for different feature list.

PA19/PA17
VDD_PSM

VDD_IO

PA06
PA07
PA10
PA11

PA04
PA05

PA20
PA21
PA22
PA23
39 38 37 36 35 34 33 32 31 30 29 28 27
PA09 40 26 AVDD

PA08 41 25 MICP

PA16 42 24 MICN

PA15 43 23 AGND

PA14 44 22 LINEP

21 LINEN
LXTAL2/PA13 45
20 VRA1
LXTAL1/PA12 46
19 VRA2

XR872AT
CHIP_PWD 47
18 LOUTP
VDD_DIG 48
17 PB18
VDD_EXT 49
16 PB17
VDD_ANA 50
15 PB16
VBAT 51

ANT 52 14 PB06
1 2 3 4 5 6 7 8 9 10 11 12 13
HXTAL2

HXTAL1
PB00

PA01

PB04
PB07

PB03
PB05
PB02
PB01
PA00

PA02
PA18/PA03

Figure 4-1 XR872AT Pin Layout

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 PA19/PA17
VDD_IO

PA23
PA04

PA06

PA20
PA21

PA22
PA05

PA07
30 29 28 27 26 25 24 23 22 21
PA11 31 20 AVDD
PA10 32 19 MICP

PA09 33 18 VRA1
PA12/PA08 34 17 AGND
CHIP_PWD 35 16 VRA2

VDD_DIG 36 15 LOUTP

VDD_EXT 37 XR872ET 14 PB06

VDD_ANA 38 13 PB02

VBAT 39 12 PB05

ANT 40 11 PB03
1 2 3 4 5 6 7 8 9 10
HXTAL2
HXTAL1

PB01

PA02
PA00
PA01

PB04

PB07
PB00

PA18/PA03

Figure 4-2 XR872ET Pin Layout

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4.2 Pin Descriptions
Table 4-1 Pin Description

Pin Name I/O XR872AT XR872ET Pin Description

HXTAL1 Analog 2 2 40MHz crystal
HXTAL2 Analog 1 1 40MHz crystal
LXTAL1 Analog 46 / 32.768KHz crystal
LXTAL2 Analog 45 / 32.768KHz crystal
CHIP_PWD Input 47 35 Chip Power Down/System Reset
VDD_ANA Power 50 38 Analog power supply
VDD_DIG Power 48 36 1.1V digital power supply
VBAT Power 51 39 1.8-5.5V power supply
VDD_EXT Power 49 37 external device power supply
VDD_IO Power 36 30 GPIO power supply
VDD_PSM Power 37 / PSRAM power supply
AVDD Power 26 20 Codec ldo output
VRA1 Analog 20 18 Codec analog decap output1
VRA2 Analog 19 16 Codec analog decap output2
AGND Ground 23 17 Codec analog gnd
PA00 In/Out 5 5 Programmable input/output
PA01 In/Out 6 6 Programmable input/output
PA02 In/Out 7 7 Programmable input/output
PA03 In/Out 8 8 Programmable input/output
PA04 In/Out 35 29 Programmable input/output, wakeup io
PA05 In/Out 34 28 Programmable input/output, wakeup io
PA06 In/Out 33 27 Programmable input/output, wakeup io
PA07 In/Out 32 26 Programmable input/output, wakeup io
PA08 In/Out 41 34 Programmable input/output, gpadc in
PA09 In/Out 40 33 Programmable input/output, gpadc in
PA10 In/Out 39 32 Programmable input/output, gpadc in
PA11 In/Out 38 31 Programmable input/output, gpadc in
PA12 In/Out 46 34 Programmable input/output, gpadc in
PA13 In/Out 45 / Programmable input/output, gpadc in

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PA14 In/Out 44 / Programmable input/output, gpadc in
PA15 In/Out 43 / Programmable input/output, gpadc in
PA16 In/Out 42 / Programmable input/output, gpadc in
PA17 In/Out 31 25 Programmable input/output, gpadc in
PA18 In/Out 8 8 Programmable input/output, gpadc in
PA19 In/Out 31 25 Programmable input/output, wakeup io
PA20 In/Out 30 24 Programmable input/output, wakeup io
PA21 In/Out 29 23 Programmable input/output, wakeup io
PA22 In/Out 28 22 Programmable input/output, wakeup io
PA23 In/Out 27 21 Programmable input/output, test strap pin/wakeup
PB00 In/Out 3 3 io
Programmable input/output
PB01 In/Out 4 4 Programmable input/output
PB02 In/Out 13 13 Programmable input/output
PB03 In/Out 11 11 Programmable input/output
PB04 In/Out 9 9 Programmable input/output
PB05 In/Out 12 12 Programmable input/output
PB06 In/Out 14 14 Programmable input/output
PB07 In/Out 10 10 Programmable input/output
PB16 In/Out 15 / Programmable input/output
PB17 In/Out 16 / Programmable input/output
PB18 In/Out 17 / Programmable input/output
ANT Analog 52 40 RF Antenna
LOUTP Output 18 15 Codec DAC output p
MICP Input 25 19 Codec ADC input p
MICN Input 24 / Codec ADC input n
LINEP Input 22 / Codec line-in input p
LINEN Input 21 / Codec line-in input n

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4.3 Package Information

Figure 4-3 QFN52 Package Outline Drawing

Figure 4-4 QFN40 Package Outline Drawing

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4.4 Package Thermal Characteristics
Table 4-2 QFN52 Package Thermal Characteristics

Symbol Parameter Conditions Typ. Unit

ΘJA Junction-to-Ambient JESD51 20 oC /W

76.2 x 114.3mm, 4-layer(2s2p) PCB

No air flow

ΘJB Junction-to-Board JESD51 7.7 oC /W

76.2 x 114.3mm, 4-layer(2s2p) PCB

No air flow

ΘJC Junction-to-Case JESD51 8 oC /W

76.2 x 114.3mm, 4-layer(2s2p) PCB

No air flow

Table 4-3 QFN40 Package Thermal Characteristics

Symbol Parameter Conditions Typ. Unit

ΘJA Junction-to-Ambient JESD51 28 oC /W

76.2 x 114.3mm, 4-layer(2s2p) PCB

No air flow

ΘJB Junction-to-Board JESD51 8.5 oC /W

76.2 x 114.3mm, 4-layer(2s2p) PCB

No air flow

ΘJC Junction-to-Case JESD51 9.2 oC /W

76.2 x 114.3mm, 4-layer(2s2p) PCB

No air flow

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 5 Carrier Information
Table 5-1 Reel Carrier Information

Item Color Size

Reel Blue 13 inches
Aluminum foil bags Silvery white 450mm x 375mm x 0.14mm
Inside Box White 336mm x 336mm x 48mm
Outside Box White 423mm x 358mm x 365mm

Figure 5-1 Tape Dimension Drawing

Table 5-2 Tape Dimension

Device W(mm) A0(mm) B0(mm) K0(mm) P0(mm) P1(mm) P2(mm) F(mm) E(mm) D0(mm) D1(mm) T(mm)

 0 . 10  0 . 10  0 . 10
XR872AT 16±0.30 6.30±0.1 6.30±0.1 1 . 10  0 . 05 4.0±0.1 8.00±0.1 2.0±0.1 7.5±0.1 1.75±0.1 1 . 5  0 . 00 1 . 5  0 . 00 0.3±0.05

 0 . 10  0 . 10  0 . 10
XR872ET 12±0.30 5.30±0.1 5.30±0.1 0 . 85  0 . 05
4.0±0.1 8.00±0.1 2.0±0.1 5.5±0.1 1.75±0.1 1 . 5  0 . 00 1 . 5  0 . 00 0.3±0.05

Table 5-3 Packing Quantity Information

Type Quantity Part Number

Tape Reel 3000pcs XR872AT

Tape Reel 3000pcs XR872ET

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6 Reflow Profile
The reflow profile recommended in this document is a lead-free reflow profile that is suitable for pure
lead-free technology of lead-free solder paste.

Figure 6-1 shows the typical reflow profile of XR872 device sample.

Figure 6-1 XR872 Typical Reflow Profile

Reflow profile conditions of XR872 device sample is given in Table 6-1.

Table 6-1 XR872 Reflow Profile Conditions

QTI typical SMT reflow profile conditions (for reference only)

Step Reflow condition

N2 purge reflow usage (yes/no) Yes, N2 purge used

Environment
If yes, O2 ppm level O2 < 1500 ppm

A Preheat ramp up temperature range 25℃ -> 150℃

B Preheat ramp up rate 1.5~2.5 ℃/sec

C Soak temperature range 150℃ -> 190℃

D Soak time 80~110 sec

E Liquidus temperature 217℃

F Time above liquidus 60-90 sec

G Peak temperature 240-250℃

H Cool down temperature rate ≤4℃/sec

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7 Application Circuit

Figure 7-1 Reference Design of XR872AT

Figure 7-2 Reference Design of XR872ET

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