Digital

Fundamentals
Tenth Edition

Floyd

Chapter 7

© 2009 Pearson Education,©Upper

2008 Pearson Education
Floyd, Digital Fundamentals, 10th ed Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches

A latch is a temporary storage device that has two stable

states (bistable). It is a basic form of memory.
The S-R (Set-Reset) latch is the most basic type. It can be constructed
from NOR gates or NAND gates. With NOR gates, the latch responds
to active-HIGH inputs; with NAND gates, it responds to active-LOW
inputs.
R S
Q Q

Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches
The active-HIGH S-R latch is in a stable (latched) condition
when both inputs are LOW.
0 R 01
Assume the latch is initially RESET Q
(Q = 0) and the inputs are at their Latch
inactive level (0). To SET the latch initially
(Q = 1), a momentary HIGH signal RESET
10
is applied to the S input while the R Q
0 S
remains LOW.
0 R 01
To RESET the latch (Q = 0), a Q
momentary HIGH signal is Latch
applied to the R input while the S initially
remains LOW. SET
01
Q
0 S

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches
The active-LOW S-R latch is in a stable (latched) condition
when both inputs are HIGH.
Assume the latch is initially RESET 1 S 01
Q
(Q = 0) and the inputs are at their
Latch
inactive level (1). To SET the latch initially
(Q = 1), a momentary LOW signal RESET
is applied to the S input while the R 01
1 R Q
remains HIGH.
To RESET the latch a momentary 1 S 01
Q
LOW is applied to the R input
Latch
while S is HIGH. initially
Never apply an active set and 01 SET
Q
reset at the same time (invalid). 1R

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches
The active-LOW S-R latch is available as the 74LS279A IC.
It features four internal latches with (2)
1S1
two having two S inputs. To SET any (3) (4) 1Q
1S2
of the latches, the S line is pulsed low. (1)
1R
It is available in several packages. (6)
2S (7)
S-R latches are frequently used for 2Q
(5)
2R
switch debounce circuits as shown:
VCC (11)
3S1
(12) (9) 3Q
3S2
(10)
3R
(15)
2 S Q 4S (13)
S (14)
4Q
4R
R R Position Position
1 1 to 2 2 to 1
74LS279A

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches
A gated latch is a variation on the basic latch.
The gated latch has an additional S
Q
input, called enable (EN) that must
be HIGH in order for the latch to
EN
respond to the S and R inputs.
Show the Q output with Q
relation to the input signals. R
Assume Q starts LOW.
Keep in mind that S and R are only active when EN is HIGH.
S
R

EN
Q

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches
The D latch is an variation of the S-R latch but combines
the S and R inputs into a single D input as shown:
D D Q
Q

EN EN

Q
Q

A simple rule for the D latch is:

Q follows D when the Enable is active.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches
The truth table for the D latch summarizes its operation. If
EN is LOW, then there is no change in the output and it is
latched.
Inputs Outputs
D EN Q Q Comments
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q0 Q0 No change

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Latches D Q

EN
Determine the Q output for the
Q
D latch, given the inputs shown.

EN

Notice that the Enable is not active during these times, so

the output is latched.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flops
A flip-flop differs from a latch in the manner it changes
states. A flip-flop is a clocked device, in which only the
clock edge determines when a new bit is entered.
The active edge can be positive or negative.
D Q D Q

C C

Dynamic Q Q
input
indicator (a) Positive edge­triggered (b) Negative edge­triggered

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flops

The truth table for a positive-edge triggered D flip-flop

shows an up arrow to remind you that it is sensitive to its
D input only on the rising edge of the clock; otherwise it is
latched. The truth table for a negative-edge triggered D
flip-flop is identical except for the direction of the arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flops

The J-K flip-flop is more versatile than the D flip flop. In

addition to the clock input, it has two inputs, labeled J and
K. When both J and K = 1, the output changes states
(toggles) on the active clock edge (in this case, the rising
edge).
Inputs Outputs
J K CLK Q Q Comments

0 0 Q0 Q0 No change
0 1 0 1 RESET
1 0 1 0 SET
1 1 Q0 Q0 Toggle

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flops Q
J

CLK
Determine the Q output for the J-K
flip-flop, given the inputs shown. K Q

Notice that the outputs change on the leading edge of the clock.

Set Toggle Set Latch

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flops

A D-flip-flop does not have a toggle mode like the J-K flip-
flop, but you can hardwire a toggle mode by connecting Q
back to D as shown. This is useful in some counters as you
will see in Chapter 8.
D Q

For example, if Q is LOW, Q is CLK CLK

HIGH and the flip-flop will toggle
on the next clock edge. Because the Q
flip-flop only changes on the active
edge, the output will only change
once for each clock pulse.
D flip-flop hardwired for
a toggle mode

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flops

Synchronous inputs are transferred in the triggering edge

of the clock (for example the D or J-K inputs). Most flip-
flops have other inputs that are asynchronous, meaning
they affect the output independent of the clock.
PRE
Two such inputs are normally labeled
preset (PRE) and clear (CLR). These Q
J
inputs are usually active LOW. A J-K
flip flop with active LOW preset and CLK
CLR is shown.
K Q

CLR

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary PRE

Flip-flops J Q

CLK

Determine the Q output for the J-K K Q

flip-flop, given the inputs shown.
CLR
Set Toggle Set Reset Toggle Latch
CLK

K Set
PRE Reset
CLR

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flop Characteristics
Propagation delay time is specified for the rising and
falling outputs. It is measured between the 50% level of the
clock to the 50% level of the output transition.
50% point on triggering edge

CLK CLK 50% point

Q 50% point on LOW-to- Q 50% point on HIGH-to-

HIGH transition of Q LOW transition of Q

tPLH tPHL

The typical propagation delay time for the 74AHC family (CMOS)
is 4 ns. Even faster logic is available for specialized applications.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flop Characteristics

Another propagation delay time specification is the time

required for an asynchronous input to cause a change in the
output. Again it is measured from the 50% levels. The
74AHC family has specified delay times under 5 ns.

PRE 50% point CLR 50% point

Q 50% Q 50% point

point

tPHL tPLH

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flop Characteristics

Set-up time and hold time are times required before and
after the clock transition that data must be present to be
reliably clocked into the flip-flop.
D
Setup time is the minimum
time for the data to be present CLK
before the clock.
Set-up time, ts

D
Hold time is the minimum
time for the data to remain after CLK
the clock.

Hold time, tH

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flop Characteristics

Other specifications include maximum clock frequency,

minimum pulse widths for various inputs, and power
dissipation. The power dissipation is the product of the
supply voltage and the average current required.
A useful comparison between logic families is the speed-power product
which uses two of the specifications discussed: the average propagation
delay and the average power dissipation. The unit is energy.
What is the speed-power product for 74AHC74A? Use
the data from Table 7-5 to determine the answer.
From Table 7-5, the average propagation delay is 4.6 ns.
The quiescent power dissipated is 1.1 mW. Therefore, the
speed-power product is 5 pJ

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Output
Flip-flop Applications lines
Q0
Principal flip-flop applications are for
D

temporary data storage, as frequency R

dividers, and in counters (which are D Q1

covered in detail in Chapter 8). C

Q2
Typically, for data storage applications, D

a group of flip-flops are connected to Parallel data

C

parallel data lines and clocked together. input lines R

Data is stored until the next clock pulse. D Q3

Clock C

R
Clear

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
Flip-flop Applications

For frequency division, it is simple to use a flip-flop in

the toggle mode or to chain a series of toggle flip flops to
continue to divide by two. HIGH HIGH

One flip-flop will divide fin

J QA J QB fout
by 2, two flip-flops will
divide fin by 4 (and so on). fin CLK CLK
A side benefit of frequency
division is that the output K K
has an exact 50% duty fin
cycle.
Waveforms:
fout

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
One-Shots
The one-shot or monostable multivibrator is a device
with only one stable state. When triggered, it goes to
its unstable state for a predetermined length of time,
then returns to its stable state. +V

REXT CEXT
For most one-shots, the length of time Q
CX
in the unstable state (tW) is determined RX/CX
Trigger
by an external RC circuit.
Q
Trigger

Q
tW

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
One-Shots
Nonretriggerable one-shots do not respond to any
triggers that occur during the unstable state.
Retriggerable one-shots respond to any trigger, even if
it occurs in the unstable state. If it occurs during the
unstable state, the state is extended by an amount
equal to the pulse width.
Retriggerable one-shot:
Trigger
Retriggers
Q
tW

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
One-Shots

An application for a retriggerable one-shot is a power

failure detection circuit. Triggers are derived from the
ac power source, and continue to retrigger the one
shot. In the event of a power failure, the one-shot is
not triggered and an alarm can be initiated.
Triggers Missing trigger
derived due to power
from ac failure

Q Retriggers Retriggers Power failure indication

tW
tW
tW

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 555 timer

The 555 timer can be configured in various ways,

including as a one-shot. A basic one shot is shown. The
pulse width is determined by R1C1 and is approximately tW
+V
= 1.1R1C1. CC

(4) (8)
R1
(7) RESET VCC
DISCH
(6) (3)
The trigger is a THRES OUT
negative-going (2) (5) tW = 1.1R1C1
TRIG CONT
pulse. GND
C1 (1)

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 555 timer
Determine the pulse width for the circuit
shown.
tW = 1.1R1C1 = 1.1(10 k)(2.2 F) = 24.2 ms
+VCC
+15 V

(4) (8)
R1
10 k (7) RESET VCC
DISCH
(6) (3)
THRES OUT
(2) (5) tW = 1.1R1C1
TRIG CONT
C1 GND
(1)
2.2 F

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 555 timer

The 555 can be configured as a basic astable multivibrator

with the circuit shown. In this circuit C1 charges through
R1 and R2 and discharges through only R2. The output
+V CC

frequency is given by:

1.44
f  (4) (8)
 R1  2 R2  C1 R1
RESET VCC
(7)
DISCH
The frequency and duty cycle R2 (6)
THRES OUT
(3)

are set by these components. (2) (5)

TRIG CONT
C1 GND
(1)

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Summary
The 555 timer
Given the components, you can read the frequency from
the chart. Alternatively, you can use the chart to pick
components for a desired frequency.
+VCC
100

10 (4) (8)
R1
RESET VCC
1.0 (7)
DISCH
C1 (F)

(6) (3)
0.1 R2 THRES OUT
(2) (5)
TRIG CONT
0.01
C1 GND
(1)
0.001
0.1 1.0 10 100 1.0k 10k 100k

f (Hz)

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Selected Key Terms

Latch   A bistable digital circuit used for storing a bit.
Bistable Having two stable states. Latches and flip­flops are 
bistable multivibrators.
Clock A triggering input of a flip­flop. 

D flip­flop A type of bistable multivibrator in which the 
output assumes the state of the D input on the 
triggering edge of a clock pulse.

J­K flip­flop A type of flip­flop that can operate in the SET, 
RESET, no­change, and toggle modes.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 Selected Key Terms

Propagation  The interval of time required after an input signal 
delay time   has been applied for the resulting output signal to 
change.
Set­up time The time interval required for the input levels to be 
on a digital circuit.
Hold time The time interval required for the input levels to
remain steady to a flip­flop after the triggering 
edge in order to reliably activate the device.
Timer A circuit that can be used as a one-shot or as an
oscillator.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
 1. The output of a D latch will not change if
a. the output is LOW
b. Enable is not active
c. D is LOW
d. all of the above

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 2. The D flip-flop shown will
D Q
a. set on the next clock pulse
CLK CLK
b. reset on the next clock pulse
c. latch on the next clock pulse Q

d. toggle on the next clock pulse

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 3. For the J-K flip-flop shown, the number of inputs that
are asynchronous is
PRE
a. 1
b. 2 J Q

c. 3 CLK

Q
d. 4 K

CLR

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 4. Assume the output is initially HIGH on a leading edge
triggered J-K flip flop. For the inputs shown, the output
will go from HIGH to LOW on which clock pulse?
a. 1
CLK
b. 2 J

c. 3 K
1 2 3 4
d. 4

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 5. The time interval illustrated is called
a. tPHL 50% point on triggering edge

b. tPLH CLK

c. set-up time
Q 50% point on LOW-to-
d. hold time HIGH transition of Q
?

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 6. The time interval illustrated is called
a. tPHL
D
b. tPLH
CLK
c. set-up time
d. hold time ?

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 7. The application illustrated is a
a. astable multivibrator HIGH HIGH

b. data storage device fout

J QA J QB
c. frequency multiplier fin CLK CLK

d. frequency divider
K K

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 Output
lines
Q0
8. The application illustrated is a
D

a. astable multivibrator R

D Q1
b. data storage device C

c. frequency multiplier D Q2

d. frequency divider
C
Parallel data
input lines R

D Q3
Clock C

R
Clear

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 9. A retriggerable one-shot with an active HIGH output has
a pulse width of 20 ms and is triggered from a 60 Hz line.
The output will be a
a. series of 16.7 ms pulses
b. series of 20 ms pulses
c. constant LOW
d. constant HIGH

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 10. The circuit illustrated is a +VCC

a. astable multivibrator
(4) (8)
R1
b. monostable multivibrator (7)
RESET VCC
DISCH
c. frequency multiplier R2 (6)
THRES OUT
(3)

(2) (5)
d. frequency divider C1
TRIG CONT
GND
(1)

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
© 2008 Pearson Education
 Answers:
1. b 6. d
2. d 7. d
3. b 8. b
4. c 9. d
5. b 10. a

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved