EMC2112

RPM-Based Linear Fan

Controller with Hardware
Thermal Shutdown

PRODUCT FEATURES Datasheet

General Description Applications

The EMC2112 is an SMBus, closed-loop, RPM-based „ Notebook Computers
fan driver with hardware (HW) thermal shutdown and „ Desktop Computers
reset controller. The EMC2112 offers a single High Side „ Embedded Applications
fan driver capable of sourcing up to 600mA from a 5V
supply. Features
The EMC2112 utilizes Beta Compensation (an „ Closed-Loop RPM-Based Fan Controller
implementation of the BJT or transistor model for — 1% accuracy with external clock input
thermal diodes) and Resistance Error Correction (REC) — 3% accuracy with internal clock
to accurately monitor up to three (3) external — Internal clock can be used as a source
— Aging fan detection
temperature zones. These features allow great accuracy
for CPU substrate thermal diodes on multiple process „ Integrated Linear Fan Driver
geometries as well as with discrete diode-connected — 600mA drive capability
transistors. Both Beta Compensation and REC can be „ HW Thermal Shutdown (SYS_SHDN)
disabled on the EMC2112 to maintain accuracy when — 1°C incremental set points for thermal shutdown
monitoring AMD thermal diodes. — Cannot be disabled by software
„ Provides Reset Function (RESET) On 5V Supply
The EMC2112 provides a stand-alone HW thermal „ Up to Three (3) Remote Thermal Zones
shutdown block. The HW thermal shutdown logic can be — ±1°C accuracy (60°C to 100°C)
configured for a few common configurations based on — 0.125°C resolution
the strapping level of the SHDN_SEL pin on the PCB. — Designed to support 45nm, 65nm, and 90nm CPU
The HW thermal shutdown point can be set in 1°C Diodes using BJT and transistor model
increments by using a discrete resistor connected to the — Eliminates temperature offset due to series resistance
TRIP_SET pin. from PCB traces and thermal ‘Diode’
„ Operates From Single 3.0 - 3.6V Supply
The EMC2112 also provides 5V supply ‘power good’ — 5V supply for linear fan driver and reset generator
function with a threshold of 4.5V. This function is „ SMBus 2.0 and I2C compatible
provided on the RESET pin. — User selectable SMBus address using pull-up resistor
on ADDR_SEL pin
— Supports Block Read and Write functionality
„ Available in 20-pin, 4x4 QFN Lead-free RoHS
Compliant package

SMSC EMC2112 DATASHEET Revision 0.88 (11-20-09)

 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

ORDERING INFORMATION:

ORDERING NUMBER PACKAGE FEATURES

EMC2112-BP-TR 20-pin QFN 4mm x 4mm Three External Diodes. High Side Fan driver
(Lead-Free RoHS w/ RPM based Fan Speed Control algorithm.
compliant) Reset generator. Hardware set critical
temperature limit

REEL SIZE IS 4,000 PIECES

This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.

Copyright © 2009 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

Revision 0.88 (11-20-09) 2 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table of Contents

Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Pin Layout for EMC2112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Pin Description for EMC2112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 4 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.3 SMBus Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.5 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.6 SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.7 SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.5 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.6 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.7 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1 Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 RPM-Based Fan Speed Control Algorithm (FSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.1 Programming the RPM-Based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . 22
5.3 Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.1 Stalled Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.2 Aging Fan or Invalid Drive Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.3 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.4 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.5.1 Temperature Bypass of Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.6.1 Power Up Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6.2 Continuous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.7 High Side Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.7.1 Overcurrent Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.8 Internal Thermal Shutdown (TSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.9 Critical/Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.9.1 TRIP_SET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.9.2 SHDN_SEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9.3 Internal HW_SHDN Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.10 5V Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SMSC EMC2112 3 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

5.11 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.11.1 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.11.2 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.11.3 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.11.4 Digital Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.12 Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.12.1 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Chapter 6 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3 Critical/Thermal Shutdown Temperature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.4 TripSet Voltage Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.5 Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.6 Beta Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.7 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.8 Critical Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.9 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.10 Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.11 Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.12 Error Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.12.1 Tcrit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.13 Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.14 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.15 Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.16 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.17 Fan Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.18 Fan Configuration 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.19 Fan Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.20 Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.21 Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.22 Fan Max Step Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.23 Fan Minimum Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.24 Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.25 Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.26 TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.27 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.28 Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.29 Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.30 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.31 Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.32 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Chapter 7 Typical Operating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

8.1 EMC2112 Package Drawings - 20-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8.2 Package Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Chapter 9 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Revision 0.88 (11-20-09) 4 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

List of Figures
Figure 1.1 EMC2112 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.1 EMC2112 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4.1 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5.1 EMC2112 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5.2 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 5.3 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 5.4 EMC2112 Critical/Thermal Shutdown Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5.5 HW_SHDN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5.6 5V Reset Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5.7 Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8.1 EMC2112 Package Drawing - 20-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 8.2 EMC2112 Package Dimensions and Notes - 20-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . 63
Figure 8.3 EMC2112 PCB Footprint - 20-Pin QFN 4mm x 4mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 8.4 EMC2112 Package Markings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

SMSC EMC2112 5 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

List of Tables
Table 2.1 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4.1 ADDR_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4.2 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4.4 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4.5 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4.6 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4.7 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4.8 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4.9 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5.1 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5.2 TRIP_SET Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5.3 SHDN_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 5.4 Dynamic Averaging Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6.1 EMC2112 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 6.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6.4 Critical/Thermal Shutdown Temperature Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6.5 Critical / Thermal Shutdown Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6.6 TripSet Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 6.7 Ideality Factor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 6.8 Ideality Factor Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6.9 Substrate Diode Ideality Factor Look-Up Table (BJT Model) . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6.10 Beta Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 6.11 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6.12 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 6.13 Tcrit Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 6.14 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6.15 Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 6.16 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6.17 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6.18 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6.19 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 6.20 Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 6.21 Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 6.22 Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6.23 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6.24 Fan Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 6.25 Fan Configuration 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 6.26 Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 6.27 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 6.28 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 6.29 Fan Configuration 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 6.30 Derivative Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 6.31 Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 6.32 Gain Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 6.33 Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 6.34 Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Revision 0.88 (11-20-09) 6 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.35 DRIVE_FAIL_CNT[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 6.36 Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 6.37 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 6.38 Fan Max Step Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 6.39 Minimum Fan Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 6.40 Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 6.41 Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 6.42 TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 6.43 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 6.44 Software Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 6.45 Product Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 6.46 ADDR_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 6.47 SHDN_CH Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 6.48 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 6.49 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 6.50 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

SMSC EMC2112 7 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 1 Block Diagram

SYS_SHDN

ADDR_SEL
SHDN_SEL
VDD_3V

RESET
VDD_5V

SMCLK
TRIP_SET SMBus
Critical / Thermal Reset Slave SMDATA
Shutdown Logic Generator Protocol
DP1 ALERT
DN1 External
Temp
DP2 / DN3 Diodes
DN2 / DP3 Ext Temp
Analog Limit
Anti- Mux Registers
parallel
Diode
11 bit Σ Δ
Internal Ext. Temp Registers
ADC
Temp
Diode
Voltage Reading
Bandgap Register
Reference Set and
Logic
Voltage ->
Temperature
Converison
Automatic
Fan Control
8-bit DAC Algorithm

High Side TACH

Fan Driver Monitor
TACH

CLK
VDD_5V (2)

FAN (2)

Figure 1.1 EMC2112 Block Diagram

Revision 0.88 (11-20-09) 8 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 2 Pin Layout

2.1 Pin Layout for EMC2112

19 VDD_5V

16 VDD_5V
20 TACH

18 FAN
17 FAN
VDD_3V 1 15 SMCLK

DN1 2 EMC2112 14 SMDATA

20-pin
DP1 3 13 GND
QFN 4mm x
DN2 / DP3 4 4mm 12 ALERT
DP2 / DN3 5 ADDR_SEL 10 11 CLK
SHDN_SEL 6
TRIP_SET 7

SYS_SHDN 8
RESET 9

GND

Figure 2.1 EMC2112 Pin Diagram

2.2 Pin Description for EMC2112

Table 2.1 Pin Description

PIN NAME FUNCTION TYPE

1 VDD_3V 3.3V Supply Voltage Power

2 DN1 Negative (cathode) Analog Input for External AIO

Diode 1

3 DP1 Positive (anode) Analog Input for External Diode AIO

1

4 DN2 / DP3 Negative (cathode) Analog Input for External AIO

Diode 2 and Positive (anode) Analog Input for
External Diode 3

SMSC EMC2112 9 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 2.1 Pin Description (continued)

PIN NAME FUNCTION TYPE

5 DP2 / DN3 Positive (anode) Analog Input for External Diode AIO
2 and Negative (cathode) Analog Input for
External Diode 3

6 SHDN_SEL Determines HW Shutdown temperature channel DIT

7 TRIP_SET Voltage input to determine HW Shutdown AIO

threshold temperature

8 SYS_SHDN Active low Critical System Shutdown output OD (5V)

9 RESET Push-Pull, active low reset output DO

10 ADDR_SEL Selects SMBus Address DIT

11 CLK Tachometer clock input DI (5V)

Tachometer clock output DO

12 ALERT Open drain, active low interrupt. Requires OD (5V)

external pull-up resistor

13 GND Ground Connection Power

14 SMDATA SMBus data input/output - requires external pull- DIOD (5V)

up resistor

15 SMCLK SMBus clock input - requires external pull-up DI (5V)

resistor

16 VDD_5V 5V supply input for the linear fan driver. Both Power
VDD_5V pins should be connected to same 5V
supply.

17 FAN Linear fan drive signal. Both FAN pins should be AO

connected together.

18 FAN Linear fan drive signal. Both FAN pins should be AO

connected together.

19 VDD_5V 5V supply input for the linear fan driver. Both Power
VDD_5V pins should be connected to same 5V
supply.

20 TACH Tachometer input from Fan DI (5V)

The pin type are described in Table 2.2. All pins labeled with (5V) are 5V tolerant.

Table 2.2 Pin Types

PIN TYPE DESCRIPTION

Power This pin is used to supply power or ground to the device.

DI Digital Input - this pin is used as a digital input. This pin is

5V tolerant.

AO Analog Output - this pin is used as an output for analog

signals.

AIO Analog Input / Output - this pin is used as an I/O for analog
signals.

Revision 0.88 (11-20-09) 10 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 2.2 Pin Types (continued)

PIN TYPE DESCRIPTION

DO Push / Pull Digital Output - this pin is used as a digital

output. It can both source and sink current.

DIOD Digital Input / Open Drain Output - this pin is used as a

digital I/O. When it is used as an output, it is open drain
and requires a pull-up resistor. This pin is 5V tolerant.

DIO Digital Input / Output - this pin is used as a digital I/O. It is

push-pull and can sink or source up to 8mA.

OD Open Drain Digital Output - this pin is used as a digital

output. It is open drain and requires a pull-up resistor. This
pin is 5V tolerant.

DIT Tri-stated Digital Input - this pin is a digital input that

supports 3 logic levels at the input: logic high, logic low, or
high impedance (open).

SMSC EMC2112 11 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 3 Electrical Specifications

3.1 Absolute Maximum Ratings

Table 3.1 Absolute Maximum Ratings

Voltage on VDD_5V Pins and 5V tolerant pins (see Table 2.1) -0.3 to 6.5 V

Voltage on VDD_3V pin -0.3 to 4 V

Voltage on FAN pins -0.3 to VDD_5V + 0.3 V

Voltage on any other pin to GND -0.3 to VDD_3V + 0.3 V

Package Power Dissipation 0.9 up to TA = 85°C Note 3.2 W

Junction to Ambient - 20 pin QFN (θJA) Note 3.3 40 °C/W

Operating Ambient Temperature Range 0 to 85 °C

Operating Die Temperature Range 0 to 125 °C

Storage Temperature Range -55 to 150 °C

ESD Rating, All Pins, HBM 2000 V

These ratings are absolute maximum values. Exceeding these values or operating at these values for
an extended period of time may cause permanent damage to the device.

Note 3.1 All voltages are relative to ground.

Note 3.2 The Package Power Dissipation specification assumes a thermal via design consisting of
four 20mil vias connected to the ground plane with a 2.6mm x 2.6mm thermal landing.

Note 3.3 Junction to Ambient (θJA) is dependent on the design of the thermal vias. Without thermal
vias and a thermal landing, the θJA is approximately 60°C/W including localized PCB
temperature increase.

3.2 Electrical Specifications

Table 3.2 Electrical Specifications

VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0°C to 85°C

all Typical values at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

DC Power

3.3V Supply Voltage VDD_3V 3 3.3 3.6 V

5V Supply Voltage VDD_5V 4.6 5 5.5 V

Supply Current from IDD3 0.750 1.6 mA Fan Driver enabled

VDD_3V pin 4 conversions / sec

Supply Current from IDD5 50 uA Fan Driver enabled

VDD_5V pin

Revision 0.88 (11-20-09) 12 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 3.2 Electrical Specifications (continued)

VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0°C to 85°C

all Typical values at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

External Temperature Monitors

Temperature ±0.25 ±1 °C 60°C < TDIODE < 100°C

Accuracy 30°C < TDIE < 85°C (Note 3.4)

±0.5 ±2 °C 0°C < TDIODE < 125°C,

0°C < TDIE < 115°C (Note 3.4)

Temperature 0.125 °C
Resolution

Diode Decoupling CFILTER 2700 pF Connected across external

Capacitor 2N3904 diode or AMD diode
(Note 3.5)

Resistance Error RSERIES 100 Ohm Series resistance in DP and DN

Corrected lines

Internal Temperature Monitor

Temperature ±1 ±2 °C (Note 3.4)

Accuracy

Temperature 0.125 °C
Resolution

Reset Generator

Reset Voltage VRESET 4.3 4.4 4.5 V VDD_5V rising edge

3V < VDD_3V < 3.6V

Hysteresis ΔVRESET 100 mV

Time Delay tRESET 220 ms

High Side Fan Driver

Output High Voltage VOH_5V VDD_5 V ISOURCE = 600mA, VDD_5V =

from 5V Supply V - 0.4 5V

Fan Drive Current ISOURCE 600 mA

Overcurrent Limit IOVER 1500 mA Momentary Current drive at

startup for < 2 seconds

DC Short Circuit ISHORT 800 mA Sourcing current, Thermal

Current Limit shutdown not triggered,
FAN_OUT = 0V

Short Circuit Delay tDFS 2 s

Output Capacitive CLOAD 100 uF

Load

ESR on CLOAD RESR 0 2 Ohm

RPM-Based Fan Controller

TACH Range TACH 480 16000 RPM

SMSC EMC2112 13 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 3.2 Electrical Specifications (continued)

VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0°C to 85°C

all Typical values at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS

RPM Control ΔTACH ±0.25 ±0.5 % External oscillator 32.768kHz

Accuracy
ΔTACH ±0.5 ±1 % Internal Oscillator
40°C < TDIE < 100°C

Thermal Shutdown

Thermal Shutdown TSDTH 150 °C

Threshold

Thermal Shutdown TSDHYST 50 °C

Hysteresis

SMBus and Digital I/O pins

Output High Voltage VOH VDD V 4 mA current drive

_3V-0.4

Output Low Voltage VOL 0.5 V 4 mA current sink

Note 3.4 TDIE refers to the internal die temperature and may not match TA due to self heating of
the device. The internal temperature sensor will return TDIE.

Note 3.5 Contact SMSC for Application Notes and guidelines when measuring GPU processor
diodes and CPU processor diodes.

Note 3.6 The ALERT, SYS_SHDN, SMDATA, and SMCLK pins will not glitch low upon power up
when pulled to VDD or another voltage.

3.3 SMBus Electrical Specifications

Table 3.3 SMBus Electrical Specifications

VDD_3V = 3V to 3.6V, VDD_5V = 4.6 to 5.5V, TA = 0°C to 85°C

Typical values are at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS

SMBus Interface

Input High Voltage VIH 2.0 V

Input Low Voltage VIL 0.8 V

Input High/Low Current IIH / IIL -1 1 uA

Input Capacitance CIN 5 pF

Output Low Sink Current 4 mA SMDATA = 0.5V

SMBus Timing

Clock Frequency fSMB 10 400 kHz

Spike Suppression tSP 50 ns

Revision 0.88 (11-20-09) 14 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 3.3 SMBus Electrical Specifications (continued)

VDD_3V = 3V to 3.6V, VDD_5V = 4.6 to 5.5V, TA = 0°C to 85°C

Typical values are at TA = 27°C unless otherwise noted.

CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS

Bus Free Time Start to tBUF 1.3 us

Stop

Setup Time: Start tSU:STA 0.6 us

Setup Time: Stop tSU:STP 0.6 us

Data Hold Time tHD:DAT 0.6 6 us

Data Setup Time tSU:DAT 0.6 72 us

Clock Low Period tLOW 1.3 us

Clock High Period tHIGH 0.6 us

Clock/Data Fall time tFALL 300 ns Min = 20+0.1CLOAD ns

Clock/Data Rise time tRISE 300 ns Min = 20+0.1CLOAD ns

Capacitive Load CLOAD 400 pF per bus line

SMSC EMC2112 15 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 4 System Management Bus Interface Protocol

4.1 System Management Bus Interface Protocol

The EMC2112 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported,
however the EMC2112 will not stretch the clock signal.

T LOW T HIGH T HD:STA T SU:STO

T FALL
SMCLK
T RISE

T SU:DAT T SU:STA
T HD:STA T HD:DAT

SMDATA
T BUF

P S S - Start Condition S P - Stop Condition P

Figure 4.1 SMBus Timing Diagram

4.1.1 SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state. When the EMC2112 detects an SMBus Start
bit, it will disable the BC-Link protocol circuitry and communicate using the SMBus Protocol

4.1.2 SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by a -bit RD / WR indicator. If
this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR
bit is a logic ‘1’, then the SMBus Host is reading data from the client device.

The slave address is determined at power up by the pin-state of the ADDR_SEL pin as shown in
Table 4.1.

Table 4.1 ADDR_SEL Pin Configuration

ADDR_SEL PIN STATE SMBUS SLAVE ADDRESS

‘0’ 0101_111xb

‘High Z’ 0111_101xb

‘1’ 0101_110xb

Revision 0.88 (11-20-09) 16 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

4.1.3 SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.

4.1.4 SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives (as well as the client address if it
matches and the ARA address if the ATF_INT# pin is asserted). This is done by the client device
pulling the SMBus Data line low after the 8th bit of each byte that is transmitted.

The Host will NACK (not acknowledge) the data received from the client by holding the SMBus data
line high after the 8th data bit has been sent.

4.1.5 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the EMC2112 detects an SMBus Stop
bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.

4.1.6 SMBus Time-out

The EMC2112 includes an SMBus time-out feature. Following a 30ms period of inactivity on the
SMBus, the device will time-out and reset the SMBus interface. The timeout can be disabled by setting
the DIS_TO bit in the Configuration 2 register.

4.1.7 SMBus and I2C Compliance

The major difference between SMBus and I2C devices is highlighted here. For complete compliance
information refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz.

2. The client protocol will reset if the clock is held for longer than 30ms.
3. The slave protocol will reset if both the clock and data lines are held high for longer than 150us.
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
5. The Block Read and Block Write protocols are only compliant with I2C data formatting. They do
not support SMBus formatting for Block Read and Block Write protocols.

4.2 SMBus Protocols

The EMC2112 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte and Write
Byte as valid protocols as shown below. It will respond to the Alert Response Address protocol but is
not in full compliance.

All of the below protocols use the convention in Table 4.2.

Table 4.2 Protocol Format

DATA SENT DATA SENT TO

TO DEVICE THE HOST

# of bits sent # of bits sent

SMSC EMC2112 17 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

4.2.1 Write Byte

The Write Byte is used to write one byte of data to the registers as shown below Table 4.3:

Table 4.3 Write Byte Protocol

SLAVE REGISTER REGISTER

START ADDRESS WR ACK ADDRESS ACK DATA ACK STOP

1 -> 0 0111_101 0 0 XXh 0 XXh 0 0 -> 1

4.2.2 Read Byte

The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.4.

Table 4.4 Read Byte Protocol

START SLAVE WR ACK Register ACK START Slave RD ACK Register NACK STOP
ADDRESS Address Address Data

1 -> 0 0111_101 0 0 XXh 0 0 -> 1 0111_101 1 0 XXh 1 0 -> 1

4.2.3 Send Byte

The Send Byte protocol is used to set the internal address register pointer to the correct address
location. No data is transferred during the Send Byte protocol as shown in Table 4.5.

Table 4.5 Send Byte Protocol

SLAVE REGISTER
START ADDRESS WR ACK ADDRESS ACK STOP

1 -> 0 0111_101 0 0 XXh 0 0 -> 1

4.2.4 Receive Byte

The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
of the same register as shown in Table 4.6.

Table 4.6 Receive Byte Protocol

SLAVE
START ADDRESS RD ACK REGISTER DATA NACK STOP

1 -> 0 0111_101 1 0 XXh 1 0 -> 1

Revision 0.88 (11-20-09) 18 SMSC EMC2112

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

4.2.5 Block Write Protocol

The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in
Table 4.7. It is an extension of the Write Byte Protocol.

Table 4.7 Block Write Protocol

SLAVE REGISTER REGISTER

START ADDRESS WR ACK ADDRESS ACK DATA ACK

1 ->0 0111_101 0 0 XXh 0 XXh 0

REGISTER REGISTER REGISTER

DATA ACK DATA ACK ... DATA ACK STOP

XXh 0 XXh 0 ... XXh 0 0 -> 1

4.2.6 Block Read Protocol

The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in
Table 4.8. It is an extension of the Read Byte Protocol.

Table 4.8 Block Read Protocol

START SLAVE WR ACK REGISTER ACK START SLAVE RD ACK REGISTER

ADDRESS ADDRESS ADDRESS DATA

1->0 0111_101 0 0 XXh 0 1 ->0 0111_101 1 0 XXh

ACK REGISTER ACK REGISTER ACK REGISTER ACK ... REGISTER NACK STOP
DATA DATA DATA DATA

0 XXh 0 XXh 0 XXh 0 ... XXh 1 0 -> 1

4.2.7 Alert Response Address

The ALERT output can be used as a processor interrupt or as an SMBus Alert when configured to
operate as an interrupt.

When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA)
to the general address of 0001_100xb. All devices with active interrupts will respond with their client
address as shown in Table 4.9.

Table 4.9 Alert Response Address Protocol

ALERT
RESPONSE DEVICE
START ADDRESS RD ACK ADDRESS NACK STOP

0 -> 1 0001_100 1 0 0111_1010b 1 1 -> 0

The EMC2112 will respond to the ARA in the following way if the ALERT pin is asserted.
1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due to a bus contention event).
2. Set the MASK bit to clear the ALERT pin.

SMSC EMC2112 19 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 5 General Description

The EMC2112 monitors up to three (3) external temperature channels. Each of the external
temperature channels can employ both Beta Compensation (an implementation of the BJT or transistor
model for thermal diodes) and Resistance Error Correction for use with thermal diodes while the third
channel is hardwired to measure a discrete diode connected NPN or PNP transistor. The temperature
data is available over a standard 2-wire serial interface using SMBus read commands. The
temperature monitoring is described in more detail in Section 5.11, "Temperature Monitoring".

The EMC2112 includes a closed-loop RPM-based Fan Control Algorithm for each fan driver. The host
writes the desired fan speed into a register of the EMC2112 via the SMBus and the integrated fan
controller will maintain the fan at the desired speed using fan speed feedback from the TACH output
from a 3-wire fan. The fan control algorithm controls an integrated 5V, 600mA, linear fan driver.

The EMC2112 provides the system with a hardware based critical/thermal shutdown function. This
critical/thermal shutdown function integrates critical signals from both the CPU and power supply and
the analog circuitry to monitor a specific temperature channel based on the system configuration. The
critical/thermal shutdown temperature threshold is configured on the PCB through a simple discrete
resistor. The Critical/Thermal Shutdown function is described in more detail in Section 5.9,
"Critical/Thermal Shutdown".

An example of a typical system configuration for the EMC2112 is provided in Figure 5.1.

3.3V 3.3V 5V

VDD_3V VDD_5V(2)
SMCLK
KBC RESET
SMDATA
FAN(2)
ALERT
3.3V 3.3V

ADDR_SEL

CPU EMC2112 tachometer

TACH
Thermal DP1
3.3V
diode
DN1

DP2 / DN3 SYS_SHDN 3.3V

Optional Anti-
parallel Diode DN2 / DP3 SHDN_SEL

VREF

TRIP_SET CLK_IN

GND 32.768kHz clock

Figure 5.1 EMC2112 System Diagram

Revision 0.88 (11-20-09) 20 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

5.1 Fan Control Modes of Operation

The EMC2112 has two modes of operation for the fan driver. Each mode of operation uses the Ramp
Rate control and Spin Up Routine.
1. Direct Setting Mode - in this mode of operation, the user directly controls the fan drive setting.
Updating the Fan Driver Setting Register (see Section 6.17) will instantly update the fan drive.
Ramp Rate control is optional and enabled via the EN_RRC bits.

„ Whenever the Direct Setting Mode is enabled, the current drive will be changed to what was
last written into the Fan Driver Setting Register.
2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a target
tachometer count and the drive setting is automatically updated to achieve this target speed. The
algorithm uses the Spin Up Routine and has user definable ramp rate controls.

Table 5.1 Fan Controls Active for Operating Mode

DIRECT SETTING MODE FSC MODE

Fan Driver Setting (read / write) Fan Driver Setting (read only)

EDGES[1:0] EDGES[1:0]
(Fan Configuration)

- RANGE[1:0]
(Fan Configuration)

UPDATE[2:0] UPDATE[2:0]
(Fan Configuration) (Fan Configuration)

LEVEL LEVEL
(Spin Up Configuration) (Spin Up Configuration)

SPINUP_TIME[1:0] SPINUP_TIME[1:0]
(Spin Up Configuration) (Spin Up Configuration)

Fan Max Step Fan Max Step

- Fan Minimum Drive

Valid TACH Count Valid TACH Count

- TACH Target (read / write)

TACH Reading TACH Reading

- DRIVE_FAIL_CNT[1:0] and Drive Band Fail Registers

5.2 RPM-Based Fan Speed Control Algorithm (FSC)

The EMC2112 includes a RPM-based Fan Speed Control Algorithm for the fan driver.

This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach
and maintain the system’s desired fan speed to an accuracy directly proportional to the accuracy of
the clock source.

The desired tachometer count is set by the user inputting the desired number of 32.768KHz cycles
that occur per fan revolution. This is done by setting the TACH Target Register. The user may change
the target count at any time. The user may also set the target count to FFh in order to disable the fan
driver for lower current operation.

SMSC EMC2112 21 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

For example, if a desired RPM rate for a 2-pole fan is 3000 RPMs, then the user would input the
hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number
of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution
when it is spinning at 3000RPMs.

The EMC2112’s RPM-based Fan Speed Control Algorithm has programmable configuration settings
for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects
and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT pin. The
EMC2112 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The
fan controller will function either with an externally supplied 32.768KHz clock source or with it’s own
internal 32kHz oscillator depending on the required accuracy.

5.2.1 Programming the RPM-Based Fan Speed Control Algorithm

The RPM-based Fan Speed Control Algorithm is disabled upon device power up. The following
registers control the algorithm. The EMC2112 fan control registers are pre-loaded with defaults that
will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed.
The other fan control registers can be used to fine-tune the algorithm behavior based on application
requirements.

Note that steps 1 - 6 are optional and need only be performed if the default settings do not provide
the desired fan response.
1. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired.

2. Set the Fan Step Register to the desired step size.

3. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation.
4. Set the Update Time, and Edges options in the Fan Configuration Register.
5. Set the Valid TACH Count Register to the highest tach count that indicates the fan is spinning.
6. Set the TACH Target Register to the desired tachometer count.
7. Enable the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit.

5.3 Tachometer Measurement

The tachometer measurement circuitry is used in conjunction with the RPM-based Fan Speed Control
Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a
diagnostic for host based fan control.

This method monitors the TACH signal in real time. It constantly updates the tachometer measurement
by reporting the number of clocks between a user programmed number of edges on the TACH signal.

The tachometer measurement provides fast response times for the RPM-based Fan Speed Control
Algorithm and the data is presented as a count value that represents the fan RPM period. When this
method is used, all fan target values must be input as a count value for proper operation.

APPLICATION NOTE: The tachometer measurement method works independently of the drive settings. If the
device is put into Direct Setting and the fan drive is set at a level that is lower than the fan
can operate (including zero drive), then the tachometer measurement may signal a Stalled
Fan condition and assert an interrupt.

5.3.1 Stalled Fan

A Stalled fan is detected if the tach counter exceeds the user-programmable Valid TACH Count setting
then it will flag the fan as stalled and trigger an interrupt.

If the RPM-based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to
restart the fan until it detects a valid tachometer level or is disabled.

Revision 0.88 (11-20-09) 22 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally
depending on the mode of operation.
„ Whenever the Direct Setting Mode is enabled or whenever the Spin Up Routine is enabled, the
FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see
Section 6.21) to allow the fan an opportunity to reach a valid speed without generating unnecessary
interrupts.
„ In Direct Setting Mode with the tachometer measurement using the Tach Period Measurement
method, whenever the TACH Reading Register value exceeds the Valid TACH Count Register
setting, the FAN_STALL status bit will be set.
„ When using the RPM-based Fan Speed Control Algorithm, the stalled fan condition is checked
whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.

5.3.2 Aging Fan or Invalid Drive Detection

This is useful to detect aging fan conditions (where the fan’s natural maximum speed degrades over
time) or incorrect fan speed settings. The EMC2112 contains circuitry that detects that the programmed
fan speed can be reached by the fan. If the target fan speed cannot be reached within a user defined
band of tach counts at maximum drive then the DRIVE_FAIL status bits are set and the ALERT pin is
asserted.

5.3.3 Clock Source

The CLK pin can be configured as an input for the EMC2112 or as an output to drive additional devices
with the internally generated tachometer clock (see Section 6.9).

When the CLK pin is configured as an input to the EMC2112, then a 32.768kHz clock must be
provided. This clock is used to by the Tachometer measurement circuitry and will directly affect the
accuracy of this measurement.

When the CLK pin is configured as an output, then it will be driven at the same frequency as the
internal tachometer clock.

5.4 Spin Up Routine

The EMC2112 also contains programmable circuitry to control the spin up behavior of the fan driver
to ensure proper fan operation.

The Spin Up Routine is initiated in Direct Setting mode when the setting value changes from 00h to
anything else.

When the Fan Speed Control Algorithm is enabled, the Spin Up Routine is initiated under the following
conditions when the Tach Period Measurement method of tach measurement is used:
1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid
TACH Count (see Section 6.24).

2. The RPM-based Fan Speed Control Algorithm’s measured TACH Reading Register value is greater
than the Valid TACH Count setting.

When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of
the total user defined spin up time. For the remaining spin up time, the fan driver output is set a a user
defined level (30% through 65% drive).

After the Spin Up Routine has finished, the EMC2112 measures the TACH signal. If the measured
TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN
status bit is set and the Spin Up Routine will automatically attempt to restart the fan.

Figure 5.2 shows an example of the Spin Up Routine in response to a programmed fan speed change
based on the first condition above.

SMSC EMC2112 23 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

100%
(optional)

30% through 65%

Fan Step

New Target Count

Algorithm controlled drive

Prev Target
Count = FFh
¼ of Spin Up Time

Update Time
Spin Up Time
Target Count Check TACH Target Count
Changed Reached

Figure 5.2 Spin Up Routine

5.5 Ramp Rate Control

The Fan Driver can be configured with automatic ramp rate control. Ramp rate control is accomplished
by adjusting the drive output settings based on the Maximum Fan Step Register settings and the
Update Time settings.

If the RPM-based Fan Speed Control Algorithm is used, then this ramp rate control is automatically
used. The user programs a maximum step size for the fan drive setting and an update time. The
update time varies from 100ms to 1.6s while the fan drive maximum step can vary from 1 count to 31
counts.

When a new fan drive setting is entered, the delta from the next fan drive setting and the previous fan
drive setting is determined. If this delta is greater than the Max Step settings, then the fan drive setting
is incrementally adjusted every 100ms to 1.6s as determined by the Update Time until the target fan
drive setting is reached. See Figure 5.3.

Revision 0.88 (11-20-09) 24 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Next Desired
Setting

Max
Step

Max
Step
Previous
Setting

Update Update
Time Time
Setting Changed

Figure 5.3 Ramp Rate Control

5.5.1 Temperature Bypass of Ramp Rate Control

As an optional feature, the Ramp Rate Control functionality can be disabled if any of the measured
temperature channels exceed their respective high limits. In this mode, once the high limit has been
exceeded, the ramp rate controls are removed which allows the fan to move instantly to the
programmed drive setting (using the FSC or in manual mode).

5.6 Watchdog Timer

The EMC2112 contains an internal Watchdog Timer for the fan driver. The Watchdog timer monitors
the SMBus traffic for signs of activity and works in two different modes based upon device operation.
These modes are Power Up Operation and Continuous Operation as described below.

For either mode of operation, if four (4) seconds elapse without activity detected by the host, then the
watchdog will be triggered and the following will occur:
1. The WATCH status bit will be set which will cause the ALERT pin to be asserted.

2. The fan driver will be set to full scale drive. It will remain at full scale drive until it is disabled.

APPLICATION NOTE: When the Watchdog timer is activated the Fan Speed Control Algorithm is automatically
disabled. Disabling the Watchdog will not automatically set the fan drive nor re-activate the
Fan Speed Control Algorithm. This must be done manually.

SMSC EMC2112 25 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

5.6.1 Power Up Operation

The Watchdog Timer only starts immediately after power-up and once it has been triggered or
deactivated will not restart (however can be configured to operate in Continuous operation)

In the Power Up Operation, the Watchdog Timer is disabled by any of the following actions:
1. Writing the Fan Setting Register will disable the Watchdog Timer.

2. Enabling the RPM-based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the
Watchdog Timer. The fan driver will be set based on the RPM-based Fan Speed Control Algorithm.
3. Changing the Watchdog operating mode by setting the WD_EN bit.

Writing any other configuration registers will not disable the Watchdog Timer upon power up.

5.6.2 Continuous Operation

When configured to operate in Continuous Operation, the Watchdog timer will start immediately. It can
be disabled by any access (read or write) to the SMBus register set. Upon completion of SMBus
activity, the Watchdog timer is reset and restarted.

5.7 High Side Fan Driver

The EMC2112’s integrates a 5V, 600mA, linear high side fan driver to directly drive a 5V fan. By fully
integrating the linear fan driver, the typical requirement for the discrete pass device and other external
linearization circuitry is completely eliminated.

5.7.1 Overcurrent Limit

The High Side Fan Driver contains circuitry to allow for significant over current levels to accommodate
transient conditions on the FAN pins. The over current limit is dependent upon the output voltage with
the limit dropping as the voltage nears 0V.

If the fan driver current detects a short-circuit condition for longer than 2 seconds, then the I_SHORT
status bit is set and an interrupt generated. Additionally, the High Side Fan Driver will be disabled for
8 seconds. After this 8 second time has elapsed, it will be allowed to restart invoking the Spin Up
Routine before returning to its previous drive setting.

APPLICATION NOTE: If the FSC Algorithm is active, then it will generate errant SPIN_FAIL interrupts during the 8
second time that the fan driver is held off.

5.8 Internal Thermal Shutdown (TSD)

The EMC2112 contains an internal thermal shutdown circuit that monitors the internal die temperature.
If the die temperature exceeds the Thermal Shutdown Threshold (see Table 3.2), then the following
will occur:
1. The High Side Fan Driver is disabled. It will remain disabled until the internal temperature drops
below the threshold temperature minus 50°C.

2. The TSD Status bit is set.

3. The SYS_SHDN pin is asserted.

5.9 Critical/Thermal Shutdown

The EMC2112 provides a hardware Critical/Thermal Shutdown function for systems. Figure 5.4 is a
block diagram of this Critical/Thermal Shutdown function. The Critical/Thermal Shutdown function in

Revision 0.88 (11-20-09) 26 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

the EMC2112 consists of both analog and digital functions. It accepts configuration information from
the fixed states of the SHDN_SEL pin as described in Section 5.9.2.

Each of the temperature limits can be configured to act as inputs to the Critical / Thermal Shutdown
independent of the hardware shutdown operation.

The analog portion of the Critical/Thermal Shutdown function monitors a specific remote temperature
channel (configured with the SHDN_SEL pin). This measured temperature is then compared with the
TRIP_SET point. This TRIP_SET point is created by the system designer with a simple resistor and
is discussed in detail in Section 5.9.1.

Critical Shutdown Logic

Register Enabled
Sensor
Temperature Configuration
SMBus Traffic
Register Enabled Conversion Register
Sensor and Limit
Registers
SW_SHDN
Register Enabled
Sensor

External
PIN
Diode 1 / 2 SHDN_SEL
Decode
Switch
External Diode 1
or External Diode 2 Temperature SYS_SHDN
Conversion
VREF

Voltage
Conversion
TRIP_SET

Figure 5.4 EMC2112 Critical/Thermal Shutdown Block Diagram

5.9.1 TRIP_SET Pin

The EMC2112’s TRIP_SET pin is an analog input to the Critical/Thermal Shutdown block which sets
the Thermal Shutdown temperature. The system designer creates a voltage level at the input through
a simple resistor connected to GND as shown in Figure 5.1. The value of this resistor is used to create
an input voltage on the TRIP_SET pin which is translated into a temperature ranging from 60°C to
122°C enumerated in Table 5.2.

VTRIP is the TRIP_SET

voltage
T TRIP – T MIN
V TRIP = ---------------------------------- TMIN is the minimum [1]
80
temperature based on the
range

SMSC EMC2112 27 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 5.2 TRIP_SET Resistor Setting

TTRIP (°C RSET (1%) TTRIP (°C) RSET (1%)

60 0.0 92 1240

61 28.7 93 1330

62 48.7 94 1400

63 69.8 95 1500

64 90.9 96 1580

65 113 97 1690

66 137 98 1820

67 158 99 1960

68 182 100 2050

69 210 101 2210

70 237 102 2370

71 261 103 2550

72 294 104 2740

73 324 105 2940

74 348 106 3160

75 383 107 3480

76 412 108 3740

77 453 109 4120

78 487 110 4530

79 523 111 4990

80 562 112 5490

81 604 113 6040

82 649 114 6810

83 698 115 7870

84 750 116 9090

85 787 117 10700

86 845 118 12700

87 909 119 15800

88 953 120 20500

Revision 0.88 (11-20-09) 28 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 5.2 TRIP_SET Resistor Setting (continued)

TTRIP (°C RSET (1%) TTRIP (°C) RSET (1%)

89 1020 121 29400

90 1100 122 49900

91 1150 60 Open

5.9.2 SHDN_SEL Pin

The EMC2112 has one ‘strappable’ input (SHDN_SEL) allowing for configuration of the hardware
Critical/Thermal Shutdown. This pin has 3 possible states and is monitored and decoded by the
EMC2112 at power-up. The three possible states are 0 (tied to GND), 1 (tied to 3.3V) or High-Z (open).
The states of this pin determine which remote temperature channel and configuration is used by the
Critical/Thermal Shutdown function. The different configurations of SHDN_SEL pin are described in
Table 5.3

A channel that is configured via the SHDN_SEL pin for the Critical/Thermal Shutdown is locked and
none of the configuration registers associated with it can be updated via the SMBus. The other two
temperature channels, however, are still configurable via the SMBus.

Table 5.3 SHDN_SEL Pin Configuration

SHDN_SEL FUNCTION NAME CRITICAL/THERMAL SHUTDOWN DETAILS

‘0’ Intel Transistor Mode The external diode 1 channel is configured with Beta
(substrate PNP) Compensation enabled and Resistance Error Correction
enabled (with automatic detection). This mode is ideal for
monitoring a substrate transistor such as an Intel CPU
thermal diode.

High-Z (open) AMD CPU / Diode The external diode 1 channel is configured with Beta
Mode Compensation disabled and Resistance Error Correction
disabled. This mode is ideal for monitoring an AMD
processor diode or a 2N3904 diode.

‘1’ External Diode 2 The External Diode 2 channel is linked to the Hardware set
Diode Mode Thermal / Critical shutdown circuitry and configured with Beta
Compensation enabled (with automatic detection) and REC
enabled.

5.9.3 Internal HW_SHDN Signal

The HW_SHDN output from the Critical/Thermal Shutdown Monitor is a logical indicator of the
temperature state of the chosen external diode channel. HW_SHDN is an internal signal routed as an
input to the Thermal / Critical Shutdown logic.

The HW_SHDN output is set to logic ‘1’ when the indicated temperature exceeds the temperature
threshold (TP) established by the TRIP_SET input pin (as shown in Figure 5.5) for a number of
consecutive measurements defined by the fault queue. If the HW_SHDN output is asserted and the
temperature drops below TP, then it will be set to a logic ‘0’ state.

SMSC EMC2112 29 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Temperature
Temperature drops to TP or
Measurements End
Exceeds TP below
TP

Temperature
not
defined
HW_SHDN

After 4th measurement,

HW_SHDN set

Figure 5.5 HW_SHDN Operation

5.10 5V Reset Controller

The EMC2112 also provides a ‘power-good’ reset controller for the system’s 5V supply rail. The reset
controller will set the RESET pin to a logic ‘0’ after power-up and set the RESET pin to a logic ‘1’
220ms after the VDD_5V supply rises above its threshold voltage (see Table 3.2).

If the VDD_5V supply drops below the reset threshold, the RESET pin will be set to ‘0’ immediately.

VDD_5V
Reset Threshold (4.4V)

Reset Threshold -
hysteresis (4.3V)

220ms

RESET#

Figure 5.6 5V Reset Controller Timing

5.11 Temperature Monitoring

The EMC2112 can monitor the temperature of up to three (3) externally connected diodes as well as
the internal or ambient temperature. Each channel is configured with the following features enabled or
disabled based on user settings and system requirements.

Revision 0.88 (11-20-09) 30 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

5.11.1 Dynamic Averaging

The EMC2112 supports dynamic averaging. When enabled, this feature changes the conversion time
for all external diode channels based on the selected conversion rate. This essentially increases the
averaging factor as shown in Table 5.4. The benefits of Dynamic Averaging are improved noise
rejection due to the longer integration time as well as less random variation on the temperature
measurement.

Table 5.4 Dynamic Averaging Behavior

AVERAGING FACTOR (RELATIVE TO 11-BIT CONVERSION)

FOR EXTERNAL DIODE CHANNELS

DYNAMIC AVERAGING DYNAMIC AVERAGING

CONVERSION RATE ENABLED DISABLED

1 / sec 8x 1x

2 / sec 4x 1x

4 / sec 2x 1x

8 / sec 1x 1x

5.11.2 Resistance Error Correction

The EMC2112 includes active Resistance Error Correction to remove the effect of up to 100 ohms of
series resistance. Without this automatic feature, voltage developed across the parasitic resistance in
the remote diode path causes the temperature to read higher than the true temperature is. The error
induced by parasitic resistance is approximately +0.7°C per ohm. Sources of parasitic resistance
include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU,
and resistance in the printed circuit board traces and package leads. Resistance error correction in the
EMC2112 eliminates the need to characterize and compensate for parasitic resistance in the remote
diode path.

5.11.3 Beta Compensation

The forward current gain, or beta, of a transistor is not constant as emitter currents change. This beta
variation causes the measured VBE (which is related to the collector current which, in turn, is related
to beta) to shift in a way that is not predicted by the ratio of emitter currents being forced into the
device. This shift cause an error in the temperature measurement. Compensating for this error is also
known as implementing the BJT or transistor model for temperature measurement.

For discrete transistors configured with the collector and base shorted together, the beta is generally
sufficiently high such that the percent change in beta variation is very small. For example, a 10%
variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute
approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction
is used for temperature measurement and the collector is tied to the substrate, the proportional beta
variation will cause large error. For example, a 10% variation in beta for two forced emitter currents
with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C.

The Beta Compensation circuitry in the EMC2112 corrects for this beta variation to eliminate any error
which would normally be induced. This Beta Compensation circuitry automatically detects the type of
diode connected and adjusts the beta settings accordingly.

SMSC EMC2112 31 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

5.11.4 Digital Averaging

The External Diode 1 channel support a 4x digital averaging filter. Every cycle, this filter updates the
temperature data based an a running average of the last 4 measured temperature values. The digital
averaging reduces temperature flickering and increases temperature measurement stability.

The digital averaging can be disabled by setting the DIS_AVG bit in the Configuration 2 Register (see
Section 6.10).

5.12 Diode Connections

The diode connection for the External Diode 1 and External Diode 2 channels are determined at
power-up based on the SHDN_SEL pin (see Section 5.9.2). This channel can support a diode-
connected transistor (such as a 2N3904) or a substrate transistor (such as those found in an CPU or
GPU) as shown in Figure 5.7.

The External Diode 3 channel is available when the External Diode 2 channel is configured to operate
is an anti-parallel diode pair. In this mode, both the External Diode 2 and External Diode 3 diodes must
be connected in the anti-parallel configuration as shown in Figure 5.7

Diode 3 Diode 2

to
to DP to DP to DP DP /
DN

to DN

to
to DN to DN DN /
Local DP
Ground

Typical remote Typical remote Typical remote

Anti-parallel diodes using
substrate transistor discrete PNP transistor discrete NPN transistor
discrete NPN transistors
i.e. CPU substrate PNP i.e. 2N3906 i.e. 2N3904

Figure 5.7 Diode Connections

5.12.1 Diode Faults

The EMC2112 actively detects an open and short condition on each measurement channel. When a
diode fault is detected, the temperature data most significant byte is forced to a value of 80h and the
FAULT bit is set in the Status Register.

Revision 0.88 (11-20-09) 32 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 6 Register Set

6.1 Register Map

The following registers are accessible through the SMBus Interface. All register bits marked as ‘-’ will
always read ‘0’. A write to these bits will have no effect.

Table 6.1 EMC2112 Register Set

REGISTER DEFAULT
ADDR R/W NAME FUNCTION VALUE LOCK PAGE

Temperature Registers

Internal Temp
Stores the integer data of the Internal
00h R Reading High 00h No Page 36
Diode
Byte

Internal Temp Stores the fractional data of the Internal

01h R 00h No Page 36
Reading Low Byte Diode

External Diode 1
Stores the integer data of External
02h R Temp Reading 00h No Page 36
Diode 1 channel
High Byte

External Diode 1
Stores the fractional data of External
03h R Temp Reading 00h No Page 36
Diode 1
Low Byte

External Diode 2
Stores the integer data of External
04h R Temp Reading 00h No Page 36
Diode 2 channel
High Byte

External Diode 2
Stores the fractional data of External
05h R Temp Reading 00h No Page 36
Diode 2
Low Byte

External Diode 3
Stores the integer data of External
06h R Temp Reading 00h No Page 36
Diode 3 channel
High Byte

External Diode 3
Stores the fractional data of External
07h R Temp Reading 00h No Page 36
Diode 3
Low Byte

Critical/Thermal Stores the calculated Critical/Thermal

7Fh
0Ah R Shutdown Shutdown temperature high limit No Page 37
(+127°C)
Temperature derived from the voltage on TRIP_SET

Stores the raw measured TRIP_SET

10h R Trip Set Voltage FFh No Page 38
voltage input

Diode Configuration

External Diode 1 Configures Ideality Factor settings for

11h R/W 12h SWL Page 38
Ideality External Diode 1

External Diode 2 Configures Ideality Factor settings for

12h R/W 12h SWL Page 38
Ideality External Diode 2

External Diode 3 Configures Ideality Factor settings for

13h R/W 12h SWL Page 38
Ideality External Diode 3

SMSC EMC2112 33 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.1 EMC2112 Register Set (continued)

REGISTER DEFAULT
ADDR R/W NAME FUNCTION VALUE LOCK PAGE

External Diode 1
Configures the beta compensation
14h R/W Beta 10h SWL Page 39
settings for External Diode 1
Configuration

External Diode 2
Configures the beta compensation
15h R/W Beta 10h SWL Page 39
settings for External Diode 2
Configuration

External Diode Configures the Resistance Error

17h R/W REC Correction functionality for all external 07h SWL Page 41
Configuration diodes

External Diode 1 Stores the Critical temperature limit for 64h Write
19h R/W Page 41
Tcrit Limit the External Diode 1 (100°C) Lock

External Diode 2 Stores the Critical temperature limit for 64h Write
1Ah R/W Page 41
Tcrit Limit the External Diode 2 (100°C) Lock

External Diode 3 Stores the Critical temperature limit for 64h Write
1Bh R/W Page 41
Tcrit Limit the External Diode 3 (100°C) Lock

Internal Diode Stores the Critical temperature limit for 64h Write
1Dh R/W Page 41
Tcrit Limit the Internal Diode (100°C) Lock

Configuration and Control

Stores the status bits for all temperature

1Fh R-C Tcrit Limit Status 00h No Page 45
channel Tcrit limits

Configures the Thermal / Critical

20h R/W Configuration Shutdown masking options and 00h SWL Page 42
software lock

Controls the conversion rate for

21h R/W Configuration 2 0Eh SWL Page 43
monitoring of all channels

Stores the status bits for temperature

23h R-C Interrupt Status 00h No Page 44
channels

Stores the status bits for all temperature

24h R-C High Limit Status 00h No Page 45
channel high limits

Stores the status bits for all temperature

26h R-C Diode Fault 00h No Page 45
channel diode faults

Stores the status bits for the RPM-

27h R-C Fan Status 00h No Page 46
based Fan Speed Control Algorithm

Interrupt Enable Controls the masking of interrupts on all

28h R/W 00h No Page 46
Register temperature channels

Fan Interrupt Controls the masking of interrupts on all

29h R/W 00h No Page 47
Enable Register fan related channels

Temperature Limit Registers

External Diode 1 55h

30h R/W High limit for External Diode 1 SWL Page 47
Temp High Limit (+85°C)

External Diode 2 55h

31h R/W High limit for External Diode 2 SWL Page 47
Temp High Limit (+85°C)

Revision 0.88 (11-20-09) 34 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.1 EMC2112 Register Set (continued)

REGISTER DEFAULT
ADDR R/W NAME FUNCTION VALUE LOCK PAGE

External Diode 3 55h

32h R/W High limit for External Diode 3 SWL Page 47
Temp High Limit (+85°C)

Internal Diode 55h

34h R/W High Limit for Internal Diode SWL Page 47
High Limit (85°C)

Fan Control Registers

Always displays the most recent fan

driver input setting for the Fan. If the
40h R/W Fan Setting RPM-based Fan Speed Control 00h No Page 48
Algorithm is disabled, allows direct user
control of the fan driver.

Sets configuration values for the RPM-

Fan Configuration
42h R/W based Fan Speed Control Algorithm for 2Bh No Page 48
1
the Fan driver

Fan Configuration Sets additional configuration values for

43h R/W 28h SWL Page 50
2 the Fan driver

Holds the gain terms used by the RPM-

45h R/W Gain based Fan Speed Control Algorithm for 2Ah SWL Page 51
the Fan driver

Fan Spin Up Sets the configuration values for Spin

46h R/W 19h SWL Page 52
Configuration Up Routine of the Fan driver

Sets the maximum change per update

47h R/W Fan Step 10h SWL Page 53
for the Fan driver

Fan Minimum Sets the minimum drive value for the 66h
48h R/W SWL Page 54
Drive Fan driver (40%)

Holds the minimum tachometer reading

Fan Valid TACH
49h R/W that indicates the fan is spinning F5h SWL Page 54
Count
properly

Fan Drive Fail

4Ah R/W Stores the number of Tach counts used 00h SWL
Band Low Byte to determine how the actual fan speed
Page 55
Fan Drive Fail must match the target fan speed at full
4Bh R/W scale drive 00h SWL
Band High Byte

TACH Target Low Holds the target tachometer reading low

4Ch R/W F8h No Page 55
Byte byte the Fan

TACH Target High Holds the target tachometer reading

4Dh R/W FFh No Page 55
Byte high byte for the Fan

TACH Reading Holds the tachometer reading high byte

4Eh R FFh No Page 55
High Byte for the Fan

TACH Reading Holds the tachometer reading low byte

4Fh R F8h No Page 55
Low Byte for the Fan

Lock Register

EF R/W Software Lock Locks all SWL registers 00h SWL Page 56

SMSC EMC2112 35 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.1 EMC2112 Register Set (continued)

REGISTER DEFAULT
ADDR R/W NAME FUNCTION VALUE LOCK PAGE

Revision Registers

Stores information about which pin

FCh R Product Features 00h No Page 57
controlled product features are set

FDh R Product ID Stores the unique Product ID 15h No Page 57

FEh R Manufacturer ID Stores the Manufacturer ID 5Dh No Page 58

FFh R Revision Revision 01h No Page 58

During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when
power is first applied to the part and the voltage on the VDD_3V supply surpasses the POR level as
specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to
undefined registers will not have an effect.

6.1.1 Lock Entries

The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL
registers are Software Locked and therefore made read-only when the LOCK bit is set.

6.2 Temperature Data Registers

Table 6.2 Temperature Data Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Internal Diode
00h R Sign 64 32 16 8 4 2 1 00h
High Byte

Internal Diode
01h R 0.5 0.25 0.125 - - - - - 00h
Low Byte

External
02h R Diode 1 High Sign 64 32 16 8 4 2 1 00h
Byte

External
03h R Diode 1 Low 0.5 0.25 0.125 - - - - - 00h
Byte

External
04h R Diode 2 High Sign 64 32 16 8 4 2 1 00h
Byte

External
05h R Diode 2 Low 0.5 0.25 0.125 - - - - - 00h
Byte

External
06h R Diode 3 High Sign 64 32 16 8 4 2 1 00h
Byte

External
07h R Diode 3 Low 0.5 0.25 0.125 - - - - - 00h
Byte

Revision 0.88 (11-20-09) 36 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

The temperature measurement range is from -64°C to +128°C. The data format is a signed two’s
complement number as shown in Table 6.3.

APPLICATION NOTE: When the External Diode 3 channel is not enabled, the data bytes will read 00h.

Table 6.3 Temperature Data Format

HEX (AS READ BY

TEMPERATURE (°C) BINARY REGISTERS)

Diode Fault 1000_0000_000b 80_00h

-63.875 1100_0000_001b C0_20h

-63 1100_0001_000b C1_00h

-1 1111_1111_000b FF_00h

-0.125 1111_1111_111b FF_E0h

0 0000_0000_000b 00_00h

0.125 0000_0000_001b 00_20h

1 0000_0001_000b 01_00h

63 0011_1111_000b 3F_00h

64 0100_0000_000b 40_00h

65 0100_0001_000b 41_00h

127 0111_1111_000b 7F_00h

127.875 0111_1111_111b 7F_E0h

6.3 Critical/Thermal Shutdown Temperature Registers

Table 6.4 Critical/Thermal Shutdown Temperature Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Critical/Thermal
7Fh
0Ah R Shutdown - 64 32 16 8 4 2 1
(+127°C)
Temperature

The Critical/Thermal Shutdown Temperature Register is a read-only register that stores the Voltage
Programmable Threshold temperature used in the Thermal / Critical Shutdown circuitry. The contents
of the register reflect the calculated temperature based on the TRIP_SET voltage. This register is
updated at the end of every monitoring cycle based on the current value of the TRIP_SET voltage.

The data format is shown in Table 6.5.

Table 6.5 Critical / Thermal Shutdown Data Format

TEMPERATURE (°C) BINARY HEX

0 0000_0000b 00h

1 0000_0001b 01h

SMSC EMC2112 37 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.5 Critical / Thermal Shutdown Data Format (continued)

TEMPERATURE (°C) BINARY HEX

63 0011_1111b 3Fh

64 0100_0000b 40h

65 0100_0001b 41h

127 0111_1111b 7Fh

6.4 TripSet Voltage Register

Table 6.6 TripSet Voltage Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

10h R TripSet 400 200 100 50 25 12.5 6.25 3.125 FFh

Voltage

The TripSet Voltage Register stores the measured voltage on the TRIP_SET pin that is used to
calculate the Critical / Thermal Shutdown temperature. Each bit weight represents mV of resolution so
that the final voltage can be determined by adding the appropriately set bits together.

6.5 Ideality Factor Registers

Table 6.7 Ideality Factor Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

External
11h R/W Diode 1 0 0 0 1 0 B2 B1 B0 12h
Ideality

External
12h R/W Diode 2 0 0 0 1 0 B2 B1 B0 12h
Ideality

External
13h R/W Diode 3 0 0 0 1 0 B2 B1 B0 12h
Ideality

These registers store the ideality factors that are applied to the external diodes.
Beta Compensation and Resistance Error Correction automatically correct for most diode ideality
errors, therefore it is not recommended that these settings be updated without consulting SMSC.
For CPU substrate transistors that require the BJT transistor model, the ideality factor behaves slightly
differently than for discrete diode-connected transistors. Refer to Table 6.9 when using a CPU
substrate transistor.
Only the lower three bits can be written. Writing to any other bit will be ignored.
The Ideality Factor Registers are software locked.

Revision 0.88 (11-20-09) 38 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.8 Ideality Factor Look-Up Table

SETTING FACTOR

10h 1.0053

11h 1.0066

12h 1.0080

13h 1.0093

14h 1.0106

15h 1.0119

16h 1.0133

17h 1.0146

Table 6.9 Substrate Diode Ideality Factor Look-Up Table (BJT Model)

SETTING FACTOR

10h 0.9973

11h 0.9986

12h 1.0000

13h 1.0013

14h 1.0026

15h 1.0039

16h 1.0053

17h 1.0066

APPLICATION NOTE: When measuring a 65nm Intel CPUs, the Ideality Setting should be the default 12h. When
measuring 45nm Intel CPUs, the Ideality Setting should be 15h.

6.6 Beta Configuration Registers

Table 6.10 Beta Configuration Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

External Diode 1
AUTO
14h R/W Beta - - - BETA1[3:0] 10h
1
Configuration

External Diode 2
AUTO
15h R/W Beta - - - BETA2[3:0] 10h
2
Configuration

SMSC EMC2112 39 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

The Beta Configuration Registers control advanced temperature measurement features for each
External Diode channel. The Beta Configuration Registers are software locked. The External Diode 1
Beta Configuration register Is hardware locked if the External Diode 1 channel is linked to the hardware
Critical / Thermal shutdown circuitry. Likewise, the External Diode 2 Beta Configuration register is
hardware locked if the External Diode 2 is linked to the Critical / Thermal shutdown circuitry - see
Section 5.9.2.

Bit 4 - AUTO - Enables the Automatic Beta detection algorithm.

„ ‘0’ - The Automatic Beta detection algorithm is disabled. The BETAx[3:0] bit settings will be used
to control the beta compensation circuitry.
„ ‘1’ (default) - The Automatic Beta detection algorithm is enabled. The circuitry will automatically
detect the transistor type and beta values and configure the BETAx[3:0] bits for optimal
performance.

Bits 3 - 0 - BETAx[3:0] - hold a value that corresponds to a range of betas that the Beta Compensation
circuitry can compensate for. These four bits will always show the current beta setting used by the
circuitry. If the AUTO bit is set (default), then these bits may updated by the device with every
temperature conversion. If the AUTO bit is not set, then the value of these bits is used to drive the
beta compensation circuitry. In this case, these bits should be set with a value corresponding to the
lowest expected value of beta for the PNP transistor being used as a temperature sensing device.

See Table 6.11 for supported beta ranges. A value of 1111b indicates that the beta compensation
circuitry is disabled. In this condition, the diode channels will function with default current levels and
will not automatically adjust for beta variation. This mode is used when measuring a discrete 2N3904
transistor or AMD thermal diode.

All of the Beta Configuration Registers are Software Locked.

Table 6.11 Beta Compensation

BETAX[3:0]
AUTO MINIMUM BETA
3 2 1 0

0 0 0 0 0 0.050

0 0 0 0 1 0.066

0 0 0 1 0 0.087

0 0 0 1 1 0.114

0 0 1 0 0 0.150

0 0 1 0 1 0.197

0 0 1 1 0 0.260

0 0 1 1 1 0.342

0 1 0 0 0 0.449

0 1 0 0 1 0.591

0 1 0 1 0 0.778

0 1 0 1 1 1.024

0 1 1 0 0 1.348

0 1 1 0 1 1.773

Revision 0.88 (11-20-09) 40 SMSC EMC2112

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.11 Beta Compensation (continued)

BETAX[3:0]
AUTO MINIMUM BETA
3 2 1 0

0 1 1 1 0 2.333

0 1 1 1 1 Disabled

1 X X X X Automatically detected

6.7 REC Configuration Register

Table 6.12 REC Configuration Register

ADDRESS R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

17h R/W REC - - - - - REC3 REC2 REC1 07h

Configuration

The REC Configuration Register determines whether Resistance Error Correction is used for each
external diode channel. The REC Configuration Register is software locked.

If either the External Diode 1 channel or External Diode 2 channel is selected by the SHDN_SEL pin
to be the hardware shutdown input channel (see Table 5.3), then the corresponding RECx bit will be
locked. Writing to the bit will have no affect and reading from it will always report the current setting.

Bit 2 - REC3 - Controls the Resistive Error Correction functionality of External Diode 3
„ ‘0’ - the REC functionality for External Diode 3 is disabled
„ ‘1’ (default) - the REC functionality for External Diode 3 is enabled.

Bit 1 - REC2 - Controls the Resistive Error Correction functionality of External Diode 2
„ ‘0’ - the REC functionality for External Diode 2 is disabled
„ ‘1’ (default) - the REC functionality for External Diode 2 is enabled.

Bit 0 - REC1 - Controls the Resistive Error Correction functionality of External Diode 1
„ ‘0’ - the REC functionality for External Diode 1 is disabled
„ ‘1’ (default) - the REC functionality for External Diode 1 is enabled.

6.8 Critical Temperature Limit Registers

Table 6.13 Tcrit Limit Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

R/W External Diode 64h

19h Sign 64 32 16 8 4 2 1
once 1 Tcrit Limit (+100°C)

R/W External Diode 64h

1Ah Sign 64 32 16 8 4 2 1
once 2 Tcrit Limit (+100°C)

SMSC EMC2112 41 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.13 Tcrit Limit Registers (continued)

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

R/W External Diode 64h

1Bh Sign 64 32 16 8 4 2 1
once 2 Tcrit Limit (+100°C)

R/W Internal Diode 64h

1Dh Sign 64 32 16 8 4 2 1
once Tcrit Limit (+100°C)

The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the
respective channels are linked to Hardware set Thermal/Critical Shutdown circuitry.

Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot
be updated again without a power on reset. Second, the respective temperature channel is linked to
the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the
measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the
appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will
be set.

6.9 Configuration Register

Table 6.14 Configuration Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

WD_ DR_ USE_ APD

20h R/W Configuration MASK - - - EXT_ EXT_ 00h
EN CLK CLK

The Configuration Register controls the basic functionality of the EMC2112. The bits are described
below. The Configuration Register is software locked.

Bit 7 - MASK - Blocks the ALERT pin from being asserted.

„ ‘0’ (default) - The ALERT pin is unmasked. If any bit in either status register is set, the ALERT pins
will be asserted (unless individually masked via the Mask Register)
„ ‘1’ - The ALERT pin is masked and will not be asserted.

Bit 6 - WD_EN - Enables the Watchdog timer to operate in Continuous Mode (see Section 5.6.2).
„ ‘0’ (default) - The Watchdog timer does not operate continuously. It will function upon power up and
at no other time.
„ ‘1’ - The Watchdog timer operates continuously as described in Section 5.6.

Bit 2 - DR_EXT_CLK - Enables the internal tachometer clock to be driven out on the CLK pin so that
multiple devices can be synced to the same source.
„ ‘0’ (default) - The CLK pin acts as a clock input.
„ ‘1’ - The CLK pin acts as a clock output and is a push-pull driver.

Bit 1 - USE_EXT_CLK - Enables the EMC2112 to use a clock present on the CLK pin as the
tachometer clock. If the DR_EXT_CLK bit is set, then this bit is ignored and the device will use the
internal oscillator.
„ ‘0’ (default) - The EMC2112 will use its internal oscillator for all Tachometer measurements.
„ ‘1’ - The EMC2112 will use the oscillator presented on the CLK pin for all Tachometer
measurements.

Revision 0.88 (11-20-09) 42 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Bit 0 - APD - Enables the External Diode 3 channel.

„ ‘0’ (default) - The External Diode 3 channel is not enabled.
„ ‘1’ - The External Diode 3 channel is enabled as an anti-parallel diode connected to DP2 / DN2
pins.

6.10 Configuration 2 Register

Table 6.15 Configuration 2 Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

DIS_ DIS_ DIS_

21h R/W Config 2 - QUEUE[1:0] CONV[1:0] 0Eh
DYN TO AVG

The Configuration 2 Register controls conversion rate of the temperature monitoring as well as the
fault queue. This register is software locked.

Bit 6 - DIS_DYN - Disables the Dynamic Averaging Feature.

„ ‘0’ (default) - The Dynamic Averaging function is enabled. The conversion time for all external diode
temperature channels is scaled based on the chosen conversion rate to maximize accuracy and
immunity to random temperature measurement variation.
„ ‘1’ - The Dynamic Averaging function is disabled. The conversion time for all temperature channels
is fixed regardless of the chosen conversion rate.

Bit 5 - DIS_TO - Disables the SMBus time out function for the SMBus client (if enabled).
„ ‘0’ (default) - The SMBus timeout and idle functionality are enabled. The SMBus interface will time
out if the clock line is held low for longer than 30ms. Likewise, it will reset if both the data and clock
lines are held high for longer than 150us.
„ ‘1’ - The SMBus timeout and idle functionality are disabled. The SMBus interface will not time out
if the clock line is held low. Likewise, it will not reset if both the data and clock lines are held high
for longer than 150us. This is used for I2C compliance.

Bit 4 - DIS_AVG - Disables digital averaging of the External Diode 1 channel.

„ ‘0’ (default) - The External Diode 1 channel has digital averaging enabled. The temperature data
is the average of the previous four measurements.
„ ‘1’ - The External Diode 1 channel has digital averaging disabled. The temperature data is the last
measured data.

Bits 3-2 - QUEUE[1:0] - Determines the number of consecutive out of limit conditions that are
necessary to trigger an interrupt. Each measurement channel has a separate fault queue associated
with the high limit and diode fault condition except the internal diode.

The Critical / Thermal Shutdown temperature has a separate fault queue that applies to the selected
hardware shutdown channel (see Section 5.9) when compared against the threshold set by the
TRIP_SET pin.

APPLICATION NOTE: If the fault queue for any channel is currently active (i.e. an out of limit condition has been
detected and caused the fault queue to increment) then changing the settings will not take
effect until the fault queue is zeroed. This occurs by the ALERT pin asserting or the out of
limit condition being removed.

SMSC EMC2112 43 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.16 Fault Queue

QUEUE[1:0]

1 0 NUMBER OF CONSECUTIVE OUT OF LIMIT CONDITIONS

0 0 1 (disabled)

0 1 2

1 0 3

1 1 4 (default)

Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion
rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the
conversion rate and the average current will increase as the conversion rate increases.

Table 6.17 Conversion Rate

TEMPERATURE OVER SAMPLING

CONV[1:0] FROM 11 BITS

1 0 CONVERSION RATE DYN_DIS = ‘0’ DYN_DIS = ‘1’

0 0 1 / sec x8 x1

0 1 2 / sec x4 x1

1 0 4 / sec (default) x2 x1

1 1 8 / sec x1 x1

6.11 Interrupt Status Register

Table 6.18 Interrupt Status Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Interrupt
23h R-C Status RESET TSD TCRIT - FAN HIGH - FAULT 00h
Register

The Interrupt Status Register reports the operating condition of the EMC2112. If any of the bits are set
to a logic ‘1’ (other than RESET and TSD), the ALERT pin will be asserted low if the corresponding
channel is enabled. If there are no set status bits, the ALERT pin will be released.

The bits that cause the ALERT pin to be asserted can be masked based on the channel they are
associated with unless stated otherwise.

Bit 7 - RESET - This bit is set to ‘1’ if the Reset Generator (see Section 5.10) has tripped, meaning
that the VDD_5V voltage level is less than its normal operating level (and the RESET pin is at a logic
‘0’ state). This bit is cleared when the RESET output changes states to a logic ‘1’. This bit will not
cause the ALERT pin to be asserted.

Revision 0.88 (11-20-09) 44 SMSC EMC2112

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Bit 6 - TSD - This bit is set to ‘1’ if the internal Thermal Shutdown (TSD) circuit trips indicating that the
die temperature has exceeded its threshold. When this bit is set, it will not cause the ALERT pin to be
asserted however will coincide with the SYS_SHDN pin being asserted. This bit is cleared when the
register is read and the error condition has been removed.

Bit 5 - TCRIT - This bit is set to ‘1’ whenever the any bit in the Tcrit Status Register is set. This bit is
automatically cleared when the Tcrit Status Register is cleared.

Bit 3 - FAN - This bit is set to ‘1’ if any bit in the Fan Status Register is set. This bit is automatically
cleared when the Fan Status Register is read and the bits are cleared.

Bit 2 - HIGH - This bit is set to ‘1’ if any bit in the High Status Register is set. This bit is automatically
cleared when the High Status Register is read and the bits are cleared.

Bit 0 - FAULT - This bit is set to ‘1’ if any bit in the Diode Fault Register is set. This bit is automatically
cleared when the Diode Fault Register is read and the bits are cleared.

6.12 Error Status Registers

Table 6.19 Error Status Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

EXT3_ EXT2_ EXT1_ INT_

1Fh R-C Tcrit Status HWS - - - 00h
CRIT CRIT CRIT CRIT

EXT3_ EXT2_ EXT1_ INT_

24h R-C High Status - - - - 00h
HI HI HI HI

EXT3_ EXT2_ EXT1_

26h R-C Diode Fault - - - - - 00h
FLT FLT FLT

The Error Status Registers report the specific error condition for all measurement channels with limits.
If any bit is set in the High, Low, or Diode Fault Status register, the corresponding High, Low, or Fault
bit is set in the Interrupt Status Register.

Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status
Register that has bits set will clear the register and the corresponding bit in the Interrupt Status
Register if the error condition has been removed. If the error condition is persistent, reading the Error
Status Registers will have no affect.

6.12.1 Tcrit Status Register

The Tcrit Status Register stores the event that caused the SYS_SHDN pin to be asserted. Each of the
temperature channels must be associated with the SYS_SHDN pin before the corresponding status bit
can be set (see Section 6.8). Once the SYS_SHDN pin is asserted, it will be released when the
temperature drops below the threshold level however the individual status bit will not be cleared until
read.

Bit 7 - HWS - This bit is set if the hardware set temperature channel meets or exceeds the temperature
threshold determined by the TRIP_SET voltage.

SMSC EMC2112 45 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

6.13 Fan Status Register

Table 6.20 Fan Status Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Fan Status DRIVE_ FAN_ FAN_ FAN_

27h R-C WATCH - - - 00h
Register FAIL SHORT SPIN STALL

The Fan Status Register contains the status bits associated with each fan driver. This register is
cleared when read if the error condition has been removed.

Bit 7 - WATCH - This bit is asserted ‘1’ if the Watchdog timer has expired (see Section 5.6).

Bit 5 - DRIVE_FAIL - Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan
to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT pin.
„ ‘0’ - The RPM-based Fan Speed Control Algorithm can drive the Fan to the desired target setting.
„ ‘1’ - The RPM-based Fan Speed Control Algorithm cannot drive the Fan to the desired target setting
at maximum drive.

Bit 4- FAN_SHORT - This bit is asserted ‘1’ if the High Side Fan Driver detects an over current
condition that lasts for longer than 2 seconds.

Bit 1- FAN_SPIN- This bit is asserted ‘1’ if the Spin up Routine for the Fan cannot detect a valid
tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT
pin.

Bit 0 - FAN_STALL - This bit is asserted ‘1’ if the tachometer measurement on the Fan detects a stalled
fan. This bit can be masked from asserting the ALERT pin.

6.14 Interrupt Enable Register

Table 6.21 Interrupt Enable Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Interrupt EXT3_ EXT2_ EXT1_ INT_

28 R/W - - - - 00h
Enable INT_EN INT_EN INT_EN INT_EN

The Interrupt Enable Register controls the masking for each temperature channel. When a channel is
masked, it will not cause the ALERT pin to be asserted when an error condition is detected.

Bit 3 - EXT3_INT_EN - Allows the External Diode 3 channel to assert the ALERT pin. This bit can only
be set if the APD bit is set.
„ ‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with External
Diode 3 channel.
„ ‘1’ - The ALERT pin will be asserted for an error condition associated with External Diode 3
channel.

Bit 2 - EXT2_INT_EN - Allows the External Diode 2 channel to assert the ALERT pin.
„ ‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with External
Diode 2 channel.
„ ‘1’ - The ALERT pin will be asserted for an error condition associated with External Diode 2
channel.

Revision 0.88 (11-20-09) 46 SMSC EMC2112

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Bit 1 - EXT1_INT_EN - Allows the External Diode 1 channel to assert the ALERT pin.
„ ‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with External
Diode 1 channel.
„ ‘1’ - The ALERT pin will be asserted for an error condition associated with External Diode 1
channel.

Bit 0 - INT_INT_EN - Allows the Internal Diode channel to assert the ALERT pin.
„ ‘0’ (default) - The ALERT pin will not be asserted for any error condition associated with the Internal
Diode.
„ ‘1’ - The ALERT pin will be asserted for an error condition associated with the Internal Diode.

6.15 Fan Interrupt Enable Register

Table 6.22 Fan Interrupt Enable Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Fan
SPIN_ STALL_
29h R/W Interrupt - - - - - - 00h
INT_EN INT_EN
Enable

The Fan Interrupt Enable controls the masking for each Fan channel. When a channel is enabled, it
will cause the ALERT pin to be asserted when an error condition is detected.

Bit 1 - SPIN_INT_EN - Allows the FAN_SPIN bit to assert the ALERT pin.
„ ‘0’ (default) - the FAN_SPIN bit will not assert the ALERT pin though it will still update the Status
Register normally.
„ ‘1’ - the FAN_SPIN bit will assert the ALERT pin.

Bit 0 - STALL_INT_EN - Allows the FAN_STALL bit or DRIVE_FAIL bit to assert the ALERT pin.
„ ‘0’ (default) - the FAN_STALL bit or DRIVE_FAIL bit will not assert the ALERT pin though will still
update the Status Register normally.
„ ‘1’ - the FAN_STALL or DRIVE_FAIL bit will assert the ALERT pin if set.

6.16 Limit Registers

Table 6.23 Limit Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

External Diode 55h

30h R/W Sign 64 32 16 8 4 2 1
1 High Limit (+85°C)

External Diode 55h

31h R/W Sign 64 32 16 8 4 2 1
2 High Limit (+85°C)

External Diode 55h

32h R/W Sign 64 32 16 8 4 2 1
3 High Limit (+85°C)

Internal Diode 55h

34h R/W Sign 64 32 16 8 4 2 1
High Limit (+85°C)

SMSC EMC2112 47 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

The EMC2112 contains high limits for all temperature channels and voltage channels. If any
measurement meets or exceeds the high limit then the appropriate status bit is set and the ALERT pin
is asserted (if enabled).

All Limit Registers are Software Locked.

6.17 Fan Setting Register

Table 6.24 Fan Setting Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

40h R/W Fan Setting 128 64 32 16 8 4 2 1 00h

The Fan Setting Register always displays the current setting of the Fan Driver. Reading from the
register will report the current fan speed setting of the fan driver regardless of the operating mode.
Therefore it is possible that reading from this register will not report data that was previously written
into this register.

While the RPM-based Fan Speed Control Algorithm is active, then the register is read only. Writing to
the register will have no affect and the data will not be stored.

If the RPM-based Fan Control Algorithm is disabled, then the register will be set with the previous
value that was used. The register is read / write and writing to this register will affect the fan speed.

The contents of the register represent the weighting of each bit in determining the final output voltage.
The output drive for the High Side Fan Driver output is given by Equation [2].

Drive = ⎛⎝ ---------------------⎞⎠ × VDD_5V

VALUE
[2]
255

6.18 Fan Configuration 1 Register

Table 6.25 Fan Configuration 1 Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Fan EN_
42h R/W RANGE[1:0] EDGES[1:0] UPDATE[2:0] 2Bh
Configuration 1 ALGO

The Fan Configuration 1 Register controls the general operation of the RPM-based Fan Speed Control
Algorithm used for the Fan 1 driver.

Bit 7 - EN_ALGO - enables the RPM-based Fan Speed Control Algorithm.

„ ‘0’ - (default) the control circuitry is disabled and the fan driver output is determined by the Fan
Driver Setting Register.
„ ‘1’ - the control circuitry is enabled and the Fan Driver output will be automatically updated to
maintain the programmed fan speed as indicated by the TACH Target Register.

Bits 6- 5 - RANGE[1:0] - Adjusts the range of reported and programmed tachometer reading values.
The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH
Target, and TACH reading) as shown in Table 6.26.

Revision 0.88 (11-20-09) 48 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.26 Range Decode

RANGE[1:0]
REPORTED MINIMUM TACH COUNT
RPM MULTIPLIER
1 0

0 0 500 1

0 1 1000 (default) 2

1 0 2000 4

1 1 4000 8

Bits 4-3 - EDGES[1:0] - determines the minimum number of edges that must be detected on the TACH
signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more
accurate tachometer measurement, the minimum number of edges measured may be increased.

Increasing the number of edges measured with respect to the number of poles of the fan will cause
the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In
order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to
accommodate this shift. The Effective Tach Multiplier shown in Table 6.27 is used as a direct multiplier
term that is applied to the Actual RPM to achieve the Reported RPM. It should only be applied if the
number of edges measured does not match the number of edges expected based on the number of
poles of the fan (which is fixed for any given fan).

Contact SMSC for recommended settings when using fans with more or less than 2 poles.

Table 6.27 Minimum Edges for Fan Rotation

EDGES[1:0] EFFECTIVE TACH

MINIMUM TACH
NUMBER OF FAN POLES MULTIPLIER (BASED ON 2
EDGES
1 0 POLE FANS)

0 0 3 1 pole 0.5

0 1 5 2 poles (default) 1

1 0 7 3 poles 1.5

1 1 9 4 poles 2

Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along
with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner
transition of the actual fan operation as the desired fan speed changes. The Update Time is set as
shown in Table 6.28.

Table 6.28 Update Time

UPDATE[2:0]
UPDATE TIME
2 1 0

0 0 0 100ms

0 0 1 200ms

0 1 0 300ms

SMSC EMC2112 49 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.28 Update Time (continued)

UPDATE[2:0]
UPDATE TIME
2 1 0

0 1 1 400ms (default)

1 0 0 500ms

1 0 1 800ms

1 1 0 1200ms

1 1 1 1600ms

6.19 Fan Configuration 2 Register

Table 6.29 Fan Configuration 1 Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Fan TEMP_ EN_ GLITCH_

43h R/W DER_OPT [1:0] ERR_RNG[1:0] - 28h
Configuration 2 RR RRC EN

The Fan Configuration 2 Register controls the tachometer measurement and advanced features of the
RPM-based Fan Speed Control Algorithm.

Bit 7 - TEMP_RR - Overrides max step controls for the FSC algorithm when any temperature exceeds
its respective high limit.
„ ‘0’ (default) - All ramp rate control circuitry works at all times for the FSC algorithm or as determined
by the EN_RRC bit for manual mode.
„ ‘1’ - If any measured temperature or the PWM Input Duty cycle meets or exceeds its respective
high limit, then the Fan Max Step register settings are not used and the FSC algorithm acts as if
the Max Step settings were at 3Fh. The device will continue to operate in this way until all
temperatures (and the PWM input duty cycle) have dropped below the respective high limit.

Bit 6 - EN_RRC - Enables ramp rate control when the fan driver is operated in the Direct Setting Mode.
„ ‘0’ (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode,
the fan setting will instantly transition to the next programmed setting.
„ ‘1’ - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode, the fan
drive setting will follow the ramp rate controls as determined by the Fan Step and Update Time
settings. The maximum fan drive setting step is capped at the Fan Step setting and is updated
based on the Update Time as given by Table 6.28.

Bit 5 - GLITCH_EN - Disables the low pass glitch filter that removes high frequency noise injected on
the TACH pin.
„ ‘0’ - The glitch filter is disabled.
„ ‘1’ (default) - The glitch filter is enabled.

Bits 4 - 3 - DER_OPT[1:0] - Control some of the advanced options that affect the derivative portion of
the RPM-based Fan Speed Control Algorithm as shown in Table 6.30.

Revision 0.88 (11-20-09) 50 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.30 Derivative Options

DER_OPT[1:0]
OPERATION
1 0

0 0 No derivative options used

Basic derivative. The derivative of the error from the

current drive setting and the target is added to the iterative
0 1
Fan Drive Register setting (in addition to proportional and
integral terms) (default)

Step derivative. The derivative of the error from the

current drive setting and the target is added to the iterative
1 0 Fan Drive Register setting and is not capped by the Fan
Step Register. This allows faster response times than the
basic derivative.

Both the basic derivative and the step derivative are used
1 1 effectively causing the derivative term to have double the
effect of the derivative term.

Bit 2 - 1 - ERR_RNG[1:0] - Control some of the advanced options that affect the error window. When
the measured fan speed is within the programmed error window around the target speed, then the fan
drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate
necessary drive setting changes based on the error, however these changes are ignored.

Table 6.31 Error Range Options

ERR_RNG[1:0]
OPERATION
1 0

0 0 0 RPM (default)

0 1 50 RPM

1 0 100 RPM

1 1 200 RPM

6.20 Gain Register

Table 6.32 Gain Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

45h R/W Gain Register - - GAIND[1:0] GAINI[1:0] GAINP[1:0] 2Ah

The Gain Register stores the gain terms used by the proportional and integral portions of each of the
RPM-based Fan Speed Control Algorithms. These gain terms are used as the KD, KI, and KP gain
terms in a classic PID control solution.

SMSC EMC2112 51 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Table 6.33 Gain Decode

GAIND OR GAINP OR GAINI [1:0]

RESPECTIVE GAIN FACTOR
1 0

0 0 1x

0 1 2x

1 0 4x (default)

1 1 8x

6.21 Fan Spin Up Configuration Register

Table 6.34 Fan Spin Up Configuration Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Fan Spin Up DRIVE_FAIL_ NOK SPINUP_

46h R/W SPIN_LVL[2:0] 19h
Configuration CNT [1:0] ICK TIME[1:0]

The Fan Spin Up Configuration Register controls the settings of Spin Up Routine. The Fan Spin Up
Configuration Register is software locked.

Bit 7 - 6 - DRIVE_FAIL_CNT[1:0] - Determines how many update cycles are used for the Drive Fail
detection function as shown in Table 6.35. This circuitry determines whether the fan can be driven to
the desired tach target.

Table 6.35 DRIVE_FAIL_CNT[1:0] Bit Decode

DRIVE_FAIL_CNT[1:0]
NUMBER OF UPDATE PERIODS
1 0

0 0 Disabled - the Drive Fail detection circuitry is disabled

(default)

0 1 16 - the Drive Fail detection circuitry will count for 16

update periods

1 0 32 - the Drive Fail detection circuitry will count for 32

update periods

1 1 64 - the Drive Fail detection circuitry will count for 64

update periods

Bit 5 - NOKICK - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the
programmed spin up time before driving it at the programmed level.
„ ‘0’ (default) - The Spin Up Routine will drive the fan driver to 100% for 1/4 of the programmed spin
up time before reverting to the programmed spin level.
„ ‘1’ - The Spin Up Routine will not drive the fan driver to 100%. It will set the drive at the
programmed spin level for the entire duration of the programmed spin up time.

Revision 0.88 (11-20-09) 52 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Bits 4 - 2 - SPIN_LVL[2:0] - Determines the final drive level that is used by the Spin Up Routine as
shown in Table 6.36.

Table 6.36 Spin Level

SPIN_LVL[2:0]
SPIN UP DRIVE LEVEL
2 1 0

0 0 0 30%

0 0 1 35%

0 1 0 40%

0 1 1 45%

1 0 0 50%

1 0 1 55%

1 1 0 60% (default)

1 1 1 65%

Bit 1 -0 - SPINUP_TIME[1:0] - determines the maximum Spin Time that the Spin Up Routine will run
for (see Section 5.2). If a valid tachometer measurement is not detected before the Spin Time has
elapsed, then an interrupt will be generated. When the RPM-based Fan Speed Control Algorithm is
active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt.

The Spin Time is set as shown in Table 6.37.

Table 6.37 Spin Time

SPINUP_TIME[1:0]
TOTAL SPIN UP TIME
1 0

0 0 250 ms

0 1 500 ms (default)

1 0 1 sec

1 1 2 sec

6.22 Fan Max Step Register

Table 6.38 Fan Max Step Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

47h R/W Fan Max Step - - 32 16 8 4 2 1 10h

The Fan Max Step Register, along with the Update Time, controls the ramp rate of the fan driver
response calculated by the RPM-based Fan Speed Control Algorithm. The value of the registers
represents the maximum step size each fan driver will take between update times (see Section 6.18).

SMSC EMC2112 53 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

When the FSC algorithm is enabled, Ramp Rate control is automatically used. When the FSC is not
active, then Ramp Rate control can be enabled by asserting the EN_RRC bit (see Section 6.19)

APPLICATION NOTE: The UPDATE bits and Fan Step Register settings operate independently of the RPM-based
Fan Speed Control Algorithm and will always limit the fan drive setting. That is, if the
programmed fan drive setting (either in determined by the RPM-based Fan Speed Control
Algorithm or by manual settings) exceeds the current fan drive setting by greater than the
Fan Step Register setting, the EMC2112 will limit the fan drive change to the value of the
Fan Step Register. It will use the Update Time to determine how often to update the drive
settings.

APPLICATION NOTE: If the Fan Speed Control Algorithm is used, the default settings in the Fan Configuration 2
Register will cause the maximum fan step settings to be ignored.

The Fan Step Registers are software locked.

6.23 Fan Minimum Drive Register

Table 6.39 Minimum Fan Drive Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

48h R/W Fan Minimum Drive 128 64 32 16 8 4 2 1 66h (40%)

The Fan Minimum Drive Register stores the minimum drive setting for each RPM-based Fan Speed
Control Algorithm. The RPM-based Fan Speed Control Algorithm will not drive the fan at a level lower
than the minimum drive unless the target Fan Speed is set at FFh (see Section 6.26)

During normal operation, if the fan stops for any reason (including low drive), the RPM-based Fan
Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a
setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control
circuitry attempts to drive it at a level that cannot support fan operation.

The Fan Minimum Drive Register is software locked.

6.24 Valid TACH Count Register

Table 6.40 Valid TACH Count Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

49h R/W Valid TACH Count 4096 2048 1024 512 256 128 64 32 F5h

The Valid TACH Count Register stores the maximum TACH Reading Register value to indicate that
the each fan is spinning properly. The value is referenced at the end of the Spin Up Routine to
determine if the fan has started operating and decide if the device needs to retry. See Equation [3] for
translating the count to an RPM. This register is only used when the FSC is active.

If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan
RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the
algorithm will automatically begin its Spin Up Routine.

If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored
and the algorithm will use the current fan drive setting.

The Valid TACH Count Register is software locked.

Revision 0.88 (11-20-09) 54 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

6.25 Fan Drive Fail Band Registers

Table 6.41 Fan Drive Fail Band Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Fan Drive Fail

4Ah R/W 16 8 4 2 1 - - - 00h
Band Low Byte

Fan Drive Fail

4Bh R/W 4096 2048 1024 512 256 128 64 32 00h
Band High Byte

The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail
detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is
enabled, the actual measured fan speed is compared against the target fan speed. These registers
are only used when the FSC is active.

This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually
capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan
Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0]
bits then the DRIVE_FAIL status bit will be set and an interrupt generated.

6.26 TACH Target Registers

Table 6.42 TACH Target Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

TACH Target Low

4Ch R/W 16 8 4 2 1 - - - F8h
Byte

TACH Target
4Dh R/W 4096 2048 1024 512 256 128 64 32 FFh
High Byte

The TACH Target Registers hold the target tachometer value that is maintained each of the RPM-
based Fan Speed Control Algorithms.

If one of the algorithms is enabled then setting the TACH Target Register to FFh will disable the fan
driver (set the fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of
FFh) will cause the algorithm to invoke the Spin Up Routine after which it will function normally.

The Tach Target is not applied until the high byte is written. Once the high byte is written, the current
value of both high and low bytes will be used as the next Tach target. 3

6.27 TACH Reading Registers

Table 6.43 TACH Reading Registers

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

4Eh R Fan TACH 4096 2048 1024 512 256 128 64 32 FFh

Fan TACH
4Fh R 16 8 4 2 1 - - - F8h
Low Byte

SMSC EMC2112 55 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

The TACH Reading Registers’ contents describe the current tachometer reading for each of the fan.
By default, the data represents the fan speed as the number of 32kHz clock periods that occur for a
single revolution of the fan.

Equation [3] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation
[4] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan,
measuring 5 edges, with a frequency of 32.768kHz. These equations are solved and tabulated for ease
of use in AN17.4 RPM to TACH Counts Conversion.

Whenever the high byte register is read, the corresponding low byte data will be loaded to internal
shadow registers so that when the low byte is read, the data will always coincide with the previously
read high byte.

where:

poles = number of poles of the fan

(typically 2)
1 (n – 1)
RPM = -------------------- × ---------------------------------- × f TACH × 60 fTACH = the tachometer [3]
( poles ) 1
COUNT × ----- measurement frequency (typically
m 32.768kHz)

n = number of edges measured

(typically 5 for a 2 pole fan)

m = the multiplier defined by the

RANGe bits
× m-
RPM = 3,932,160
------------------------------------- [4]
COUNT COUNT = TACH Reading Register
value (in decimal)

Bit 2 - IDCF_5 - Sets the bit state of IDCFx bit 5.

BIt 1 - IDCF_4 - Sets the bit state of IDCFx bit 4.

Bit 0 - IDCF_3 - Sets the bit state of IDCFx bit 3.

Prior to enabling the RUN_ALl bit, the TATRIM and TYPE[1:0] bits must be set to the desired settings.

6.28 Software Lock Register

Table 6.44 Software Lock Register

ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Software
EFh R/W - - - - - - - LOCK 00h
Lock

The Software Lock Register controls the software locking of critical registers. This register is software
locked.

Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked
registers become read only and cannot be updated.
„ ‘0’ (default) - all SWL registers can be updated normally.
„ ‘1’ - all SWL registers cannot be updated and a hard-reset is required to unlock them.

Revision 0.88 (11-20-09) 56 SMSC EMC2112

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

6.29 Product Features Register

Table 6.45 Product Features Register

ADDRESS R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Product SHDN_CH
FCh R - - - - ADR[1:0] 00h
Features [1:0]

The Product Features register shows those functions that are enabled by external pin states.

Bits 3-2 - ADR[2:0] - Indicates the selected SMBus address as determined by the ADDR_SEL pin.

Table 6.46 ADDR_SEL Pin Configuration

ADR[1:0]
SLAVE ADDRESS
1 0

0 0 0101_111xb

0 1 0111_101xb

1 0 0101_110xb

Bits 1-0 - SHDN_CH[1:0] - Indicates the selected temperature channel associated with the Critical /
Thermal Shutdown logic (see Section 5.9).

Table 6.47 SHDN_CH Pin Configuration

SHDN_CH [1:0]
HARDWARE SHUTDOWN CHANNEL
1 0

0 0 External Diode 1 measuring CPU / GPU diode

0 1 External Diode 1 measuring AMD or discrete diode

1 0 External Diode 2 measuring discrete diode

6.30 Product ID Register

Table 6.48 Product ID Register

ADDRESS R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

FDh R Product ID 0 0 0 1 0 1 0 1 15h

The Product ID Register contains a unique 8 bit word that identifies the product.

SMSC EMC2112 57 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

6.31 Manufacturer ID Register

Table 6.49 Manufacturer ID Register

ADDRESS R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

Manufacturer
FEh R 0 1 0 1 1 1 0 1 5Dh
ID

The Manufacturer ID Register contains a unique 8 bit word that identifies SMSC.

6.32 Revision Register

Table 6.50 Revision Register

ADDRESS R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT

FFh R Revision 0 0 0 0 0 0 0 1 01h

The Revision Register contains a 8 bit word that identifies the die revision.

Revision 0.88 (11-20-09) 58 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 7 Typical Operating Curves

The following Typical Operating Curves are included.

„ Supply Current vs. Temperature
„ Supply Current vs. Supply Voltage
„ Temperature Error vs. Series Resistance
„ Temperature Error vs. CFILTER
„ Temperature Error vs. Ambient Temperature
„ Temperature Error vs. Supply Voltage
„ Tachometer Measurement Accuracy vs. Temperature
„ Tachometer Measurement Accuracy vs. Supply Voltage
„ High Side Drive Voltage vs. Temperature
„ Reset Generator Threshold vs. Temperature
„ Reset Generator Threshold vs. Supply Voltage

Supply Current vs. Ambient Temperature Supply Current vs. Supply Voltage

1.25
1.25

1.2 1.2
Supply Current (mA)
Supply Current (mA)

1.15 1.15

1.1 1.1

1.05 1.05

1 1
0 20 40 60 80 100 120 140 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
Ambient Temperature (°C) Supply Voltage (V)

Temperature Error vs. Series Resistance Temperature Error vs. CFILTER

2.5 120 1
REC off 0.8
2 100
Temperature Error (°C – REC off)
Temperature Error (°C – REC on)

0.6
(°C)(C

1.5 80 0.4
Error

0.2
Error
Temperature

1 60 0
Temperature

-0.2
0.5 40
-0.4

0 REC on 20 -0.6
-0.8
-0.5 0 -1
0 50 100 150 200 250 0 1000 2000 3000 4000 5000
Series Resistance (Ohm) CFILTER (pF)

SMSC EMC2112 59 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Temperature Error vs. Ambient Temperature Temperature Error vs. Supply Voltage

0.5 0.5

0.4 0.4

0.3 0.3

(°C
Error(°C)
(°C
(°C)

0.2 0.2
Error

TemperatureError
0.1
Error

0.1
Temperature

Temperature
0
Temperature

-0.1 -0.1
-0.2 -0.2
-0.3 -0.3
-0.4 -0.4
-0.5 -0.5
0 20 40 60 80 100 120 140 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
Ambient
Ambient Temperature
Temperature (°C)
(°C) Supply Voltage (V)

Tachometer Measurement Accuracy vs. Ambient Temperature Tachometer Measurement Accuracy vs. Supply Voltage

1 1
0.9 0.9
(%

(%
Accuracy(%)
Accuracy(%)

0.8 0.8
Tach Measurement Accuracy
MeasurementAccuracy

0.7 0.7
0.6 0.6
Tach Measurement

0.5 Internal Clock 0.5

Internal Clock
0.4 0.4
0.3 0.3
0.2
Tach

0.2
Tach

External Clock External Clock

0.1 0.1
0 0
0 20 40 60 80 100 120 140 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
Ambient Temperuture (°C) Supply Voltage (V)

High Side Drive Voltage vs. Ambient Temperature Reset Generator Threshold vs. Ambient Temperature

5 4.7

4.99
(V)
Threshold(V)

Unloaded
4.98
Reset Generator Threshold

(100kOhm) 4.65
4.97
Drive Voltage (V)

4.96
4.6
4.95
4.94
4.93 Loaded 4.55
Reset

(8.11Ohm)
4.92
4.91
4.5
4.9 0 20 40 60 80 100 120 140
0 20 40 60 80 100 120 140
Ambient Temperature (°C)
Ambient Temperature (°C)

Revision 0.88 (11-20-09) 60 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Reset Generator Threshold vs. Supply Voltage

4.7
(V
Threshold(V)
Reset Generator Threshold

4.65

4.6
Reset

4.55

4.5
2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65
Supply Voltage (V)

SMSC EMC2112 61 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 8 Package Outline

8.1 EMC2112 Package Drawings - 20-Pin QFN 4mm x 4mm

Figure 8.1 EMC2112 Package Drawing - 20-Pin QFN 4mm x 4mm

Revision 0.88 (11-20-09) 62 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Figure 8.2 EMC2112 Package Dimensions and Notes - 20-Pin QFN 4mm x 4mm

Figure 8.3 EMC2112 PCB Footprint - 20-Pin QFN 4mm x 4mm

SMSC EMC2112 63 Revision 0.88 (11-20-09)

DATASHEET
 RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

8.2 Package Marking Information

TOP
0.41

LINE: 1 – SMSC Logo without circled (R) symbol

3x 0.56
LINE: 2 – Device Number E MC 2 1 1 2
LINE: 3 – Last 7 digits of Lot Number 1 2 3 4 5 6 a
LINE: 4 – Revision and Country Code (RCC) RCC e3

PIN 1 PB-FREE/GREEN SYMBOL

(Matte Sn)
LINES 1 to 3: CENTER HORIZONTAL ALIGNMENT
LINE 4: LEFT HORIZONTAL ALIGNMENT

BOTTOM
BOTTOM MARKING NOT ALLOWED

Figure 8.4 EMC2112 Package Markings

Revision 0.88 (11-20-09) 64 SMSC EMC2112

DATASHEET
RPM-Based Linear Fan Controller with Hardware Thermal Shutdown

Datasheet

Chapter 9 Datasheet Revision History

Table 9.1 Customer Revision History

REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION

Rev. 0.88 Figure 5.4, "EMC2112 Updated figure to show SYS_SHDN# is open
(11-20-09) Critical/Thermal Shutdown drain.
Block Diagram"

Section 6.32, "Revision Updated value of Revision Register (FFh) from 00h
Register" to 01h to reflect the new die revision.

Chapter 7, Typical Added.

Operating Curves

Rev. 0.87 Table 3.1, "Absolute Updated “Junction to Ambient”:

(05-21-09) Maximum Ratings" from “16 pin QFN”
to “20 pin QFN”

Note 3.2 (following Note modified:

Table 3.1, "Absolute from “ground plane with 3.1mm x 3.1mm”
Maximum Ratings") to “ground plane with 2.6mm x 2.6mm”

Section 6.27, "TACH Added reference to AN17.4

Reading Registers"

Table 3.2, "Electrical Updated electrical specifications for supply current,

Specifications" tach accuracy, and VOH / VOL conditions on digital
pins

Rev. 0.85 Initial datasheet release

(01-08-09)

SMSC EMC2112 65 Revision 0.88 (11-20-09)

DATASHEET