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Digital System Design Question Paper

1. The document is an exam for a Digital System Design course, outlining 10 questions related to digital logic design topics like counters, multiplexers, decoders, and flip-flops. Students must answer all 10 questions, each worth 10 marks, within a 3 hour time period. The questions cover designing asynchronous and synchronous counters, multiplexers, priority encoders, decoders, registers, and converting between flip-flop types.

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wahid
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279 views

Digital System Design Question Paper

1. The document is an exam for a Digital System Design course, outlining 10 questions related to digital logic design topics like counters, multiplexers, decoders, and flip-flops. Students must answer all 10 questions, each worth 10 marks, within a 3 hour time period. The questions cover designing asynchronous and synchronous counters, multiplexers, priority encoders, decoders, registers, and converting between flip-flop types.

Uploaded by

wahid
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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University of Engineering & Management, Kolkata

End Semester Examination, December 2020


Course: B.Tech(CSE/CSIT/CST) Semester: 3rd
Paper Name: Digital System Design
Paper Code: ESC301
Full Marks: 100 Time: 3 hours

Answer all the questions. Each question is of 10 marks.

1. A. Explain, with the help of timing diagram and truth table, the functioning of a MOD-8
asynchronous UP counter.
OR
B. Design a MOD-13 asynchronous UP counter.

2. A. Design the following function using suitable MUX: F(A, B, C, D)=∑ (1, 2, 3, 4, 7, 12,
14, 15).
OR
B. Design a 8: 1 MUX using 2:1 MUXES. Explain the operation with proper truth table.

3. A. Design a full subtactor using two half subtractors. Explain the operation of a priority
Encoder.
OR
B. What is ripple counter? Design a presettable 4-Bit up asynchronous counter using J-K
flip-flop.

4. A. A binary ripple counter is required to count up to (16383)10 How many flip-flops are
required? If the clock frequency is 8-192 MHz, what is the frequency at the output of the
MSB?
OR
B. Design and explain a BCS to seven segment display decoder and explain its operation.

5. A. Design a Universal register with Flip Flops and Multiplexers and explain its operation.
What is the purpose of Multiplexer in it?
OR
B. State and explain the process of representatin a Full adder using Multiplexer. What is
the advantage of using priority encoder in error cechecking?

6. A. Simplify the following switching function using karnaugh map F(A,B,C,D) = Σ


(1,5,7,10,11,12,14) + Φ (2,3,15)
OR
B. Draw and explain a 4 to 16 line decoder using NOT and NAND gates only. Mention
the advantages of using NAND gate.

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7. A. Define Multiplexer. Implement the expression using a multiplexer along with the truth
table: f(A,B,C,D)=ΣM(1,2,4,6,8,10,12,15)
OR
B. Explain how a JK flip flop can be converted to T flip flop and a D flip flop can be
convetred to a JK Flip Flop using proper circuit diagram.

8. A. Design a MOD-10 asynchronous up counter and down counter.


OR
B. What is the difference between Ripple counter and Synchronous counter? Explain with
a short example.

9. A. Design an asynchronous up counter that will count value from 2 to 6.


OR
B. What is shift register? Classify different types of shift register with design of a SISO
register.

10. A. Design a MOD-7 Johnson counter using JK flip flop.


OR
B. Design a MOD 16 synchronous up counter using JK flip flops

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