Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 1

Chapter Topics Hours Marks

No
1. Basics of Microprocessor 06 08
1.1 Evolution of Microprocessor and types
1.2 Silent features of 8085 Microprocessor,
architecture of 8085 (Block diagram), register
organization, limitations of 8-bit Microprocessor.
(Refer chapter 1)
2. 16-bit Microprocessor 8086 08 16
2.1 Silent features of 8086 Microprocessor,
architecture of 8086 (Block diagram, pin
description), register organization, concepts of
pipelining, memory segmentation and memory
address generation.
2.2Minimum and Maximum Mode operation and
diagram (Refer chapter 2)
3. 8086 Instruction set 12 16
3.1 Machine Language Instruction format,
addressing modes.
3.2 Instruction set (Arithmetic, logical, data
transfer, bit manipulation, string, program control
transfer, process control) (Refer chapter 3)
4. The art of assembly Language Programming 14 16
4.1 Program development steps defining
problem, algorithms flowchart, initialization
checklist, choosing instructions, converting
algorithms to assembly language programs.
4.2 Assembly Language Programming Tools
Editors, Assembler, Linker, Debugger.
4.3 Assembler directives, model of 8086
assembly language programming,
programming using assembler.(Refer chapter 4)
5. Procedureand Macro 06 12
5.1 Defining Procedure (Directives used, FAR
and NEAR, CALL and RET instructions)
5.2 Defining Macros.
5.3 Assembly Language Programs using
Procedure and Macros.
(Refer chapter 5)
6. System Interfacing 04 08
6.1 Interfacing Techniques (I mapped I/O,
Memory mapped I/O, memory and I/O
addressing, 8086 addressing, and address
decoding, memory interfacing as Even and Odd
bank) (Refer chapter 6)

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 2
Chapter No-1
Basic of Microprocessor
With the rapid advances in semiconductor technology it became possible to fabricate
whole CPU of a digital computer on a single chip using LSI or VLSI technology. The term LSI
refer to ICs containing component usually transistor in the range of 1000-10,000.
A VLSI chip contain more then 10,000 transistor. A CPU built into a single LSI or VLSI
chip is called a microprocessor.
A digital computer whose CPU is a microprocessor is called as microcomputer. A
microprocessor combined with memory and input/output devices forms a microcomputer.
When all the functional components of the CPU are fabricated on a single silicon
chip using microelectronics technology ie LSI or VLSI is called MICROPROCESSOR.

Q.List features of MicroComputer

Ans: Features
1. It is a low speed computer.
2. The storage capacity is also less.
3. It consists of only one CPU. This CPU is a single chip device which is called a
microprocessor. -
4. Microcomputer is also called a microprocessor based system.
5. The word length for a microcomputer is not fixed.
6. It is a software controlled d system because, without the software it is a dead
7. machine.
8. It is available in two types (9 Single board, and (II) Multi board.
9. It consists of semiconductor chips and electromechanical devices like the floppy disk
drive, the hard disk drive, etc.
In applications point of view, the microcomputer is classified into the following categories
(i) Dedicated controllers,
(ii) Personal computers and work stations,
(iii) Real time controllers, and
(iv) Communication system controllers.

Q.Describe Microcomputer Architecture and Organization

Ans.Microcomputer consists of three basic blocks as shown in Fig. viz. CPU (Central Processing
Unit), Memory Unit and Input/Output Unit.

Fig. Block Diagram of Microcomputer Architecture

Central Processing Unit :

It is the heart of the microcomputer. In a microcomputer, the CPU is single chip device, hence
this single chip CPU is also called microprocessor.
 It controls all other units of the microcomputer.
 CPU is a synchronous sequential circuit, hence it operates with reference to clock signal.,
It is also program controlled device.
 The CPU (microprocessor) fetches, decodes and executes instructions.
 It performs arithmetic, logical, data transfer and decision making operations.
 It generates all necessary control signals and controls other units. It handles binary
information. Some microprocessors can handle BCD and ASCII informations also. It
provides an instructions set, and hence, the user or system designer must use valid
instructions (instructions available in instruction set) to operate a microprocessor. It
reduces system implementation time and improves reliability of the final product.

Main Memory Unit :

It consists of semiconductor memory chips like RAM, ROM, PROM, EPROM, EEPROM, etc. It is
able to store program and data.
 ROM, PROM, EPROM, EEPROM are non-volatile memory chips, hence they are used for
permanent data storage.
 RAM is volatile memory, hence, it is used for temporary storage of data.
The main memory must be divided into three sections, viz.
Program Memory, Data Memory and Stack Memory.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 3
This is necessary for reliable software design. Some microprocessors can distinguish
between program, data and Stack memories and hence the software design becomes simple.

Program Memory
It is used to store all programs (system software and user software). It consists of ROM
and RAM chips.
 ROM is used to store system programs.
 RAM is used to store user or application programs. In PC system, RAM is also used to
store disk operating system software temporarily.

Data Memory : It is used to store data (operands and results). It consists of ROM and RAMS
chips.
 ROM is used to store fixed data like look up tables, codes constants, etc.
 RAM is used to store variable data.
 RAM can be used as a scratch pad memory.

Stack Memory
It is used by the CPU to store contents of registers
temporarily. It contains only RAM chips. It operates in LIFO
mode (Last In First Out mode) i.e. it can read saved byte first.
This is the property of the Stack as shown in Fig.

Memory unit consists of memory locations. So, each location

is used to store one word of program or data. In a
microcomputer, the secondary memories like floppy disk,
hard disk are not treated as memory units, but are treated as
I/O peripherals.

I/O unit
It is used to interface external peripherals to the microprocessor. It provides I/O ports and
interface circuitry.
 I/O ports are used to transfer binary information between the microprocessor and the
peripherals.
 The interface circuitry converts voltages and currents of the external peripheral into
digital form or vice versa.
 The microprocessor may communicate with external peripherals via two or more I/O
ports.
 The I/O unit can be implemented b using buffers, latches and LSI or VLSI interface chips.
 Input unit is used by I/O peripherals like keyboard while the Output unit is used to
interface output peripherals like display.
There are two types of I/O units viz, general purpose and special purpose.
I. The general purpose I/O unit is used to interface any type of peripherals while
II. special purpose I/O unit is used to interface specific types of peripherals, example is
printer interface unit which is used to interface a printer. So, the I/O unit is an important
part of the microcomputer.

System bus
It is a group of conductors. It is used to transfer information (electrical signal ) between
two units. It consists of Data Bus, Address Bus and Control Bus.

Data bus : It is a bidirectional bus. It is used to transfer data between two units. The
length of a microcomputer depends upon the width of the Data Bus (number of data lines). It
has three levels, viz. Logic 0, logic 1 and HIGH IMPEDANCE.

Control bus : It consists of input and output control signals. The main control signals are Read
and Write. These signals are used to control the operation of the microcomputer. It is also used
to synchronize all operations.

There are two types of modules present in a microcomputer viz.

 Bus Master and
 Bus Slave.
Bus Master
It is a device which controls the system bus. It generates address and control signal for
bus slaves.
In a microcomputer, microprocessor, special purpose processors and DMA controllers
functions as bus master.
A Bus Master operates with reference to a clock signal. It controls all the timings and
events of a microcomputer.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 4
Bus Slave
It is a device which responds to the Bus Master. It accepts address and control signals
from the Bus Master. It does not control timings and events of the microcomputer, examples are
memory unit and I/O unit.
In a single board microcomputer, all units are mounted on one PCB, while in a
multiboard computer, CPU, some part of the memory and I/O are mounted on the main board
(mother board)and additional memories and special purpose I/O interfaces are mounted on
small PCBs adaptor cards).

Q.List and Describe Characteristics Microcomputer

Ans.Most of the characteristics of a microcomputer depend upon the following parameters
of the microprocessors
Word Length
The word length of a microcomputer depends upon the width of the Data Bus.
 The word length of a memory unit depends upon the number of data lines provided
by the microprocessor.
 The word length of the I/O unit is not fixed. It varies from peripherals to
peripherals, for example we can connect an 8 bit I/O unit to a 16 bit microcomputer.
Nowadays, the basic unit of word length is bytes.

Processor to memory band width : This parameter decides the speed of microcomputer. ,.I
 It is the number of bytes to be transferred between, a microprocessor and the
memory.
 This parameter depends upon the memory access time of a microprocessor, band
width of the PCB (maximum frequency of PCB) and word length.
 This bandwidth should be maximum. The band width is measured in terms
bytes/second.

Processor to I/O band width : It is the number of bytes to be transferred between the processor
and I/O unit. This parameter is not fixed.
 This parameter depends upon the I/O access time of a microprocessor, bandwidth
 adaptor cards and word length of I/O interfaces.
 The actual value of this parameter depends upon the speed of the peripherals. The
unit of this parameter is bytes/second.

Throughput : It is the number of tasks to be executed in one second. The task is a set of
programs including I/O programs.
This parameter depends upon the system software, process scheduling, microprocessor speed,
bandwidth (processor to memory and processor to I/O), word length, etc.

Memory storage capacity : The maximum size of memory unit depends upon the
number of address lines provided by the microprocessor,
Example
N = 2K where N is the number of memory locations and k is the number of address
Lines.

I/O unit capacity : The maximum size of the VO unit depends upon the number of I/O address
bits available in I/O instructions,
N = 2P where N is the number of I/O ports and P is the number of address bits present in at I/O
instruction.

Power consumption : It is the power consumed by all units of the microcomputer. This
parameter depends upon the complexity of the system and simultaneous operations of the
system. To save power, the microcomputer should be operated in a stand by mode.

Q.What architecture means and list various functions performed by Architecture & Its
Operation ?
Ans. A micro-processor is a semiconductor chip or a chip set that implements the central
processor of the computer. It is the heart of a microcomputer . Microprocessor consist of at a
minimum an ALU ( arithmetic and logic unit) and a control unit(CU).Thus a central processing
unit (CPU) built into a single LSI or VLSI chip is called a microprocessor. Or When all the
functional component of CPU are fabricated on the single silicon chip using microelectronics
technology is called as microprocessor.
The microprocessor is a programmable logic device designed with flip-flop, registers and
timing elements. A microprocessor has a set of instructions designed internally to manipulate
data and communicate with peripherals, the process of data manipulation and communication
is determined by logic design of microprocessor called the architecture logic

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Design of microprocessor called the architecture. In addition to internal operation
microprocessor can respond to external signals that is it can be interrupted, reseted or asked to
wait, so as to Synchronize with slower peripherals. The various functions performed by
microprocessor can be classified in these general categories: -
1> Microprocessor initiated signal.
2> Internal data operation.
3> Peripheral or externally initiated operations.

Q.List the operations initiated by Microprocessor ?

Ans. A microprocessor unit can perform primarily four operations: -
1. Memory read i.e. read data from memory
2. Memory writes i.e. writes data to memory
3. I/O read i.e. accepting data from input device
4. I/O writes i.e. sending the data to output device
All this operations are part of communication process between microprocessor and
peripheral device including memory to communicate with a device (peripheral or memory) the
microprocessor need to perform following steps.
1. Identify the device with its address
2. Transfer the data
3. Provide timing signal
The CPU performs the above following functions using three sets communication lines
called as buses (group of wires carrying information) those three sets are
a. Address bus (A- bus )
b. Data bus ( D-bus )
c. Control bus (C-bus )
This address , data , control bus as a group is called as system bus.

Q.List architecture Application of Microprocessor

Ans.Microprocessors are used in Dedicated Controllers, Personal Computers, low to moderate
speed data communication peripherals, Instrumentation point of sale terminals, replacement of
microcomputers and replacement of random logic, etc.
Application of up are
1.Microprocessor based dedicated systems
2.Personal computer and Workstation
3.Ciommunication system
4.Automobiles
5.Medical instruments
6.Peripherals
7.Replacement of random logic
8.Telex system

Q.Describe Evolution of Microprocessor

Ans.Before 1950, the CPU of the microcomputer was implemented by using discrete
components like transistors, diodes and resistors, etc. The first IC appeared on the scene at the
end of 1950s in the form of logic gates. This type of IC is called a Small Scale Integrated circuit
(SSI).
But the IC designer could fabricate many more logic gates on one chip by 1960. Hence, Medium
Scale Integrated (MSI)chips and Large Scale Integrated (LSI) chips came into the Nowadays, IC
manufacturers are manufacturing VLSI (Very Large Scale Integrated circuits) and ULS1 (Ultra
Large Scale Integrated circuits) ICs.
In 1971, Intel introduced a group of four LSI devices that made up a simple but complete
computer MCS-4.
The MCS-4 consists of 4 bit CPU namely 4004. The other components in the set were a
4001 ROM, a 4002 ROM and a 4003 shift register. The 4004 consists of an ALU and a control
unit. It provides only 45 instructions. The 4001 contains 4 bit I/O ports.
After the MCS-4, three other General Purpose microprocessors were introduced viz, the
Rockwell International 4 bit PPS-4, the Intel 8 bit 8008 and National semiconductor 16 bit zmp-
16.
The microprocessors introduced between 1971 and 1973 were the first generation
systems. They were designed using the PMOS technology.
In the mid of 1970s, the Intel introduced 8080 microprocessor.
After 1973, the second generation microprocessors such as the Motorola 6800 and 6809,
Intel 8085 and Zilog Z80 evolved. These processors were fabricated using the NMOS technology.
The 8085 is improved version of 8080. The 8085 and Z-80 were designed as upward
compatible with the 8080 (i.e. we can execute 8080 programs on 8085 and Z-80, reverse is not
possible).
After 1978, the third generation microprocessors were introduced. These processors were
16 bits wide, examples are the Intel 8086, 80186, 80286 and the Motorola 68000/68010.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 6
These microprocessors were designed using the HMOS (High density MOS) technology.
The HMOS is four times faster than NMOS. The density of HMOS is also doubled.
In 1980, the fourth generation microprocessors evolved. Intel introduced the first 32 bit
viz. Intel 486.
In 1985, Motorola M6 68020/68030/68040 and the Intel 80386/80486 were introduced.
They provide cache memory features. Also, Intel and Motorola introduced a 32 bit RISC
(Reduced Instruction Set Computer) microprocessor (Intel 80960 and Motorola 88100) with
simplified instruction sets.
In 1993, the IBM/Apple introduced the Power PC 603 processor having (64 bit Data Bus).
In 1998, Intel introduced the Pentium and Celeron processors.
Nowadays, Intel processors like Pentium I Pentium III and Pentium IV have captured the whole
market of microprocessors.

Q.List theSalient Features of 8 bit microprocessor 8085

Ans. Salient features of 8085 are
 8 bit microprocessor, i.e. 8085 mP can read or write or perform arithmetic and logical
operations on 8 bit data at a time.
 Single chip NMOS device implemented with 6200 transistors.
 Requires a single +5 Volt power supply.
 Provides on-chip clock generator, so 8085 uP does not require external clock generator,
but require external tuned circuit like RC, LC or crystal.
 Requires 2 phases, 50% duty cycle TTL clock.
 On chip bus controller
 Provides 74 instructions with five addressing modes.
 Maximum clock frequency is 3 MHz and minimum clock frequency is 500 KHz.
 Provides 16 address line, so 8085 uP can access 216 = 64 Kbytes of memory.
 Provides 5 level hardware interrupts and 8 software interrupts.
 Can generate 8 bit I/0 address, so 28= 256 input and 256 output port can be accessed.
 Provide two serial I/O lines, so serial peripheral can be interfaced directly with 8085 uP.

Q.Draw the Pin Diagram and Functional diagram of 8085 microprocessor

Ans.Functional Description
8085 is an 8-bit general purpose µp capable of addressing 64-kbytes of memory and 256
I/O device. This device has 40 pins, require +5v supply and can operate with 3.125mhz single
phase clock . figure shows the logic or functional pin out of 8085 µp. All 40 signals are
classified into 6 groups those are

Functional Layout of 8085 Microprocessor

1.Address bus
2.Multiplexed address data bus
3.Control and status signal
4.Power supply and frequency signal
5.Interrupt and peripheral initiated signal
6.Serial IO signal
Q.Describe Multiplexed Address/data Bus and Undirectional Address bus
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Ans. 16 bit address is generated by two set of busses those are
1. Multiplexed Address / Data Bus (AD0-7)
2. Unidirectional Address bus(A8-15)

I> Unidirectional Address Bus (A8-A15)

8085 has 8 address lines A8-A15 which are unidirectional and this address lines used as
higher order address bus.It is not multiplexed

II>Multiplex Address/Data Bus (AD0-AD7)

This signal lines are bi-directional and is Multiplexed ie it can be used as lower order
address bus A0 to A7 and 8 bit data bus D0 to D7 .In early part of execution cycle(T1 State) ,
this lines are used as address bus and during later part of cycle ,this lines are used ad data
bus. Thus address/Data bus operate in timeshare mode. This technique is called as
multiplexing. Multiplexing means many into one operation.
The lower order address bus and data bus can be separated using the signals ALE and
latch. so that separate address bus A0 – A7 can be generated.

Q.Describe the Control and Status signal of 8085

Ans.Control And Status Signal
This group includes two control signals
1> Read(RD)
2> Write(WR)
and three status signals
1> S1
2> S0
3> IO/ M
These signals are used to identify the nature of operation along with special signal ALE to
indicate beginning of operation.

ALE (Address Latch Enable/Pin 30)

This positive going pulse generated every time the 8085 starts the operation. It indicates
that the bits AD0-AD7 has valid address on it. This signal is used to latch this address, so that
separate set of address lines A0-A7 can be generated.

RD (pin 32)
This is a read control signal which is active low (negative going). A low level on RD
indicates that the selected memory or I/O device to perform read operation and the data bus
is available for data transfer.

WR (pin 31 )
This is a write control signal which is active low (negative going). A low level on WR
indicates that data on the data Bus is to be written in selected memory or I/O location

IO/M ( pin 34 )
This is status signal use to differentiate between memory and I/O operation. When this
signal is low it indicates memory operation and when this signal is high it indicates I/O
operation
These three control lines, RD, WR and IO/M functions together. TABLE show the truth table
Truth table for memory and I/O control
IO/M WR RD Action
0 1 0 Memory read
0 0 1 Memory write
1 1 0 I/o read
1 0 1 I/o write
X 0 0 Illegal
X 1 1 No memory or I/O access

Example :- During memory write, IO/M goes low(0), RD goes high (1), and WR goes low(0).
Remember that RD and WR never be active simultaneously. The last line of the truth table
indicates that the microprocessor is not currently accessing memory or I/O.

S1 , S0 (PIN 33 , 29) : S0 and S1 are status output pins. They indicate to the outside world
the current operation being performed by the 8085. Using S0, S1 and IO/M, advance
information of the 8085

IO/M S1 S0 Status
0 0 1 Memory write
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0 1 0 Memory read
1 0 1 I/o write
1 1 0 I/o read
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
* 0 0 Halt
* X X Hold
* X X Reset
* - tri state (high impedance) X - unspecified
Activities can be decoded. Table shows the machine cycle status. Most 8085 circuits do not
make use of the status pins. i.e rarely used

Q.List and Describe Power Supply And Clock Frequency Signals 0f 8085
Ans.To make µp compatible with TTL power supplies, the 8085 requires only a VCC of +5v and
ground. Ground is called VSS (substrate voltage) because the 8085 is a MOS device.
VCC ( pin 40) : +5 volt power supply
VSS ( pin 20) : Ground reference .All signals are measured or checked with respect to this pin.
X1 ,X2 (PIN 1,2 ):The 8085 does not require an external clock generator ,crystal is connected
between the X1 and X2 inputs of the 8085. The input frequency of the crystal is divided by 2 to
produce the internal reference frequency. The CLK OUT is a same frequency of the 8085's
internal clock. It is used to synchronize the rest of system to the 8085. Maximum operating
clock frequency of 8085 is 3.125 Mhz. Which can be obtain by connecting crystal of 6.25 Mhz
between X1 and X2.

Q.Describe different Externally Initiated Signals Including Interrupt Signals of 8085

Ans.8085 has five hardware interrupt signals that can be used to interrupt the program
execution .these signals are
1.Trap
2.RST 7.5
3.RST 6.5
4.RST 5.5
5.INTR /INTA
And three externally initiated signal those are
1.Ready
2.Reset ( Reset in and Reset out)
3.Hold / HLDA
TRAP ( PIN 6 )
Trap is highest priority , Nonmaskable interrupt .when trap is received , µp starts the
program execution from location (4.5 * 8 )h. i.e why trap is called as vectored interrupt.
RST 7.5 , 6.5 , 5.5 ( pin 7,8,9)
This are restart interrupts or vectored interrupt when recognized by µp ,µp start program
execution from fixed memory location listed below. This are maskable interrupts and has priority
lower than trap ,but among themselves RST 7.5 has highest priority followed by 6.5 and 5.5.
INTR ( PIN 10 )
Interrupt request signal used as general purpose interrupt .it has lowest priority and it is
maskable interrupt.
INTA (PIN 11 )
This is active low signal. This signal is acknowledgement sent by µp when INTR is
recognized .interrupt acknowledge is used instead of RD during the instruction cycle after an
INTR is accepted.
READY ( PIN 35 )
It is used by µp to sense whether a peripheral is ready for data transfer. If ready is high
during a read or write cycle, it indicates that the memory or peripheral is ready to send or
receive data. If ready is low, the CPU will wait till ready to go high before completing the read or
write cycle .Basically this signal is used to delay the µp read / write cycle and to interface slower
peripherals.
RESET Signal
Reset in ( PIN 36 ) : This signal may activated by reset button or other source. When reset in is
at an active-low level, the internal operation of microprocessor stops. During reset the program
counter is set to 0000h. It also sends a high signal to reset out. When reset in goes to inactive-
high level, the 8085 will fetch an instruction from memory location 0000h. When 8085 is reset
the following events occur :
1. Program counter is reset to 0000h.
2. The instruction register is cleared.
3. Interrupts are disabled.
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4. The RST7.5, RST 6.5, RST 5.5 are masked.
5. All tri-state bus lines except ALE are floated.
Reset out(PIN 3) : A high signal on reset out indicates that the CPU is being reset ,i.e the
program counter, instruction register and so on are being reset to zero. The reset out signal goes
to peripheral chips and is used to reset other devices in the system.
Hold ( pin 39 )
This is an externally initiated signal. HOLD indicates that another peripheral device such
as DMA controller is requesting the use of Address and Data buses. The CPU, upon receiving the
Hold request, will relinquish(release) the use of the bus as soon as the completion of the current
bus transfer. It floats Address, Data bus, RD , WR, IO/M and ALE Control signals. Internal
processing can continue. The processor can regain the bus only after the hold is removed.
HLDA (pin 38 )
Hold acknowledge indicates that the CPU has received the hold request and that it will
relinquish the bus in the next clock cycle. HLDA goes low after the hold request is removed.

Q.List and Describe signals responsible for Serial I/O Communication in 8085
Ans.The 8085 has two signal for implementing the serial transmission
1.SID ( serial input data )
2.SOD (serial output data )
SID (pin 5 ) : This is a serial input data line. The data on this line is loaded into bit 7 of
accumulator whenever a RIM instruction is executed.
SOD (pin 4 ):This is a serial output data line. The output sod is set or reset as specified by SIM
instruction.

Q.Draw the Architecture of 8085 and List the different block of 8085 and Describe
Ans.Architecture of 8085
8085 is an 8-bit microprocessor , it has 40 pins fabricated on single LSI chip .8085
operates with single +5V DC supply and its clock speed is about 3.125Mhz .The architecture
shows following functional units :-
1> Timing and Control Unit
2> Arithmetic and Logic Unit
3> Address and Data buffer
4> Instruction Register and Decoder
5> CPU Register Array
6> Interrupt Control and
7> Serial Control

Figure shows architecture of 8085 .

Timing and Control Unit :
Timing and control unit generates timing and control signals which are necessary for
the execution of the instruction . This unit synchronizes all the µP operations with the clock

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and generate signals necessary for communication between the microprocessor between
peripherals. It also generates RD and WR indicating availability of data on data bus
Address and Data Buffer
The 8085 contains unidirectional address bus buffer and a bi-directional data bus buffer.
These buffers isolate the internal bus system of the 8085 from the external system bus and
provide enough current gain to drive few memory and I/O chips.
Arithmetic and Logic Unit
The ALU carries out the arithmetic and logic operations i.e computing function. The
arithmetic operation performed are addition, subtraction, increment, decrement etc.
The logical operation performed are AND, OR, EXOR, Complement ,shift Compare etc .
ALU consist of
1. Accumulator
2. Temporary Register
3. Flag register
Accumulator
Accumulator is a 8 bit register. The results of nearly all arithmetic and logical operations
on data are stored in the accumulator.. Also accumulator is used as one of the source register
for arithmetic and logical operation .It is also called as register A. It is the only register for which
there are rotate instructions. It is used to enable and disable the interrupt system. It is only
register to have data transfer between input and output devices. It is accessible to user through
instruction.

Temporary Register
Temporary register is 8 bit register. This register stores the operands of arithmetic and
logic operation for short period of times. This register is not available to the programmer.

Flag Register
The flag register contains five single bit flags, and three unused bits The flags are affected
by the arithmetic and logic operation in ALU. In most of these operation result is stored in
accumulator , therefore the flags generally reflects data condition in the accumulator with some
exception. The five flags are
1. S - Sign Flag
2. Z – Zero Flag
3. Ac-Auxiliary carry Flag
4. P – Parity Flag
5. C – Carry Flag

S Z X AC X P X CY
Carry Flag
Parity Flag
Auxiliary Carry Flag
Zero Flag
Sign Flag
The description and condition of flag are as follows :

Carry Flag(CF) :- The carry flag is set when the result of an operation produces a number that
will not fit into the 8 bit accumulator. Thus the carry flag reflects the final carry out of the most
significant bit of any arithmetic operation .The carry flag also serves as a borrow for
subtraction.

Zero Flag (ZF) :- The zero flag is one of he most useful flag. The zero flag is set if ALU operation
results in 00H. Flag is reset if the result is not 00H.This flag is modified by the result in the
accumulator as well as the other register.

Parity Flag (PF) :- The parity flag is set to 1 if an arithmetic or logic instruction generates an
even number of 1s in accumulator i.e even parity . The flag is 0 if the arithmetic or logic
instruction containing an odd number of 1s, in accumulator i.e odd parity. The parity flag is the
least used of all the flags.

Sign Flag (SF) :- The sign flag is set to the condition of the most significant bit of the
accumulator following the execution of arithmetic or logical instruction. This flag is used with
signed numbers.
In a given byte, if bit 7 is 1, the number is viewed as a negative number and if bit 7 is 0,
the number will be considered positive. In arithmetic operations with signed numbers, bit 7 is
reserved for indicating the sign, and the remaining seven bits are used to represent the
magnitude of a number. Thus a set sign flag represents a negative number, whereas a reset flag
means a positive number.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 11
Auxiliary Carry (AcF) :-In arithmetic operation if a carry is generated in the digit d3 and
passed to digit d4 then Ac flag is set. This flag is commonly used in BCD arithmetic. This flag is
not available for the programmer to change the sequence of program with a jump instruction.
Instruction register and decoder
During the fetch cycle, the op-code of an instruction is stored in the instruction register.
This op-code then transferred into the instruction decoder and machine cycle encoder. The
decoder decodes the instruction and establishes the sequence of the events to follow. The
instruction register is not programmable and it is not available to the programmer.

Q.Describe the CPU Registers Array of 8085 microprocessor

The are various type of registers in Intel 8085.This register are used for storage
,manipulation of data and instruction. The different registers are
1.Temporary register ( W & Z )
2.General purpose register (B,C,D,E,H,& L)
3.Program Counter (PC)
4.Stack Pointer (SP)
5.Accumulator (A)
6.Instruction Register (IR)
7.Flag Register
Fig : Cpu Array
Register
Temporary Register
Other than one 8 – bit
temporary register there
are two more register W
and Z .These register
are used to hold
temporary data during
execution of some
instruction. This register
are non programmable
and cannot be accessed
through any instruction.

General purpose register

The 8085 has six general-purpose registers. These registers are identified as B, C, D, E, H
and L. These are 8 bit registers: CPU can either load a register from the 8 bit internal data bus
or output the register contents to this data bus. These registers can be combined to form register
pairs BC , DE , and HL .Register pairs are used to perform some 16 bit operations.
This register are programmable i.e the programmer can use them to load , transfer data
from memory to register and memory.
Program Counter (PC)
The program counter is used to hold an 16 bit address. The contents of the program
counter always points to the memory location from where the next instruction or data byte is to
fetched. The program counter is incremented automatically after each instruction or data byte is
fetched from memory. After resetting the content of PC = 0000H
Stack Pointer (SP)
The stack pointer is a 16 bit register. The stack pointer contains the address of the last
data byte written into read/write memory called the stack. Stack pointer is always loaded with
the maximum address of memory .While storing the data stack pointer decrements by two and
while retrieving the data the stack pointer is incremented by Two.
Interrupt Control
The 8085 has five hardware interrupt inputs as TRAP, RST7.5, RST6.5, RST5.5, and
INTR. Also the 8085 has interrupt acknowledgment output line as INTA . When interrupt occurs
it is to be acknowledge or not to be acknowledge , when generate INTA signal is decided by
Interrupt control.
Serial I/O control
Serial communication is basically used to reduce number wires in long distance
communication. For serial communication 8085 has two signal
1. SID
2. SOD
The serial input data enters the 8085 from SID input. The SOD output is where the serial data
leaves the 8085.The serial transmission is controlled by Serial I/O control.
Q.List the Limitation of a 8 bit Microprocessor 8085
 In 8 bit microprocessor, microprocessor can perform any arithmetic or logical operation
only on 8 bit data at a time. For multi-byte numbers, microprocessor takes more time, as
ALU is 8 bit.

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 Due to the 16 address lines, we can address only up to 64kbyte of memory, so we can
not use Intel 8085 in IBM Standard PC Because, in IBM architecture standard, minimum
640kbyte of memory is required.
 8085 has multiplexed address and data bus, so extra hardware is required to separate
address signals from the data signals. It is required compulsorily, because other device in
the microprocessor based system have separate address lines and data lines.
 8085 reads one instruction at a time. Unless first instruction gets executed completely,
microprocessor can not read second instruction from memory as 8085 has only one
instruction register. So, pipelining of the instruction execution can not be achieved.
 Flag register has limited flags. There is no flag in flag register to indicate overflow
condition of result’ of arithmetic operation on signed magnitude numbers. In signed
magnitude number, most significant bit is sign bit.
 Interrupts are very limited in 8085. Normally in large microprocessor based system, more
interrupts are required to perform data transfer between I/O and microprocessor in
interrupt driven I/O
 0perating frequency is less, so the speed of execution is slow.
 While reading or writing 16 bit or more bytes of data from the memory or I/O device, the
microprocessor needs more operation [machine] cycles. So, data transfer speed is slow.
 Using 8085, we can not design multi-processor system.
 Due to limited 8 bit size of the all register, we can store limited data bytes in the
microprocessor memory.
 There is no memory management unit.
 Only 256 input and 256 output devices can be interface with 8085, as I/0 address is 8
bit.
 The word length is 8 bit, hence the processing speed is slow.
 The resolution is less.
 Most of the 8 bit microprocessors are non-pipelined, hence the performance is less.
 The instruction set is limited, hence the processing power is less.
 Processor to memory bandwidth is less.
 Processor to I0 bandwidth is less.
 It provides very few addressing modes, hence the instruction set is not flexible. It very to
design a compiler for an 8 bit microprocessor.
 It cannot be used in scientific calculations.
 It doesnot handle real numbers.
 It is used for control applications only.
 It is not used in work-stations and servers.
 It cannot be used in multiprocessor systems.
Q.How Memory read operation is performed ?
Ans. To read an instruction from a memory location , the µp
1. First places the address on
address bus
2. This address is decoded by
address decoder to locate particular
location
3. The µp then send a pulse
called memory read a control signal ,
this signal activates the memory
chip ,after activation the content of
that particular memory location
pointed by the address on the
address bus, are placed on data bus
and transferred into µp.

Fig. Memory Read operation

Q. Explain the Internal Data Operation performed by the microprocessor
Ans. The internal architecture of µp determines how and what operations can be performed
with the data ,this operation are
1. Storing the data
2. Performing arithmetic and logical operations
3. Test for condition
4. Sequencing the execution of instruction
5. Store the data temporarily in the read/write memory during execution called as
stack
To perform this operation µp requires
a. Register
b. ALU
c. Control unit
d. Internal buses

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Q What is interrupts explain ?
Ans. The interrupt is the process of data transfer where by and external device or peripheral can
inform processor that it is ready for communication and it requires attention .The process is
initiated by external device and is asynchronous meaning that it can be initiated at any time
without reference to the system clock. The interrupt process allows the µp to respond to these
external request for attention or service on a demand basis and leaves the µp free to perform
other task.
Q Explain the different classification of the interrupts ?
Ans :
 The interrupt request is classified into two categories those are
1. Non – maskable interrupt 2. Maskable interrupt.

 Non maskable interrupts :- Non maskable interrupt mean which cannot be ignored . µp
has to respond to request immediately. 8085 has one NMI ie TRAP

 Maskable interrupts :- A maskable interrupt request can be ignored or delayed by µp if it

is performing some important critical task.8085 µp has 4 – maskable interrupts as listed
RST 7.5 , RST 6.5 , RST 5.5 and INTR
 The interrupt request is also classified as :-
1. Hardware Interrupt 2.Software Interrupt
 Hardware Interrupt : They are available as pins on 8085. The hardware interrupts
activated by I/O devices .There 5 – hardware interrupts with 8085 those are TRAP ,
RST7.5 ,RST 6.5, RST5.5 and INTR.
 Software Interrupts : This are instructions included in instruction set , using which
operation of µp can interrupted ,such an interrupt is called as software interrupts.8085
instruction set consist of 8 software interrupt those are RST 0, RST 1 ,RST 2 ,RST 3 ,RST 4,
RST 5 ,RST 6 and RST 7.This are also called as one byte call instructions.
 Further Interrupts are classified as
1. Vectored Interrupt 2. Non – vectored Interrupt.
 Vectored Interrupts : Vectored interrupts have specific address in memory. When this
interrupts are initiated they will start the execution of the program from specific memory
location. There are 4 vectored interrupts in 8085 that are TRAP , RST 7.5 , RST 6.5 , RST 5.5.
 Non vectored Interrupt :- Non Vectored interrupts do not have specific address but it
requires external hardware to supply call Location to restart execution . 8085 has one Non
– Vectored interrupt ie INTR.
 The Hardware interrupt are further classified as
1.Level triggered interrupt
2.Edge triggered interrupt
 Level triggered interrupt :- The level triggered interrupts means it should go high and
remain high until it is acknowledgement.
 Edge triggered interrupt :- The edge triggered means it is triggered with the help of
short duration pulse.
Among the 5 – interrupts of 8085 TRAP has highest priority , then RST 7.5 , RST 6.6 ,
RST5.5 and INTR has lowest priority.
Q Explain the Interrupt system of 8085 µp
Ans. 8085 has 5 – interrupts inputs as shown in fig. One is called as INTR, Three are called
as RST 7.5 , RST 6.5 , RST 5.5 respectively and last is called as TRAP a non maskable
interrupt.
INTR: It is maskable, lowest priority non-vectored interrupt. It is called as handshake
interrupt. INTR is high level sensitive interrupt, when no other interrupts are active and if
signal on INTR pin goes high the 8085 completes its present instruction and generates the
interrupt acknowledge signal which is an active low going signal on control bus. The INTA
signal can be used to generate the instructions like RST or CALL from external hardware.
TRAP:It is non maskable known as NMI. It has highest priority among the interrupt signals, it
need not be enabled or disabled. It is level and edge sensitive meaning that input should go
high and remain high to be acknowledge. It can’t be recognized again until it makes
transaction from high to low to high.
TRAP is also a vectored interrupt when is triggered the program control is transferred to
the location 0024H without any external hardware or interrupt enable instruction EI . TRAP is
generally used for the critical events such as power failure or emergency shut down
8085 interrupt system
RST 7.5 , RST 6.5 , RST 5.5 :- These are maskable vectored interrupts. There are three
hardware pins on the 8085, RST 5.5, RST 6.5 and RST 7.5. This interrupts can be enabled or
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 14
disabled during using instruction such as EI , DI , SIM .These are also called as vectored
interrupts because when these interrupts are recognized they to location equal to there number
multiplied by eight without any need of external hardware.
Out of 3 interrupts 7.5 has highest priority , then 6.5 and 5.5 has lowest priority .RST
7.5 is edge sensitive interrupt and it can be triggered with a short pulse .The request is stored
internally in the D-flip flop until the µp responds to the request or until it is cleared by reset or
by SIM instruction.
RST 5.5 and RST 6.5 are level sensitive meaning that triggering should be ON ( high) until
the execution of current instruction. If the µP in unable to respond the request the
immediately ,they should be stored or held by the external hardware.
The 8085 interrupt process is controlled interrupt enabled flip flop which is internal to
the processor .It can be reseted by ant one of three way :
1 1.By DI instruction
2 2.By system reset
3.By recognition of any interrupt.
The interrupt can enabled by executing EI instruction .RST 7.5 , 6.5 ,5.5 can be masked
individually using SIM instruction.

Q.Circuit diagram to demultiplex the address/data bus of 8085

Ans.

Q.Generating the control signal MEMR,MEMW,IOR,IOW using the signal IO/M, RD, WR
Ans.

Q.What is Stacks , explain

Ans.Stack a group of memory locations in read/write memory is used for temporary storage of
binary information during the execution of program. This area is specified by the programmer
The beginning of the stack is defined in the main program by using the instruction LXI SP
address which loads the 16 bit memory address in register SP (stack pointer).Once the stack
location is defined the storing of data bit begin at the memory location one less than the
address specified by the stack pointer register.
Data byte in the register pair of the microprocessor can be stored on the stack (two at a
time) in reverse order (decreasing memory location) by using the instruction PUSH. Data byte
can be transferred from the stack to the respective register by using the instruction POP. The
stack pointer register keeps track of storage and retrieval of information. Data stored in the RAM

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 15
(stack) in a LIFO. Stack pointer is always decremented by 2 when the data is stored on the
stack and is always incremented by 2 when data is retrieved from the stack, because 2 data
bytes are stored at a time.
The stack is shared by the programmer and the microprocessor. The programmer can store
and retrieve the content of register pair byte using PUSH and POP instruction .Similarly
microprocessor stores the content of program counter when an subroutine is called.
Instruction Related To Stack
1> Push rp
2> Push PSW
3> Pop rp
4> Pop PSW ( refer instruction set )
Q. Explain What is PSW ?
Ans. The Operand PSW ( program status word ) of the instruction( PUSH PSW , POP PSW )
represent the content of the accumulator and the flag register , the accumulator is the High
order register and the flag is the Low order register. Content of the source are not altered after
the PUSH/POP instruction.
PSW stands for program status word. In flag register 5bit indicates 5-status and three are
undefined. The combination of these 8 bits is called as PSW Programs status word. PSW and the
accumulator content are treated as 16 bit data for stack operation.
The five flags are
S Z X AC X P X C
PSW is used as 16 bit operand for Stack related operation which is useful for writing
/reading the content of flag on stack. For saving the content of flag on stack PUSH PSW is
used and for reading/restoring the content of flag from stack POP PSW is used .
By this technique the various flags can be set or reset. For example PUSH PSW will store
the content of flag on Stack ,POP B will restore the content of flag and Accumulator in register
pair BC .Now programmer can modify the content of BC register by Anding and Oring with
suitable data and then using the PUSH B will store content of BC on stack and the finally suing
the instruction POP PSW. With this the content of the flag register can be changed indirectly.
Note : Explain the instruction PUSH PSW and POP PSW from the instruction set page
Q.What is Subroutine , describe
Ans.A subroutine is a group of instruction written separately from the main program
for eg : If time delay is required between 3 successive events, 3 delay routines can be written in
main program. TO avoid repetition of same delay instruction a subroutine is used . Delay
instructions are written and separately from main program and they are called by main program
when needed.
8085 microprocessor has two instruction to implement subroutines:-
1> CALL 2> RET
Question Bank
1. Describe the function of following blocks of 8085.
a) General purpose register
b) ALU
c) Timing and control unit
d) Instruction decoder and machine cycle encoding.
e) Instruction register
f) Flags
2. What is de-multiplexing of the address and data bus? Which signal is used to de-
multiplex the address and data bus.
3. State the vector addresses of all hardware interrupts of 8085 microprocessor.
4. Draw the format of the flag register of 8085 microprocessor and describe the
condition which set and reset these flags.
5. Describe INTR interrupt.
6. List maskable and non-maskable interrupts of 8085 microprocessor.
7. Explain why
a) 8085 microprocessor is 8 bit CPU ?
b) Memory capacity of 8085 microprocessor is 64K bytes?
c) RESET IN signal is essential for microprocessor?
d) First instruction is executed after rest operation from the memory location
0000H ?
8. Draw the flag register format and explain in brief various flags related to 8085.
9. Describe TRAP interrupt. State its priority and triggering level.
10. Draw the neat labeled architecture of 8085 indicating different signals of the all the
blocks.
11. Describe the function of SID and SOD pins of 8085 microprocessor.
12. List all registers of the 8085 microprocessor and categorize them into 8 bit and 16
bit registers.
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13. State the function of RESET IN and READY pins of 8085 microprocessor.

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Chapter-2 16 bit Microprocessor
About 8086 microprocessor
Intel 8086 is a 16-bit microprocessor, which contains 29000 transistors manufactured
using HCMOS or H-MOS technology. It is an improvement over its predecessor 8080 and 8085
8-bit processor .By increasing number of address pins the memory addressing capacity is
increased up to 1-megabyte and I/O devices up to 64K.
A powerful feature of 8086 is supporting co-processor, which is also called as floating
point processor or math coprocessor 8087. It is used in to increase overall performance for
scientific applications, also used for software like ‘CAD’, ‘DTP’, ‘GRAPHICS’, etc., which requires
large and complicated calculations. The 8086 is intended to use as CPU in microcomputer. The
term 16-bit means that its arithmetic and logic unit , internal register and most of the
instruction are designed to work with 16 – bit word.
8086 has 16-bit data bus so that it can read data from or write data to memory and I/O
ports. 8086 has 20 address pins, 16 out of which are also used as data pins i.e. address and
data bus are multiplexed. 8086 requires only single +5 Volt supply and single-phase clock of
5MHZ. 8088 was designed with external data bus 8-bit and internal 16-bit. The ALU, Registers
and Instruction are same as 8086.
This was done so that peripherals and memories designed for 8085 can be directly
interfaced with 8088. Since address bus of 8086/88 is of 20 bits, it can address up to 1MB of
memory. 8086 data bus is of 16-bit and it stores data in two consecutive memory locations. If
the first byte of the word is at an even address, then 8086 can read the entire word in one
operation. But if it is an odd address, 8086 requires two operations, whereas there is no such
restriction with 8088 because its data length is 8-bit and irrespective of address it has to
perform two operations to read or write the word. 8088 is used in IBM personal computer and
its clones.
Q.List Salient Features of 8086 microprocessor
 It supports pipelined architecture and has two parallel processors ie the Bus interface
unit and the Execution unit. -
 Provides 20 address lines , so 1MB memory can be addressed
 Multiplexed 16 bit address and data bus AD0 –AD19 to minimize numbers of pin on IC.
 Operating Clock frequencies are 5 MHz, 8 MHz, 10 MHz
 Capable of executing about 0.33MIPS(Million Instruction per seconds)
 Arithmetic operation can be performed on 8 bit or 16 bit signed and unsigned data
including multiplication and division.
 Can operate in single processor and multiprocessor configuration i.e. operating modes.
 Needs single +5v supply.
 The instruction set is powerful, flexible and can be programmed in high level language
like C language.
 Provides 256 types of vectored software interrupts.
 Provide 6 byte instruction queue for pipelining of instructions execution.
 Generate 8 bit of 16 bit I/0 address so it can access maximum 64 K devices.
 Operate in maximum and minimum mode to achieve high performance level.
 Supports 24operands addressing modes.
 Supports multiprogramming.
 Provides separate instructions for string manipulation.
Q.Draw Architecture of 8086 processor and List it additional features

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The 8086 has following plus points :
1>It has 16 bit ALU and Registers
2> It has 20 bit Address bus so that it can address up to 1Mbyte of address space
3> It has 16- bit of data bus
4> It can address up to 64k of I/O ports
5>It supports coprocessor
6> It has multiple interrupt handling facility
7> It also provides supports for DMA and NMI .
8> It supports synchronization to slow peripheral and I/O devices.

Q.Describe the Internal Architecture of 8086

Ans The Internal Architecture of 8086 is divided in two parts: -
1)Bus interface unit (BIU)
2)Execution unit (EU)
Thus the works is divided between two functional unit which speeds up processing
Bus interface unit
The main function of bus interface unit is to handle all bus related external operations such as
1. outputting address,
2. fetching instructions from memory,
3. perform read/write operations from memory and I/O.
i.e it handles all address and data transactions for execution unit.
Execution unit
Execution unit carries out all the internal operations of decoding and executing. Both
BIU and EU work independent. Bus interface unit fetches the instruction in advance and stores
them in instruction queue. Execution unit takes the instructions from instruction queue and
executes them. Whenever execution unit needs communication with memory or I/O device, it
requests to Bus interface unit.

BIU consists of the following function units: -

1) Instruction Queue
2) Address calculation unit
3) Segment registers
4) Instruction pointer

Q.Describe the Concept of PipeLining

Fetching the next instruction while the recent instruction executes is known as
pipelining.
To speed up program execution, the Bus Interface Unit
fetches as many as 6 instruction bytes ahead of time from the
memory and these are held for execution unit in the (FIFO)
group of registers called QUEUE.
The BIU can be fetching instruction bytes while EU is
decoding or executing an instruction which does not require the
use of buses. When the EU is ready for the next instruction, it
simply reads the instruction from the QUEUE in the BIU. This is
much faster than sending out addresses to system memory and
waiting for the memory to send back the next instruction byte.
In case of JUMP or CALL instructions however, the
instructions prefetched in the queue are of no use. Hence the QUEUE has to be dumped and
new instructions are fetched from the addresses specified by the JUMP or CALL instructions.

Q.What is use of Instruction Queue in 8086

Ans.Bus interface unit fetches 6 bytes in case of 8086 and 4 bytes in case of 8088 ahead of time
from memory. These pre-fetched instructions are stored in FIFO group of registers called as
queue. BIU fetches this instruction when execution unit is decoding and executing previous
instructions during which EU does not require the system bus. Execution unit reads the
instruction from the queue in BIU. Fetching of next instruction while current instruction is
executed is called as pipelining. This is there to increase the operational speed.

Q.List the Segment registers and There use in 8086

Ans. BIU consists of four sixteen bit segment registers those are: - (refer the Figure)
1) Code segment register (CS)
2) Stack segment register (SS)
3) Extra segment register (ES)
4) Data segment register (DS)

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The segment registers are used to store the upper 16-bit of starting address of four
memory segments. 8086 BIU sends 20-bit address, so that it can address any of 1MB memory.
However, at any given time 8086/88 can work with 64KB segment within 1MB range.

1. Code segment register is used to store the 16-bit starting address for the program memory
i.e where code is stored.
2. The stack segment register SS is used to hold upper 16 – bit of the starting address for the
program stack.
3. The Extra segment register ES and data segment register DS are used to hold upper 16 – bit
of two memory segments used for data storage in memory.

Q.State the function of Address generator

Ans.8086 BIU sends 20 bit physical address so that 1Megabyte of memory can be accessed
.To generate 20 bit physical address, address generator add data of segment
register and instruction pointer or stack pointer .

Q.Define the function of Instruction pointer

Ans.Instruction pointer register holds 16-bit address of the next instruction to be fetched within
code segment. The value stored in IP is called as ‘offset’ or the ‘effective value’ because this
16-bit value of the instruction pointer is added as an offset to code segment register in order to
generate 20-bit physical address.

Q.Describe the function and components of Execution unit

Ans.It consists of following functional parts: -
1) ALU, control circuitry and instruction decoder.
2) Flag registers
3) General purpose register
4) 0Pointer and indexing register
5) Scratch pad register (Temporary register)

ALU, control circuitry and instruction decoder: -

The main function of ALU is to perform arithmetic and logical operations like ADD ,
SUB , INR DCR , AND , OR , NOT. Instruction decoder decodes the instruction and on
basis of decoded instruction execution unit carries series of operations. To direct control
of operations of EU control circuitry is used.

Q.List and describe the General Purpose Registers of 8086

Ans.Execution unit consists of four general purpose registers’ of 16-bit each, named as AX, BX,
CX and DX. These register is also called as
AX – Accumulator
BX – Base registers
CX – Count Register
DX – Data Register( address register)
These registers can be used as : -
1. 8- 8 bit register AH, AL, BH, BL, CH, CL, DH and DL. These registers can be used to store
both operands and results.
2. 4-16 bit register as AX , BX ,CX and DX These register can be used to store address and
data.
AX is called as accumulator. In addition to serving as arithmetic registers. It is used in I/O
operation , String operation , rotate and shift operation.
BX is can be used as base register for address calculation.
CX is used as counter. It is used as count register in string loop, rotate and shift instruction.
DX is used for storing I/O address during I/O operation.

When these register are used as 8 bit register MSB is stored in AH and LSB is stored in AL
register. Same is the case with other registers.

Q.List and Describe Flag register in 8086

Ans.8086-processor status word consists of 16 bits, out of which 7 are not used. Each bit in
processor status word is called as flag.
A flag is a flip-flop, which indicates some conditions generated by execution of an instruction
or to control certain operations of the execution unit. EU contains 9 active flags .8086 flags are
grouped in two groups: -
(1) 6 - Status /conditional flags
(2) 3 -Control flags
Status/conditional flags are used to register the status of the latest arithmetic or logical
operation performed these flags are
1. Carry flag (CF) 4. Sign flag (SF)
2. Parity flag (PF) 5. Overflow flag (OF)

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 20
3. Zero flag (ZF) 6. Auxiliary carry flag (AF)
The meaning of these flags is similar to 8085 flags.

U U U U O DF I TF SF ZF U AF U PF U CF
F F
Carry Flag
Undefined
Parity Flag

Auxiliary carry Fag

Zero Flag
Sign Flag
Single Step (Trap) Flag
Interrupt Flag
String Direction Flag
Overflow Flag

Fig. Flag Register

Carry Flag (CF) :

When addition of two 8 bit numbers is greater than FF or addition of two-16 bit numbers
is greater than FFFF then carry flag is set i.e. CF = 1.
During subtraction, if a larger number is subtracted from a smaller number the carry flag
is set to 1 to indicate that a borrow was needed.
Parity Flag (P)
The parity flag is set when lower 8 bits of the result of arithmetic or logical operations in
destination register has even number of l

Auxillary Carry Flag (AF)

During addition of two 8 bit or two 16 bit numbers, if there is a carry from lower nibble to
higher nibble, then the Auxiliary Carry flag is set.
Similarly if subtraction of two nibbles require a borrow, then the AuxilIary Carry flag is set. It is
used during BCD addition and subtraction.

Zero Flag (ZF)

If the result of an arithmetic or logical operation in the destination register is zero then
the Zero flag is set.
Sign Flag (SF)
The sign flag is set to indicate that the result of on arithmetic or a logical operation is
negative. Since 2’s complement method is used to indicate negative numbers, the MSB of the
result in the destination register will be 1 whenever the result is negative.

Overflow Flag (OF)

In the 2’s compliment numbering system, the MSB is reserved to indicate the sign. Hence
only 7 bits in case of an 8 bit operation and 15 bits in case of a 16 bit operation are available to
indicate the magnitude of the number. Therefore, if the result of an operation is greater than 7F
(for 8 bit operation) or 7FFF (for 16 bit operation), the Overflow Tag will be set to indicate that
the result has overflown into the sign bit.

Control flags control the execution of special functions. This group consists of 3 flags named as
1. Trap flag (TF)
2. Interrupt flag (IF)
3. Direction flag (DF).
These flags are different from conditional flags and are set or reset by execution unit on the
bases of result generated by ALU.

Trap Flag (TF)

By setting the TF, 8086 is forced into single step mode which generates the internal
interrupt after execution of each instruction.

Direction Flag (DF)

During string operations, string pointers are auto incremented if DF = 0 and auto
documented if DF = 1. (Refer to string operations discussed in this chapter)

Interrupt Flag (IF)

Setting of the interrupt flag IF causes 8086 to recognize external interrupts and resetting
of IF disables the interrupts.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 21

Q.Describe the special purpose , index other Scratch pad registers of 8086
Ans.The processor for storing temporary data and intermediate results uses these registers.
These are not accessible by instructions.

Pointers and index registers: -

The pointers and index group consists of
1> Instruction pointer (IP)
2> Stack pointer (SP)
3> Base pointer (BP)
4> Source index registers (SI) and
5> Destination index register (DI)
Instruction Pointer
It is used to hold the 16 bit offset address of the next byte of the code to be fetched from
the memory. This offset is also called as displacement. This offset value is added to the code
segment register after shifting it by 4- bit.
Stack Pointer Register
The stack pointer register contains a 16 bit offset which when added to the Stack
Segment register indicates the address of the memory location where a word was most recently
stored. It holds the address of the stack in LIFO(Last In First Out) mode.
Base pointer
Base pointer register is used for accessing the stack and may be used with other registers. It
holds the address of the stack in Random mode. The source index register, destination register
and base pointer register used for accessing or storing temporary data. Although SI and DI can
be used as individual registers but they are used with BX or BP.
The 20 bit physical Stack address can then be obtained by shifting the contents of the
Stack Segment register by 4 bits and adding the contents of BP to it.
Source Index Register
The source index register SI is used to load the 16 bit offset of a data word in the Data
Segment. The physical address of the data word can then be obtained shifting left the contents
of DS register by 4 bits and adding the contents of SI to it. It holds the offset address of memory
in indexed addressing mode. But it holds the offset address of source string in string.

Destination Index Register (DI) :

The Destination index register DI is used to hold the 16 bit offset of a data word in the
Extra Segment while executing string instructions. The 20 bit physical address is then
calculated from DS and DI. It holds the offset address of memory in indexed addressing mode.
But it holds the offset address of destination string in string.
The above registers can also be used for temporary storage of data just as other general
purpose registers.

Q.Describe the Physical Address is generated by Address generator in 8086

Fig. 20 bit physical address generator

For example
1. Code segment register stores upper 16-bit address of program memory from where BIU will
fetch the current instruction.
2. BIU always inserts 0’s at lower nibble of code segment to make it 20 bits. Let CS = 384FH,
then the starting address of code segment will be 384F0H.
3. Then content of IP is added by address generator to the content CS to generate physical
address for the next instruction to be fetch from memory
4. The part of the segment starting address stored in a segment register is called as segment
base

Example : CS = 1234 , IP = 0120

12340  segment base address
0120  offset
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 22
12460  Physical address

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 23

Fig. segmented memory Fig : Physical Address Generation

Instruction pointer’s use to generate 20 bit physical address

Instruction pointer register holds 16-bit address of the next instruction to be fetche d within
code segment. The value stored in IP is called as ‘offset’ or the ‘effective value’ because this
16-bit value of the instruction pointer is added as an offset to code segment register in order to
generate 20-bit physical address.

For example: -
If IP = 0123H & CS = 3000H, then
physical address will be calculated as: -
Base address: CS: 3 0 0 0 0 H
Effective address: IP: + 0 1 2 3 H
Physical address: 3 0 1 2 3H

Therefore Physical Address = CS +

IP and it is represented as CS: IP.
Similarly using DS, SS and ES
address of different segments are
generated.

Q.Describe the Stack pointer’s use to generate 20 bit physical address

Ans.The 8086 allows Us to set aside an entire 64 Kbytes segment as a stack.
The upper 16-bit of the starting address of this segment is loaded in the stack segment SS
register.
The stack pointer SP register gives the 16-bit offset from the starting address of the segment
where the word was most recently stored on the stack.
The memory location where a
word was most recently stored
in stack segment is called as
‘top of stack’.
The physical address of the
stack while reading or writing
the word is produced by adding
the contents of the stack
pointer to the stack segment
base register.
The content of SS stack base
segment register is shifted left by four bits. For example, assume SS contains 6000 H and SP
contains FFE0 H.
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 24
The SS is shifted left four bit position to give 60000 H.
After adding SP i.e. offset in to it, the resultant physical address for the top of the stack will be
6FFEO H as shown in Fig . This can be represented as SS:SP.

Q.State Advantages of memory segmentation in 8086

1) Allows accessing full 1MB memory even though each register is of 16-bit wide.
2) Allows the instruction, data or stack portion of a program to be more than 64K long by using
more than one code, data and extra segment.
3) Facilitates use of separate memory area for program, data and stack.
4) Permits a program and/or its data to be put in different areas of memory, each time the
program is executed.
5) Segmentation can be used in Multi-User system
6) Segmentation allows two processes to share the data.

Note : It is not necessary that segments are separated but they can be overlapped.
Q.State Flag organization of 8086 up
Ans.8086-processor status word consists of 16 bits, out of which 7 are not used. Each bit in
processor status word is called as flag.
A flag is a flip-flop, which indicates some conditions generated by execution of an instruction
or to control certain operations of the execution unit. EU contains 9 active flags .8086 flags are
grouped in two groups: -
(1)Status flags (2)Control flags
Status flags are used to register the status of the latest arithmetic or logical operation
performed these flags are
1. Carry flag (CF) 4. Sign flag (SF)
2. Parity flag (PF) 5. Overflow flag (OF)
3. Zero flag (ZF) 6. Auxiliary carry flag (AF)

The meaning of these flags is similar to 8085 flags.

U U U U O DF I TF S ZF U AF U PF U CF
F F F
Fig. Flag Register
Control flags control the execution of special functions. This group consists of 3 flags named as
1. Trap flag (TF) 2. Interrupt flag (IF) 3. Direction flag (DF).
These flags are different from conditional flags and are set or reset by execution unit on the
bases of result generated by ALU.
Status/Conditional Flags Description
 Carry Flag (CF) :- This Flag is set if there is a carry from MSB position during addition or a
borrow into MSB position during subtraction
 Parity Flag (PF) :- This flag serves as odd parity bit for the eight LSB of the result.
 Auxiliary carry flag (AF) :- This flag is used for BCD arithmetic .It is set if there is a carry
from lower nibble or a borrow from higher to lower nibble.
 Zero flag (ZF) :- This flag is set if the result is zero .It is reset if result is non – zero
 Sign Flag (SF) :- This flag indicates whether the result is positive or negative .It is reset if
the result is positive and set if result is negative.
 Over flow flag (OF) :- This flag is set when there is an overflow condition in the result of the
addition and subtraction operation.
 Direction flag: -It is used by string manipulation instructions. If DF = 0, string is
processed from lower to higher address and when DF = 1, string is processed from
higher to lower address.
 Interrupt flag: - When IF = 1, processor can recognize the interrupt (maskable interrupt)
on INTR pin and when this flag is 0, processor ignores all the interrupts on INTR pin.
 Trap flag: -When TF = 1, then processor will work in single stepping mode. After each
instruction executed, an internal interrupt is generated.

Q.How 8088 differs from 8086

Ans.8088 Microprocessor : 8088 is 8-bit version of 8086 which is fully compatible software-
wise with 8086 i.e. 8086 & 8088 have same instruction set. 8088 can use all the peripheral
chips that were built for 8085 system. The internal architecture of 8088 is similar to 8086, its
pin assignment is same as 8086 except address pins A8-A15 are used for only address and one
of control pins.

The BHE/S7 i.e. Byte High Enable pin is changed to status pin(SS0) because 8088 can
access only one byte at a time.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 25
The other difference between 8086 and 8088 is that 8088 has 4-byte instruction queue,
which is of 6 bytes in 8086. The reason for smaller queue is that 8088 can fetch one byte at a
time.
The signal M/IO of 8086 is reversed in 8088 and named as IO/M.

Q.Draw and Describe Register Organization of

8086
Refer the notes for the answer

Q.Draw the Pin diagram of 8086 and 8088

Pin Diagram of 8086 and 8088

Q.Describe the Pin to Pin Description of 8086/88 pins in minimum mode

Pin(s) Symbol In/out Description

3-
st
at
e
1 GND - Ground
1
2-16 AD15- I/O-- 3 Outputs address during the first part of the bus cycle and
AD0 inputs or outputs data during the remaining part of the bus
cycle.
17 NMI I Non maskable interrupt request - positive-going edge
triggered.
18 INTR I Maskable interrupt request - level triggered.
2
19 CLK I Clock - 33% duty cycle, maximum rate depends on CPU
model . 5 MHz for 8086 , 8 MHz for 8086-2 , 10 MHz for
8086-1
20 GND - Ground
21 RESET I Terminates activity, clears PSW, IP, DS, SS,ES and the

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 26
instruction queue, and sets CS to FFFFh. Processing begins
at FFFF0 when signal is dropped.
22 READY I Acknowledgment from memory or I/O interface the CPU can
complete the current bus cycle.
23 TEST I Used in along with the WAIT instruction in multiprocessing
environments. A WAIT instruction will cause the CPU to
idle, except for processing interrupts, until a 0 is applied to
this pin
24-31 - - Definitions depends on mode - see Figs. And next tables
32 RD 0-3 Indicates a memory or I/O read is to be perform.
33 MN/M I CPU is in minimum mode when connected to +5V and
X maximum mode when connected to ground.
343 BHE/S 0-3 If 0 during first part of bus cycle this pin indicates that at
7 least one byte of the current transfer is to be made on pins
S7- Not AD15-AD8; if 1 the transfer is made on AD7-AD0.
Assign
ed
35-38 A19/S 0-3 During the first part of the bus cycle the upper 4 bits of the
6- address are output and during the remainder of the bus
A16/S cycle status is output. S3 and S4 indicate the segment
3 register being used .
391 AD15 I/O-3 Same as AD14-AD0
40 VCC Supply voltage- +5V ± 10%
-
1
On 8088, AD15-AD8 are A15-A8 and are only for outputting address bit.
2
5 MHz for the 8088, and 8 MHz for the 8088-2.
3
On 8088, this pin is denoted SS0 and is used in minimum mode to denote status. Logically
equivalent to S0. It is always 1 in maximum mode.

Q.Describe pin 24-31in Maximum mode pin definitions of 8086

Pin Symbol In/out 3-state Description
24,2 QS1,QS0 O Gives the status of the instruction queue.
5
26,2 S0,S1,S2 0-3 Indicates the type of transfer to take place
7,28 during the current bus cycle: For details refer
notes.
29 LOCK 0-3 Indicates the bus is not to be released to
other bus masters. It is initiated by a LOCK
instructions prefix and is maintained until the
end of the next instruction-
30 RQ/GT1 I/O For inputting bus requests and outputting bus
grants.
31 RQ/GT0 I/O Same as RQ/GT1 except that a request on
RQ/GT0 has higher priority.
Note: In maximum mode the 8086 and 8088 pins have the same definitions except for pin 34,
which on the 8088 is always 1.

Q.Describe pin 24-31 in Minimum mode pin definitions:

Pin Symbol In/out 3- Description
state
24 INTA 0-3 Indicates recognition of an interrupt request..
25 ALE 0 Outputs a pulse at the beginning of the bus cycle
and is to indicate an address is available on the
address pins.
26 DEN 0-3 Output during the later portion of the bus cycle
and is to inform the transceivers that the CPU is
ready to send or receive data.
27 DT/R 0-3 Indicates to the set of transceivers whether they are
to transmit (1) or receive (0) data.
281 M/IO 0-3 Distinguishes a memory transfer from an I/O
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 27
transfer. For a memory transfer it is 1.
29 WR 0-3 When 0, it indicates a write operation is being
performed.
30 HLDA O Outputs a bus grant to a requesting master. Pins
with tristate gates are put in high impedance state
while HLDA=1.
31 HOLD I Receives bus requests from bus masters. The
8086/88 will not gain control of the bus until this
signal is dropped.
1
For the 8088, the symbol is IO/M and a 1 indicates an I/O transfer,

Q.Describe the function of Status signal S0 ,S1,S2 and Queue status signal
S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O read
0 1 0 I/O write
0 1 1 Halt
1 0 0 Op-Code Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive

Queue Status
QS0 QS1 Status
0 0 No Operation
0 1 1st byte of opcode from queue
1 0 Empty Queue
1 1 Subsequent bye from queue

Q.List the Dumb Chip /non programmable chip used along with 8086
Ans.The dumb chip are not intelligent i.e there behavior remains the same. They operate always
according to the inputs. Dumb chip do not have memory to store, controller command
information. Once the circuit is designed it cannot be modified ie the input and output remains
same. Trouble shooting dumb chip related problem are easier and straight forward. Dumb chip
used in IBM PC design is
1. 8282 – Octal Latch ( Address Latch )
2. 8284 – Clock Generator
3. 8286 – Bi-directional buffer ( data bus transceiver )
4. 8288 – Bus controller

Q.What is Octal latch and describe8282 /74ls373

Ans.IC 8282 is an octal latch with 3-state buffered output. They can be used to implement
latches, buffers or multiplexers. It is 20 pin package. It has companion IC 8283 with inverted
output.
It has high current driving capability for driving the system data bus. This IC is generally
used to de-multiplex , multiplexed address and data bus .

 A pulse on strobe pin latches the

data bit available at the input data
pins DI0-DI7 .
 An active low signal on OE
enables the latches output DO0-
DO7 .
 A logic 1 at this pin forces the
output DO0 - DO7 to high
impedance state or tri-states .

Fig Pin Diagram

It is used to Demultiplex , multiplexed address / data . While demultiplexing the

address/data bus of 8086 , 3 – 8282’s are needed since it has to demultiplex AD0-AD15 ,
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 28
A16/S3-A19/S6 and BHE/S7. When 8088 only 2-8282’s are needed because in 8088 only 8
data bus is multiplexed with address bus. ie AD0-AD7 A16/S3-A19/S6 and BHE is absent .

Q.What is Transceiver ? Describe 8286/74ls245 – Octal Buffer

Ans.8286 is a bi-directional data bus buffer, transceiver i.e. driver and receiver. 8286 is 8-bit
bi-directional data bus buffer with 3-state output. It has companion Ic 8287 with inverted
outputs. This IC is basically used to improved driving capability of the data busdata bus.

 It has A0 – A7, B0 – B7 as I/O

pins. A low at OE pin enables the
buffer, it is also called as output
enable.
 Pin ‘T’ is used for direction
control. A low on this pin
transfers the data from B inputs to
A outputs i.e. from B0 – B7 to A0
– A7 .
 A high on ‘T’ pin transfers the
data from A input to B output i.e.
from A0 – A7 to B0 – B7.

It is used to increase current driving capability of the data bus . 2-8286 are needed
when in interfaced with 8086 since there 16-bit data bus with 8086 and 1-8286 is needed
when interfaced with 8088 since 8088 has only 8 – bit data bus.

Q.Describe the function 8284 Clock Generator

Ans.As the name specifies, this IC 8284 provides clock to system on which the functioning and
operation of system is dependent This IC performs following functions ,
1.Generate system clock for the
processor
2.Generate ready signal for the
processor
3.Generate reset signal for the
processor
The 8284 is functionally divided
into three
1. Clock logic
2. Reset logic
3. Ready logic

CLK = 1/3 * Input Frequency

PCLK = 1/2 * clock Frequency
OSC = Input Frequency
OSC = 14.31MHZ.
CLK = 1/3 * Crystal = 4.77MHZ.
PCLK = 1/2 * 4.77 = 2.38MHZ.
Clock Logic :
 The logic section generate three different output signals.
1.Clock 2.Osc 3.Pclk
 This section has two source or inputs
1. EFI ( External Frequency interface ) 2. X1 , X2 or crystal input
 Which is to be taken as source is decided by logic level at pin F/C.
 If F / C = 1 then input is supplied through clock generator like LC or Oscillator and
 if F / C = 0 then crystal is used as frequency source. In either of the cases
CLK = 1/3 * Input Frequency
PCLK = 1/2 * clock Frequency
OSC = Input Frequency
All clocks are TTL level clock signals .This clock are used by microprocessor , coprocessor
and bus controllers .If a crystal of 14.31MHZ is connected to X1 and X2 inputs then frequency
of three outputs will be: -

OSC = 14.31MHZ.
CLK = 1/3 * Crystal = 4.77MHZ.
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 29
PCLK = 1/2 * 4.77 = 2.38MHZ.

CSYNC is a synchronization signal which synchronizes multiple 8284’s in the system. In Pc

this signal is not used because only one 8284 is used .Hence CSYNC is grounded . Also in PC
the tank input (EFI) is grounded permanently because in PC crystal is used as a frequency
source.
External crystal oscillator of 24Mhz is connected to EFI input and the signal F/C is made
1 or 0 using an external mechanical switch .This can also be done by output port controlled
software or toggle switch. The frequencies of clock logic are
Clock : 8Mhz ,
Osc : 14.31Mhz
Pclk : 4Mhz
when crystal is 24Mhz.
RESET Logic :-
Reset logic of 8284 generates a reset signal for 8088 /86 .When RES pin is made low ,
the reset logic generates active high reset signal .Fig shows the reset logic.
The RES input goes to Schmitt trigger circuit
.The output of the Schmitt trigger is applied to the
D- input of the flip flop. The flip flop is set at the
positive edge of the clock input . upon reset first
instruction is fetched from memory location
FFFF0h.

READY Logic :
This logic of 8284 generates READY signal for the microprocessor to introduce a WAIT
state in 8088/86 bus cycle. The Ready input is made low by 8284 else Ready in maintained
high. There are two pair of Ready signal which can make Ready low , those are

1.RDY1 and AEN1

2.RDY2 and AEN2
The ready signal is low if any signal in both the pair is
inactive. Whenever the external devices wants to add
wait state in bus cycle of the 8086 during the data
transfer, the external device activate either RDYI or RDY2 where it is connected.
Then the 8284 generates synchronized READY signal for 8086. Thus 8086 adds wait state in
processor’s bus cycle.

Q.Describe the use of Bus controller 8288

AnsIC 8288 is a bus controller specially designed to work with Intel’s 8086 and 8088 processor.
Its important function is to generate control signals necessary for interfacing of memory and
input/output sub-systems with the processor.
The functions performed by 8288 are grouped into three groups: -
1) To generate address latch enable (ALE) to control address latch.
2) To generate DT/R (data transmit/receive) and DEN (Data enable) for controlling operation
of data bus transceiver.
3) To generate read/write control signals for memory and I/O read/write operation on behalf
of processor 8086/8088.(IOW , IOR , MEMW, MEMR).

8288 has two different sections: -

1) Bus command logic
2) Control signal logic.
Bus Command Logic :
Bus command logic generates command signals by decoding status signals S0, S1 and S2
signals. All command signals generated by 8288 are active low. The command signal generated
by 8288 for different combination of status bit are as shown in table .

All the command signal generated by 8288 are active low when there is no bus cycle by
8086/88. The command signal are inactive ie HIGH when the CEN input is low .When CEN is
HIGH then only 8288 generates command signal. S4 S3 Register
AEN input is a tristate control for the command signal. i.e 0 0 ES
When AEN = 1 all command output becomes tristate. 0 1 SS
When AEN = 0 all command output are enabled 1 0 CS or none
AEN has no effect over command output if IOB =1 . 1 1 DS
Functions of status signals
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 30
S2 S1 S0 Function
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Instruction fetch
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Inactive
S5 = Current setting of IF. S6 is always 0.
Control Signal Logic :
Control signal logic generates signals for controlling hardware connected to 8086/88’s
address bus and data bus. Description of those signals is as follows : -
DT/ R: - Used to control bi-directional data bus through data bus transceiver. If DT/R = 1, CPU
writes the data (transmits) to external circuit, if DT/R = 0, CPU reads the data (receives) from
external circuit(IC 74ls245 or 8286).
DEN :- When DEN = 1 data bus transceiver is enabled and when DEN = 0 transceiver are
disabled and its outputs are made tristate
ALE : - ALE is used by address latches to latch the address
MCE / PDEN (Master cascade enable / Peripheral device enable)
 It is a dual function pin used along with CEN and IOB pins. If IOB = 0, then this pin is
Master Cascade Enable (MCE) and is useful when more than one interrupt controllers(like
8259) are cascaded.
 IF IOB = 1 then it is called as Peripheral Device enable(PDEN) .When IOB = 1, it
operates 8288 in I/O bus mode in the systems where there are separate system buses and
I/O buses.
Q.List two Operating modes of 8086/8088
The most important and good feature of 8086/88 is that it can be operated in two different
modes: -
1) Maximum mode
2) Minimum mode
These modes of operation can be set by MN / MX pin.
Q.Describe with neat diagram Minimum mode of 8086
Ans.In this mode, all control signals are generated by microprocessor itself. It does not support
multiprocessor configuration. Memory devices and peripherals can be directly interfaced to the
µp signal. This mode is used for the small systems with a single processor. A processor can be
operated in minimum mode when it MN/MX pin is connected to +5V (HIGH).The different IC’s
used in these mode are
As shown in figure pin
1.8086/88 processor
diagram of 8086 and 8088, both
2.8282 Octal latch
processors have multiplexed data and
3.8284 clock generator
address bus with 20 address pins.
4.8286 data bus transceiver
The status signals are multiplexed
with 4MSB address bits.
8088 has 8 data pins
multiplexed with address bus and
8086 has 16 data pins multiplexed
with address bus. Except for pin 28
and 34, both the processors have same
pin definition.
Pin 28 is IO/M in 8088 and
M/IO in 8086 in minimum as well as
maximum mode. Pin 34 that is BHE in
8086, a logic 0 on this pin indicates
that MSB data lines are used but in
8088, only 8-bit data bus is available,
hence there is no need for this pin.

Interfacing figure shows clock generator - 8284,

octal latch - 8282 and transceiver - 8286 along with processor 8086. Function of different
components.
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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 31

8282
The address available during first part of bus cycle must be latched, hence to latch the
address 8-bit octal latch 8282 is used. 8086 requires 2 to latches for 16 bit address and 3 are
needed for de-multiplexing full 20 bit address. In 8086 BHE is also latched with the address .

But in 8088 minimum 2 can also be used because address lines A8 – A15 in 8088 are not
multiplexed and it is acting as full address bus through out the cycle.

STB pin of 8282 ins connected to ALE of processor .ALE is active HIGH when address is
outputted on address bus. The output enable (OE) signal is permanently grounded to enable the
output of latch through the machine cycle. Input is applied to DI0-DI7 pin and output latched
address is available from D0o-Do7.

8286
If a system has large number of interfaces then drivers and receivers like 8286 are used
to increase the current driving capability of the bus whereas this transceivers are not required in
small systems where number of interfaces are less.

8286 has 8 inputs and 8 outputs, bi-directional with two control signals T and OE, which
are connected to DT/R (direction control) and DEN (data enable ) of the processor.

8284
The third component is 8284 - clock generator. Other than generating clock, it
synchronizes Reset which initializes system with clock pulse and Ready signal which indicates
that an interface is ready to complete data transfer . 8284 accept Reset and Ready signal any
instant of time but they are not outputted till the trailing edge of the clock pulse in which they
are received.

Timing Diagram
T state:
One clock cycle is referred to as one T state. A
T state is measured from 50% falling edge of one
clock pulse to that of the next clock pulse.

Machine cycle
The time required to access a data byte from port or a memory and the time required to
write a data byte to ports or memories requires a specified number of T states. This group of T
states required for a basic bus operation is called a machine cycle.

Instruction cycle
The time required by 8086 to fetch and execute an instruction is known as an Instruction cycle

Bus operation
Each processor Bus cycle consists of at least four CLK cycles. These are referred to as T 1
and T4.
 The address is outputted by processor during T1
 Data transfer occurs on the bus during T3 and 14
 T2 is used primarily for changing the direction of the bus during Read operations.
 In case a NOT READY indication is given by the addressed device, “wait” states (Tw) are
inserted between T3 and T4 Each inserted “wait” state is of the same duration as a c
cycle.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 32
Q.Describe 8086 Read Machine Cycle in minimum mode
T1 State
In the T1 state of the first
machine cycle, the M/IO signal
is asserted HIGH for a memory
operation and LOW for an I/O
operation.
1. 8086 places the low order
address AD0 on AD7 bus
and High bits address AD8-
AD15 and upper 4bit
address on A16/s4 –
A19/s6 , as well as status
BHE/S7 signal
2. The ALE signal is connected
to the STB or enable inputs
of 8282/74ls373 latches.
The 20 bit address and the
BHE signal is latched on
trailing edge of ALE.
3. The DT/R line is made low
in order to keep the data
bus in a receive mode.

T2 State
1. 8086 now places the status
information on the A16/s3-
A19/s6 Bus and floats the AD0 to AD15 bus to read valid data.
2. In the middle of T2 the RD and DEN signals are asserted LOW in order to enable the data
buffers 8286/8287. The 8086 is now ready to read the valid data. .
3. If the access time of ROM is longer than specified one then the READY input goes
4. If the READY pin is HIGH, the 8086 continues its normal operation, whereas if it goes at
the end of T or in the middle of T then 8086 introduces “wait state” between the T3 and
the T4 state.
T3 State
If the READY pin goes HIGH during T3 or the “wait state”, then 8086 will execute its
normal operation from T4. Otherwise “WAIT STATES” are introduced as long as READY signal
remains LOW
T4 State
When the READY goes HIGH, the 8086 reads the data byte via 16 bit data The RD signal
and hence DEN signal are asserted HIGH. The AD0-15 bus is now to indicate completion of a
READ cycle.
Q.Describe Write Machine cycle
of 8086 in minimum mode
T1 State
1. During the T1 state of the
Write Machine Cycle
2. M/IO signal is asserted
HIGH for memory operations
and low for I/O operations.
3. 8086 asserts the ALE signal
HIGH to enable address
Latches.
4. The processor then sends
out the Address on the lines
AD0-AD7,A16-A19 and the
status of the BHE signal. For
I/O operations lines A0-16
are always low, since the
port addresses are always 16
bit.
5. This address and status of
BHE is latched on the
trailing edge of ALE signal.
6. The 8086 asserts the DT/R
HIGH for placing the buffers
in transmit mode.

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Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 33

T2 State
1. During the T2 state, 8086 removes the address information from AD lines and puts the
data to be written on this bus.
2. 8086 then asserts the WR signal LOW.
3. If a Memory or a Port device needs more time to take in the. data from the data bus, then
an external hardware is used to pulse the READY LINE LOW before or during

T3 State
1. After asserting the WR signal LOW, 8086 waits for the memory or the port device to
accept data in this state.
2. Wait State : If the READY INPUT is made LOW by external hardware before or during T2
then ‘WAIT’ states are inserted after T3
3. If the Ready input is made HIGH before the end of ‘WAIT state’, the 8086 continues with
T4 else it inserts another WAIT state. This continues till READY goes HIGH.
4. During this state, 8086 freezes its operations and logic levels on the buses remain
constant.
T4 State
After the addressed memory or port has accepted the data, 8086 raises its WR signal and floats
the Data bus.
This completes one Write machine cycle.
Q.With neat diagram describe Maximum mode 0f 8086
The maximum mode is for
medium to large systems
which often includes two or
more processor. In this mode
the processor does not
generate control signals
directly .Instead it issues bus
status signals S0, S1, S2. The
bus controller 8288 decodes
this status signal and
generates appropriate control
signal. In PCs, 8088 is used
in maximum mode. Figure
shows pin definition of the
processor in maximum mode.

A processor is in
maximum mode when MN/MX
is logic 0 (Grounded). In this
definition of the pin 24
through 31 is changed. This mode need of additional circuitry to translate control signals ie Bus
Controller other than Latches, Clock generators, Transceivers used . Main function bus
controller is to decode signals S0, S1 and S2 and generate signals for I/O and memory
interfacing i.e. for data transfer.
The functioning of the other components like 8282, 8284, 8286 is same as that in
minimum mode. The So, S1, S2 specify which type of transfer is to be carried out.8288
generates MEMR , IOR , MEMW , IOW, DT/R, DEN, ALE , INTA , MCE/PDEN after decoding
status signals
The QS0 and QS1 pins are to allow the system external to processor to check the status
of processor instruction queue to determine which instruction is currently executing. The Lock
pin is needed in multiprocessor system to lock the buses

Q.Describe the Timing Diagram Read/Write Mode in maximum mode of 8086

1. AD0-15, A16-19 and BHE /S7 are generated by the microprocessor during T1of read
cycle.
2. But DT/R, ALE, DEN and control signals IORC/MRDC are generated by 8288 bus
controller after receiving status signals on status lines So, S1 and S2 in T2 and T3
3. The ALE is generated by 8288 during T1 state of the read bus cycle.
4. DT/R, DEN and MRDC or IORC are generated during T state by bus controller 8288 and
make data available on the data bus D0-15

Write Mode

Prof. Manoj S. Kavedia (9773552051 / 9423088039 ) (Gayatri Engineering Classes – Contact – 9423087749)
Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 34
1. In this mode, the control signal MWTC or IOWC is generated by 8288 bus controller to
write data to the memory or I/0 device during T2 state of write bus cycle.
2. AD0-AD15, A16-19 and BHE/S7 are generated by the microprocessor during T1 of read
cycle.
3. But DT/R, ALE, DEN and control signals MWTC/IOWC are generated by 8288 bus
controller after receiving status signals on status lines S0, S1 and S2
4. The ALE is generated by 8288 during T1 state of the read bus cycle.
5. DT/R, DEN and MWTC or IOWC are generated during T2 state by bus controller 8288
and make data available on the data bus D0-D15

Fig.Write Cycle Max.Mode Fig.Read Cycle Max.Mode

Q.Comparison of 8085 and 8086

SrNo 8085 8086
1 8-bit processor 16-bit processor
2 Non Pipelined Architecture Pipelined architecture
3 On chip clock generator Requires external clock generator
4 Can access 64k memory and 256 Can access 1MB memory and 64K I/o
I/O devices devices
5 Memory is not segmented Memory is segmented
6 Single mode operation Two mode of operation Min. and Max
mode
7 Single processor system Multiprocessor system
8 Serial I/O through SID and SOD No such facility
9 5 Hardware Interrupt 2 Hardware interrupt
10 8 software Interrupt 256 Software Interrupt
11 Does not have instruction for Have instruction for Multiply and Divide
Multiply and Divide operation operation
12 Length of machine cycle is Length of machine cycle is fixed
variable
13 No address generator unit Address generator on chip
14. 5-Addressing mode 8-addressing mode

Question Bank
1. State the advantages of pipelined architecture
2. State the functions of segment registers.
3. DS contains 5B24, CS contains 5A2B and ip contain 52. Calculate the address of the instruction to
be executed.
4. State the use of overflow flag.
5. List the elements of 8086 execution unit.
6. Describe the functioning of the Bus Interface Unit of Intel’s 8086 processor. What are the advantages
of pipelining implemented in BIU? How is a 20 bit phyical address generated by 8086 using 16
segment and pointer registers? Draw a neatly labelled block diagram of 8288 bus controller
indicating all input/output signals. Describe it in brief.
7. Illustrate with an example the physical memory address generation process in 8086.
8. Differentiate between the minimum and maximum mode operations of 8086.
9. Describe the process of clock signal generation for 8086 using IC 8284.
10. List the function of pins 24 to 31 of 8086 in minimum mode.
11. List and explain the control signals of 8086 in maximum mode.

Prof. Manoj S. Kavedia (9773552051 / 9423088039 ) (Gayatri Engineering Classes – Contact – 9423087749)
Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 35
12. Describe the flag register in 8086 and list the status flags and their functions.
13. Draw the functional diagram of 8086 microprocessor and describe it in details.
14. State at least eight differences between 8085 and 8086 microprocessors.
15. What is a bus? Describe the data bus of the 8086 microprocessor.
16. How does 8086 enter into a WAIT state? At what point in a machine cycle does an 8086 enter a
WAIT state?
17. Draw the memory read timing diagram of the 8086 in minimum mode.
18. Draw and elaborate on a typical 8284 clock connection to the 8066 microprocessor.
19. List all the signals of the 8086 microprocessor in minimum mode. Draw a typical minimum mode
system.
20. What is a Queue? How does a Queue speed up the processing of the 8086 microprocessor?
21. Describe how 20-bit physical address is generated in the 8086 microprocessor?
22. Calculate the physical address generated by 4370:561E H and (ii) 1A32:0028 H
23. List and explain control flags of the 8086 microprocessor. Describe the Difference between carry flag
and overflow flag of the 8086 microprocessor.
24. Draw schematic which shows connections to the 8288 in maximum mode system of the 8086
microprocessor. Describe all signals of the 8288.
25. The contents of flag register is read as (F32F) What is the status of each of the flags?
26. Why memory segmentation is adopted in 8086?
27. List the pointer and index registers and explain their normal functions.
28. Describe the function of the execution unit of 8086.
29. State the use of NM! and DT/R signals.
30. State the functions of the following
i. DEN
ii. QSo , QS1
iii. DT/R
iv. READY.
31. Describe the Minimum mode and Maximum mode of 8086.
32. Mention the time at which the READY signal of 8086 is polled.
33. State the use of MN/MX and TEST signal.
34. Draw a neat labelled pin diagram of 8086.
35. State the pin functions of 8086 in minimum mode.
36. State the pin functions of 8086 in maximum mode.
37. State the two operating modes of 8086 and explain any one.
38. Describe the minimum mode configuration of 8086 with a neat diagram.
39. Draw the Register structure of 8086 and state the function of each Register. Write in brief about the
Memory pointer registers, Queue and Segmentation in 8086 processor.
40. Mention the default segment base and offset pairs. State the use of all Segment Base Registers.
41. Show the interfacing of 8086 in maximum mode and describe the use of all functional units.
42. List at least eight features of 8086 microprocessor.
43. Describe the flag register of the 8086 microprocessor.
44. What do you mean by segmented memory? List any two advantages.
45. State the meaning of logical addresses and physical addresses. Explain the address generation
process. If DS = 34581h and SI = 13DCH, calculate the physical address.
46. List the significant differences between the minimum and maximum mode operations of8086.
47. Describe under what situations the maximum mode operation is useful.
48. How is the clock signal provided to 8086 processor? List the various outputs of this circuit.
49. Describe segmented memory and list its four advantages.
50. State the meaning of logical and physical addresses with proper example.
51. Describe the address generation process in 8086. If the DS = C2391H and SI = 8ABCH. Find the
physical address.
52. Describe pipelined architecture concept and how it helps in improving the system throughput.
Explain the functioning of Stack and Queue.
53. Describe with a neat timing diagram the Memory Read machine cycle of 8086 in maximum mode.
54. Describe how IC 8284 is useful in providing clock and reset signals. Give the circuit diagram.
55. Describe the use of Bus Controller IC 8288 in maximum mode operation of8086.
56. Various features of 8284 clock generator.
57. Describe the function of the Bus Controller IC with its functional diagram.
58. State the importance of a maximum mode 8086 based system.
59. With timing diagram describe minimum mode read cycle.
60. Describe the minimum mode configuration of 8086 with the help of a schematic diagram.
61. Compare the features of 8085 and 8086 (eight points).
62. Elaborate the concept of Segmentation in 8086.
63. State the use of Direction, Overflow, Trap and Interrupt Enable Flags.
64. State the significance of DT/R and DEN.
65. Draw a diagram of 8284.
Prof. Manoj S. Kavedia (9773552051 / 9423088039 ) (Gayatri Engineering Classes – Contact – 9423087749)
Microprocessor – (MSK-9860174297 / 9324258878) Chapter-1 Basic of Microprocessor 36
66. Draw the interface of 8086 in max. mode and give the function of all the signals.
67. Mention function of following ICs
1. 8288 2. 8286 3. 8284
68. What is meant by pipelined structure? Explain.
69. Mention the default segment base offset pairs. If CS = 1000H, IP = 2000H, DI= 3000H, find the
physical address.
70. Name the General Purpose Registers of 8086 giving brief description of each.
71. Draw a neatly labeled block diagram of 8284A clock generator showing all the signals.
72. Why is 8086 memory set up as odd and even memory banks?
73. What is the width of the FLAG REGISTER of 8086? [ Draw the FLAG REGISTER naming and
indicating all the CONDITIONAL FLAGS, CONTROL FLAGS and UNDEFINED FLAGS.

Other Subject By Kavedia Sir At Gayatri Engg Classes

Sem – II C prog / Basic Electronics (CM/IF)
Sem –III Digital Techniques / OOP / RDBMS
Sem –IV All subject of CM / IF /EJ
Sem – V All Subject CM/IF/EJ
Sem – VI All Subject CM/IF/EJ

Prof. Manoj S. Kavedia (9773552051 / 9423088039 ) (Gayatri Engineering Classes – Contact – 9423087749)