Introduction to PLD

Logic

Standard Logic ASIC

PLD Gate Array Cell-Based IC Full Custom IC

SPLD CPLD FPGA

PLD : Programmable Logic Device

SPLD : Small/Simple Programmable Logic Device
CPLD : Complex Programmable Logic Device
FPGA : Field Programmable Gate Array
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FPGA

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1
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FPGA

Gate Array

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2
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FPGA

Standard Cell

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3
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FPGA

Full Custom

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FPGA

z Combinational Logic Implementation

z Basic Logic Gate
z Multiplexer/Decoder
z ROM
z PLD (PAL, PLA)

z Example
Solution A: (Basic Logic Gate) Solution B: (Multiplexer)
F(A, B, C) = Σ(1, 3, 5, 6) I0 I1 I2 I3
00 01 10 11
BC
A 00 01 11 10 A 0 1 0 1
0 0 1 1 0
A 0 1 1 0
1 0 1 0 1
0 1 A A
F=AC+BC+ABC
0 I0
A 1 I1 4×1
C Y F
B A I2 MUX
C F A I3 S1 S2
A
B B
C C
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2
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FPGA
F(A, B, C) = Σ(1, 3, 5, 6)
Solution C: (ROM) Solution D: (PLD)
A B C
Y0
Y1
A I0
Y2
AC P1
3×8 Y3
B I1
Decoder Y4 P2
BC
Y5
C I2 P3
Y6 ABC
Y7 P4
Fuse

1 3 56
Ｆ1 Ｆ2

Solution E: (Decoder)

Y0
Y1
A I0
Y2
3×8 Y3
B I1 F
Decoder Y4
Y5
C I2
Y6
Y7

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3
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FPGA

Gate-level diagram of a PLA Customary schematic for the PLA in the left-side hand

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4
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FPGA

An Example of a PAL Extra circuitry added to OR-gate outputs

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FPGA

Function logic block of Cypress’ 16V8

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6
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FPGA

Macro-cell structure of Cypress’ 16V8

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FPGA

Structure of a complex programmable logic device

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FPGA

Logic block diagram of Cypress’s Ultra37128

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FPGA

General structure of an FPGA

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FPGA

A Three-input LUT

A two-input lookup table (LUT) Inclusion of a Filp-flop in an FPGA logic block

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11
Main Features

‹ Field-programmable
‹ Reprogrammable
‹ In-circuit design verification
‹ Rapid prototyping
‹ Fast time-to-market
‹ No IC-test & NRE cost
‹ H/W emulation instead of S/W simulation
‹ Good software
‹ ...
 Programmability
‹ Why programmable? Why reprogrammable?
• Logic is implemented by programming the “configuration memory”
• Various configuration memory technologies
– One-Time Programmable: anti-fuse, EPROM
– Reprogrammable: EPROM, EEPROM, Flash & SRAM

configuratio
n
memory
 Programmable Combinational
Logic

configuratio LUT
n (Look-Up Table)
memory

Product Term-based Building Block Look-up Table-based Building Block

* 2-level logic * 4 to 5 inputs, fine grain architecture
* High fan-in * ROM-like
Programmable Register

preset select

M
PR output select
M
D Q
M
clock select edge control

M
M
M
EN
enable select
CLR
M
clear select 1 M

M
M

* Typical register controls: clock, enable, preset/clear, ...

Programmable Interconnect

switching switching
element element

logic cells logic cells

logic block

logic cells logic cells

switching switching
element element

Typical routing resources: switching elements, local/global lines, clock buffers...

Programmable I/O

output
select Vcc
output enable
M M
pull-up
PR control
D Q
M
M
slew-rate
M control PAD
input select
M CLR pull-down
M
control
PR
Q D
M Gnd

CLR M

Typical I/O controls: direction, I/O registers, 3-state, slew rate, ...
 Field-Programmability a
b
z

FPGA
CPLD

‹ Why filed-programmable? 01011...

• You can verify your designs at any time by configuring the FPGA/CPLD devices on
board via the download cable or hardware programmer

download cable

FPGA
or
programmer & adapter CPLD

output display
 Rapid Prototyping
‹ Reduce system prototyping time : Design
Feasibility
• You can see the “real” things
– In-circuit design verification Detailed
Design
• Quick delivery instead of IC manufacture
• No test development, no re-spin potential (i.e. no NRE cost)
IC
• Satisfied for educational purposes Manufacture

‹ Fast time-to-market
0. Design, simulation, & compilation Test &
1. Downloading configuration bitstream Debug

Prototyping

FPGA 3. Obtaining output data

2. Entering input data or
CPLD 4. Analysis Products

FPGA/CPLD is on the board!

 Software Environment
‹ Various design entries and interfaces
• HDL: Verilog, VHDL, ABEL, ...
• Graphic: Viewlogic, OrCAD, Cadence, ...
‹ Primitives & macrofunctions provided
• Primitive gates, arithmetic modules, flip-flops, counters, I/O elements, ...
‹ Constraint-driven compilation/implementation
• Logic fitting, partition, placement & routing (P&R)
‹ Simulation netlist generation
• Functional simulation & timing simulation netlist extraction
‹ Programmer/download program
 FPGA/CPLD Benefits
Full-Custom Cell-Based Gate Arrays High-
ICs ICs Density
PLDs
Speed √√ √ √
Integration Density √√ √ √ √
High-Volume device cost √√ √√ √ √
Low-volume device cost √ √
√√
Time to Market √
Risk Reduction √√
Future Modification √√
Development Tool √ √ √ √√
√√
Educational Purpose
√√
√ Good
√√ Excellent
CIC Altera & CIC
‹ Altera
• One of the world leaders in high-performance & high-density PLDs & associated
CAE tools
• Supports university program in Taiwan via CIC
‹ From CIC, you can apply:
• Altera software - it’s free for educational purpose!
)PC : MAX+PLUS II (full design environment)
– WS : MAX+PLUS II (full design environment)
Synopsys interface (Cadence & Viewlogic interfaces are optional)
• Altera hardware -
• University Program Design Laboratory Package (since 9709):
• UP1 Education Board
• ByteBlaster download cable
• Student Edition Software
• Of course, CIC is responsible for technical supports
• WWW: http://www.cic.edu.tw/chip_design/design_intr/altera/
 Altera Device Families

APEX

APEX 20K
FLEX APEX 20KE

FLEX 10KE
I/O FLEX 10KA
FLEX 10K
FLEX 6000
MAX FLEX 8000

MAX 7000B
MAX 7000AE
MAX 7000S
MAX 9000A

Usable Gates
 Altera Device Families
‹ Altera offers 7 device families
Reconfigurabl Logic Cell Usable/Typica
Device Family Members
e Element Structure l Gates
Family
Classic EPROM SOP 200 ~ 900 EP610, 910, 1810
MAX 5000 EPROM SOP 800 ~ 3,200 EPM5032, 064, 128, 130, 192
MAX 7000/E/S EEPROM SOP 600 ~ 5,000 EPM7032/V/S, 064/S, 096/S,
EPM7128E/S, 160E/S, 192E/S, 256E/S
FLEX 6000(1) SRAM LUT 10,000 ~ 24,000 EPF6016/A, 024A
FLEX 8000A SRAM LUT 2,500 ~ 16,000 EPF8282A, 452A, 636A, 820A, 1188A, 1500A
MAX 9000/A(1) EEPROM SOP 6,000 ~ 12,000 EPM9320/A, 400/A, 480/A, 560/A
FLEX 10K/A/B(1) SRAM LUT 10,000 ~ 100,000 EPF10K10/A, 20/A, 30/A, 40/A, 50/V/A,
EPF10K70/V/A, 100/A, 130/V/A, 250A
Note:
(1) Not all devices are currently available.
(2) Altera plans to ship new MAX7000A family in the near future.
 Device Part Numbers
‹ EPM7128STC100-7
• EPM = Family Signature (Erasable Programmable MAX device)
• 7128S = Device type (128 = number of macrocells)
• T = Package type (L = PLCC, T = TQFP...)
• C = Operating temperature (Commercial, Industrial)
• 100 = Pin count (number of pins on the package)
• -7 = Speed Grade in nsec
• Suffix may follow speed grade (for special device features)

‹ Another Example:
• EPM7064SLC44-5
– EPM7064S in a commercial-temp, 44 pin PLCC package with a 5 ns speed
grade
 MAX & FLEX Architectures - (1)
Global Global
Clear Clock

MAX architecture
Parallel Logic
Expanders
(from other MCs) Programmable
Register
Register
Bypass

PRn
Product- D Q to I/O
Term Control
Select ENA Block
Matrix CLRn
VCC
Clear
Select

Clock/
Shared Logic Enable
Expanders to PIA
Select
Carry-In Cascade-In
36 Programmable 16 Expander
Interconnect Programmable Register
Product Terms
Signals
DATA1
Look-Up LE Out
DATA2 Carry Cascade PRn
Table D Q
DATA3 Chain Chain
(LUT)
DATA4
CLRn

Clear/
LABCTRL1 Preset
LABCTRL2 Logic

Clock Select
LABCTRL3 FLEX architecture
LABCTRL4

Carry-Out Cascade-Out
 MAX & FLEX Architectures - (2)
‹ Choose the appropriate architecture
• Different PLD architectures provide different performance & capacity results for
same application

MAX FLEX
Feature
Architecture Architecture
Basic Building Block
Course Grain Fine Grain

Logic Cell StructureSOP LUT

Technology EEPROM SRAM

Optimization Combinational-Intensive Logic Register-Intensive, Arithmetic Functions

e.g. Large Decoders, State Machines,e.g.
... Adders, Comparators, Counters, ...
 FLEX 8000A Family
‹ Today’s FLEX 8000A family members

Device Gates LEs FFs Speed Grade Package Options I/O Pins

EPF8282A 2,500 208 282 -2,-3,-4 PLCC84, TQFP100 68,78

EPF8282AV 2,500 208 282 -4 TQFP100 68,78
EPF8452A 4,000 336 452 -2,-3,-4 PLCC84, TQFP100, PQFP160, PGA160 68,120
EPF8636A 6,000 504 636 -2,-3,-4 PLCC84, PQFP160/208, PGA192 68,118,136
EPF8820A 8,000 672 820 -2,-3,-4 TQFP144, PQFP160/208, PGA192, BGA225 120,152
EPF81188A 12,000 1,008 1,188 -2,-3,-4 PQFP208/240, PGA232 148,184
EPF81500A 16,000 1,296 1,500 -2,-3,-4 PQFP240, PGA280, RQFP304 181,208
 FLEX 8000A Features
‹ FLEX 8000A main features...
• SRAM-based devices based on Altera’s FLEX architecture
• 282 ~ 1,500 registers
• 2,500 ~ 16,000 usable gates
• Programmable flip-flops with individual clear & preset controls
• Dedicated carry chain & cascade chain
• FastTrack continuous routing structure
• Programmable output slew-rate control
• Supports in-circuit reconfiguration (ICR)
• JTAG boundary-scan test circuitry
• PCI-compliant -2 speed grade
• 3.3-V or 5-V operation
– Full 3.3-V EPF8282AV
– 3.3-V or 5-V I/O for EPF8636A and larger devices
FLEX 8000A Architecture
IOE IOE IOE IOE

1 IOE IOE 1

8 IOE LAB LAB IOE 8

A1 A2

Logic Element

1 IOE IOE 1

8 IOE LAB LAB IOE 8

B1 B2

IOE IOE IOE IOE

FLEX 8000A Logic Element

Carry-In Cascade-In
Programmable Register

DATA1
Look-Up LE Out
DATA2 Carry Cascade PRn
Table D Q
DATA3 Chain Chain
(LUT)
DATA4
CLRn

Clear/
LABCTRL1 Preset
LABCTRL2 Logic

Clock Select
LABCTRL3
LABCTRL4

Carry-Out Cascade-Out
 Carry Chains
Carry-In

A1 LUT Register S1
B1

Carry Chain
LE1

A2 LUT Register S2
B2

Carry Chain
LE2

An LUT Register Sn
Bn

Carry Chain
LEn

LUT Register Carry-Out

Carry Chain
LEn+1
 Cascade Chains
AND Cascade Chain OR Cascade Chain

D[3..0] LUT D[3..0] LUT

LE1 LE1

D[7..4] LUT D[7..4] LUT

LE2 LE2

LUT LUT
LEn LEn
FLEX 8000A Logic Array Block
Row FastTrack Interconnect

24
4
Carry-In &
LAB local 8
4 Cascade-In
Interconnect from LAB
(32 channels) on left
2 8 16
4
LAB Control Column-to-Row
Signals 4 LE 1 Interconnect

4 LE 2

4 LE 3 Column FastTrack
LE 4 Interconnect
4
4 LE 5

4 LE 6

4 LE 7

4 LE 8

8 Carry-Out &
2
Cascade-Out
to LAB on right
 FLEX 8000A FastTrack
Interconnect
Column FastTrack
(16 channels)
Row FastTrack
(168/216 channels)

LAB

LE

Local FastTrack(32 channels)

 FLEX 8000A I/O Element

to Row or Column 6
Interconnect
Programmable
Inversion
6
VCC
from Row or Column
Interconnect D Q

GND

CLRn
Slew-Rate
Control
VCC
CLR1/OE0

(OE[4..9])
CLK1/OE1
CLR0
CLK0
OE2
OE3

(OE[4..9]) are for EPF81500A devices only

 FLEX 8000A Configuration
‹ Configuration schemes & data source
• Refer to Altera’s Application Notes for details
– AN033: Configuring FLEX 8000 Devices
– AN038: Configuring Multiple FLEX 8000 Devices

Configuration Scheme Data Source

AS (Active Serial) Serial configuration EPROM
APU (Active Parallel Up) Parallel EPROM
APD (Active Parallel Down) Parallel EPROM
PS (Passive Serial) Serial data path (e.g. serial download cable)
PPS (Passive Parallel Synchronous) Intelligent host
PPA (Passive Parallel Asynchronous)Intelligent host
FLEX 10K Devices
 FLEX 10K Families

EPF10K10 EFP10K20 EFP10K30 EFP10K40 EFP10K50 EFP10K70 EFP10K100

EPF10K50V EPF10K130V
EPF10K10A EPF10K30A EPF10K100A EPF10K250A
Features
Typical 10,000 20,000 30,000 40,000 50,000 70,000 100,000 130,000 250,000
Gates

Logic 576 1,152 1,728 2,304 2,880 3,744 4,992 6,656 12,160
Elements

RAM Bits 6.144 12,288 12,288 16,384 20,480 18,432 24,576 32,768 40,960

Registers 720 1,344 1,968 2,576 3,184 4,096 5,392 7,120 12,624

Max. 134 189 246 189 310 358 406 470 470
User
I/O
 FLEX 10K Features
‹ FLEX 10K/A main features...
• SRAM-based devices based on Altera’s FLEX architecture
• Embedded programmable logic family
– Embedded array for implementing RAMs & specialized logic functions
– Logic array for general logic functions
• High density
– 10,000 ~ 100,000 typical gates (logic & RAMs)
– 720 ~ 5,392 registers
– 6,144 ~ 24,576 RAM bits
• Flexible interconnect
– FastTrack continuous routing structure
– Dedicated carry chain & cascade chain
– Up to 6 global clock & 4 global clear signals
 FLEX 10K Features - (2)
‹ FLEX 10K main features... (continued)
• Powerful I/O pins
– Individual tri-state control for each pin
– Programmable output slew-rate control
– Open-drain option on each I/O pin
– Peripheral register
• System-level features
– Supports in-circuit reconfiguration (ICR)
– JTAG boundary-scan test circuitry
– PCI-compliant -3 speed grade
– 3.3-V or 5-V I/O pins on devices in PGA, BGA & 208-pin QFP packages
– ClockLock & ClockBoost option(for EPF10K100GC503-3DX device only)
• Flexible package options
– Pin-compatibility with other FLEX 10K devices in the same packages
 Flex10KE Family Member

Features EPF10K30E EPF10K50E EPF10K100E EPF10K130E EPF10K200E

Typical
30,000 50,000 100,000 130,000 200,000
Gates
Logic
1,728 2,880 4,992 6,656 9,984
Elements

RAM Bits 24,576 40,960 49,152 65,536 98,304

Registers 1,968 3,184 5,392 7,120 10,448

Max. User I/O 246 310 406 470 470

 FLEX 10K Architecture
IOE IOE IOE IOE IOE IOE IOE IOE

1 IOE IOE 1

8 IOE IOE 8

EAB

1 IOE IOE 1

8 IOE IOE 8

EAB

LAB
Logic Element

Embedded
Array
Logic Array Logic Array

IOE IOE IOE IOE IOE IOE IOE IOE

 What is the EAB?
‹ What is the EAB?
• Larger block of RAM embedded into the PLD
• Can be preloaded with a pattern
• EAB size is flexible - 256x8 / 512x4 / 1024x2 / 2048x1
• You can combine EABs to create larger blocks
• Using RAM does not impact logic capacity
‹ EAB as logic
• EAB is preloadable at configuration time
• You can use EAB to create a large lookup table or ROM
• EAB is the same die size of 16 LEs, however, one EAB can perform complex
functions requiring more than 16 LEs
– Example: 4x4 Multiplier (40 LEs, 43MHz) vs. (1 EAB, 73MHz)
 FLEX 10K/V/A EAB
1, 2, 4, 8
Data In D 1, 2, 4, 8

RAM/RO D Data Out

M
11, 10, 9, 8 2,048 Bits
Address D
‹ EAB contains
256 x registers for
8 incoming and
Write
512 x outgoing
Enable
4 signals
D 1,024 x
Write
2
Pulse
Circui 2,048 x
In Clock 1
t

Out
Clock
 10KE EAB
Data Out
D
Data In D RAM/ROM ENA
ENA 4,096 Bits

Write Address D
ENA
256x16
Write Enable 512x8
D Write ‹ EAB contains
ENA Pulse
1024x4 registers for
Circu 2048x2 incoming and
it
outgoing
Read Address D signals
ENA

Read Enable D
ENA

Clock 1
Clock 1 Enable

Clock 2
Clock 2 Enable
 FLEX 10K Logic Element

Carry-In Cascade-In
Programmable Register

DATA1
Look-Up
DATA2 Carry Cascade to FastTrack
Table PRn
DATA3 Chain Chain D/T Q Interconnect
(LUT)
DATA4
ENA
CLRn
to LAB Local
Interconnect

LABCTRL1 Clear/
LABCTRL2 Preset
Logic
Device-Wide Clear
Clock Select
LABCTRL3
LABCTRL4
Carry-Out Cascade-Out
 FLEX 10K Register Packing

Carry-In Cascade-In
Programmable Register

DATA1
Look-Up
DATA2 Carry Cascade to FastTrack
Table PRn
DATA3 Chain Chain D/T Q Interconnect
(LUT)
DATA4
ENA
CLRn
to LAB Local
Interconnect

LABCTRL1 Clear/
LABCTRL2 Preset
Logic
Device-Wide Clear
Clock Select
LABCTRL3
LABCTRL4
Carry-Out Cascade-Out
FLEX 10K Logic Array Block
Dedicated Inputs & Global Signals
Row FastTrack Interconnect

22/26
6
16 4
LAB local
4
Interconnect Carry-In &
(30/34 channels) Cascade-In
8 24
2
4
LAB Control
Signals 4 LE 1
LE 2 Column-to-Row
4
Interconnect
4 LE 3

4 LE 4 16 Column FastTrack
8
4 LE 5 Interconnect

4 LE 6

4 LE 7

4 LE 8

8
2
Carry-Out &
Cascade-Out
FLEX 10K FastTrack Interconnect

Column FastTrack
(24 channels)
Row FastTrack
(144/216/312 channels)

LAB

LE

Local FastTrack(30/34 channels)

 FLEX 10K I/O Element
Device-Wide
VCC
from One Row or Output Disable
OE[7..0]
Column Channel
to Row or Column
Interconnect GND

12 Programmable
2
Inversion
from Row or Column VCC
Interconnect
D Q

GND
CLK[2..1] ENA Open-Drain Slew-Rate
CLRn
Output Control
CLK[3..2]
VCC
from One Row or ENA[5..0]
Column Channel

VCC
CLRn[1..0]
2 Dedicated
Clock Inputs

Peripheral Control Bus[11..0]

 ClockLock Feature
‹ ClockLock: faster system performance
• ClockLock feature incorporates a phase-locked loop (PLL) with a balanced clock
tree to minimize on-device clock delay & skew

Clock at Pin ClockLock Clock Clock at Register

D Q

Clock
Clock
Delay
ClockLock
D Q

Clock at Pin

ClockLock Clock

Clock at Register
Effective clock delay is small.
 ClockBoost Feature
‹ ClockBoost: increased system bandwidth & reduced area
• ClockBoost feature provides clock multiplication, which increases clock frequencies
by as much as 4 times the incoming clock rate
• You can distribute a low-speed clock on the PCB with ClockBoost
• ClockBoost allows designers to implement time-domain multiplexed applications.
The same functionality is accomplished with fewer logic resources.

– Note:
(1) Up to now, only EPF10K100-3DX devices support ClockLock & ClockBoost features.
(2) All new FLEX 10KA devices will support ClockBoost option.
 FLEX 10K Configuration
‹ Configuration schemes & data source
• Refer to Altera’s Application Notes for details
– AN059: Configuring FLEX 10K Devices
– AN039: JTAG Boundary-Scan Testing in Altera Devices

Configuration Scheme Data Source

PS (Passive Serial) Altera’s EPC1 configuration EPROM, BitBlaster
or ByteBlaster download cable, serial data source
PPS (Passive Parallel Synchronous)Intelligent host, parallel data source
PPA (Passive Parallel Asynchronous)Intelligent host, parallel data source
JTAG JTAG controller
 Configuration Application Notes,
Data Sheets
‹Application Notes
• AN 33: Configuring FLEX 8000 Devices
• AN 38: Configuring Multiple FLEX 8000 Devices
• AN 87: Configuring FLEX 6000 Devices
‹Data Sheets
• BitBlaster Serial Download Cable
• ByteBlasterMV Parallel Port Download Cable
• Configuration Devices for FLEX Devices
• Altera Programming Hardware
Altera Architecture Evolution

FLEX 10K/A
FLEX 8000A
FLEX 6000
Classic MAX 5000 MAX 7000/E/S MAX 9000/A

Global PIA : Enhanced PIA FastTrack

Interconnect Programmable Interconnect
Interconnect Array
 Low-Power/MultiVolt Design
‹Providing 2.5-V Power Supply for FLEX 10KE
‹Interfacing with Multi-Voltage Systems
 2.5-V Power Advantage
‹0.25-µm Process Reduces Power by 54%
‹Example
• 50-MHz Design Uses 821 mW in EPF10K30A Device
• Uses 379 mW in EPF10K30E Device
‹Benefits
• Smaller Power Supply
• Simpler Cooling System
• Less Heat Buildup
 Designing for 2.5-V Power Supply

‹2.5-V Devices Becoming Common

• Memory, Microprocessors
‹What if FLEX 10KE Device Is Only 2.5-V Device?
• Generate 2.5-V Supply from 3.3-V or 5.0-V Supply

Low-Voltage Systems
5.0 V Become More Prevalent
100%

80%
% of
Design
60% 3.3 V
2.5 V
Starts 40%

20%
1.8 V
Source: Altera0%
1992 1993 1994 1995 1996 1997 1998 1999 2000 2001
 Interfacing 2.5-V PLD to System
‹Most Systems Today Incorporate 5.0-V & 3.3-V Devices
‹2.5-V FLEX 10KE Device Must Interface to System
‹2.5-V I/O Standards Incompatible with LVTTL/LVCMOS

What’s The Solution?

 FLEX 10KE & Multi-Voltage
Boards
‹FLEX 10KE Interfaces with Multiple Voltage Levels
• MultiVolt™ I/O Feature
• 2.5-V, 3.3-V, 5.0-V I/O
• 3.3-V PCI

5.0-V FLEX 10KE 3.3-V

Device Device

2.5-V
Device
 3.3-V I/O with 2.5-V Logic
2.5 3.3
V V Min. VOH = VCC –
FLEX 0.2
10KE 3.3-V
Device Device

2.5-V Input
3.3-V Input Logic 5.0-V
5.0-V Input Device

GND
GND

2.5-V & 5.0-V Tolerant • 3.3-V Outputs Can Drive 3.3-V

Input Buffers or 5.0-V Devices
• Altera Min. VOH (VCC – 0.2 V)
Exceeds 5.0-V TTL or 3.3-V
CMOS/TTL Specifications
 2.5-V I/O with 2.5-V Logic
2.5 2.5
V V Min. VOH = 2.1 V
FLEX 10KE
Device
2.5-V
2.5-V Input Device
3.3-V Input Logic
5.0-V Input

GND
GND 2.5-V Output Can
Drive 2.5-V Devices
2.5-V & 5.0-V Tolerant
Input Buffers
Simulating Timing of MultiVolt I/O
‹Increasing VCCIO Reduces Output Delay
‹MAX+PLUS® II Accurately Models Timing Effect

Turn on MultiVolt™
I/O Setting when
VCCIO Is Not Equal
to VCCINT
 FLEX 10KE MultiVolt I/O
Summary
‹Separate VCC Pins for Logic & I/O Pins
• Logic Driven by VCCINT
• I/O Pins Driven by VCCIO
‹Connect VCCINT to 2.5-V Supply
‹Connect VCCIO to 2.5-V or 3.3-V Supply

Drives Driven by
VCCINT VCCIO
2.5 V 3.3 V 5.0 V 2.5 V 3.3 V 5.0 V

2.5 V 3.3 V Ok Ok Ok Ok Ok Ok
2.5 V 2.5 V Ok Ok Ok Ok
 Altera’s Multivolt Offering
Device Technology VccINT VccIO Drives(TTL) Driven by

2.5 3.3 5 2.5 3.3 5

FLEX6000 0.5 5 5 Y Y Y
3.3 Y Y Y Y
FLEX6000A 0.35 3.3 3.3 Y Y Y Y Y
2.5 Y Y Y Y
FLEX8000A .6,.5 5 5 Y Y Y
.6,.5 5 5 Y Y Y
3.3 Y Y Y Y
EPF8282AV .6,.5 3.3 3.3 Y Y Y
FLEX10K 0.5 5 5 Y Y Y
3.3 Y Y Y Y Y
FLEX10A 0.35 3.3 3.3 Y Y Y Y Y
2.5 Y Y Y
EPF10KE 0.22 2.5 3.3 Y Y Y Y Y
2.5 Y Y Y Y
 Device feature summary
Open Dedicated
3.3V ISP ICR EAB Drain GCLK Input OE
FLEX10K(A) Y Y Y Y 2(+4) 4 ALL
FLEX8K Y Y (+4) 4 10
FLEX6K(A) Y Y (+4) 4 ALL
MAX9000 Y 2 8
MAX7000S Y Y Y 2 6

Notes :
„ Multi-Volt ; PCI ; Slew slow rate ; JTAG-BST ==> All
Devices
„ PLL = Phase Locked Loop (ClockBoost)
„ ISP = In System Programmability
„ ICR = In Circuit Reconfiguration
„ OE = Output Enable
FPGA/CPLD Design Flow

Design
Design Detailed
Detailed Functional
Functional
Ideas
Ideas Design
Design Simulation
Simulation

Device
Device Timing
Timing Implementation
Implementation
Programming
Programming Simulation
Simulation (P&R)
(P&R)
FPGA
CPLD tpd=22.1ns
fmax=47.1MHz
 Design Ideas
‹ What are the main design considerations?
• Design feasibility?
• Design spec?
• Cost?
• FPGA/CPLD or ASIC?
• Which FPGA/CPLD vendor?
• Which device family?
• Development time?
 Detailed Design
‹ Choose the design entry method
• Schematic
– Gate level design
– Intuitive & easy to debug
• HDL (Hardware Description Language), e.g. Verilog & VHDL
– Descriptive & portable
– Easy to modify
• Mixed HDL & schematic
‹ Manage the design hierarchy
• Design partitioning
– Chip partitioning
– Logic partitioning
• Use vendor-supplied libraries or parameterized libraries to reduce design time
• Create & manage user-created libraries (circuits)
 Functional Simulation
‹ Preparation for simulation
• Generate simulation patterns
– Waveform entry
– HDL testbench
• Generate simulation netlist
‹ Functional simulation
• To verify the functionality of your design only
‹ Simulation results
• Waveform display
• Text output
‹ Challenge
• Sufficient & efficient test patterns
 Design Implementation
a
z
b
FPGA
‹ Implementation flow 01011...
CPLD

• Netlist merging, flattening, data base building

• Design rule checking
• Logic optimization
• Block mapping & placement
• Net routing
• Configuration bitstream generation
‹ Implementation results
• Design error or warnings
• Device utilization
• Timing reports
‹ Challenge
• How to reach high performance & high utilization implementation?
 Timing Analysis & Simulation
tpd=22.1ns

‹Timing analysis
fmax=47.1MHz

• Timing analysis is static, i.e., independent of input & output patterns

• To examine the timing constraints
• To show the detailed timing paths
• Can find the critical path
‹ Timing simulation
• To verify both the functionality & timing of the design
 Device Programming
‹ Choose the appropriate configuration scheme FPGA

• SRAM-based FPGA/CPLD devices

CPLD

– Downloading the bitstream via a download cable

– Programming onto a non-volatile memory device & attaching it on the circuit
board
• OTP, EPROM, EEPROM or Flash-based FPGA/CPLD devices
– Using hardware programmer
– ISP
‹ Finish the board design
‹ Program the device
‹ Challenge
• Board design
• System considerations
 Altera Design Flow

‹Operate seamlessly with other EDA tools

Verilog HDL &

VHDL Design Files FLEX
MAX+PLUS II MAX
Standard EDA Classic
HDL Files EDIF

Standard EDA
Schematics
Verilog HDL
Standard EDA VHDL
Simulator EDIF
SDF
 MAX+PLUS II
Altera’s Fully-Integrated Development System

Design Entry Project Processing

MAX+PLUS II MAX+PLUS II MAX+PLUS II Compiler
Text Editor Graphic Editor CNF Database Logic
Extractor Builder Synthesizer
MAX+PLUS II MAX+PLUS II SNF
Partitioner Fitter
Waveform Editor Symbol Editor Extractor
Netlist Design
MAX+PLUS II Assembler
Writer Doctor
Floorplan Editor MAX+PLUS II
Message Processor
&
Project Verification Hierarchy Display Device Programming
MAX+PLUS II MAX+PLUS II
Simulator Waveform Editor
MAX+PLUS II
MAX+PLUS II Programmer
Timing Analyzer
 Design Entry
‹ MAX+PLUS II design entry tools
• Graphic Editor & Symbol Editor
– For schematic designs
• Text Editor
– For AHDL and VHDL designs
– However, VHDL is not covered by this course
• Waveform Editor
• Floorplan Editor
• Hierarchy Display
MAX+PLUS II Design Entry
 MAX+PLUS II Features
‹ MAX+PLUS II, Altera’s fully integrated design environment
• Schematic, text (AHDL), waveform design entry & hierarchy display
• Floorplan editing
• DRC, logic synthesis & fitting, timing-driven compilation
• Multi-device partitioning
• Automatic error location
• Functional simulation, timing simulation, and multi-device simulation
• Timing analysis
• Programming file generation & device programming
• EDA interface : industry-standard library support, EDA design entry & output formats
(EDIF, Verilog & VHDL)
• On-line help
 Design Entry Files

MAX+PLUS II MAX+PLUS II
Symbol Editor Floorplan Editor

Verilog
MAX+PLUS II MAX+PLUS II
VHDL Graphic Editor Text Editor OrCAD

AHDL
Top- Top-level design files Synopsys,
Level can be .gdf, .tdf, .vhd, Synplicity,
Waveform File .v, .sch, or .edf Mentor Graphics,
etc...
Schematic
.gdf .wdf .tdf .vhd .v .sch .edf

Graphic Waveform Text Text Text Graphic Text

File File File File File File File

Generated within Imported from

MAX+PLUS II other EDA tools
 More on LPM Libraries
‹Library of Parameterized Modules
• Standard Library of basic and functional elements
• Based on EDIF standard
‹Advantage of LPMs
• Portability of design
• Architecture independence
‹MAX+PLUS II and LPMs
• LPM can be used in graphical design and HDL designs
• LPM can be customized via the Megawizard feature
Standard LPM without Megawizard
 Using MegaWizard Plug-In Manager
‹Click on the MegaWizard Plug-In Manager Button

Double click in
Graphic Editor Click on the
MegaWizard
Plug-In Manager
Accessing the MegaWizard

Select MegaWizard Plug-In Manager

 New vs Existing Megafunction
‹Choose between a new custom megafunction variation or an
existing megafunction variation

New Custom
Megafunction

Edit Existing
Custom
Megafunction
 Available Megafunctions & Output
File

Select a function
from the available
megafunction Select a type
of
output file

Select a
directory
and a output
file
name
Customizing the Megafunction
 Files generated by the MegaWizard

Design file implemented

in the language you selected
(.tdf, .vhd, or .v)

INC an AHDL include file

CMP a VHDL component

declaration file

SYM a Graphic design

symbol file
 Entering Customized Megafunction

Double click in
Graphic Editor

Customized megafunction appears

the same way as other symbols in
the Enter symbol window
 Make Changes to Customized
Megafunction
Double Click symbol
will bring you back
to the MegaWizard
Plug-in Manager

After the changes, MegaWizard will

over-write the source file (tdf, vhd, v),
inc file and cmp file for you.

Remember to update the symbol

in your graphic editor
 Example: Multiplier
‹ Design a multiplier with LPM_MULT
• The easiest way to create a multiplier is to use the LPM_MULT function
– Can be unsigned or signed
– Can be pipelined
– Also can create a MAC(Multiplier-Accumulator) circuit
 Example: Multiplexer
‹ Design a multiplexer with LPM_MUX
• Use WIRE primitive to rename
a bus or node
• LPM_MUX data input is a dual
range bus
 Example: RAM
‹ Design RAM circuit with LPM
• Use LPM_RAM_IO to design RAM with a single input & output port
• Use LPM_RAM_DQ to design RAM with separate input & output ports
 Example: Sequencer
‹ Design a sequencer with LPM_COUNTER & LPM_ROM
• ROM data is specified in a Memory Initialization File (.mif) or a Intel-Hex File (.hex)
• This example only sequences through 19 states so the modulus of lpm_counter is
set to 19. It uses a small section of an EAB (19 out of 256-address locations)
 Example: Bidirectional Pin
‹ Use TRI & BIDIR pin symbol
• If the TRI symbol feeds to a output or bidirectional pin, it will be implemented as tri-
state buffer in the I/O cell
 Example: Tri-State Buses - (1)
‹ Tri-state emulation
• Altera devices do not have internal tri-state buses
• MAX+PLUS II can emulate tri-state buses by using multiplexers and by routing the
bidirectional line outside of the device and then back in through another pin

MAX+PLUS II will automatically convert it into a multiplexer.

If the tri-state buffers feed a pin, a tri-state buffer will be available
after the multiplexer.
 Example: Tri-State Buses - (2)
‹ Tri-state buses for bidirectional communication
• When tri-state buses are used to multiplex signals, MAX+PLUS II will convert the
logic to a combinatorial multiplexer
• When tri-state buses are used for bidirectional communication, you can rout this
bidirectional line outside of the device, which uses the tri-states present at the I/O
pins, or you can convert the tri-state bus into a multiplexer
Example: Tri-State Buses - (3)
Rout this bidirectional line outside of the device

Tri-state emulation
 Example: Decoder
‹ Design a decoder with...
• If-Then statements SUBDESIGN priority
• Case statements (
low, middle, high : INPUT;
• Table statements highest_level[1..0] : OUTPUT;
)
• LPM function: LPM_DECODE BEGIN
IF high THEN
highest_level[] = 3;
SUBDESIGN decoder ELSIF middle THEN
( highest_level[] = 2;
code[1..0] : INPUT; ELSIF low THEN
out[3..0] : OUTPUT; highest_level[] = 1;
) ELSE
highest_level[] = 0;
BEGIN END IF;
CASE code[] IS END;
WHEN 0 => out[] = B"0001";
WHEN 1 => out[] = B"0010";
WHEN 2 => out[] = B"0100";
WHEN 3 => out[] = B"1000";
END CASE;
END;
 Example: Counter
‹ Create a counter with DFF/DFFE or LPM_COUNTER
SUBDESIGN ahdlcnt
(
clk, load, ena, clr, d[15..0] : INPUT;
q[15..0] : OUTPUT;
)
VARIABLE
count[15..0] : DFF;
BEGIN INCLUDE "lpm_counter.inc"
count[].clk = clk; SUBDESIGN lpm_cnt
count[].clrn = !clr; (
clk, load, ena, clr, d[15..0] : INPUT;
IF load THEN q[15..0] : OUTPUT;
count[].d = d[]; )
ELSIF ena THEN VARIABLE
count[].d = count[].q + 1; my_cntr: lpm_counter WITH (LPM_WIDTH=16);
ELSE BEGIN
count[].d = count[].q; my_cntr.clock = clk;
END IF; my_cntr.aload = load;
my_cntr.cnt_en = ena;
q[] = count[]; my_cntr.aclr = clr;
END; my_cntr.data[] = d[];
q[] = my_cntr.q[];
END;
 Example: Multiplier
‹ Design a multiplier with LPM_MULT
CONSTANT WIDTH = 4;
INCLUDE "lpm_mult.inc";

SUBDESIGN tmul3t
(
a[WIDTH-1..0] : INPUT;
b[WIDTH-1..0] : INPUT;
out[2*WIDTH-1..0] : OUTPUT;
)

VARIABLE
mult : lpm_mult WITH (LPM_REPRESENTATION="SIGNED",
LPM_WIDTHA=WIDTH, LPM_WIDTHB=WIDTH,
LPM_WIDTHS=WIDTH, LPM_WIDTHP=WIDTH*2);

BEGIN
mult.dataa[] = a[];
mult.datab[] = b[];
out[] = mult.result[];
END;
 Example: Multiplexer
‹ Design a multiplexer with LPM_MUX
FUNCTION lpm_mux (data[LPM_SIZE-1..0][LPM_WIDTH-1..0], sel[LPM_WIDTHS-1..0])
WITH (LPM_WIDTH, LPM_SIZE, LPM_WIDTHS, CASCADE_CHAIN)
RETURNS (result[LPM_WIDTH-1..0]);

SUBDESIGN mux
(
a[3..0], b[3..0], c[3..0], d[3..0] : INPUT;
select[1..0] : INPUT;
result[3..0] : OUTPUT;
)

BEGIN
result[3..0] = lpm_mux (a[3..0], b[3..0], c[3..0], d[3..0], select[1..0])
WITH (LPM_WIDTH=4, LPM_SIZE=4, LPM_WIDTHS=2);
END;
 Example: RAM
‹ Design RAM circuit with LPM
INCLUDE "lpm_ram_dq.inc";

SUBDESIGN ram_dq
(
clk : INPUT;
we : INPUT;
ram_data[31..0] : INPUT;
ram_add[7..0] : INPUT;
data_out[31..0] : OUTPUT;
)

BEGIN

data_out[31..0] = lpm_ram_dq (ram_data[31..0], ram_add[7..0], we, clk, clk)

WITH (LPM_WIDTH=32, LPM_WIDTHAD=8);

END;
 Example: Tri-State Buses
‹ Design tri-state buses with TRI
SUBDESIGN tribus
(
ina[7..0], inb[7..0], inc[7..0], oe_a, oe_b, oe_c, clock : INPUT;
out[7..0] : OUTPUT;
)

VARIABLE
flip[7..0] : DFF;
tri_a[7..0], tri_b[7..0], tri_c[7..0] : TRI;
mid[7..0] : TRI_STATE_NODE;

BEGIN
-- Declare the data inputs to the tri-state buses
tri_a[] = ina[]; tri_b[] = inb[]; tri_c[] = inc[];
-- Declare the output enable inputs to the tri-state buses
tri_a[].oe = oe_a; tri_b[].oe = oe_b; tri_c[].oe = oe_c;
-- Connect the outputs of the tri-state buses together
mid[] = tri_a[]; mid[] = tri_b[]; mid[] = tri_c[];
-- Feed the output pins
flip[].d = mid[]; flip[].clk = clock; out[] = flip[].q;
END;
 Example: Moore State Machine
‹ Moore state SUBDESIGN moore1
(
machine clk : INPUT;
reset : INPUT;
• The outputs of a state y : INPUT;
machine depend only z : OUTPUT;
)
the the state VARIABLE
ss: MACHINE OF BITS (z)
WITH STATES (s0 = 0, s1 = 1, s2 = 1, s3 = 0);
% current_state =
current_output%
BEGIN
ss.clk = clk;
ss.reset = reset;
TABLE
ss, y => ss;
s0, 0 => s0;
s0, 1 => S2;
s1, 0 => s0;
s1, 1 => s2;
s2, 0 => s2;
s2, 1 => s3;
s3, 0 => s3;
s3, 1 => s1;
END TABLE;
END;
 Example: Mealy State Machine
‹ Mealy state machine SUBDESIGN mealy
(
• A state machine with clk : INPUT;
reset : INPUT;
asynchronous output(s) y : INPUT;
z : OUTPUT;
)
VARIABLE
ss: MACHINE WITH STATES (s0, s1, s2, s3);
BEGIN
ss.clk = clk;
ss.reset = reset;
TABLE
ss, y => z, ss;
s0, 0 => 0, s0;
s0, 1 => 1, s1;
s1, 0 => 1, s1;
s1, 1 => 0, s2;
s2, 0 => 0, s2;
s2, 1 => 1, s3;
s3, 0 => 0, s3;
s3, 1 => 1, s0;
END TABLE;
END;
 Compiler Input and Output Files
3rd Party EDA
Design Files Mapping Files
(.edf, .sch) (.lmf)
Functional SNF
Files
(.snf)
MAX+PLUS II Compiler
MAX+PLUS II Compiler Netlist Database Logic
Extractor (includes Builder Synthesizer
Design Files all netlist readers Timing SNF
(.gdf, .tdf, .vhd, .v, Functional, Timing, Files
.wdf) or Linked SNF Partitioner Fitter
(.snf)
Assignments Extractor
(.acf) EDIF, VHDL &
Design
Verilog Netlist Assembler
Doctor
Writers
Programming
Files
(.pof, .sof, .jed)
3rd Party EDA
Simulation/Timing Files
(.edo, vo, vho, sdo)
 Compiler Input Files
‹Design files
• MAX+PLUS II
– Graphics file (.gdf), AHDL file (.tdf), VHDL file (.vhd), Verilog (.v), Wavefrom
file (.wdf)
• 3rd Party EDA Tools
– EDIF file (.edf)
• Select Vendor in EDIF Netlist Reader Settings
• Library Mapping File (.lmf) required for vendors not listed
– OrCAD file (.sch)
‹Assignment and Configuration File (.acf)
• Controls the Compiler’s synthesis and place & route operations
• Automatically generated when user enter assignments
• Automatically updated when user changes assignments or back-annotates
project
 Compiler Output Files
‹Design verification files
• MAX+PLUS II
– Simulation Netlist File (.snf)
• 3rd Party EDA Tools
– VHDL netlist file (.vho)
– EDIF netlist file (.edo)
– Verilog netlist file (.vo)
– Standard Delay Format SDF file (.sdo)
‹Programming files
• Programmer Object file (.pof)
• SRAM Object file (.sof)
• JEDEC file (.jed)
 MAX+PLUS II Compiler Window

Compiler
Output File modules

Message
Processor

To invoke MAX+PLUS II Compiler

Menu: MAX+PLUS II -> Compiler
 Compiler Modules - (1)
‹ Compiler Netlist Extractor
• The Compiler module that converts each design file in a project (or each cell of an
EDIF input file) into a separate binary CNF (Compiler Netlist File)
• The Compiler Netlist Extractor also creates a single HIF that documents the
hierarchical connections between design files
• This module contains a built-in EDIF Netlist Reader, VHDL Netlist Reader, and XNF
Netlist Reader for use with MAX+PLUS II.
• During netlist extraction, this module checks each design file for problems such as
duplicate node names, missing inputs and outputs, and outputs that are tied
together.
• If the project has been compiled before, the Compiler Netlist Extractor creates new
CNFs and a HIF only for those files that have changed since the last compilation,
unless Total Recompile (File menu) is turned on
 Compiler Modules - (2)
‹Database Builder
• The Compiler module that builds a single, fully flattened project database that
integrates all the design files in a project hierarchy
• As it creates the database, the Database Builder examines the logical completeness
and consistency of the project, and checks for boundary connectivity and syntactical
errors (e.g., a node without a source or destination)
 Compiler Modules - (3)
‹ Logic Synthesizer
• The Compiler module that synthesizes the logic in a project's design files.
• The Logic Synthesizer calculates Boolean equations for each input to a primitive
and minimizes the logic according to your specifications
• The Logic Synthesizer also synthesizes equations for flip-flops to implement state
registers of state machines
• As part of the logic minimization and optimization process, logic and nodes in the
project may be changed or removed
• Throughout logic synthesis, the Logic Synthesizer detects and reports errors such
as illegal combinatorial feedback and tri-state buffer outputs wired together ("wired
ORs")
‹ Design Doctor Utility
• The Compiler utility that checks each design file in a project for poor design
practices that may cause reliability problems when the project is implemented in one
or more devices
 Compiler Modules - (4)
‹ Partitioner
• The Compiler module that partitions the logic in a project among multiple devices
from the same device family
• Partitioning occurs if you have created two or more chips in the project's design files
or if the project cannot fit into a single device
• This module splits the database updated by the Logic Synthesizer into different
parts that correspond to each device
• A project is partitioned along logic cell boundaries, with a minimum number of pins
used for inter-device communication
 Compiler Modules - (5)
‹ Fitter
• The Compiler module that fits the logic of a project into one or more devices
• Using the database updated by the Partitioner, the Fitter matches the logic
requirements of the project with the available resources of one or more devices
• It assigns each logic function to the best logic cell location and selects appropriate
interconnection paths and pin assignments
• The Fitter module generates a “fit file”(*.fit) that documents pin, buried logic cell,
chip, clique, and device assignments made by the Fitter module in the last
successful compilation
• Regardless of whether a fit is achieved, the Fitter generates a report file(*.rpt) that
shows how the project is implemented in one or more devices
 Compiler Modules - (6)
‹ SNF(Simulation Netlist File) Extractor
• Functional SNF Extractor
– The Compiler module that creates a functional SNF containing the logic
information required for functional simulation.
– Since the functional SNF is created before logic synthesis, partitioning, and
fitting are performed, it includes all nodes in the original design files for the
project
• Timing SNF Extractor
– The Compiler module that creates a timing SNF containing the logic and timing
information required for timing simulation, delay prediction, and timing analysis
– The timing SNF describes a project as a whole. Neither timing simulation nor
functional testing is available for individual devices in a multi-device project.
• Linked SNF Extractor
– The Compiler module that creates a linked SNF containing timing and/or
functional information for several projects
– A linked SNF of a super-project combines the timing and/or functional
information for each project, allowing you to perform a board-level simulation
 Compiler Modules - (7)
‹ Netlist Writer
• EDIF Netlist Writer
– The Compiler module that creates one or more EDIF output files(*.edo). It can
also generate one or more optional SDF output files(*.sdo).
– EDIF output Files contain the logic and timing information for the optimized
project and can be used with industry-standard simulators. An EDIF Output
File is generated for each device in a project.
• Verilog Netlist Writer
– The Compiler module that creates one or more Verilog output files(*.vo). It can
also generate one or more optional SDF output files.
• VHDL Netlist Writer
– The Compiler module that creates one or more VHDL output files(*.vho). It can
also generate one or more optional VITAL-compliant SDF output files.
 Compiler Modules - (8)
‹ Assembler
• The Compiler module that creates one or more programming files for programming
or configuring the device(s) for a project
• The assembler generates one or more device programming files
– POFs and JEDEC Files are always generated
– SOFs, Hex Files, and TTFs are also generated if the project uses FLEX
devices
– You can generate additional device programming files for use in other
programming environment. For example, you can create SBF and RBF to
configure FLEX devices.
– File format:
• POF: Programming Object File
• SOF: SRAM Object File
• TTF: Tabular Text File
• HEX: Intel-format Hexadecimal File
• SBF: Serial Bitstream File
• RBF: Raw Binary File
 Compiler Processing Options
‹Functional
• Compilation generates file for Functional Simulation
– Functional SNF file (.snf)
‹Timing
• Compilation generates user selectable files for
– Timing Simulation and Timing Analysis
• Timing SNF file (.snf)
– 3rd party EDA Simulation
• Verilog file (.vo)
• VHDL file (.vho)
• SDF file (.sdo)
– Device Programming
• Altera Programmer file (e.g. .pof, .sof)
 Floorplan Editor (Read Only)
‹Last Compilation Floorplan Full Screen LAB View with
Report File Equation Viewer

Display
control
Highlighted LCELL

Fan-in and Fan-

out

LCELL
equation
 Floorplan Editor (Read Only)
‹Last Compilation Floorplan Device View

Color
Legend
definition
Pin name

Pin number
 Floorplan Editor (Editable)
‹Current Assignment view has drag and drop capability
(Note: Auto Device can not be used)

Click on Node ,hold left mouse, drag to location

Floorplan Editor (Editable)
Report File Equation Viewer
Routing Statistics
 Floorplan Editor Utilities Menu
‹ To find text, node, ...
• “Find Text” command: to search the current chip for
the first occurrence of the specified text
• “Find Node” command: to find one or more nodes or
other logic function(s) in the design file or in the
floorplan
‹ To help running timing analysis
• You can specify source and destination nodes in the
floorplan to run timing analysis

Floorplan Editor Utilities Menu

 Assigning Logic to Physical
Resources
‹ Use Floorplan Editor to assign logic to physical resources
• You can assign logic to a device, to any row or column within a device, or to a
specific LAB, pin, logic cell, or I/O cell in Floorplan Editor very easily
• To toggle between current assignment & last compilation floorplan
Menu: Layout -> Current Assignments Floorplan
Menu: Layout -> Last Compilation Floorplan
‹ Back-annotate the floorplan for subsequent compilation
• If necessary, you can back-annotate the floorplan to ACF(Assignment &
Configuration File) and it is useful for retaining the current resource and device
assignments for future compilations
Menu: Assign -> Back-Annotate Project...
Current Pin Assignment Floorplan
 Current LAB Assignment
Floorplan

Anywhere
on this
Column
Anywhere
on Device

Anywhere
on this
Row
 Project Compilation Summary
Design Simulation/
Files Timing Files

.gdf .snf

.wdf
MAX+PLUS II Compiler
.tdf Programming
Compiler Netlist Database Logic Files
Extractor (includes Builder Synthesizer
.v all netlist readers
.pof
.vhd Functional, Timing,
or Linked SNF Partitioner Fitter
Extractor
EDIF, VHDL &
Design Report
Verilog Netlist Assembler
Doctor Files
Writers
.sch

.rpt

.edf

.sdo .edo .vo .vho 3rd Party

EDA Files
 Project Verification Methodology

.snf .mif .hex .cm .vec

d

MAX+PLUS II MAX+PLUS II .scf

MAX+PLUS II
Timing Analyzer Simulator Waveform Editor

.tao .hst .sif .log .tbl .tbl

 Design Specification

Design Entry

Design Modification

Project Compilation

Command-
Simulation
Line
Mode Timing Analysis

Device Programming

In-System Verification

System Production
Create Vector Simulation Stimulus
„ Open Text Editor
„ Type in vector stimulus
– Clock % units default to ns %
START 0 ;
STOP 1000 ;
INTERVAL 100 ;
INPUTS CLOCK ;
PATTERN
0 1 ; % CLOCK ticks every 100 ns %

– Pattern INPUTS A B ;
PATTERN
0> 0 0
220> 1 0
320> 1 1
570> 0 1
720> 1 1;

– Output OUTPUTS Y1 Y0 ;
PATTERN % check output at every Clock pulse %
=XX
=00
=01
=10
= 1 1;
 Save the Vector Stimulus File
„ Save the vector stimulus file with .vec extension
– You must change the .vec extension since MAX+PLUS
II defaults to .tdf extension for text files

Change the
extension to .vec
 Simulation Input & Output Files
‹ Specify simulation input and output
files File Menu
• You can specify SCF or VEC file as the source of
simulation input vectors
Menu: File -> Inputs/Outputs...
– VEC file will be converted into SCF file by
Simulator
– You can specify a history(*.hst) or log(*.log)
file to record simulation commands and
outputs
• During and after simulation, the simulation results
are written to the SCF file, you can create
another ASCII-format table file
Menu: File -> Create Table File...
– TBL file format is a subset of VEC file
format
– A TBL file can be specified as a vector input
file for another simulation
 Memory Initialization
Initialize Menu
‹ Give memory initialization values for functional simulation
• To generate memory initialization values in Simulator
Menu: Initialize -> Initialize Memory...
• You can save the data in the Initialize Memory dialog box to a Hexadecimal File
(*.hex) or Memory Initialization File (*.mif) for future use
Menu: Initialize -> Initialize Memory... -> Export File...
– An MIF is used as an input file for memory initialization in the Compiler and
Simulator. You can also use a Hexadecimal File (.hex) to provide memory
initialization data.
• You can load the memory initialization data for a memory block that is saved in a
HEX or MIF file
Menu: Initialize -> Initialize Memory... -> Import File...
Initialize Memory Window
Memory Initialization File Formats
WIDTH = 16; :020000000000fe
DEPTH = 256; :020001000000fd
:020002000000fc
ADDRESS_RADIX = HEX; :020003000000fb
DATA_RADIX = HEX; :020004000000fa
:020005000000f9
CONTENT BEGIN :020006000000f8
0 : 0000; :020007000000f7
1 : 0000; :02000800fffff8
2 : 0000; :02000900fffff7
3 : 0000; :02000a00fffff6
4 : 0000; :02000b00fffff5
5 : 0000; :02000c00fffff4
6 : 0000; :02000d00fffff3
7 : 0000; :02000e00fffff2
8 : ffff; :02000f00fffff1
9 : ffff; ...
a : ffff; :0200ff000000ff
b : ffff; :00000001ff
c : ffff;
d : ffff; HEX file example
e : ffff;
f : ffff;
...
ff : 0000;
END;

MIF file example

 MIF File Format
‹ To edit a MIF file...
• MIF file is an ASCII text file that specifies the initial content of a memory block
– You can create an MIF in the MAX+PLUS II Text Editor or any ASCII text
editor
– You can also very easily generate an MIF by exporting data from the
Simulator's Initialize Memory dialog box
• Example:
DEPTH = 32; % Memory depth and width are required %
WIDTH = 14; % Enter a decimal number %
ADDRESS_RADIX = HEX; % Address and value radixes are optional %
DATA_RADIX = HEX; % Enter BIN, DEC, ,OCT or HEX(default) %

-- Specify values for addresses, which can be single address or range

CONTENT
BEGIN
[0..F] : 3FFF; % Range--Every address from 0 to F = 3FFF %
6 : F; % Single address--Address 6 = F %
8 : F E 5; % Range starting from specific address %
END; % Addr[8]=F, Addr[9]=E, Addr[A]=5 %
 Notes for Compiling &
Simulating RAM / ROM - (1)
‹ Remember: MAX+PLUS II Compiler uses MIF or HEX file(s) to
create ROM or RAM initialization circuit in FLEX 10K EAB
• Specify the LPM_FILE parameter to a MIF or HEX file for each RAM and ROM
block
– Memory initialization file is optional for RAM
– Using MIF files is recommended because its file format is simple
‹ If the memory initial file does not exist when MAX+PLUS II
Compiler is generating functional SNF file, you must initialize
the memory by using Initialize Memory command before
starting the functional simulation
• MAX+PLUS II Compiler reports an warning when it can’t read the memory
initialization file when processing Functional SNF Extractor
• However, the memory initialization file must exist when MAX+PLUS II processes
Timing SNF Extractor
 Notes for Compiling &
Simulating RAM / ROM - (2)
‹ If you do not have MIF or HEX files, do the following:
• Run MAX+PLUS II Compiler to generate a functional SNF file first
• Then invoke MAX+PLUS II Simulator, use Memory Initialization command to create
memory content for each ROM or RAM block
• Export memory content to a MIF or HEX file
– And now, you can perform functional simulation for your project
• Invoke MAX+PLUS II Compiler again, turn on “Timing SNF Extractor” and start
complete compilation for FLEX 10K devices
 Cut Off I/O Pin Feedback
‹Used to break bi-directional pin from the analysis
‹When on, paths A and B true C false
‹When off, path A, B and C are true

A
B
D Q D Q
C
 Run Delay Matrix Analysis
„ Select Delay Matrix Analysis and click on Start
button
„ Matrix shows all paths, longest path, or shortest
path depending on Time Restrictions option
selected
„ Use List Path to analyze the path of delays
 Setup/Hold Matrix Analysis
‹Setup/Hold Matrix calculates setup & hold times for device
flip-flops
tsetup, thold

Comb D Q

‹Setup
• tsetup = tdata - tclock + tsetup
‹Hold
• thold = tclock - tdata + thold
 Run Setup/Hold Matrix Analysis
‹Click on Start button
‹Setup/Hold times are displayed with respect to the clocks
 Saving Timing Analysis Results
‹ Save the current Timing Analyzer results to a TAO File
• Timing Analyzer can save the information in the current timing analysis display to an
ASCII-format Timing Analyzer Output file (*.tao)
Menu: File -> Save Analysis As...

Destination

y3 y4 y5
----------------- ----------------- -----------------
S aclr . . .
o clk 10.8ns 12.7ns 11.7ns
u xin1 . . .
r xin2 . . .
c xin3 . . .
e xin4 . . .
xin5 . . .
xin6 . . .
xin7 . . .
xin8 . . .
 Listing & Locating Delay Paths
‹ To trace delay paths or clock paths in the design file
• After you run a timing analysis, you can list selected signal paths and locate them in
the original design file(s) for the project
• Select the matrix cell or clock, click List Paths
• Select one of the delay paths shown in Message Processor, and click Locate to
trace the path in the source file(s)
Listing & Locating Paths