Digital Logic Design

Post Lab Task 1

Submitted To:
Dr. Sikandar Gull
Submitted By:
Ghulam Mujtaba (SP21-BSE-030)
Abubakar (SP21-BSE-005)
Ahmed Afzal (SP21-BSE-006)
Ali Hamza (SP21-BSE-010)

Date: 23rd Feb 2022

 Topic: Introduction to Basic Logic Gate ICs on Digital Logic
Trainer and Proteus Simulation

Objectives:
Students will be able to
1. Solve all types of Gates practically

2. Do Simulation on Proteus efficiently

Pre-Lab:
Before performing this Lab, students should go through the basic
concepts of Voltage, Integrated Circuits (ICs), Gates, and some intermediate know-
how of Simulation.

In-Lab:
Students have to perform the following tasks in Lab
1. Verify the gates using ICs, Breadboard, and Trainer

2. Simulate the performed tasks in Proteus

3. Bonus Question:

Perform this function in Lab and simulate it in Proteus i.e., A’B + AB’

Equipment Required:
1. Breadboard and Trainer
2. Wires and IC’s
 Lab Task 1
Steps:

1. First of all, look at the IC number written on your IC and identify whether it
is a TTL or CMOS IC.

2. Then download the datasheet of that IC from the internet. Now place the IC
on the breadboard in such a way that there is no short-circuiting.

3. Take two wires and connect one end with the switches of their respective
transistors and input pins.

4. Now take another wire and connect its one end with LEDs placed at the top
and the other end with the output pin.

5. Now give the ground connection to IC on the 7th pin and Voltage connection
to IC on the 14th pin.

6. Remember that you are providing the appropriate voltage to the respective
IC.

7. Start switching on and off the switches and record the measurements.

8. Jot down these recorded measurements in the observation table given below.

Note:
Make sure that you have taken safety precautions before performing this
lab.
 Observation Table

Inputs Outputs

A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1

Not Gate
Inputs Outputs
A A’
0 1

1 0
 Lab Task 2:
Proteus Simulation:
Here we have attached the pics and measurements given by
simulated circuits so that we can verify these simulated values with calculated
values at the end.

OR Gate
U1:A
0 1
3
2
D1
0 4071 LED-GREEN

U1:A
0 1
3
2
D1
1 4071 LED-GREEN

U1:A
1 1
3
2
D1
0 4071 LED-GREEN

U1:A
1 1
3
2
D1
0 4071 LED-GREEN

Measurement Table

A B A+B
0 0 0

0 1 1
1 0 1

1 1 1
NOR Gate

U1:A
0 1
3
2
D1
0 4001 LED-GREEN

U1:A
0 1
3
2
D1
1 4001 LED-GREEN

U1:A
1 1
3
2
D1
0 4001 LED-GREEN

U1:A
1 1
3
2
D1
1 4001 LED-GREEN

Measurement Table

A B (A + B)’
0 0 1

0 1 0

1 0 0

1 1 0
XOR Gate

U1:A
0 1
3
2
D1
0 74LS386 LED-GREEN

U1:A
0 1
3
2
D1
1 74LS386 LED-GREEN

U1:A
1 1
3
2
D1
0 74LS386 LED-GREEN

U1:A
1 1
3
2
D1
1 74LS386 LED-GREEN

Measurement Table
A B A⊕B
0 0 0

0 1 1

1 0 1

1 1 0
XNOR Gate

U1:A
0 1
3
2
D1
0 4077 LED-GREEN

U1:A
0 1
3
2
D1
1 4077 LED-GREEN

U1:A
1 1
3
2
D1
0 4077 LED-GREEN

U1:A
1 1
3
2
D1
1 4077 LED-GREEN

Measurement Table

A B (A⊕B)’
0 0 1

0 1 0

1 0 0

1 1 1
AND Gate

U1:A
0 1
3
2
D1
0 4081 LED-GREEN

U1:A
0 1
3
2
D1
1 4081 LED-GREEN

U1:A
1 1
3
2
D1
0 4081 LED-GREEN

U1:A
1 1
3
2
D1
1 4081 LED-GREEN

Measurement Table

A B A.B
0 0 0

0 1 0

1 0 0

1 1 1
NAND Gate

U1:A
0 1
3
2
D1
0 4011 LED-GREEN

U1:A
0 1
3
2
D1
1 4011 LED-GREEN

U1:A
1 1
3
2
D1
0 4011 LED-GREEN

U1:A
1 1
3
2
D1
1 4011 LED-GREEN

Measurement Table

A B (A . B)’
0 0 1

0 1 1

1 0 1

1 1 0
 Simulated Observation Table

Inputs Outputs

A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1
 Bonus Question:
Simulate A’B + B’A on Proteus.
Steps:
• Take two input signals named A and B
• Take a simple connection from B and connect it with NOT of A (which will
be called as A’)
• Now apply AND gate on A’ and B which will be qual to A’. B
• Similarly take a simple connection from A and connect it with NOT of B
(which will be called as B’)
• Apply AND gate on B’ and A which will be equal to “B’.A”
• At last take the output of “A’.B” as input 1 for an OR gate and the output of
“B’.A” as input 2 for the same OR gate.
• This will become (A’B +B’A)

Simulation:
U1
0
NOT

U3:A
1
3
2

4081

U4:A
1
3
2
U2
4071 D1
0 LED-RED

NOT U3:B
5
4
6

4081

U1
0
NOT

U3:A
1
3
2

4081

U4:A
1
3
2
U2
4071 D1
1 LED-RED

NOT U3:B
5
4
6

4081
 U1
1
NOT

U3:A
1
3
2

4081

U4:A
1
3
2
U2
4071 D1
0 LED-RED

NOT U3:B
5
4
6

4081

U1
1
NOT

U3:A
1
3
2

4081

U4:A
1
3
2
U2
4071 D1
1 LED-RED

NOT U3:B
5
4
6

4081

Measurement Table
A B A⊕B
0 0 0

0 1 1

1 0 1

1 1 0

Conclusion
After having a look at the truth table for this function it is confirmed that it is an
XOR gate
 Post Lab Questions
Make a list of logic gate ICs of the TTL family and CMOS family along with the
IC’s names. (Note: Each family should contain at least 15 IC’s)

7400 Series 4000 Series

1 7425 dual 4-input NOR gate with strobe 4011 Quad 2-input NAND Gate

2 7432 quad 2-input OR gate 4071 Quad 2-input OR Gate

3 7429 dual 4-input NOR gate 4072 Dual 4-input OR Gate

4 7415 triple 3-input AND gate 4011 Quad 2-input NAND Gate

5 7413 dual 4-input NAND gate 4012 Dual 4-input NAND Gate

6 7415 triple 3-input AND gate 4019 Quad AND/OR Select Gate

7 7409 quad 2-input AND gate 4012 Dual 4-input NAND Gate

8 7424 quad 2-input NAND gate 4023 Triple 3-input NAND Gate

9 7425 dual 4-input NOR gate 4070 Quad 2- input XOR Gate

10 7437 quad 2-input NAND gate 4068 8-input NAND Gate

11 7427 triple 3-input NOR gate 4076 Quad 2-input XOR Gate

12 7428 quad 2-input NOR gate 4071 Quad 2-input OR Gate

13 7429 dual 4-input NOR gate 4072 Dual 4-input OR Gate

14 7420dual 4-input NAND gate 4025 Triple 3-input NOR Gate

Question: What are Fan-in and Fan-out?
Answer:
Fan-In:
Fan-in is defined as the number of inputs that a logic gate can
handle at its most. Every logic gate has its own number of Fan-in e.g., a
NOT gate has a Fan-in of 1, a NAND gate has a Fan-in of 3, etc.
Fan-Out:
Fan-out is defined as the number of inputs that the output of a
logic gate can give. Max Fan-out is calculated by the following
formulas:
1. Logic =1
2. Logic = 0

Critical Analysis/Conclusion:

After performing this lab, we have analyzed how to practically implement the logic gates on
the breadboard and simulate them on Proteus. Moreover, we learned how to use Digital
Logic Trainer and its different features and how to verify our calculated values with the
simulated values of Proteus. We found this lab very helpful and beneficial and learned
beyond our expectations.