gh Need for Low Power Circuit Design, & curves of Power Dissipation - Switching Power Dissipation, Short Circuit Power Dissipation, Leakage Power Dissipation, litching Power Dissipation, Short Channel Effects -Drain Inset Pai Lowering and Punch Through, Surface Setrng, Voy Satu, Impoctlonzton, ot Electron Effect. LEARNING OBJECTIVES Need of Low power circuit design F Switching power dissipation. and Short circuit power dissipation in CMOS ct ‘F_ Expression for short circuit power dissipation in CMOS logie gates TF Leckage power dissipation, Reverse diode leakage current and Sub threshold leckage current & ‘Glitch power disipation, and concept of short channel effects \duced bairier lowering, punch through, velocity satbration, surface scattering phenomena i short-channel effect Impact fonization and hot electron effect INTRODUCTION Power consumption has been a prominent challenge in VLSI design due to decreasing feature. size’ and increasing chip, de cvetheating, lowering performance and chip If. The heed for pertable communication and computer devices has raised ity and operation frequency. The IC’s high power consumption hinders their usage in portable systems. It also causes. the need to optimize chip power consumption. Therefore, low-power design Is a vital technology in today’s semiconductor “industry, PECTRUM ALLAN-ONE JOURNAL FOR eRBINE UN STUDENTS Scanned with CamScannereen UTIONS \PART-A) SHORT QUESTIONS WITH SOL! at, Ans: What is the need of Low Power VLSI? Model Papert, aia) Power consumption has been a prominent challdhge in VLSI design due to decreasing feature size and increasing chip density and operation frequency. The IC's high power consumption hinders their usage in portable systems, It also Seuses overheating, lowering performance and chip life, ‘The need for portable communication and computer devices has raised the need to optimize chip power consumption, ‘Therefore, low-power design is a vital technology in today’s semiconductor industry, 92, What aro the sources of power dissipation in conventional CMOS digital circuits? Ans: In standardsCMOS digital circuits, dissipation can be divided into three follows: the average power types, which are ‘as 1. Dynamic (switching) power dissipation, 2. Short-circuit power dissipation, and ~ Leakage power dissipation, 4, Glitching power dissipation. This dynamic power dissi Q3. What is Glitch and Glitch power dissiy Ans: is a special case of in? Model Papert, a9 Glitch A glitch is any unwanted pulse at the output of.a digital circuit. In other words, a glitch is 4 small spike that happens at the output of a digital circuit before the output reaches its steady state, Glitch Power Dissipation Glitching power dissipation is the power consumed by “the glitches. In other'words, glitch power dissipation is the power dissipated in the intermediate transitions during the evaluation of the logic function of the circui a4. What are two most significant leakage current components observed in a MOSFET? Ans: Model Paper, 19 ‘The two most significant Jeakage current components observed in a MOSFET iransistor are, (2 WARNING: P* transistor is reversely biased, reverse | LOW POWER VLSI DESIGN [JNTU-HYDERABap, irrent 1. Reverse Diode leakage Curré eS . surent is one of the mog * Reverse diode Jeakage © she ignificant leakage current components that Contribuye Significantly to leakage power dissipation, Wheneyg, the pnjunetion between the drain and the bulk ofthe the pnsj af curs, In other words,. reverse’ saturation current jg extracted from the power supply by the reverse-biaseg dain junction. 2. Sub Threshold Leakage Current Sub-threshold current is a type of leakage current that arises in CMOS circuits. This current is produced by the diffusion of carriers between the source and drain it is in a weak inversion What are short channel effects? List five different short channel effects. a5, Ans: Model Paper, ae) Short-channel effects are a set of events that occur when the MOSFET’s channel length gets closer to the width + ‘of the space charge regions of the source and drain junctions. List of five different short channel effects are 1. Drain-induced barrier lowering and punch through 2. Surface scattering . 3. Velocity saturation 4. Impact ionization 5:__Hoteelectron effect. Q6. Whatare adverse effects caused by hot ‘caused, by hot electrons effect, An: 2 Model Paper-2, a1) A few of the adverse affects associated with hot carriet effects on MOSFET behavior encompass: A shiftin threshold voltage, reduction in transconductance, additional leakage currents, instabilities and excess roise. i Q7. What are the methods to reduce punch through effect? "Ans: Fa gitd Mo parasitic current path will form Other methods 10 reduce the effect of punch through are, use. of, spatially constrained dopant implantations, such as (@) "Halo ot pocket implantation and ©) Detta doping. LEGAL proceedings. Scanned with CamScanner_ UNIT-1 (Fundamentals) 4A NE FoR Low Power Gincurt Desicon Q8.. What is the need of Low power circuit design? : Explain. ans: ‘There has been a lot of progress in low-power design over the last few years to keep power consumption (and heat dissipation) to a minimum in very-high density VLSI chips. ‘The main driving force behind the development of high-density | VLSI chips is portable devices such as smart phones, tablets, | nash memory devices, handheld mobile telephones, personal | digital assistants (PDAs), and laptop computers. Because of the-ever-decreasing feature size and increase in chip density, power consumption has become a big issue in high-density. VLSI design. The use of integrated circuits in portable systems is constrained due to their excessive power dissipation Portable devices need very low power consumption (and dissipation) along with high chip density and high throughput. Thus, low-power digital integrated circuit design has evolved ~ asa highly active and quickly emerging field of CMOS design. In high-performance digital systems, such as micro- | processors, digital signal processors (DSPs), and other | applications, the chips have high clock frequencies. Ifthe clock | frequency of the chip increases, then the power dissipation of the chip, and thus the temperature, will increase linearly To control the temperature levels, the chips need specialized and costly packaging and cooling arrangements, which would result ina further escalation of the system cost. An alternative solution o this igsue is the use of a low-power VLSI design, f ‘Another problem that indicates the need for low- | power design is the reliability of VLSI chips. There.is indeed “a significant connection between the peak power dissipation | of digital circuits and the reliability of VLSI chips, such as ‘electron migration and hot-carrier induced device degradation. Further, the thermal stress generated by heat dissipation on the “chip is the main reliability problem. Therefore, to enhance the _reliability of VLSI chips, their power consumption is reduced sng low-power design techniques. | 4.2 Sources oF Power DissiPaTion-SwiTcHING | Power Dissipation, SHort Circuit Power Dissipation, Leakace Power DissiPATION, |» Guitciinc Power Dissipation Q9. Explain switching power dissipation in CMOS circuits. Model Paper, a3) Switching power dissipation is also known as dynamic = power dissipation. The switching power dissipation occurs _ whenever there is a switching in the output of the CMOS logic "gate. In other words, power dissipation océtirs when the output node of a CMOS logic gate makes a transition (HIGH-LOW ‘or LOW-HIGH). CMOS circuits generate dynamic power Ans: (PARTE) ESSAY QUESTIONS WITH SOLUTIONS Consider the circuit illustrated in Figure (1) that demonstrates how dynamic power dissipation occurs during switching. In this circuit, a two-input NOR gate is used to ‘operate two NAND gates, which’are connected together by interconnection lines. The total capacitive load at the output of the NOR gate is composed of three components: 1. The output capacitance of the NOR gate itself, 2. The total intercontect capacitance, and 3. > The input capacitances of the gates that are being driven. Power consuming, transition atthe output node => G, 1g NAND Gates Figure (1): NOR Gate D ‘The output capacitance of the NOR gate denoted as C,,.. is primarily made up of junction parasitic capacitances, which are formed by the drain diffusion areas of the MOS transistors in the circuit and contribute to the overall capacitance of the NOR gate, The interconnect lines that connect the gates together make contbutions tthe total interconnect capacitance and is denoted 28 Cygesaiy The input capacitances denoted as C_, are primarily caused by the gate oxide capacitances of the transistors that are linked to the input terminal. A CMOS Logie Gate in Generic Form AAs illustrated in figure (2), a CMOS logic gate that undergoes an output transition can be described by the nMOS network, pMOS network, and the total load capacitance linked to its output node. Figure (2) illustrates the generic (basic) form of a CMOS logic gate. | pmo: : PMOS | Power consuming network | transition at the : output node 7 Vou 4 ! +2C, ZC, Vu) amos et V,— network : Figure (2): Generic form of a CMOS Gate Scanned with CamScannerLSI DESIGN [JNTU-HYDERABAD) Low Eove = aveform with preferably 2éro wi ‘The average dynamic power dissipation of the CMOS los (ann ye output node (Vag) 8 Pop and chi and fall-times, can be determined by calculating the energy neede ver ines ‘the total output load cdpacitance to ground. Mathematically it is expres a Praline Sa mt Pe Af Va Ci Met} SL Co0~VYoud| Coda a . 7 = : js obtained by simplifying the integra, ‘The equation for the average dynamic power consumption in CMOS logic cite a! in equation (1), gee ab, 2 Pa™ T Coad P= Cu Vigf = ag! sf the. power supply From eqaton (3) tis lear tha, the verge dmamie power dsipaton i elated fo the save of Pees oly ‘voltage V,,. So, lowering the voltage of the power source will reduce power rity saltalio decrease power dissipation, power dissipation is exactly proportional to the load capacitance C,,,, hence lowering Cosa 10, Explain how switching power dissipation gets affected by reducing the power supply voltage Voo, Ans: : p ” The expression for dynamic power dissipation ‘P’ is given as, cz P= CueVEof , ~@) * Where, a Cas~ Total output load capacitance Vp ~ Power supply voltage Ff ~ Frequency of transitions at the output From equation (1), itis clear that, the average dynamic power dissipation is related to-the square of the power supply voltage V5, So, lowering the voltage of the power source will reduce power consumption significantly. However, the inevitable design trade-off isan inerease inthe propagation delay. This is demonstrated for the CMOS inverter circuit by inspecting the, propagation delay formula shown below. Goa 25 j A, Yoo — Yeo) Yoo — Van Ifthe power supply voltage is reduced while keeping the other variables constant, then from equation (2) it is clear that the propagation delay will increase. The graph in figure (1) illustrates the normalized variation of the propagation delay as a function of power supply voltage Vp, In this example, the threshold voltages of the nMOS and pMOS transistors are considered to be consiant with V,, and ¥,, being equal to .08V and ~ 0.8V, respectively. Similarly, the normalized variation in dynamic power dissipation as a function of the supply voltage Vis shown in the same graph, fae QD 14.0 ¢ 40 120 , . 30 =" » 10.0 z i 4 80 2 2. we e 1a i - : 2 40 ] eet a 2.0 } O Bot en 3 oe eee 0.0 eth i 0 1380 40.1509 69. gg jae padi nite "Power supply voltage V,..(V) : ~ Figure (i Normalized ‘Function of V,, 1 GMB wannins: xecournropvng oF ws wixisacriaw ct ood at LUMBLE tacean roceedings. Scanned with CamScanner: = _ UNIT-4)(Fundamentals) : The study of dynamic power dissipation described above is based on the premise that the output node of a CMOS gate - undergoes,only one power-consuming transition (0-to-,,) in every single clock eycle, But, 1 sumption may not always be right. Depending on the circuit design, logic style, and input signal characteristics, the node transition rate might be lower than the clock rate. . In order to properly describe this behavior, we shall introduce the concept of «(node transition factor), which represents the effective number of power-consuming transitions occurring in every single clock eycle. Then, the expression for average dynamic power dissipation is given as Pan = 8 Cwne V0 fee i ~@) Q11. Explain short circuit power dissipation in CMOS logic gates. ; Ans: Model Papers, 2a) : : ‘Usually, for a CMOS logic gate (with input waveforms having zero rise and fall times), when the pull-up network (PMOS transistors) is tumed OFF, the pull-down network (NMOS transistors) is turned ON and vice versa. Both the PUN and PDN are not conducted simultaneously. But, in practice, the input waveforms driving the CMOS logic gate are associated with finite rise and fall timés. As a consequence, both the pull-up and pull-down networks in the CMOS gate conduct simultaneously for a short - period of tinge during the finite slope period of inputs. This creates a direct current path between the power supply and ground, as illustrated in figure (1). The direct current path is alo known as short circuit current path and the power dissipation caused by this is known as short circuit power dissipation, = Ve. a awn T. = ¢ Input signal = with finite rise jot : and fall time 4 Lr Figure (1): Shortcircuit Current Flowing Through Both NMOS and PMOS Transistors Simultaneously ‘The short circuit current is highly dependent on the’output load capacitance as well as the rise and fall durations of the input signals. When the output load capacitance is smaller and the input signals rise and fall durations are longer, the short circuit current will be quite high. With a larger output load capacitance and reduced rise and fall duration of input signal, the short circuit _ current will be extremely low. > : ‘When a short circuit current flows through a CMOS logic gate, the energy consumed (E) per switching period and the average power consumption (P) are given by the following equations E *. Dvatbeg ss, pies . ‘ Ba Vg Ot Vag a = heV och =) Voda l= CV dof : ~@ Here, ‘t,,’ represents the time for which short-circuit current flows from V_,,, to GND. Assuming the rise and fall durations are linear, a close estimate of this time 4, P= Yo0=2,, . Yow= he , tan : © Tay Voy. 8 = ‘Where, ‘1,’ denotes the 0-100% transition time and ¢,,, indicates rise or fall time. : ‘The power consumption caused by short-circuit currents is minimized by matching the rise and fall times of the input and output "signals. In other words, atthe circuit level, the rise and fall times of al signals must be held constant within a fixed range at all times. | Q12. Defive the expression for short circuit power dissipation in CMOS logic gates. Ans: / ‘ Model Paper2, 2 _* In static CMOS circuits both the NMOS sub-network and the PMOS sub-hetwork conduct simultaneously arid a short "circuit path arises for direct current flow from Vg to the ground terminal, when, In this Vy, is threshold voltage of NMOS transistors, Vy, is the threshold voltage of PMOS transistors and Vy isthe changing input, PECTRUM ALL-IN-ONE JOURNAL FOR.ENGIN RING STUDENTS! Scanned with CamScannerow POWER VLSI DESIGN [JNTU-HYDERABAp; Le jsipation and its average vai The direet current low (from V7, to the ground terminal) produces short circuit eee i or ytitcdl fevered is given as 1, ,Vo. To obtain the expression of average sliort circuit power diss eel his makes the analysis simple. Furth, a symmetrical inverter illustrated in fighre (1) we have P= B, and V, = Vig = Wn Tal time as illustrated in figure (2) ang ‘the input signal applied to the inverter is also symmetrical that is the signals rise time = f is periodic with period 7, AVow e z Vey Von dK ttt nine Figure (1): Symmetrical Inverter Figure (2): Symmetrical Input Signal Short-cireuit Power Dissipation. 7 From figure (2), it is evident thatthe short circuit current increases from 0 to J,,, during the internal f, to f,. The NMOS is in saturation and the drain current for long channel transistor is given as, 1-$0,-1, ross 1, ‘ w(t) ‘Since it is assumed that the inverter is symmetrical, the current expressed by equation (1) reached its peak value when ¥, “> and the current waveform is symmetrical about the vertical axis (figure (2)). ‘The average short circuit current is obtained by integrating the instantaneous current as follows, 7 Ing= Ff Moat a = Q) Substituting equation (1) in equation (2), we get, 1n22 f $00 Vout ~@) ‘Since the raising and falling portions of the input waveform are linear ramps, we have, V, Va) = saat fo) At time f, the transistor starts conducting. Hence, ¥,(t,)= Vand V4) = G Vy s O. . Yn, ‘o : “@ Substituting equations (4), (5) and (6) into equation (3), we get, F Bl Yoot oo J 5 raja 0 Ha), ; Teo “ .@) ne fout quit is LABLE to face LEGAL procantnne Scanned with CamScannerUNIT:4' Fundamentals) ‘ fF ee Substituting equat nu oy += (10) es : = 1 ‘ f = 2Be Vy - Vey)? : ‘ 2B Wop Fy)” > Ine" Tih 2a = , _ 7 Therefore, the expression for average short circuit current is, . : abu pts 3 : , Ine Far Voo- Yn) Te (11) Therefore, the expression for average short circuit power dissipation P,, P= lag ¥o0 5 SPl= Ly, -2V,)° e+ (12) 12 V0 Va) : ‘4 ” __G19. Wile short notes on leakage power dissipation. Ans: Model Paper-1,03(0) -The nMOS and pMOS transistors included in every CMOS logic gate often exhibit non-zero reverse leakage and sub- | threshold currents. In a CMOS VLSI chip (that encompasses an enormous numberof transistors), these currents contribute - significantly tq the total power dissipation even though the transistors are not undergoing any switching activity. Leakage power isipation is the term used to describe the dissipation that occurs as a result of leakage currents. The leakage current magnitude is primarily affected by processing parameters. ‘The two most significant leakage current components observed in a MOSFET transistor are 1. Reverse diode leakage current -2.___ Sub threshold leakage current, Q14, Explain Reverse diodé leakage current. Ans: f Mose! Paper, aa) _ Reverse Diode Leakage Current Reverse diode leakage current is one of the most significant leakage current components that contribute significantly to diode leakage occurs. In other words, reverse saturation current is extracted from the power supply by the reverse-biased drain _ junction. For instance, take a CMOS inverter (figure 1) with.a high input voltage, by which it turns OFF the PMOS transistor and turns ON the nMOS transistor and discharges the output node voltage to zero (making the output LOW). Even if the pMOS "transistor is turned off, the reverse voltage difference of VDD between its drain and the n-well will cause diode leakage through _ its drain junction, In addition, the n-well séction of the pMOS transistor is reverse-biased relative to the p-type substrate. This “will generate another considerable leakage current component. ‘When the input to the CMOS inverter is low (equal to zero), it turns OFF the nMOS transistor, tums ON the pMOS iransistor, and charges the output node'voltage to VDD (making the output HIGH). Under these circumstances, a condition similar to the one described above may be seen. Even though the nMOS transistor is tuned off, the reverse voltage difference tween its drain and the p-type substrate will generate a reverse leakage current, which is'also pulled from the Power supply through the pMOS transistor). S2SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING svunewrs GME) Scanned with CamScannermMs transistor [aL c,., ; ON iE re] Voo, il ‘ V, tn Te at p-type substrate igure 1): Revers Leakage Current in CMOS Cireuit Figure (1): Reverse Leakage Curr ls ‘ ng the followi ‘The magnitude of the reverse leakage current of a pn-junction is evaluated using the fe ‘i " Iamma™ A641) ta J represents the reverse In this equation, V,, represents the magnitude of the reverse bias voltage aeross the junction, on saturation current density and A is the area of the junction. Usually, the magnitude of the reverse’ saturation Cron italy increases remarkably with temperature, In essence, the pn-junction reverse bias leakage current isa function of junction area and doping concentration and strongly associates with temperature. ; ‘Sub threshold leakage current. Model Paper-, 02%) Q15. Expl Ans: ‘Sub-threshold current is a type of leakage current that atises in CMOS circuits. This current is produced by the diffusion . of carriers between the source and drain regions of the transistor when it is in a weak inversion, ‘When ‘the MOS transistor is operating in the sub-threshold region, its sub-threshold current exhibits an exponential relationship with the. gate voltage. The magnitude of the sub-threshold current becomes considerable (large) when the gate-to-source voltage is lesser than and extremely close to the threshold voltage of the device. Especially in this particular sitiation, the magnitude of power dissipation caused by the sub-threshold leakage current can be equivalent to the switching (dynamic) power dissipation of the circuit. Figure (1) illustrates the sub-threshold leakage current in the CMOS circuit nMOS transistor [1 & nMOS transistor ON pie OFF | : Dove Veo Vc = L | vero fey : Le m7 eae Le Sub-threshold_p.well leakage current p-type subsirate Figure (1): Sub-threshold Curront in CMOS Circiit : "The sub-threshold curent component is very erucial ine evaluation ofthe total power dissipation when the iuit isin standby operating mode: This is because sub-threshold leakage current occurs éven though there is no svi en a ; cireut. The sub-threshold current ofa MOS transistor i exponentially related to its terminal voltages and is given as, te 8 gM E ID,Weary ol el los*Bo9) . Niecy 7 : a “To keep the sub-threshold current component urider control, one relatively simple measure is to avoid using Very low threshold voltages. This way, the V, ofthe nMOS transistor can be kept safely below, when the input is logic zero and the WV, 7, of the pMOS transistor can be kept safely below |V,, when the input is logic one, ¢ P ®{ WARNING: YoroxPiotocoping os bck 2 CRIA st von oid uty ABLE fab LEGAL proceedings J Scanned with CamScanneritch is «small spike ‘a circuit due to Ans: digitaleircuit, In other words, UNIT- | G16. Explain Glitch power dissipation | oui {As per definition, a glitch is any unwanted pulse at the at happens atthe ouput ofa digital cic before the output renches its sen es are produced in a ; opus of gate. For instance, consider the digital ercut us odin figure (1), Each val times of signals atthe inputs the difference in signal arrival times at th gale in this circuit has a unit delay, From figure (1), itis clea tat there s a differenve in the arri sihe AND gate, Because of ths, there isa glitch of | unit width inthe outpu.or the AND gs SAC AND gate reaches a steady stat, is input has multiple transitions. As a result, there Mainly due to a difference ot inequality inthe path lengths in the logic notwork. When all of a gate same time, there is no glitching. tlle igure (1) ‘This means before the output of plitch in its output, Glitches occur input signals arrive at the .s. In other words, glitch pawer dissipation is the power Tunction of the circuit, The power consumed is directly ssary transitions inerease power consumption. Glitch the chip, and even 70% in some typical cases, such as 1d in figure (2). The OR gate produces a delay of 1 unit. Glitching power dissipation is the power consumed by the glitehe: ~ dissipated inthe intermediate transitions during the evaluation of the lo proportional tothe number of transitions at the input of agate; these unnes power usually amounts to about 20% ofthe overall power consumption of the combinational adder. For instance, consider the digital circuit ilustrate a araeinat gesponse of the output contains three edges: to rsing and one falling, This ia gliteh witha combined ‘width of 2 nits, The number of edges in the transient response at the output of agate js equal to the number of areiving signals at the gate’s Jnput (number of tangitions) The maximum difference in arrival, time of signals atthe inputs of a ote is called “differential path delay” and is also the maximum width of the possible glitch at the circuit output iw : L L ap eed : . aie Figure (2) « path balancing. Due to differences in the arrival times of signals at + One of the earliest methods to reduce glitch power was p gate inputs, glitches are produced. The concept behind this approach isto avoid glitch generation by balancing the delays of the | paths so that at any specified gate inthe digital circuit, the signals arrive at ts input a the same time, This is described ivith the Felp ofthe digital circuits illustrated in figures (3) and (4). In igure (3), the signals arrive a the gates at diferent mes, causing slitches, Restructuring the circuit, as seen in Figure (4), prevents the occurrence of glitches. 0 ; py sea oe AD Figure a CHANNEL Errects— DRAIN Inouceo Barrier Lowenine ano, Puncu TurousH, SURFACE Scarteninc, ry Sarurarion, IMPACT Jonization, Hor Evectron Erect... 4 rief about the problems caused by short channel effects. * ‘Mode! Paper-2, 23(6) Le Q17. What are short channel effects? Explain in br Ans: 5 channel length gets closer to the width of Short-channel effects are a set of events that occur when the MOSF: 1 limitation is, imposed on electron drift 1¢ source and drain junctions. Under this condition, id threshold voltage is modified due to the shortening channel length. As a consequence, these polysilicon gate depletion, threshold voltage roll-off, drain-induced barrier lowering (DIBL), mobility decrease, hot cartier effects, and other disturbances. the space charge regions of the characteristics in the channel ani produce multiple problems such as ‘velocity saturation, reverse leakage current increase, SSR SPECTRUM ALLAN-ONE JOURNAL FOR ENGINEERING STUDENTS, ay Rega eD Scanned with CamScannerDESIGN [JNTU-HYDERABAD) | WER VLSI — Lown? cr Biectostate interaction bebween The reduced threshold voltage makes it hatder to totally switch off the trans! sor Fe is reduced By VelOcitY saturation, Source and drain causes the gate to become inefiient due tothe DIBL effet. The current WY A aricr mobility, |OWering ‘The power dissipation is increased by the leakage current, Increased surf vealiering rt Hesse MOSFET performangs,e8usng ‘output current. Aside from these considerations, impact ionization and hot cartier effects da : the transistor to behave differently from long-channel devices, NS Q18. Explain the “drain-induced barrier lowering” short-channel effect. pase ; in MOSFETS, It reduces the transfstor's Drs induced barier lowering (DIBL) is shor-channel phenomenon oeeurring in MONET ase needed tireshold voltage with ineeasing drain voltages. The threshold voltage ofa MOSFET is the least BAEC HT A {© generate an inversion region for conduction of charge carriers between the drain and the souree, properly biased. 7 - n'a MOSFET wit fong channel, tere exis a potential barrier between souree and drain ine i fate voltage ‘The barier is electrosttclly protected fom th drain by the conjunction ofthe substrate and eve Th Pc and ‘drain ate separated far enough in long-charnel devices that their depletion areas have little influence on the potent hence the threshold voltage is almost independent of channel length and drain voltage. : This is no longer true in short-channel devites. In short channel devices'in addition to the gate voltage, bapa ae also has a significant effect on reducing this barrier. In this drain is pretty close to control the channel formation, 328 hiph deh ‘voltage can open the barrier and switch on the transistor prematurely. The DIBL effect not only reduces threshold voltage it also increases sub-threshold current. The effect is illusrated with the help of energy band diagram in figure (1). : Model Paper, a2jy) is lowered by applying | ‘The source and Barrier lowering - Drain (2) Long Channel MOSFET (a) Short Channel MOSFET Figure (1) DIBL arises when the depletion layer of the drain comes into contact withthe source in the vicinity of the channel ‘surface to decrease the source potential barrier. When a high drain voltage is provided:to short-channel device, the barrier height is reduced, causing the threshold voltage to drop further. The source then injects carriers direetly into the channel surface, bypassing the gate as illustrated in figure (Ib). v Higher drain voltage and shorter L ,, enhances DIBL. The DIBL efféct can be reduced of mini doping toncentration, reducing oxide thickness and by performing Halo Dopiiig, Q19.. Explain the phenomena of “punch through” in short-channel effect. An: «by increasing substrate “Punch through” isa term used:to describe a phenomenon occurring in MOSFET st depletion regions of the drain and source junctions meet and create a single depletion region in to oceur. In other words, because the channel length is ini ie keeping the doping c in anid source depletion region boundaries is reduced. The voltage V, acts as a reverse bias for se io regioa’s cise in Vy, caubes the borders to be pushed farther away from the junction and closer to each Stet eeen res length is reduced, th reverse bias voltage Vg Provoke the depletion region to merge, then itis said the unch-through bs occurred. Under this condition, the current low in the channel is not regulated bythe gate voltage, but ine increases swift with an increase in the drain-source voltage V/,,(even if the gate voltage is zero, current continues t0 flow), Punch through curres! ‘mostly determined by the applied drain voltage and the depth of the source/drain junction, ‘ RIL Wahne: recumtoemng of sot 9 CANINA Aen oad ys LALE fay Lesa p iort-channel devices... When tle MOSFETs, punch through is said ‘onstant, the distance between bolt roceedings, | Scanned with CamScanner11 S value needed to trigger the punch-throwgh, it deeréases the 1 the drain voltage above the value needed to trigger 1s in the source. As a result, many of these carriers (Fundamentals) [When the reverse bias voltage Vis increased above th ° potent barre lve for the majority of cries inthe sures, An nereas é ‘h-through decreases the potential barrier for the majority of the carrier it oe Siew rons the energy barrier and penetate the substrate. The drain accumulates a few of them. Th ‘| faa reais re sab-threshold current ineredses. Moreover, punch-through provokes the sub-threshold slope fo diminisH The pani Nt ised to characterize the punch-through effect is the punich-through voltage /,,. This parameter pees al of Vg whieh + punch-through takes place with gate voltage V, = 0. Itis estimated approximately as the value of the V,,, for of drain and source depletion region is equivalent to the effective channel length as follows: Vip N(L- 0) Where, N,— Doping concentration at the bulk L— Channel length W, Junction width ‘The punch through effect may be reduced by increasing the degree of doping in the transistor body (bulk). The drain and "source depletion regions would be minimized in this case, and no parasitic current path will form. Other methods to reduce the | effect of punch through are use of spatially constrained dopant implantations, such as © (@) Halo or pocket implantations and (b)__Delta doping. ‘20. Explain in brief about velocity saturation in short-channel effect. Ans: ~ Velocity Saturation : ‘When the size of the MOS device is reduced for low power VLSI design, the electric fields within the device increase Significantly. In an effort to keep the electric field within limits, the voltages used in short-channel MOSFETs are lowered from '5 Vto about I V. However, the channel lengths have gone from 5 ym to 70 nm, and the gate oxide thickness has gone from 100 ‘nm to 1.5 nm. This clearly shows that sizes are scaled down proportionally faster than electric field reduction. Obviously, both the horizontal and vertical electric fields have increased by a lot in short-channel MOSFETs. At higher electric fields, the drift velocity of charge carriers in a semiconductor will never rise linearly with the electric field. In contrast, the velocity of charge carriers begins to level out and then reaches its saturation (maximum)'value V,,. Atroom ~ temperature, the value of saturation velocity. V, for carriers in silicon is roughly 1 x 10” em/sec. A range of models have been "used to calculate the drift velocity as a function of the electric field £. One of the most widely used is, ear 1, is the low-field electron mobility, . Ee qa) ‘Model Paper-1, 03(a) on (1) e Where, V,/ u,)is the critical field determining velocity satufation, snd : E, isthe electric field in the diréction of motion of the electrons; When applied to low fields, equation (1) accurately produces = 48 and when used for high fields, it correctly prodkicés /° The value of n is usually between 1 and 2 and is chosen to closely reflect experimental results, The value of ¥,,,. is essentially zero for relatively small values of L. This is comprehensible because it implies that the channel's velocity is saturated even at low drain voltages. The draifi current /, is then always saturated, and is approximately equal to, - Lo WC Val Ves Vs) Q). From equation (2) its evident thatthe drain current is independent of channél length L. That is, regardless of how sinall is made, the current does not grow beyond a level'as Velocity saturation limits it, performance (greater currents and speeds) in future technologies, ‘This means that decreasing L will not iricrease Scanned with CamScannerz short-shannel oe ore 4 he surface, CaUSINE Sura, tes electrons oT that of the bulk mobility, Ans: elerat a ity is nearl Surface scattering: The vertical component of the electric field #, a6°8 scattering: Due to surface scattering, mobility is reduced. The average Sut eee : == vo oy Depletion ‘at ‘ Tegion ~ $—>¥ 3 TL Figure (1) . lateral current flow. In MOSFET, ‘The following isthe physical explanation why transyerse fields cause scattering and effect late Mom) carriers travel via a thin inversion layer nearer the silicon surface (figure (1), where they are subjected to numerous Scattering ‘events with the surface, especially when itis micrascopically“rough”. When the chat m expansion of the depletion layer into the channel region, the longitudinal electric field component £, increases, and the surfece ; mobility becomes field-dependent. Because the carrier transport is confined within the narrow inversion layer, and the surface scattering (that isthe collisions suffered by the electrons that are accelerated toward the interface by £,) causes reduction of te mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for small values of E, is about half of the bulk mobility. Experiments have demonstrated that the mobility of electrons and holes in silicon rnnel length becomes smaller because of te can be expressed mathematically as, ate TF Eg)” onl) Where, E.qis an effective transverse electric field, 1, is the mobility without the transverse field effect, and vis a factor between I-and 2. The above equation has a physical origin, and can be derived using Mathiessen’s rule. If 0 represent mobility ofearies due to low transverse fields andj, represent mobility of extra scattering caused by the vertical field, Presuming thatthe latte! scattering enhances with effective field, we have, 1 1 1 1 * Lids de Licey HO Hp Be Ho = This gives us the p, equation we want. Q22. Explain about impact ionization and hot electron effect. Ans: : ‘The issue of hot electrons has continved to increase as technologies sal ‘ Mol fears cy issue of hot electrons has con logis scale down because the dimensi _ sealed down proportinally faster than voltage. This resus in higher field stengths and thinner ste en i . The High fields cause electrons lowing though the channel to gain enough energy to become er, nyo ek can cause impact ionization thts, they sik thesilison stoms (nthe dsiny and fone hen ng THe Bt generation of extra holes dislodged from the drain, This causes an increase in drain cuentas well woe ne Ot ey ade up of ionization-generate hoes tat fw towards he substrate (he transistors most nopatne cae re, produced by impact ionization éan also get heated up and be injected into insulator. ative point). Some of the ho! ‘ound gutty ABLE to Fa¢6 LEGAL proceedings. (GRRE Wann: xeon os Wok CRNA ct Scanned with CamScannerUNIT-4:(Fundamentals) ‘Another effect of hot carriers is that they may gain suflicient energy to overcome the potontial barrier at the insulatgrjnterface, and get injected into the insulator. In other words, the hot electrons enter the gate-oxide layer and will produce gate current. A schematic ofthese effects is illustrated in figure (1). ‘ont a Figura (1) The holes and electrons entering into the oxide layer cause many issues, ineluding electron and hole trapping, interface ___ State generation, and generation of bulk and “border” traps in the oxide layer. These phenomena are known as “hot carrier effects,” and they constitute a significant reliability challenge for MOSFETs. A few of the adverse affects associated with hot carrier effects on MOSFET behavior encompass: A shift in threshold voltage, reduction in transconductance, additional leakage currents, instabilities and excess noise, - » SPECTRUM ALL-IN-ONE JOURNAL FoR EuCINECOINe Orin: SANA Scanned with CamScanner neat3 ABAD) Pt GN TJNTU-HYDEI LOW POWER VLSI DESI 0) Q1. Explain switching Power dissipation in CMOS circuits. Important Quen, Ans: Refer Qo. pply voltage V,. jer su 92. Explain how switching power dissipation gets affectod by reducing the pow woes Ans: Refer Ql0. ; 93. Derive the expression for short circuit power dissipation in CMOS logic gates. ~ Important Que i Ans: Refer Q12. e “ Q4, Explain Reverse de leakage current. Ans: Refer Q14, s at aie Q5. Explain Glitch Power dissipation. Ans: Refer Q16. ii : Important Quest Q6. Explain the “drain-induced barrier lowering” short-channel effect. Ans: Refer Q18. Important Quest: Q7. Explain the Phenomena of “punch through” in short-channel effect. Ans: Refer Q19. , Important Questa Q8. Explain in’brief about velocity saturation in short-channel effect. 7 Ans: Refer Q20. Important Quest Q9. Explain surface scattering phenomena occurring in short-channel effect. ‘Ans: Refer Q21. : Important Questo 210. Explain about impact ionization and hot electron effect. Ans: Refer Q22. . : Important Quest Scanned with CamScanner