Basic Computer

System
Lesson 02

Dr. Mohammed Majid Al Khalidy

 Part one

Basic Computer System

Dr. Mohammed Majid Al Khalidy 2

The Von Neumann Computer Model

• CPU (Central Processing Unit)

• Input
• Output
• Memory

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 The invention of stored program
computers has been ascribed to a
mathematician, John von Neumann,
who was a contemporary of Mauchley
and Eckert.
 Stored-program computers have
become known as von Neumann
Architecture systems.

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 Today’s stored-program computers have the
following characteristics:
➢ Three hardware systems:
A central processing unit (CPU)
A main memory system
An I/O system
➢ The capacity to carry out sequential
instruction processing.
➢ A single data path between the CPU
and main memory.
 This single path is known as the von
Neumann bottleneck.

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Computer System

Dr. Mohammed Majid Al Khalidy 6

 Basic Computer System
Computer is a system of hardware that performs arithmetic operations,
manipulates data (usually in binary forms) and makes decisions. There are
several types of computer systems, but each can be broken down into three
elements or units, each unit performs specific function, and all units function
together to carry out the instructions given in the program, these parts are:
Central Processing Unit (CPU), memory (RAM and ROM), input/output (I/O) unit.

Address bus

I/O I/O
ROM RAM
interface devices
CPU

Data bus
Control bus

Block diagram of a basic computer system 7

Computer Basic Component:

1. CPU - Central Processing Unit

◦ the portion of a computer system that carries
out the instructions of a computer program
◦ the primary element carrying out the
computer's functions. It is the unit that reads
and executes program instructions.
◦ The data in the instruction tells the processor
what to do.

Pentium D dual core processors 8

2. Memory
◦ Physical devices used to store data or programs (sequences of
instructions) on a temporary or permanent basis for use in an
electronic digital computer.
◦ Computer main memory comes in two principal varieties: random-
access memory (RAM) and read-only memory (ROM).
◦ RAM can be read and written to anytime, the CPU commands it,
but ROM is pre-loaded with data and software that never
changes, so the CPU can only read from it.
◦ ROM is typically used to store the computer's initial start-up
instructions.
◦ In general, the contents of RAM are erased when the power to
the computer is turned off, but ROM retains its data indefinitely.
◦ In a PC, the ROM contains a specialized program called the BIOS
that orchestrates loading the computer’s Operating System OS
from the hard disk drive into RAM whenever the computer is
turned on or reset.

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The memory stores groups of binary digits (words)
that can be represent instructions (programs) that
the computer is perform and the data that are to be
operated on by the program and storage for
intermediate and final results of arithmetic
operations. The memory is connected with the
control unit for read or write operation.
Basic Operations: read/write
 LOAD
◦ read a value from a memory location
 STORE
◦ write a value to a memory location

Dr. Mohammed Majid Al Khalidy 10

Levels of memory:
• Level 1 or Register –
It is a type of memory in which data is stored and accepted that are
immediately stored in CPU. Most commonly used register is accumulator,
Program counter, address register etc.
• Level 2 or Cache memory –
It is the fastest memory which has faster access time where data is
temporarily stored for faster access.
• Level 3 or Main Memory –
It is memory on which computer works currently. It is small in size and
once power is off data no longer stays in this memory.
• Level 4 or Secondary Memory –
It is external memory which is not as fast as main memory but data stays
permanently in this memory.

Dr. Mohammed Majid Al Khalidy 11

Types of memory

Dr. Mohammed Majid Al Khalidy 12

Types of memory
1. Volatile: Read/Write information. It is not permanent and is
“flushed” if the power cuts off.
➢ RAM: Random Access Memory. It is called random because data
stored can be randomly accessed, as compared to old
memories where it was sequential. There are two types of
RAM:
▪ DRAM: The bit of information is stored as a charge on a
capacitor, which leaks charge, therefore it needs to be
pumped with a pulse to recharge it continuously, (Made
of CMOS and capacitor).
▪ SRAM: biased transistors (6 BJT’s for each bit), so it does
not require “reminding”. SRAM is used in cache and
registers.

Dr. Mohammed Majid Al Khalidy 13

2. Non-volatile: Erase/Program information. It is not lost when
power cuts off
• ROM: Read-Only Memory, it comes from the
factory, and cannot be updated. The information
contained there are permanently stored via
burning.
• PROM: like a blank CD, you can program it once,
and then it is permanently burned.
• EPROM: can be erased but requires the chip to be
placed in an ultraviolet eraser.
• EEPROM: can be erased on board, just pulsed
with electricity, no need to remove the chip.
• Hard Disk Drive.
• Flash memory.

Dr. Mohammed Majid Al Khalidy 14

There are some important definitions:

Memory cell: A device or electrical circuit used to

store a single bit (0 or 1) like flip-flop.

Memory word: A group of bits (cells) in a memory

that represents instructions or data of some type. For
example, a register consist of eight flip-flops can be
considered to be a memory that is storing 8-bit word.

Byte: A special terms used for an 8-bits.

Dr. Mohammed Majid Al Khalidy 15

Address: A number that identifies the location of a word
(data) in memory. This address represents as binary or octal,
hexadecimal or decimal number.

address words

0000
0001
0010 01101100
0011 00101001
0100
0101
0110
•
•
•
1101 01100010
1110 01111010
1111

Dr. Mohammed Majid Al Khalidy 16

Memory Capacity:
A way of specifying how many bits can be stored
in a particular memory device or a complete
memory system.
Step 1: calculate the length of the address in bits (n bits)
Step 2: calculate the number of memory locations 2^n(bits)
Step 3: take the number of memory locations and multiply it by
the Byte size of the memory cells.

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Dr. Mohammed Majid Al Khalidy 17

▪ Always remember a simple trick for address line calculation
for a specific memory capacity;
10 Address lines can access 1K of memory. if we increase only
1 address line, the memory capacity increases twice than
before.
so now 11 address lines can access 2k memory.
12 address lines - 4K memory
13 address lines - 8K memory
14 address lines - 16K memory
15 address lines - 32K memory
16 address lines - 64k memory
Dr. Mohammed Majid Al Khalidy 18
Example:
If a CPU has a 32-bit address bus, what is the maximum amount of memory it
can directly address?

We know that:
1 GB = 1024 MB
1 MB = 1024 KB
1 KB = 1024 B
1 B = 8 bits
So, 32-bit address bus has access to 2^32 locations with 8
bits(1Byte) of information.
2^32 locations =2^2 * 2^10 * 2^10 * 2^10 locations
2^32 locations =2^2 * 2^10 * 2^10 * 1024 B
2^32 locations =2^2 * 2^10 * 1024 KB
2^32 locations =2^2 * 1024 MB
2^32 locations =4 GB of location containing 8 bits (1Byte)
of information.
Therefore, 4 GB * 1 B = 4 GB information.
Dr. Mohammed Majid Al Khalidy 19
 therefore, general formula to find out ROM memory size is 2^m * n,
where m is address lines and n is data lines.

Example:

For 1M×16 memory chips, how many address lines and data lines
are required?
Since, we know that 1K = 2^10, 1M = 2^20, 1G = 2^30, ….
> 1M * 16
> 2^20 * 16
→ it means 20 address lines and 16 data lines.

Dr. Mohammed Majid Al Khalidy 20

To access the memory location:
1. Address it: give the location of this memory (which address)
2. Switch it: allow it to be read or be written to (role of control bits)
3. Transfer data: receive or send data through the data bus.

To select
a certain address
input
memory
from the If E=1 the
memory memory will
be active
system If E=0 the
memory is
disable

No. of word = 2n

n = No. of address inputs

Dr. Mohammed Majid Al Khalidy 21
Access Time: A measure of a memory devices operating
speed. Like the amount of time of real form, the memory and
write into it operations.

1. Registers: fastest level, access time = 1/3 nsec.

Maximum availablilty around 100 bytes
2. L1 Cache: access time = ½ nsec. Almost as fast as the
processor, but max = 1 MB
3. L2 Cache: 1 nsec, 4MB
4. DRAM: 50 nsec, 16 GB
5. HDD: 1 msec, 1 TB

Dr. Mohammed Majid Al Khalidy 22

 Cache (case three)
▪ Cache is a special very high-speed memory. It is used
to speed up and synchronizing with high-speed CPU,
the CPU never directly accesses RAM. Modern CPUs
have one or more layers of cache. The CPU's ability to
perform calculations is much faster than the RAM's
ability to feed data to the CPU.
▪ Cache memory is faster than the system RAM,
and it is closer to the CPU because it is on the
processor chip. The cache provides data
storage and instructions to prevent the
CPU from waiting for data to be retrieved
from RAM. When the CPU needs data—and
program instructions are also considered to be
data—the cache determines whether the data is
already in residence and provides itDr. Mohammed
to theMajidCPU.
Al Khalidy 23
Cache memory is used to reduce the average time to access
data from the Main memory. The cache is a smaller and faster
memory which stores copies of the data from frequently used
main memory locations. There are various different
independent caches in a CPU, which store instructions and data.

Dr. Mohammed Majid Al Khalidy 24

Types of Cache
Primary Cache
A primary cache (L1)is always located on the processor chip.
This cache is small and its access time is comparable to that
of processor registers.
Secondary Cache
Secondary cache is placed between the primary cache and
the rest of the memory. It is referred to as the level 2 (L2)
cache. Often, the Level 2 cache is also housed on the
processor chip.

Dr. Mohammed Majid Al Khalidy 25

▪ If the requested data is not in the cache, it's retrieved from RAM
and uses predictive algorithms to move more data from RAM
into the cache. The cache controller analyzes the requested data
and tries to predict what additional data will be needed from
RAM. It loads the anticipated data into the cache. By keeping
some data closer to the CPU in a cache that is faster than RAM,
the CPU can remain busy and not waste cycles waiting for data.
▪ Some simple CPU has three levels of cache. Levels 2 and 3 are
designed to predict what data and program instructions will be
needed next, move that data from RAM, and move it ever closer
to the CPU to be ready when needed. These cache sizes
typically range from 1 MB to 32 MB, depending upon the speed
and intended use of the processor.
▪ The Level 1 cache is closest to the CPU. There are two types of
L1 cache. L1i is the instruction cache, and L1d is the data
cache. Level 1 cache sizes typically range from 64 KB to 512
KB. Dr. Mohammed Majid Al Khalidy 26
Interface to Memory

How does processing unit (CPU) get data to/from

memory?
 MAR: Memory Address Register
 MDR: Memory Data Register M EMO RY
M
AR M
DR
 To read a location (A):
1. Write the address (A) into the MAR.
2. Send a “read” signal to the memory.
3. Read the data from MDR.
 To write a value (X) to a location (A):
1. Write the data (X) to the MDR.
2. Write the address (A) into the MAR.
3. Send a “write” signal to the memory.

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3. I/O Unit
◦ Input/output (I/O), refers to the communication
between an information processing system (such as a
computer), and the outside world possibly a human, or
another information processing system.
◦ Inputs are the signals or data received by the system,
and outputs are the signals or data sent from it
◦ Devices that provide input or output to the computer
are called peripherals
◦ On a typical personal computer, peripherals include
input devices like the keyboard and mouse, and output
devices such as the display and printer. Hard disk
drives, floppy disk drives and optical disc drives serve as
both input and output devices. Computer networking is
another form of I/O.

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4. The Bus System:
The processor has three buses which carry out all
the information and signals involved in the
system operation. These buses connect the
microprocessor to each of the memory and I/O
elements so that data and information can flow
between the µp and any of their other elements.
▪ Address bus
▪ Data bus
▪ Control bus
Dr. Mohammed Majid Al Khalidy 29
 Address bus

I/O I/O
ROM RAM
interface devices
CPU

Data bus
Control bus

Dr. Mohammed Majid Al Khalidy 30

4.1 Address bus

 The address bus is 'unidirectional', because

information flows over it in only one direction.
From the CPU to the memory or I/O
elements.
 over which the microprocessor sends an
address code to the memory or input/output.
 The size (width) of the address bus is
specified by the number of bits it can handle.
 The more bits there are in the address bus,
the more memory locations a microprocessor
can access.
 A 16 bit address bus is capable of addressing
65,536 (64K) (ex. 8085) addresses.
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4.2 Data bus

 The data bus is 'bi-directional‘, The

data can flow to or from the CPU
(read/write) µp has 8 data pins.
◦ data or instruction codes from memory or
input/output are transferred into the
microprocessor
◦ the result of an operation or computation is
sent out from the microprocessor to the
memory or input/output.
 Depending on the particular
microprocessor, the data bus can handle
8 bit or 16 bit data.
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4.3 Control bus

 The control bus is the set of signals that is

used to synchronize the activities of the
separate µc elements.
 The control bus is used by the microprocessor
to send out or receive timing and control
signals in order to coordinate and regulate its
operation and to communicate with other
devices, i.e. memory or input/output.

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 Part Two
Basic Microprocessor
Architecture

Dr. Mohammed Majid Al Khalidy 34

 Introduction to the
Microprocessor Architecture

The microprocessor consists of ALU and Register section and control

and timing section. Dr. Mohammed Majid Al Khalidy 35
Microprocessor (µp) functions :
All computers or microcomputers although they vary in their
architecture, they have one element in common the
microprocessor chip. The µp functions as a CPU of the
computer .
The µp performs a large number of functions. Including:
1-providing timing and control signals for all elements of the
computer.
2-Fetching instructions and data from memory.
3-Transferring data to and from I/O devices.
4-Decoding instructions.
5-Performing arithmetic and logic operations called for by
instructions.
6-Responding to I/O, generated control signals such as RESET
and INTERPURT. Dr. Mohammed Majid Al Khalidy 36
1. Arithmetic/Logic unit:
The ALU is the area of the processor (CPU)
in which arithmetic and logic operations are
performed on data. The type of operations
that is to be performed is determined by
signals from the control unit. The data that
are to be operated on by ALU can come
from either the memory unit or the input
unit. Results of operations performed in the
ALU can be transferred to either the
memory unit for storage or to the output
unit. Dr. Mohammed Majid Al Khalidy 38
Internal structure of ALU

2 bits of ALU 4 bits of ALU

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➢ Most modern ALUs capable of performing a wide variety of
arithmetic and logic operations.
➢ The operations can involve two operands such as the
accumulator and a data word from the memory, or the
accumulator and another µp internal register.
➢ Some of the operation involve only a single operand, such as
the accumulator, a register, or a word from memory.

Dr. Mohammed Majid Al Khalidy 40

Note that there
are two operand
inputs, only one
operand is used.
One of them
comes from the
register and the
other comes from
the memory.
Dr. Mohammed Majid Al Khalidy 41
Instruction words:
The instruction word carries two basic units of information the
op-code to be performed and the address of the operand
(Data).
Op-code 16-bit operand address

1. The single address instructions

For example: for 20-bit word it will be divided into two
parts. The first part contains 4 bits which is called the
operation code (op code) that means these are 2^4 =16
possible addresses
0100 0101101001110010
Op-code Address code

Dr. Mohammed Majid Al Khalidy 42

2. Multiple address instructions
This type contains more than one address.
The two-address instruction has the opcode plus the address
of two operand.
Address of Address of
Op-code
operand 1 operand 2

The three-address instruction has the addresses of both

operands plus the address in memory where the result is to
be stored.
Address of
Address of Address of
Op-code where to
operand 1 operand 2
store result

Dr. Mohammed Majid Al Khalidy 43

3. Multi-byte instructions:
This type of instruction contains more than one byte for two
bytes the first one for the opcode and the other for the address
operand.
For the three bytes the first one for the opcode and the two
other bytes for the two operand addresses.
The single byte instructions are for opcode and there is no
operand address but it is not efficient.
Single-byte instruction
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Two-byte instruction
Op code
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Address of operand
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Dr. Mohammed Majid Al Khalidy 44

2. Registers:
• The most common operation that tales place inside
the µp chip is the transfer of binary information
from one register to another, and it has a major
effect on the programming effort. They are used to
store data, addresses, instruction codes and
information on the status of various up operations.
• The register section/array consists completely of
circuitry used to temporarily store data or
program codes until they are sent to the ALU
or to the control section or to memory.

Dr. Mohammed Majid Al Khalidy 45

 The number of registers are different for any
particular CPU and the more register a CPU have
will result in easier programming tasks.

 Registers are normally measured by the number

of bits they can hold, for example, an "8-bit
register“, “16-bit register". or a "32-bit register".

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Anatomy of a Register

Extended Register
Word Register

Bits 16-31 Bits 8-15 Bits 0-7

High Byte Low Byte

Register Register
The most common types of registers are:
• The instruction registers (IR): This register is used to store
the opcode of the current instruction that is being fetched
and executed.
• The program counter (PC) : It is always containing the
address in memory of the next instruction that the CPU is
to fetch.
• Memory address register (MAR): It is used to hold the
address of data the CPU is reading from or writ into
memory.
• Accumulator A: It is a register that takes part in most of
the operations performed by the ALU and it’s the place
where the results are placed after most ALU operations.
Dr. Mohammed Majid Al Khalidy 48
• General purpose registers: These registers are used for many
of the temporary storage functions required inside the CPU
(like: BC, DE, and HL in 8085 µp). They can be used to store
data that are used frequently during a program also it is used
as a counter.
• Index registers: They are like general purpose registers, in
addition it takes part in determining the address of data that
the CPU is accessing.
• The status registers: Also referred to as a condition register it
consists of individual bits with different meanings. These bits
are called flags.
• The stack pointer register (SP): The stack is apportion of RAM
reserved for the temporary storage and retrieval of information
The stack pointer register acts as a special memory address
register used only for the stack portion of RAM .
Dr. Mohammed Majid Al Khalidy 49
Example: The 8088/8086…Registers

AX
16-bit register
AH AL
8-bit reg. 8-bit reg.

Category Bits Register Names

General 16 AX, BX, CX, DX
8 AH, AL, BH, BL, CH, CL, DH, DL
Pointer 16 SP (stack pointer), BP (base pointer)
Index 16 SI (source index), DI (destination index)
Segment 16 CS (code segment), DS (data segment)
SS (stack segment), ES (extra segment)
Instruction 16 IP (instruction pointer)
Flag 16 FR (flag register)
Example: Register in motorola 68000 microprocessor
31 16 15 8 7 0
D0
D1
D2
D3 DATA REGISTERS
D4
D5
D6
D7
31 16 15 8 7 0
A0
A1
A2
A3 ADDRESS REGISTERS
A4
A5
A6
A7

USER STACK POINTER

A7 STACK POINTER
SUPERVISOR STACK POINTER

PC PROGRAM CONTER
15 8 7 0
SYSTEM BYTE USER VYTE SR STATUS REGISTER 51
➢ Accumulator: A
 a register in which intermediate arithmetic
and logic results are stored.
 In most cases it is implicit source operand,
and implicit destination (like, ADD C ; add C
with A and stor the result in A).
 example for accumulator use is summing a
list of numbers.
◦ The accumulator is initially set to zero, then each
number in turn is added to the value in the
accumulator.
◦ Only when all numbers have been added is the
result held in the accumulator written to main
memory or to another, non-accumulator, CPU
register.

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➢ Condition code register (CCR)

 an 8 bit register used to store the

status of CPU, such as carry, zero,
overflow and half carry.

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➢ Flag Register
The Flag register is a Special Purpose Register and is completely different
from the other registers in a microprocessor. It consists of 8 bits and only 5 of
them are useful in 8085. The other 3 are left vacant and are in the future Intel
versions. Therefore, 8085 has five flags - Sign flag, Zero flag, Auxillary
carry flag, Parity flag and the Carry flag.

PIC : - BIT POSITIONS OF VARIOUS FLAGS IN A FLAG REGISTER OF 8085

The flag acts like a Status Register which provides the status of the ALU
operations performed in the microprocessor. It means that the information
stored in the accumulator is provided to the programmer via the flag
register and this is the main function of the flag.
Dr. Mohammed Majid Al Khalidy 54
1. SIGN FLAG
Sign flag occupies the 7th bit of the flag register which is also known as the
Most Significant Bit ( MSB ). It helps the programmer to know whether the
number stored in the accumulator is positive or negative. According to the
logic of flag, ‘1’(binary number) signifies that the flag is set whereas ‘0’ means
the flag is reset. Now if the sign flag is set(1), it means that the number
stored in the accumulator is negative and if reset(0), the number is positive.

2. ZERO FLAG

Zero flag occupies the 6th bit of the flag register. It is set(1) when the
operation performed in the ALU ( Arithmetic and Logic unit ) results in 0 and
is reset(0) when the result is not zero.

Dr. Mohammed Majid Al Khalidy 55

3. AUXILIARY CARRY FLAG

It occupies the 4th bit of the flag register. In an arithmetic operation, when
the carry is generated by the 3rd bit and is passed on to the 4th bit,
Auxillary Carry flag is set(1). If not, flag is reset(0). This flag is used only for
BCD( Binary Coded Decimal) operations.

Example of binary addition in which auxiliary carry is generated.

Dr. Mohammed Majid Al Khalidy 56

4. PARITY FLAG

2nd bit of flag register. This flag tests for number of 1 bits in the
accumulator(final result). If the accumulator holds even number of 1’s , even
parity exists and the flag bit is set(1). On the other hand, if the number of 1’s is
odd, parity is odd and the flag is reset(0).

5. CARRY FLAG

0th bit of the flag register. Also known as the Least Significant bit( LSB ). If the
arithmetic operation finally results in a carry, carry flag is set(1). Else, it is
reset(0).

Dr. Mohammed Majid Al Khalidy 57

 Example
Let’s assume the value of the flag register to be 35 H, i.e. 0011 0101

Now let’s check what each bit means. Refer the above explanations
simultaneously to connect them with these examples.

• 7th bit is reset(0), which means number stored in the accumulator is positive.
• 6th bit is also reset(0), thus result of the operations performed in the ALU is
non-zero.
• 4th bit is set(1). Therefore, Auxillary carry is generated in the operations
performed in the ALU operation.
• 2nd bit is set(1). It means that even parity exists,i.e. accumulator holds even
number of 1s.
• 0th bit is set(1), which means carry flag is generated in the arithmetic
operation.
Dr. Mohammed Majid Al Khalidy 58
Flag Name Description
Indicates that the result of a mathematical or logical operation
Z Zero flag
was zero.

Indicates that the result of an operation produced an answer

greater than the number of available bits. (This flag may also
C Carry flag
be set before a mathematical operation as an extra operand to
certain instructions, e.g. "add with carry".)

Masks the XIRQ request when set. It is set by the hardware

X Extend flag and cleared by the software as well is set by unmaskable
XIRQ.

Indicates that the result of a mathematical operation is

negative. In some processors, the N and S flags have different
N Negative/ Sign flag meanings: the S flag indicates whether a subtraction or
addition has taken place, whereas the N flag indicates
whether the last operation result is positive or negative.

Indicates that the result of an operation has overflowed

V Overflow Flag according to the CPU's word representation, similar to the
carry flag but for signed operations.

Interrupts can be enabled or disabled by respectively setting

I interrupts or clearing this flag. Modifying this flag may be restricted to
programs executing in supervisor mode
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➢ Program counter (PC)
 a 16 bit register, used to store the next
address of the operation code (instruction) to
be fetched (excuted) by the CPU.
 Not much use in programming, but as an
indicator to user only.
 Purpose of PC in a Microprocessor:
◦ to store address of top (top of stack)
◦ to store address of next instruction to be
executed.
◦ count the number of instructions.
◦ to store base address of the stack.

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➢ Stack pointer (SP)
 Used as memory pointer. It points to the
memory location called stack. Generally stack is
a reserved portion of memory where
information can be stores or taken back
together.
 The stack is configured as a data structure that
grows downward from high memory to low
memory. (first in last out)
 At any given time, the SP holds the 16-bit
address of the next free location in the stack.
 The stack acts like any other stack when there
is a subroutine call or on an interrupt. ie.
pushing the return address on a jump, and
retrieving it after the operation is complete to
come back to its original location.

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➢ Buffers
▪ Used to isolate the weak internal busses from the
external busses.
▪ They are important because of loading effects, which
happens when there isn’t enough output current to drive
another unit.
▪ Buffers in μP’s are amplifiers that amplify the current so
that the μP can drive many loads.
▪ There are two types of buffers:
• Address buffers
• Data buffers, that of two types:
Internal Data Buffer and External Data Buffer.
Alternatively, only one data buffer can be used.
Dr. Mohammed Majid Al Khalidy 62
3. Timing and Control section:
The major function of this µp section is to
fetch and decode instructions from program
memory and then to generate the necessary
control signals required by the ALU and
register section for executing these
instructions.

Dr. Mohammed Majid Al Khalidy 63

Control Unit:

It directs the operation of all the other units by

providing timing and control signals. The control unit
is like the conductor of an orchestra members.
The control unit fetching an instruction from memory
by sending an address and read command to the
memory unit.

Dr. Mohammed Majid Al Khalidy 64

Dr. Mohammed Majid Al Khalidy 65
Dr. Mohammed Majid Al Khalidy 66
Example how execution of the program
CONTROL UNIT
PC IR

 Instruction Register (IR) contains the current

instruction.
 Program Counter (PC) contains the address of
the next instruction to be executed.
 Control unit:
◦ reads an instruction from memory
 the instruction’s address is in the PC
◦ interprets the instruction, generating signals
that tell the other components what to do
 an instruction may take many machine cycles to complete
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Control bus signals
The control section also generates external control
signals that are sent to other computer elements as
part of the system control bus. The µp-control
section also responds to control bus signals that are
sent from other computer elements to the µp chip.

R/w’ : This µp output informs the computer to be in

Read or Write operation.

R/W’ = 1 READ
R/W’ = 0 WRITE
Dr. Mohammed Majid Al Khalidy 68
RESET (RES)’: When this input is active. Most of the microprocessor
internal registers are reset to 0.

Dr. Mohammed Majid Al Khalidy 69

MREQ (memory request): This µp output
indicate that memory access is in progress.

IORQ (I/O request): A µp output which indicates

that an I/O device is being accessed. Some µps
use this signal along with MREQ to distinguish
between memory and I/O operations. This
allows memory and I/O to use the same
addresses because the IORQ and MREQ signals
determine which one (I/O, or memory) is
enabled.

Dr. Mohammed Majid Al Khalidy 70

READY: This µp input is used by slow memory and I/o devices
which cannot respond to a up access request, when the slow
device is selected by the address decoder circuit it immediately
sends a READY signal to the up.

INT or IRQ (Interrupt Request ) : This is a up input used by I/O

devices to interrupt the execution of the current program and
cause the up jump to a special program. Called the interrupt
service routine.
INTE (Interrupt Enable) : This is a up output that indicates to
external device whether or not the internal up interrupt logic is
enable or disable.
NMI ( Non-Maskable Interrupt ): This is another up interrupt
input but it differ from INT that its effect cannot be disable.
Dr. Mohammed Majid Al Khalidy 71
Microprocessor based Interface
Microprocessor can be interfaced with the peripherals via
several techniques:

➢ Memory space interface.

➢ I/O ports interface such as serial and parallel ports.
➢ Direct/internal bus interface using internal buses such as ISA,
EISA, PCI, AGP, USB, SATA, IDE, SCSI.
➢ Indirect/external bus interface using external buses such as
GPIB, CAMAC, CAN, etc.

72
 Motherboard

Microprocessor Internal External

Bus Bus Peripheral

Indirect bus interface

Peripheral

Direct bus interface

Bus Interface (Direct-Indirect)

73
Dynamic Power

P 
dyn k
iCiVAif
2

i
units
 Static CMOS: current flows when active
◦ Combinational logic evaluates new inputs
◦ Flip-flop, latch captures new value (clock edge)
 Terms
◦ C: capacitance of circuit
 wire length, number and size of transistors
◦ V: supply voltage
◦ A: activity factor
◦ f: frequency
 Future: Fundamentally power-constrained
Iron Law
Time
Processor Performance = ---------------
Program

Instructions Cycles Time

= X X
Program Instruction Cycle
(code size) (CPI) (cycle time)

Architecture --> Implementation --> Realization

Compiler Designer Processor Designer Chip Designer

75
Computer Performance
 CPU operates on data. If no data, CPU has to
wait; performance degrades.
◦ typical workstation: 3.2GHz CPU, Memory
667MHz. Memory 5 times slower.
◦ Moore’s law: CPU speed doubles every 18
months
◦ Memory speed increases much much slower;
 Fast CPU requires sufficiently fast memory.
 Rule of thumb: Memory size in GB=R_theor in
GFLOPS
◦ 1CPU cycle (1 FLOPS) handles 1 byte of data
◦ 1MFLOPS needs 1MB of data/memory
◦ 1GFLOPS needs 1GB of data/memory
Many “tricks” designed for performance improvement
targets the memory 76
CPU Performance
 Computer time is measured in terms of
CPU cycles
◦ Minimum time to execute 1 instruction is 1 CPU
cycle
 Time to execute a given program:
nc
T = nc  tc = ni   tc = ni  CPI  tc
ni
n_c: total number of CPU cycles
n_i: total number of instructions
CPI = n_c/n_i, average cycles per instruction
t_c: cycle time, 1GHz → t_c=1/(10^9Hz) = 10^(-9)sec = 1ns
77
To Make a Program/Computer
Faster…
 Reduce cycle time t_c:
◦ Increase clock frequency; however, there is a physical
limit
◦ In 1ns, light travels 30cm
◦ Currently ~ GHz; 3GHz cpu → light travels 10cm within 1
cpu cycle → length/size must be < 10cm.
◦ 1 atom about 0.2 nm;
 Reduce number of instructions n_i:
◦ More efficient algorithms
◦ Better compilers
 Reduce CPI -- The key is parallelism.
◦ Instruction-level parallelism. Pipelining technology
◦ Internal parallelism, multiple functional units; superscalar
processors; multi-core processors
◦ External parallelism, multiple CPUs, parallel machine
78