Semester : 06 Course code : C342 EC8095 – VLSI DESIGN

COURSE OUTCOMES (CO)

Upon completion of the course, the students will be able to

C342.1 Demonstrate the concepts of digital building blocks using MOS transistor.

C342.2 Design combinational MOS circuits and power strategies.

C342.3 Design and construct Sequential Circuits and Timing systems.
Design arithmetic building blocks and memory subsystems.
C342.4

C342.5 Apply and implement FPGA design flow and testing.

CORRELATION OF COURSE OUTCOMES (CO) WITH PROGRAM OUTCOMES (PO) AND PROGRAM
SPECIFIC OUTCOMES (PSO)

PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO

3 2 2 2 1 - - - - - - - 3 1
C342.1

3 2 2 2 1 - - - - - - - 3 1
C342.2

3 2 2 2 1 - - - - - - - 3 1
C342.3
 3 2 2 2 1 - - - - - - - 3 1
C342.4

3 2 2 2 1 - - - - - - - 3 1
C342.5

‘3’ – HIGH
‘2’ – MODERATE
‘1’ – LOW
‘-‘ – NO CORRELATION

JUSTIFICATION

COURSE PROGRAM CORRELATION COMMENTS

OUTCOMES OUTCOMES LEVEL

HIGH Engineering Knowledge is Highly Correlated with the fundamentals of

PO1 CMOS Circuits and its Characteristics.

C342.1 Problem Analysis is Moderately correlated to realize the concepts of

MODERATE
PO2 digital building blocks using MOS transistor.
 COURSE PROGRAM CORRELATION COMMENTS
OUTCOMES OUTCOMES LEVEL

MODERATE Design system is moderately correlated to meet CMOS process

PO3 technology.

MODERATE Conduct investigations of complex problems is moderately correlated

PO4 with the fundamentals of CMOS Circuits and its Characteristics.

LOW Modern tool usage is less correlated for engineering practice.

PO5
- -
PO6
-
PO7 -

-
PO8 -

-
PO9 -

- -
PO10
- -
PO11
- -
PO12

HIGH Engineering Knowledge is Highly Correlated to learn the design and

PO1 realization of combinational digital circuits.
C342.2
 COURSE PROGRAM CORRELATION COMMENTS
OUTCOMES OUTCOMES LEVEL

MODERATE Problem Analysis is Moderately correlated with combinational MOS

PO2 circuits and power strategies.

MODERATE Design system is moderately correlated with the realization of

PO3 combinational digital circuits.

MODERATE Conduct investigations of complex problem is moderately correlated

PO4 with the combinational MOS circuits and power strategies.

LOW Modern tool usage is less correlated with design and realization of
PO5 combinational digital circuits.

- -
PO6
- -
PO7
- -
PO8
- -
PO9
- -
PO10
- -
PO11
- -
PO12
 COURSE PROGRAM CORRELATION COMMENTS
OUTCOMES OUTCOMES LEVEL

HIGH Engineering Knowledge is Highly Correlated to learn the design and

PO1 realization of sequential digital circuits.

MODERATE Problem Analysis is Moderately correlated with Sequential MOS

PO2 circuits and timing systems.

MODERATE Design system is moderately correlated with the realization of

PO3 sequencial digital circuits.

MODERATE Conduct investigations of complex problem is moderately correlated

PO4 with the sequential MOS circuits and timing systems.

LOW Modern tool usage is less correlated with design and realization of
PO5 sequential digital circuits.
C342.3
- -
PO6
- -
PO7
- -
PO8
- -
PO9
- -
PO10
- -
PO11
 COURSE PROGRAM CORRELATION COMMENTS
OUTCOMES OUTCOMES LEVEL

- -
PO12
Engineering Knowledge is Highly Correlated with architectural
HIGH choices and performance tradeoffs involved in designing and realizing
PO1
the circuits in CMOS technology.

MODERATE Problem Analysis is Moderately correlated with arithmetic building

PO2 blocks and memory subsystems.

MODERATE Design system is moderately correlated with the architectural choices

and performance tradeoffs involved in designing and realizing the
PO3
circuits in CMOS technology.

MODERATE Conduct investigations of complex problem is moderately correlated

PO4 with the arithmetic building blocks and memory subsystems.
C342.4
Modern tool usage is less correlated with architectural choices and
LOW performance tradeoffs involved in designing and realizing the circuits in
PO5
CMOS technology.

- -
PO6
- -
PO7
- -
PO8
 COURSE PROGRAM CORRELATION COMMENTS
OUTCOMES OUTCOMES LEVEL

- -
PO9
- -
PO10
- -
PO11
- -
PO12

HIGH Engineering Knowledge is Highly Correlated to apply and implement

PO1 FPGA Design flow and testing.

MODERATE Problem Analysis is Moderately correlated to learn the different FPGA

PO2 architectures and testability of VLSI Circuits.

MODERATE Design system is moderately correlated with apply and implement

PO3 FPGA Design flow and testing.

MODERATE Conduct investigations of complex problem is moderately correlated to

C342.5 PO4 learn the different FPGA architectures and testability of VLSI Circuits.

LOW Modern tool usage is less correlated with apply and implement FPGA
PO5 Design flow and testing.

- -
PO6
- -
PO7
 COURSE PROGRAM CORRELATION COMMENTS
OUTCOMES OUTCOMES LEVEL

- -
PO8
- -
PO9
- -
PO10
- -
PO11
- -
PO12

Prepared by : Mr. K. Srinivasan Verified by: Ms. M. Methini