1.

ARCHITECTURE OF 8086

Internal architecture of Intel 8086:

Intel 8086 is a 16 bit integer processor. It has 16-bit data bus and 20-bit address bus.
The lower 16- bit address lines and 16-bit data lines are multiplexed (AD0-AD15). Since 20-
bit address lines are available, 8086 can access up to 220 or 1 Mega byte of physical memory.

The basic architecture of 8086 is shown below.

The internal architecture of Intel 8086 is divided into two units, viz., Bus Interface
Unit (BIU) and Execution Unit (EU).

Bus Interface Unit (BIU)

The Bus Interface Unit (BIU) generates the 20-bit physical memory address and
provides the interface with external memory (ROM/RAM). As mentioned earlier, 8086 has a
single memory interface. To speed up the execution, 6-bytes of instruction are fetched in
advance and kept in a 6- byte Instruction Queue while other instructions are being
executed in the Execution Unit (EU). Hence after the execution of an instruction, the
next instruction is directly fetched from the instruction queue without having to wait for
the external memory to send the instruction. This is called pipe-lining and is helpful for
speeding up the overall execution process.

8086's BIU produces the 20-bit physical memory address by combining a 16-bit
segment address with a 16-bit offset address. There are four 16-bit segment registers, viz.,
the code segment (CS) register, the stack segment (SS) register, the extra segment (ES)
register, and the data segment (DS) register. These segment registers indicate starting
address or base address of corresponding segments. A segment address is the upper 16-bits
of the starting address of that segment. The lower 4-bits of the starting address of a segment is
always zero. The offset address is held by another 16-bit register. The physical 20-bit
address is calculated by shifting the segment address 4-bit left and then adding that to the
offset address.

Instruction Pointer (IP) is a register used as offset address for Code Segment.

 It is a 16 bit register. It holds offset of the next instructions in the Code Segment.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch instruction occurs.
 CS is multiplied by 10H to give the 20 bit physical address of the Code Segment.
 Address of the next instruction is calculated as CS×10H + IP.

1
Figure 3.1:8086 Architecture

2
Most of the registers contain data/instruction offsets within 64 KB memory segment. There
are four different 64 KB segments for instructions, stack, data and extra data. To specify
where in 1 MB of processor memory these 4 segments are located the processor uses four
segment registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program
stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and
base pointer (BP) registers is located in the stack segment. SS register can be changed directly
using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program
data. By default, the processor assumes that all data referenced by general registers (AX, BX,
CX, DX) and index register (SI, DI) is located in the data segment. DS register can be
changed directly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the ES
segment in string manipulation instructions. ES register can be changed directly using POP
and LES instructions.

It is possible to change default segments used by general and index registers by prefixing
instructions with a CS, SS, DS or ES prefix.

3
Execution Unit:

All general registers of the 8086 microprocessor can be used for arithmetic and logic
operations.

The general registers are:

Accumulator (AX) register consists of 2 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the low-order byte of the
word, and AH contains the high-order byte. Accumulator can be used for I/O operations and
string manipulation.

Base (BX) register consists of 2 8-bit registers BL and BH, which can be combined together
and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and
BH contains the high-order byte. BX register usually contains a data pointer used for based,
based indexed or register indirect addressing.

Count (CX) register consists of 2 8-bit registers CL and CH, which can be combined together
and used as a 16-bit register CX. When combined, CL register contains the low-order byte of
the word, and CH contains the high-order byte. Count register can be used as a counter in
string manipulation and shift/rotate instructions.

Data (DX) register consists of 2 8-bit registers DL and DH, which can be combined together
and used as a 16-bit register DX. When combined, DL register contains the low-order byte of
the word, and DH contains the high-order byte. Data register can be used as a port number in
I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-
order word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register is used to hold the offset address of the data stored at
the top of the stack segment. SP is used along with the SS register to decide the address at
which the data is to be pushed or popped, during the execution of PUSH or POP instruction.

Base Pointer (BP) is a 16-bit register used to hold the offset address of the data to be read
from or written into the stack segment.

Source Index (SI) is a 16-bit register used to hold the offset address of the source data in the
data segment, while executing string instructions.

Destination Index (DI) is a 16-bit register used to hold the offset address of the destination
data in the extra segment, while executing string instructions.

Here, the term segment refers to the portion of the memory where the data, code or stack for a
program is stored. In the 8086, the maximum size of a segment can be 64 KB.

4
ACCESSING MEMORY LOCATIONS

Each address in the physical memory (ROM/EPROM) is called a physical address. To access
an operand (either data or instruction) from a particular segment of the memory, the 8086 has
to first calculate the physical address of that operand. To accomplish this task, the 8086 adds
the base address of the corresponding segment with an offset address, which may be the
content of a register, an 8-bit or 16-bit displacement given in the instruction, or a combination
of both, depending upon the addressing mode used by the instruction. The designers of the
8086 have assigned certain register(s) as default offset register(s) for the segment registers, as
shown in following Table. However, this default assignment can be changed by using the
segment override prefix in the instruction

.
Segment Registers Default offset registers
CS IP
DS BX, SI, DI, 8-bit or 16-bit displacement
SS SP and BP
ES DI for string instructions

Example:

Code segment Register CS holds the segment address which is 4569 H Instruction
pointer IP holds the offset address which is 10A0 H The physical 20-bit address is
calculated as follows

Segment address: 45690 H

Offset address: + 10A0 H
Physical address: 46730 H

5
Flags is a 16-bit register containing 9 flags:

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

X X X X OF DF IF TF SF ZF X AF X PF X CF

 Overflow Flag (OF) - set if the result is too large positive number, or is too small
negative number to fit into destination operand.
 Direction Flag (DF) – DF selects either the increment or decrement mode for the DI
and/or SI register, during the execution of string instructions. If D=0, the registers are
automatically incremented; if D=1, the registers are automatically decremented.
 Interrupt-enable Flag (IF) – IF controls the operation of the INTR interrupt pin of
the 8086. If IF=0, the INTR pin is disabled and if IF=1, the INTR pin is enabled.
 Trap Flag (TF) – TF is used to debug a program using the single-step technique. If it
is set (i.e. TF = 1), the 8086 gets interrupted (trap or single-step interrupt) after the
execution of each instruction in the program. If TF is cleared (i.e. TF=0), the trapping
or debugging feature is disabled.
 Sign Flag (SF) - set if the most significant bit of the result is set.
 Zero Flag (ZF) - set if the result is zero.
 Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the
AL register.
 Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the
result is even.
 Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit
during last result calculation.

6
2. PIN DETAILS OF 8086

The 8086 can operate in any one of the following two modes – minimum mode and
maximum mode. In the minimum mode, all the control signals for the memory and I/O are
generated by the 8086. In the maximum mode, some control signals must be externally
generated. This requires the addition of an external bus controller such as the 8288 to the
8086. Some pins in the 8086 have the same function in both modes; other pins have different
functions.

7
Functions of Pins Common to Minimum and Maximum Modes:

 AD15-AD0 - ADDRESS DATA BUS: These lines constitute the time multiplexed
address and data bus. Whenever the ALE (Address Latch Enable) pin is high (i.e. 1),
these pins carry the address, and when the ALE pin is low (i.e. 0), these pins carry
data.

 A19/S6, A18/S5, A17/S4, A16/S3 - ADDRESS/STATUS: These pins are multiplexed

to provide the address signals A19-A16 and the status bits S6-S3. Whenever the ALE
(Address Latch Enable) pin is high (i.e. 1), these pins carry the address, and when the
ALE pin is low (i.e. 0), these pins carry status lines. S3 and S4 indicate the segment
accessed by the 8086 during the current bus cycle. He status bit S5 indicates the
condition of the IF flag bit. S6 always remains at logic 0.

S4 S3 Segment Accessed
0 0 Extra Segment
0 1 Stack Segment
1 0 Code Segment or no segment
1 1 Data segment

 NMI - NON-MASKABLE INTERRUPT a positive edge triggered input which causes

a type 2 interrupt. It is a hardware interrupt. A subroutine is vectored to via an
interrupt vector lookup table located in system memory. NMI cannot be maskable or
disabled by software. A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally synchronized.

 INTR - INTERRUPT REQUEST: is a level triggered input which is sampled during

the last clock cycle of each instruction to determine if the processor should enter into
an interrupt acknowledge operation. It is a hardware interrupt. A subroutine is
vectored to via an interrupt vector lookup table located in system memory. It can be
internally masked by software by resetting the interrupt enable bit. INTR is internally
synchronized. This signal is active HIGH.

 CLK - CLOCK: The maximum frequency can be 5, 8 and 10 MHz for different
versions of the 8086.

 RD′ - READ: Whenever the Read signal (RD′) is at logic 0, the 8086 reads the data
from the memory or I/O device through the data bus.

 RESET - RESET: This input causes the 8086 to reset, if it is held at logic 1 for a
minimum of four clocking periods. It causes the processor to immediately terminate
its present activity.

 BHE′/S7 - BUS HIGH ENABLE/STATUS: This signal is used to enable most

significant data bus, pins D15-D8 during a read/write operation. The state of the status
line S7 is always logic 1.

8
  TEST′ - TEST: The TEST′ pin is an input that is tested by the WAIT instruction. If
this pin is at logic 0, the WAIT instruction functions as a NOP (no operation)
instruction. If this pin is at logic 1, the WAIT instruction waits for the TEST′ pin to
become logic 0. This pin is often connected to the BUSY pin of the 8087 (numeric
coprocessor) to perform floating-point operations.

 READY - READY: This input is used to insert wait states into the timing cycle of the
8086. If the READY pin is at logic 1, it has no effect on the operation of the
microprocessor. If it is at logic 0, the 8086 enters the wait state and remains idle. This
pin is used to interface the slowly operating peripherals with the 8086.

 MN/MX′ - MINIMUM/MAXIMUM: This pin indicates what mode the processor is

to operate in. When MN/MX′ is high the CPU operates in the minimum mode. When
MN/MX′ is low the CPU operates in the maximum mode.

 VCC: This power supply pin provides a +5 V signal to the 8086.

 GND: The GND connection is the return for the power supply (Vcc). The 8086 has
two GND pins and both must be connected to ground for proper operation

The two modes are discussed in the following sections.

Operating Modes of 8086

There are two modes of operation for Intel 8086, namely the minimum mode and the
maximum mode. When only one 8086 CPU is to be used in a microcomputer system the 8086
is used in the minimum mode of operation. In this mode the CPU issues the control signals
required by memory and I/O devices. In a multiprocessor system it operates in the maximum
mode. In case of maximum mode of operation control signals are issued by Intel 8288 bus
controller which is used with 8086 for this very purpose. The level of the pin MN/MX′
decides the operating mode of 8086. When MN/MX′ is high the CPU operates in the
minimum mode. When it is low the CPU operates in the maximum mode. From pin 24 to 31
issue two different sets of signals. One set of signals is issued when the CPU operates in the
maximum mode. Thus the pins from 24 to 31 have alternate functions.

9
Pin description for Minimum Mode:

For the minimum mode of operation the pin MN / MX′ is connected to 5V D.C. supply, i.e.,
MN / MX′ = Vcc.

The description of the pins from 24 to 31 for the minimum mode is as follows:

 INTA′ (Output): Pin No. 24 Interrupt acknowledge:

In response to interrupt signal INTR, the processor issues an interrupt acknowledge

signal. It is active LOW.

 ALE (Output) Pin No. 25 Address latch enable:

When the Address Latch Enable (ALE) signal is high, it indicates that the 8086
multiplexed address/data bus (AD15-AD0) and multiplexed address/status bus
(A19/S6, A18/S5, A17/S4, A16/S3) contain an address. When the Address Latch
Enable (ALE) signal is low, it indicates that the 8086 multiplexed address/data bus
(AD15-AD0) contains data and multiplexed address/status bus (A19/S6, A18/S5,
A17/S4, A16/S3) contain status signals S6, S5, S4 and S3.

 DEN′ (Output) Pin No. 26. Data Bus Enable:

This signal activates external data bus buffers. When data is transferred through the
data bus of the 8086, this signal is at logic 0. When DEN′ is High, no data flows in the
data bus.

 DT / R′ (Output) Pin No. 27. Data Transmit / Receive:

This signal indicates that the 8086 data bus is transmitting (DT/R′=1) or receiving
(DT/R′=0) data. This signal is used to control the data flow direction in external data
bus buffers.

 M / IO′ (Output) Pin No. 28. Memory or I/O access:

When this signal is HIGH the CPU wants to access memory. When it is LOW the CPU
wants to access I/O device.

 WR′ (Output): Pin No. 29 Write.

When this signal is LOW the CPU performs memory or I/O write operation.

 HLDA(Output): Pin No. 30. HOLD acknowledge.

HLDA is an acknowledge signal which is needed to synchronize the MPU with DMA
controller. HLDA signal acknowledges the Hold request.

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  HOLD (Input) Pin No. 31. Hold:

When HLD (Hold) signal is HIGH, MPU is reset and buses are not tri-stated. This
signal indicates that a peripheral such as a DMA controller is requesting the use of the
address and data buses, i.e. DMA transfer can be done when HLD is HIGH.

Pin description for Maximum Mode:

For the maximum mode of operation the pin MN / MX′ is connected to Ground, i.e., MN /
MX′ = Vcc.

The description of the pins from 24 to 31 for the maximum mode is as follows:

 QS1, QS0 (Output): Pin No. 24, 25. Instruction Queue Status.

The queue status bits show the status of the instruction queue in the 8086. Following
table shows the function of the QS1 and QS0 bits.

QS1 QS2 Function

0 0 Queue is idle (or no operation)
0 1 1st byte of opcode is read from the queue
1 0 Queue is empty
1 1 Subsequent byte of opcode is read from the queue

Table 4.1: Functions of QS1 and QS2

 S2, S1, S0 (Output) Pin No. 26,27,28. STATUS:

The status bits indicate the function of the current bus cycle. These signals are
normally decoded by the 8288 (bus controller). Following table shows the function of
these three status bits in the maximum mode.

S2 S1 S0 Function
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory write
1 1 1 Passive (inactive)

Table 4.2: Functions of S2, S1 and S0

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 LOCK′ (Output) Pin No. 29. Lock:

It is an active low pin. It indicates that other system bus masters have not been
allowed to gain control of the system bus while LOCK′ is active low (0). The LOCK′
signal will be active until the completion of the next instruction.

 RQ′/GT0′ and RQ′/GT1′ (Input / Output): Pin No. 30-31. Request/Grant:

These are the Request/Grant signals used by the other processors or by some
peripheral devices such as DMA requesting the 8086 Processor to release the system
bus. These signals are bidirectional. When the signal is received by CPU, then it sends
acknowledgment. RQ′/GT0′ has a higher priority than RQ′/GT1′.

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3. ADDRESSING MODES

Addressing mode indicates a way of locating data or operands. Depending upon the data
types used in the instruction and the memory addressing modes, any instruction may belong
to one or more addressing modes, or some instruction may not belong to any of the
addressing modes. Thus the addressing modes describe the types of operands and the way
they are accessed for executing an instruction. Here, we will present the addressing modes of
the instructions depending upon their types. According to the flow of instruction execution,
the instructions may be categorized as
i. Sequential control flow instructions and
ii. Control transfer instructions

Sequential control flow instructions are the instructions, which after execution, transfer
control to the next instruction appearing immediately after it (in the sequence) in the program.
For example, the arithmetic, logical, data transfer and processor control instructions are
sequential control flow instructions. The control transfer instructions, on the other hand,
transfer control to some predefined address somehow specified in the instruction after their
execution. For example, INT, CALL, RET and JUMP instructions fall under this category.
The addressing modes for sequential control transfer instructions are explained as follows:

1. Immediate: In this type of addressing, immediate data is a part of instruction, and

appears in the form of successive byte or bytes.

Example: MOV AX, 0005H

MOV DL, 80H

In the above example, 0005H is the immediate data. The immediate data may be 8-bit
or 16-bit in size.

2. Direct: In the direct addressing mode, a 16-bit memory address (offset) is directly
specified in the instruction as a part of it.

Example: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective address
may be computed using 5000H as the offset address and content of DS as segment
address. The effective address, here, is (DS)×10H+5000H.

3. Register: In the direct addressing mode, the data is stored in a register and it is
referred using the particular register. All the registers, except IP, may be used in this
mode.

Example: MOV BX, AX

4. Register Indirect: Sometimes, the address of the memory location, which contains

13
 data or operand, is determined in an indirect way, using the offset registers. This mode
of addressing is known as register indirect mode. In this addressing mode, the offset
address of data is in either BX or SI or DI registers. The default segment is either DS
or ES. The data is supposed to be available at the address pointed to by the content of
any of the above registers in the default data segment.

Example: MOV AX, [BX]

Here, data is present in a memory location in DS whose offset address is in BX. The
effective address of the data is given as (DS)×10H+(BX).

5. Indexed: In this addressing mode, offset of the operand is stored in one of the index
registers. DS and ES are the default segments for index registers SI and DI
respectively. This mode is a special case of the above discussed register indirect
addressing mode.

Example: MOV AX, [SI]

Here, data is available at an offset address stored in SI in DS. The effective address, in
this case, is computed as (DS)×10H + (SI)

6. Register Relative: In this addressing mode, the data is available at an effective

address formed by adding an 8-bit or 16-bit displacement with the content of any one
of the registers BX, BP, SI and DI in the default (either DS or ES) segment. The
example given before explains this mode.

Example: MOV AX, 50H [BX]

Here, effective address is given as (DS)×10H+50H+(BX).

7. Based Indexed: The effective address of data is formed, in this addressing mode, by
adding content of a base register (any one of BX or BP) to the content of an index
register (any one of SI or DI). The default segment register may be ES or DS.

Example: MOV DX, [BX] [SI]

Here, BX is the base register and SI is the index register. The effective address is
computed as (DS)×10+(BX)+(SI).

Example: MOV AX, [BP] [SI]

Here, BP is the base register and SI is the index register. The effective address is
computed as (SS)×10+(BX)+(SI).

8. Relative Based Indexed: The effective address is formed by adding an 8-bit or 16-bit

14
displacement with the sum of contents of any one of the bases registers (BX or BP)
and any one of the index registers, in a default segment.

Example: MOV AX, 50H [BX] [SI]

Here, 50H is an immediate displacement, BX is a base register and SI is an index

register. The effective address of data is computed as (DS)×10H+(BX)+(SI)+50H.

15
4. 8086 INSTRUCTION SET

The 8086 microprocessor supports 8 types of instructions −

 Data Transfer Instructions

 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions
Let us now discuss these instruction sets in detail.

Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group −
Instruction to transfer a word
 MOV − Used to copy the byte or word from the provided source to the provided
destination.
 PPUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.
 POPA − Used to get words from the stack to all registers.
 XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the memory.
Instructions for input and output port transfer
 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the provided port.
Instructions to transfer the address
 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
 LES − Used to load ES register and other provided register from the memory.
Instructions to transfer flag registers
 LAHF − Used to load AH with the low byte of the flag register.
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.

Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.

16
Following is the list of instructions under this group −
Instructions to perform addition
 ADD − Used to add the provided byte to byte/word to word.
 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.
Instructions to perform subtraction
 SUB − Used to subtract the byte from byte/word from word.
 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.
Instruction to perform multiplication
 MUL − Used to multiply unsigned byte by byte/word by word.
 IMUL − Used to multiply signed byte by byte/word by word.
 AAM − Used to adjust ASCII codes after multiplication.
Instructions to perform division
 DIV − Used to divide the unsigned word by byte or unsigned double word by word.
 IDIV − Used to divide the signed word by byte or signed double word by word.
 AAD − Used to adjust ASCII codes after division.
 CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower
byte.
 CWD − Used to fill the upper word of the double word with the sign bit of the lower
word.

Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations
like logical, shift, etc.
Following is the list of instructions under this group −
Instructions to perform logical operation
 NOT − Used to invert each bit of a byte or word.
 AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with
the corresponding bit in another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.
Instructions to perform shift operations
 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.

17
  SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into
the new MSB.
Instructions to perform rotate operations
 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to
Carry Flag [CF].
 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to
Carry Flag [CF].
 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to
MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to
LSB.

String Instructions

String is a group of bytes/words and their memory is always allocated in a sequential order.
Following is the list of instructions under this group −
 REP − Used to repeat the given instruction till CX ≠ 0.
 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF
= 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the
provided memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided
memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in
AL or string word with a word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string word into
AX.

Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It includes
the following instructions −
Instructions to transfer the instruction during an execution without any condition −
 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
 JMP − Used to jump to the provided address to proceed to the next instruction.
Instructions to transfer the instruction during an execution with some conditions −
 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
 JAE/JNB − Used to jump if above/not below instruction satisfies.
 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
 JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.

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  JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1

Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag values.
Following are the instructions under this group −
 STC − Used to set carry flag CF to 1
 CLC − Used to clear/reset carry flag CF to 0
 CMC − Used to put complement at the state of carry flag CF.
 STD − Used to set the direction flag DF to 1
 CLD − Used to clear/reset the direction flag DF to 0
 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following
is the list of instructions under this group −
 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX
=0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 &
CX = 0
 JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions

These instructions are used to call the interrupt during program execution.
 INT − Used to interrupt the program during execution and calling service specified.
 INTO − Used to interrupt the program during execution if OF = 1
 IRET − Used to return from interrupt service to the main program

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Sample Assembly Language Program:

1. Write an assembly language program in 8086 to add two 16-bit numbers.

PROGRAM:

LABEL OPCODE OPERAND COMMENTS

START MOV CX, 9273 Get 16-bit data in AX
MOV DX, 2464 Get another 16-bit data in DX
ADD CX, DX (CX) ← (CX) + (DX)
END INT3 Halt the program

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