Digital VLSI Design

Lecture 2: Verilog
Semester B, 2021 - 22
Lecturer: Mr. Deivis Hanan
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Verilog
Let’s assume we want to design this:
VERILOG
• Verilog is a Hardware Description Language (HDL).
First Version – 1984

• VHDL and SystemVerilog are other HDL languages

commonly used in the industry
Verilog is a Hardware Description Language (HDL)

DFF
DFF q
At every positive edge of clock:
d If reset is not low:
set q to the value of d
set qb to inverse of d

Whenever reset goes low:

set q to 0
clock qb set qb to 1

reset
 HDL- Example
DFF
DFF q module DFF ();
d

At every positive edge of clock:

If reset is not low:
set q to the value of d
set qb to inverse of d
clock qb
Whenever reset goes low:
set q to 0
set qb to 1
endmodule
reset
 HDL- Example
DFF
DFF q module DFF (clock, reset, d, q, qb);
d
input d, clock, reset;
output q, qb;

reg q, qb;
At every positive edge of clock:
If reset is not low:
set q to the value of d
set qb to inverse of d
clock qb
Whenever reset goes low:
set q to 0
set qb to 1
endmodule
reset
 HDL- Example
DFF
DFF q module DFF (clock, reset, d, q, qb);
d
input d, clock, reset;
output q, qb;

reg q, qb;
At every positive edge of clock:
If reset is not low: always @(posedge clock)
set q to the value of d if (~reset) begin
set qb to inverse of d q <= d;
qb <= ~d;
clock qb
Whenever reset goes low:
set q to 0
set qb to 1
endmodule
reset
 HDL- Example
DFF
DFF q module DFF (clock, reset, d, q, qb);
d
input d, clock, reset;
output q, qb;

reg q, qb;
At every positive edge of clock:
If reset is not low: always @(posedge clock or negedge reset)
set q to the value of d if (~reset) begin
set qb to inverse of d q <= d;
qb <= ~d;
clock qb else begin
Whenever reset goes low: q <= 0;
set q to 0 qb <= 1;
set qb to 1 end
endmodule
reset
Simulation Algorithms
Simulation Algorithms
 Different Level of Abstractions
• Architectural/Algorithmic
• A system is described in terms of the algorithms it performs

• Behavioral
• A system is described by the flow of data between its functional blocks

• Register Transfer Logic (RTL) or Functional

• A system is described by the flow of data and control signals within and between
functional blocks
• Schedule assignments at all clocks boundaries, at every clock edge

• Structural/Gate-Level
• Components are modeled by connecting primitives (or gates) for greater accuracy,
especially in timing

• Switch
• Components are modeled by the logic behavior of their transistor circuits for maximum
accuracy
 Lexical Convention - Comments

Comments can be specified in two ways (exactly the same way as in C/C++):
➢ Begin the comment with double slashes (//). All text between these characters and the end of the line will be
ignored by the Verilog compiler.
➢ Enclose comments between the characters /* and */. Using this method allows you to continue comments on
more than one line. This is good for “commenting out” many lines code, or for very brief in-line comments.

Example
assign y = z;
a = c + d; // this is a simple comment
/* however, this comment continues more
than one line */
assign x = w /* plus its compliment*/ + t
Lexical Elements - Identifiers

➢ Identifiers are user-defined words for variables, function names, module names, block
names and instance names.
➢ Identifiers begin with a letter or underscore (Not with a number or $) and can include
any number of letters, digits and underscores. Identifiers in Verilog are case-sensitive.
 Lexical Elements - Literals
Literals
Literals are constant-valued operands that can be used in Verilog expressions. The two common Verilog literals are:
(a) String: A string literal is a one-dimensional array of characters enclosed in double quotes (“ “) and cannot span
multiple lines.
(b) Numeric: constant numbers specified in binary, octal, decimal or hexadecimal.

Numeric literals can have underscores embedded in them for improved readability.
For example, Decimal literal 24_000
Lexical Elements - Reserved Keywords
always endmodule large reg
and endprimitive macromodule release
tranif0
assign endspecify nand repeat
tranif1
attribute endtable negedge rnmos
tri
begin endtask nmos rpmos
tri0
buf event nor rtran
tri1
bufif0 for not rtranif0
triand
bufif1 force notif0 rtranif1
trior
case forever notif1 scalared
trireg
casex fork or signed
unsigned
casez function output small
vectored
cmos highz0 parameter specify
wait
deassign highz1 pmos specparam
wand
default if posedge strength
weak0
defparam ifnone primitive strong0
weak1
disable initial pull0 strong1
while
edge inout pull1 supply0
wire
else input pulldown supply1
wor
end integer pullup table
xnor
endattribute join rcmos task
xor
endcase medium real time
endfunction module realtime tran
Hierarchical Modeling Concepts

Intel’s PC with Core i5/i7 CPUs

Hierarchical Modeling Concepts
Module Declaration
A module is the principal design entity in Verilog. The first line of a module declaration specifies the name and port
list (arguments). The next few lines specifies the i/o type (input, output or inout) and width of each port. The
default port width is 1 bit.
Then the port variables must be declared wire, wand,. . ., reg.
The default is wire. Typically, inputs are wire since their data is latched outside the module.
Outputs are type reg if their signals were stored inside an always or initial block.
Hierarchical Modeling Concepts
Module Instantiations
Module declarations are templates from which one creates actual objects (instantiations). Modules are instantiated
inside other modules, and each instantiation creates a unique object from the template. The exception is the top-level
module which is its own instantiation.
The instantiated module’s ports must be matched to those defined in the template. This is specified:
(i) by name, using a dot(.) “ .template_port_name (name_of_wire_connected_to_port)”.
(ii) by position, placing the ports in exactly the same positions in the port lists of both the template and the instance.
Data Types - Verilog has 4 logic values

Value Description

0 zero, low, or false

1 one, high, or true

z High Impedance (tri-stated or floating)

x Unknown (ambiguous or uninitialized)

Data Types - Registers and Nets

A Register stores its value from one assignment to the next and is used to model data storage elements.

Nets correspond to physical wires that connect instances. The default range of a wire or reg is one bit. Nets do not store
values and have to be continuously driven.

If a net has multiple drivers (i.e.: two gate outputs are tied together), then the net value is resolved according to its type.
Choosing the Correct Data Type
Module Boundary
Input Port Output Port

net/register net net/register net

net
Inout Port

net
Inputs
Internally, input port must always be of the type net.
Externally, the inputs can be connected to a variable which is a reg or a net.

Outputs
Internally, output port must be of the type net or reg.
Externally, the outputs must always be connected to a net. They cannot be connected to a reg.

Inouts
Internally, inout port must always be of the type net.
Externally, the outputs must always be connected to a net. They cannot be connected to a reg.
Data Types – Net Types
Keyword Functionality

wire or tri Simple interconnecting wire

wor or trior Wired outputs OR together
wand or triand Wired outputs AND together
tri0 Pulls down when tri-stated
tri1 Pulls up when tri-stated
supply0 Constant logic 0 (supply strength)
supply1 Constant logic 1 (supply strength)
trireg Stores last value when tri-stated (capacitance strength)
Data Types – Net Types

Logic Strength Conflict Resolution

Logic Conflict Resolution with Net Types

Pull1
a
Strong0
y
Strong0
b

Supply1 Supply1

Large0
Data Types – Register Types

Keyword Functionality

reg unsigned variable of any bit size

integer signed 32-bit variable
time unsigned 64-bit variable
real or realtime double-precision floating point variable
Data Types – Register Types

Integer
Integers are general-purpose variables. For synthesis they are mainly used for loops-indices, parameters, and
constants.
They are of implicitly of type reg.
However, they store data as signed numbers whereas explicitly declared reg types store them as unsigned.
If they hold numbers which are not defined at compile time, their size will default to 32-bits.
If they hold constants, the synthesizer adjusts them to the minimum width needed at compilation.

integer counter; // general purpose variable used as a counter

initial
counter = -1 // A negative one is stored in the counter
Data Types – Register Types

Real
They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6 ).
Their default value is 0. When a real value is assigned to an integer, the real number is rounded off to the nearest integer.

Time
Time is a 64-bit quantity that can be used in conjunction with the $time system task to hold simulation time.
Time is not supported for synthesis and hence is used only for simulation purposes.

real delta; // define a real variable called delta

integer i;
time c;
initial begin
delta = 2.13;
i = delta; // What is the value of i ?
c = $time;
end
Data Types – Array

Arrays are allowed in Verilog for reg, integer, time and vector register data types. Not allowed for real types

It is important not to confuse arrays with net or register vectors. A vector is a single element that is n-bits wide.
On the other hand, arrays are multiple elements that are 1-bit or n-bits wide.

reg [4:0] port; // This is a 5-bit vector!! Not an array!

reg [4:0] port_id [0:7]; // Array of 8 port_ids, each port_id is 5 bits wide

integer count [0:7]; // An array of 8 count variables

count[5]; //6th element of array of count variables

Data Types – Parameter
module stam (q, data);

A parameter defines a constant that can be set when you instantiate a module. parameter end_bit = 1;
This allows customization of a module during instantiation. parameter delay = 5;

output [end_bit:0] q;
input [end_bit:0] data;

assign #(delay) q = data;

endmodule

The customization can be done explicitly or implicitly.

Explicit Implicit

module top1; module top2;

wire [2:0] data; wire [2:0] data;

wire [2:0] q; wire [2:0] q;

defparam stam1.delay = 3;
===
defparam stam1.end_bit = 2;

stam stam1 (.q(q[2:0]),.data(data[2:0])); stam #(2,3) stam2 (.q(q[2:0]),.data(data[2:0]));

endmodule endmodule
Operators

Operators perform an operation on one or two operands:

• Unary expressions
➢ operator operand

• Binary expressions
➢ operand operator operand

•Ternary expressions
➢ operand operator operand operator operand

• The operands may be either net or register data types.

• Operands may be scalar, vector, or bit selects of a vector.
• Operators which return a true/false result will return a 1-bit value where 1 is true, 0 is false, and X is indeterminate.
Operators
Type Symbols Operation Performed Descriptions/Examples
~ Bitwise NOT (1's complement) ~X evaluates to 4’b0101
X & Y evaluates to 4’b1000 X = 4’b1010
& Bitwise AND
X & Z evaluates to 4’b10x0 Y = 4’b1101
Bitwise Z = 4’b10x1
| Bitwise OR X | Y evaluates to 4’b1111
^ Bitwise XOR X ^ Y evaluates to 4’b0111
~^ or ^~ Bitwise XNOR X ^~ Y evaluates to 4’b1000
! NOT !A=0, !B=1
A=3
Logical* && AND A && B evaluates to 0 B=0
|| OR A || B evaluates to 1
& Reduction AND &X is equivalent to 1 & 0 & 1 & 0. Evaluates to 1’b0
~& Reduction NAND
| Reduction OR |X evaluates to 1’b1 X = 4’b1010
Reduction
~| Reduction NOR
^ Reduction XOR ^X evaluates to 1’b0
~^ or ^~ Reduction XNOR
+ Addition A+B evaluates to 4’b0111
- Subtraction B-A evaluates to 4’b0001 A=4’b0011
Arithmetic
* Multiplication A*B evaluates to 4’b1100 B=4’b0100
/ Division A/B evaluates to 4’b0001

* Logical operators always evaluate to a 1-bit value, 0 (false), 1 (true), or x (ambiguous)

If an operand is not equal to zero, it is equivalent to a logical 1 (true condition).
If it is equal to zero a logical 0 (false), and if any operand bit is x or z, it is equivalent to x and treated as a false condition)
 Operators
Type Symbols Operation performed Descriptions/Examples
> Greater than A > B evaluates to a logical 1
< Less than Y < N evaluates to an x
>= Greater than or equal to Y >= X evaluates to a logical 1
A=4
<= Less than or equal to A <= B evaluates to a logical 0
B=3
Logical equality A == B evaluates to logical 0 X = 4’b1010
==
Relational* (bit-value 1'bX is removed from comparison) X == Z evaluates to x
Y = 4’b1101
Logical inequality Z = 4’b1xxz
!= X != Y evaluates to logical 1
(bit-value 1'bX is removed from comparison) M = 4’b1xxz
4-state logical equality Z === M evaluates to logical 1 N = 4’b1xxx
===
(bit-value 1'bX is taken as literal) Z === N evaluates to logical 0
4-state logical inequality
!== M !== N evaluates to logical 1
(bit-value 1'bX is taken as literal)
>> Logical right shift X >> 1 evaluates to 4’b0110
X << 1 evaluates to 4’b1000 X = 4’b1100
<< Logical left shift
Shift X << 2 evaluates to 4’b0000 Y = 4’b1000
>>> Arithmetic right shift Y >>> 2 evaluates to 4’b1110
<<< Arithmetic left shift Y <<< 2 evaluates to 4’b0000
{B, C} evaluates to 4’b0010
Concatenation {, } Concatenation {A, B, 3’b001} evaluates to 6’b100001 A = 1’b1, B = 2’b00, C = 2’b10
{A, B[0], C[1]} evaluates to 3’b101
{4{A}} evaluates to 4’b1111
Replication {n{m}} Replicate value m for n times
{4{A}, 2{B}} evaluates to 8’b11110000
assign out = control ? In1 : in0
Conditional ?: condition_expr ? true_expr : false_expr
(2-1 MUX)

* Relational operators evaluate to a logical value of 1 if the expression is true and 0 if the expression is false
If there are any unknown or z bits in the operands, the expression takes a value x, except for === and !==
 Assignments - Continuous Assignment
The continuous assignment is used to assign a value onto a wire in a module.

Continuous assignment is done with an explicit assign statement or by assigning a value to a wire during its declaration.

Note that continuous assignment statements are concurrent and are continuously executed during simulation.
The order of assign statements does not matter.

Any change in any of the right-hand-side inputs will immediately change a left-hand-side output.
Assignments - Regular Assignment Delay
The first method is to assign a delay value in a continuous assignment statement.
The delay value is specified after the keyword assign.

Any change in values in in1 or in2 will result in a delay of 10-time units before recomputation of the
expression in1&in2, and the result will be assigned to out.

assign #10 out = in1 & in2; // Delay in continuous assign

in1

A pulse of width less than the specified

in2 assignment delay is not propagated to
xxx the output
out
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
Behavior Modeling – Procedural Assignments

Procedural assignments are assignment statements used within Verilog procedures (always and initial blocks).
Only reg variables and integers (and their bit/part-selects and concatenations) can be placed left of the “=” in procedures.
The right-hand side of the assignment is an expression which may use any of the operator types.
 Verilog Processes – Always and Initial
Always Block
Like the continuous assignment, it is a concurrent statement that is continuously executed during simulation.
This also means that all always blocks in a module execute simultaneously.
The always block can be used to imply latches, flip-flops or combinational logic.
If the statements in the always block are enclosed within begin ... end, the statements are executed sequentially.
If enclosed within the fork... join, they are executed concurrently (simulation only).
The always block is triggered to execute by the level, positive edge or negative edge of one or more signals
(separate signals by the keyword or).
A double-edge trigger is implied if you include a signal in the event list of the module DFF (clock, reset, d, q, qb);
always statement.
input d, clock, reset;
The single edge-triggers are specified by posedge and negedge keywords. output q, qb;

reg q, qb;

always @(posedge clock or negedge reset)

if (~reset) begin
q <= d;
qb <= ~d;
else begin
q <= 0;
qb <= 1;
end
endmodule
Verilog Processes – Always and Initial
Initial Block
The initial block is like the always block except that it is executed only once at the beginning of the simulation.
It is typically used to initialize variables and specify signal waveforms during simulation.
Behavior Modeling – Procedural Assignments

Blocking Assignments
Blocking assignments (=) are done sequentially in the order the statements are written.
A second assignment is not started until the preceding one is complete.

Delay in Assignment
In a delayed assignment Dt time units pass before the statement is executed and the left-hand assignment is made.
With intra-assignment delay, the right side is evaluated immediately but there is a delay of Dt before the result is place
in the left-hand assignment. If another procedure changes a right-hand side signal during Dt, it does not affect the
output.

Example
sum [7] = b[7] ^ c[7]; // executes now.
#10 d = e&f; /* 10-time units after ‘sum’ changes,
e&f is evaluated and ‘d’ changes. */
a = #15 b&c; /* b&c is evaluated now; ‘a’ changed
after 15-time units. */
Behavior Modeling – Procedural Assignments
Nonblocking Assignments
Nonblocking assignments (<=), which follow each other in the code, are done in parallel.

The right-hand side of nonblocking assignments is evaluated starting from the completion of the last
blocking assignment or if none, the start of the procedure.

The transfer to the left-hand side is made according to the delays.

A delay in a non-blocking statement will not delay the start of any subsequent statement blocking or
non-blocking.
• Don’t mix “<=” or “=” in the same procedure.

b <= #3 a; //
x <= #6 b + c; /*
Behavior Modeling – Procedural Assignments
Application of Nonblocking Assignments
Nonblocking assignments are important in digital design and used as a method to model several concurrent
data transfers that take place after a common event.

Consider the following example where three concurrent data transfers take place at the positive edge of clock

always @(posedge clock) begin

reg1 <= #1 in1;

reg2 <= @(negedge clock) in2 ^ in3;

reg3 <= #1 reg1;

end

If you really understood this example, what value reg1 gets? The newer or the older?
Behavior Modeling – Procedural Assignments
A good example
Just understand it, never mix blocking and non-blocking in the same procedure!

initial begin Time statement executed

0 a=1, b=2, c=3, x=4
a=1; b=2; c=3; x=4;
5 a=5, d=5
#5 a = b + c; // wait for 5 units, then grab b,c and execute a=2+3. 6 y=5
7 Try to
b=5
d = a; // Time continues from last line, d=5 = b+c at t=5. Calculate
8 z=8,w=4
Alone !!
x <= #6 b + c;// grab b+c now at t=5, don’t stop, make x=5 at t=11. 11 x=5
Final a=5, b=5, c=3,
b <= #2 a; /* grab a at t=5 (end of last blocking statement).
d=5, x=5, y=5,
Deliver b=5 at t=7. previous x is unaffected by b change. */ z=8, w=4
y <= #1 b + c;// grab b+c at t=5, don’t stop, make y=5 at t=6.
#3 z = b + c; // grab b+c at t=8 (#5+#3), make z=8 at t=8.
w <= x // make w=4 at t=8. Starting at last blocking assignment.
Behavior Modeling – Loops

for Loops
Similar to for loops in C/C++, they are used to repeatedly execute a statement or block of statements.
If the loop contains only one statement, the begin ... end statements may be omitted.
Behavior Modeling – Loops
while Loops
The while loop repeatedly executes a statement or block of statements until the expression in the while
statement evaluates to false.

To avoid combinational feedback during synthesis, a while loop must be broken with an
@(posedge/negedge clock) statement. For simulation, a delay inside the loop will suffice.
Behavior Modeling – Loops
forever Loops
The forever statement executes an infinite loop of a statement or block of statements.

To avoid combinational feedback during synthesis, a forever loop must be broken with an
@(posedge/negedge clock) statement. For simulation, a delay inside the loop will suffice.
Behavior Modeling – Disable
disable
Execution of a disable statement terminates a block and passes control to the next statement after the
block.
It is like the C break statement except it can terminate any loop, not just the one in which it appears.
Disable statements can only be used with named blocks.
Behavior Modeling – Branching
if ... else if ... else
The if ... else if ... else statements execute a statement or block of statements depending on the result of the
expression following the if.

Both the
else if and else
statements are
optional.
Behavior Modeling – Branching
case
The case statement allows a multipath branch based on comparing the expression with a list of case choices.
Statements in the default block executes when none of the case choice comparisons are true.
Case choices may be a simple constant or expression, or a comma-separated list of same.
Behavior Modeling – Branching
casex
In casex the case choices in the statement may contain z, x or ? which are used as don’t cares for comparison. With
case the corresponding simulation variable would have to match a tri-state, unknown, or either signal. In short, case
uses x to compare with an unknown signal. casex uses x as a don’t care which can be used to minimize logic.

casez
casez is the same as casex except only ? and z (not x) are used in the case choice constants as don’t cares.
casez is favored over casex since in simulation, an inadvertent x signal, will not be matched by a 0 or 1 in the case choice.
Behavior Modeling – Timing Control
Delay Control
This specifies the delay time units before a statement is executed during simulation.
A delay time of zero can also be specified to force the statement to the end of the list of statements to be
evaluated at the current simulation time, this is used to eliminate race conditions.

Intra-Assignment Delay
This delay #D is placed after the equal sign. The left-hand assignment is delayed by the specified time
units, but the right-hand side of the assignment is evaluated before the delay instead of after the delay.
This is important when a variable may be changed in a concurrent procedure.
Behavior Modeling – Timing Control
Event Control, @
This causes a statement or begin-end block to be executed only after specified events occur. An event is a change in
a variable, and the change may be: a positive edge, a negative edge, or either (a level change), and is specified by the
keyword posedge, negedge, or no keyword respectively. Several events can be combined with the or keyword.

Event specification begins with the character @ and are usually used in always statements.
Behavior Modeling – Timing Control
Wait Statement
The wait statement makes the simulator wait to execute the statement(s) following the wait
until the specified condition evaluates to true.

Named Event Statement

You can declare an event and then trigger and recognize the occurrence of that event.
The event does not hold any data. A named event is declared by the keyword event.
An event is triggered by the symbol .
The triggering of the event is recognized by the symbol @. event received_data;
always @(posedge clock)
if (last_data)
received_data;
always @(received_data)
data = 8’b0;
Tasks and Functions - Functions
Functions are declared within a module, and can be called from continuous assignments, always blocks or other functions.

In a continuous assignment, they are evaluated when any of its declared inputs change.
In a procedure, they are evaluated when invoked.

Functions are a good way to reuse procedural code, since modules cannot be invoked from a procedure.
Function Declaration
A function declaration specifies the name of the function, the width of the function return value, the function input
arguments, the variables (reg) used within the function, and the function local parameters and integers.

{temp, i[2:0]};
Tasks and Functions - Functions
Function Return Value
When you declare a function, a variable is also implicitly declared with the same name as the function name,
and with the width specified for the function name (The default width is 1-bit).
At least one statement in the function must assign the function return value to this variable.

Function Call
A function call must specify in its terminal list all the input parameters.

Function Rules
The following are some of the general rules for functions:
- Functions must contain at least one input argument.
- Functions cannot contain an inout or output declaration.
- Functions cannot contain time-controlled statements (#, @, wait).
- Functions cannot enable tasks.
- Functions must contain a statement that assigns the return value to the implicit function name register.
Tasks and Functions - Functions
Function Example
Tasks and Functions - Functions
A Function has only one output.
If more than one return value is required, the outputs should be concatenated
into one vector before assigning it to the function name.

Example
module simple_processor (instruction, outp);
input [31:0] instruction;
reg header;
reg [7:0] op1, op2;
function [16:0] decode_add;
input [31:0] instr;
reg add_header;
reg [7:0] opcode, opr1, opr2;
decode_add = {add_header, opr2, opr1}; //concatenated into 17-bits
endfunction
always @(instruction)
{header, op2, op1} = decode_add (instruction);
endmodule
Tasks and Functions - Tasks
A task is similar to a function, but unlike a function it has both
input and output ports. Therefore, tasks do not return values.
Tasks are similar to procedures in most programming
languages.
The syntax and statements allowed in tasks are those
specified for functions
Tasks and Functions – Tasks Vs. Functions
Tasks and Functions – Force and Release

They can be used to override assignments on both registers and nets.

force on a register overrides any procedural assignments on the register until the force is released.
The register will continue to store the forced value after being released but can then be changed by a
future procedural assignment.
force on nets overrides any continuous assignments until the force is released. The net will immediately
return to its normal value when it is released.
A net can be forced to an expression or a value.

module top1; module top3;

module top2;
reg data; reg data;
wire out,a,b,c;
assign out = a & b & c;
initial begin stam stam1 (.data(data));
data = 1’b0;
initial begin
#50 force data = 1’b1; initial begin
#50 force out = a | b & c;
#50 release data; #50 force stam1.data = 1’b1;
#50 release out;
#50 data = 1’b0; #50 release stam1.data;
end
end end
endmodule
endmodule endmodule
System Tasks - Display

$display, $strobe, $monitor

These commands have the same syntax and display their values as text on the screen during simulation. $display
and $strobe display once every time they are executed, whereas $monitor displays every time one of its parameters
changes.
The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current
simulation time unit.

The format string is like that in C/C++ and may contain format characters. Format characters include %d
(decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t (time). Append b, h, o to the task
name to change default format to binary, octal or hexadecimal.

reg [31:0] val;

val = 101;
$display(“val = %h in hexadecimal and %d in decimal”, val, val);

val = 00000065 in hexadecimal and 101 in decimal

System Tasks – Simulation Time Control

$time, $stime, $realtime

These return the current simulation time as a 64-bit integer, a 32-bit integer, and a real number, respectively.

$reset, $stop, $finish

$reset resets the simulation back to time 0
$stop halts the simulator and puts it in the interactive mode where the user can enter commands
$finish exits the simulator back to the operating system.
System Tasks - Random

$random
$random generates a random integer every time it is called.
If the sequence is to be repeatable, the first time one invokes random give it a numerical argument (a seed).
Otherwise, the seed is derived from the computer clock.
Compiler Directives

➢ Compiler directives begin with the grave accent character ( ` ).

➢ Compiler directives are not Verilog HDL statements; there is no semi-colon at the end of compiler directives.
➢ Compiler directives are not bound by modules or by files. When a tool encounters a compiler directive, the
directive remains in effect until another compiler directive either modifies it or turns it off.
 Compiler Directives - `timescale

`timescale time_unit base / precision base

Specifies the time units and precision for delays:

time_unit is the amount of time a delay of 1 represents. The time unit must be 1 10 or 100
base is the time base for each unit, ranging from seconds to femtoseconds, and must be: s ms us ns ps or fs
precision and base represent how many decimal points of precision to use relative to the time units.

Example: `timescale 1 ns / 10 ps
Indicates delays are in 1 nanosecond units with 2 decimal points of precision (10 ps is .01 ns).
 Compiler Directives - `define

`define macro_name text_string

`define macro_name (arguments) text_string (arguments)

Text substitution macro.

Allows a text string to be defined as a macro name.

text_string will be substituted in place of the macro_name wherever the macro name is used.
text_string is terminated by a carriage return. The string must be on one line.
arguments are evaluated before text is substituted.
macro_name must also be preceded by the grave accent mark ( ` ) each time the macro name is used.

`define cycle 20 //clock period

always #(`cycle/2) clk = ~clk;
Compiler Directives - `ifdef
`ifdef macro_name
verilog_source_code
`else
verilog_source_code
`endif

Conditional compilation.

Allows Verilog source code to be optionally included, based on whether

or not macro_name has been defined using `define or an invocation option.

`ifdef RTL
wire y = a & b;
`else
and #1 (y,a,b);
`endif
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How to Build and Test a Module
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