UNIT-3

Input/Output Organisation

“Accessing I/O Devices”

1. In memory-mapped I/O ____________
a) The I/O devices and the memory share the same address space
b) The I/O devices have a separate address space
c) The memory and I/O devices have an associated address space
d) A part of the memory is specifically set aside for the I/O operation

Explanation: Its the different modes of accessing the i/o devices.

2. The usual BUS structure used to connect the I/O devices is ___________
a) Star BUS structure
b) Multiple BUS structure
c) Single BUS structure
d) Node to Node BUS structure

Explanation: BUS is a collection of address, control and data lines used to connect the various devices of the
computer.

3. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.
a) False
b) True

Explanation: This type of access is called as I/O mapped devices.

4. The advantage of I/O mapped devices to memory mapped is ___________

a) The former offers faster transfer of data
b) The devices connected using I/O mapping have a bigger buffer space
c) The devices have to deal with fewer address lines
d) No advantage as such

Explanation: Since the I/O mapped devices have a separate address space the address lines are limited by the
amount of the space allocated.

5. The system is notified of a read or write operation by ___________

a) Appending an extra bit of the address
b) Enabling the read or write bits of the devices
c) Raising an appropriate interrupt signal
d) Sending a special signal along the BUS

Explanation: It is necessary for the processor to send a signal intimating the request as either read or write.

6. To overcome the lag in the operating speeds of the I/O device and the processor we use ___________
a) Buffer spaces
b) Status flags
c) Interrupt signals
d) Exceptions

Explanation: The processor operating is much faster than that of the I/O devices, so by using the status flags
the processor need not wait till the I/O operation is done. It can continue with its work until the status flag is
set.

7. The method of accessing the I/O devices by repeatedly checking the status flags is ___________
a) Program-controlled I/O
b) Memory-mapped I/O
c) I/O mapped
d) None of the mentioned

Explanation: In this method, the processor constantly checks the status flags, and when it finds that the flag is
set it performs the appropriate operation.

8. The method of synchronising the processor with the I/O device in which the device sends a signal when it is
ready is?
a) Exceptions
b) Signal handling
c) Interrupts
d) DMA

Explanation: This is a method of accessing the I/O devices which gives the complete power to the devices,
enabling them to intimate the processor when they’re ready for transfer.

9. The method which offers higher speeds of I/O transfers is ___________

a) Interrupts
b) Memory mapping
c) Program-controlled I/O
d) DMA

Explanation: In DMA the I/O devices are directly allowed to interact with the memory without the intervention of
the processor and the transfers take place in the form of blocks increasing the speed of operation.

10. The process wherein the processor constantly checks the status flags is called as ___________
a) Polling
b) Inspection
c) Reviewing
d) Echoing

“Interrupts ”
11. The interrupt-request line is a part of the ___________
a) Data line
b) Control line
c) Address line
d) None of the mentioned

Explanation: The Interrupt-request line is a control line along which the device is allowed to send the interrupt
signal.

12. The return address from the interrupt-service routine is stored on the ___________
a) System heap
b) Processor register
c) Processor stack
d) Memory

Explanation: The Processor after servicing the interrupts as to load the address of the previous process and
this address is stored in the stack.

13. The signal sent to the device from the processor to the device after receiving an interrupt is ___________
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal

Explanation: The Processor upon receiving the interrupt should let the device know that its request is received.
14. When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i, iv
b) ii, iii and iv
c) iii, iv
d) i, ii
15. The time between the receiver of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time

Explanation: The delay in servicing of an interrupt happens due to the time is taken for contact switch to take
place.

16. Interrupts form an important part of _____ systems.

a) Batch processing
b) Multitasking
c) Real-time processing
d) Multi-user

Explanation: This forms an important part of the Real time system since if a process arrives with greater
priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced.

17. A single Interrupt line can be used to service n different devices.

a) True
b) False
View Answer
18. ______ type circuits are generally used for interrupt service lines.
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR
a) i, ii
b) ii
c) ii, iii
d) ii, iv

19. The resistor which is attached to the service line is called _____
a) Push-down resistor
b) Pull-up resistor
c) Break down resistor
d) Line resistor

Explanation: This resistor is used to pull up the voltage of the interrupt service line.

20. From amongst the following given scenarios determine the right one to justify interrupt mode of data
transfer.
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
a) i and ii
b) ii
c) i, ii and iv
d) iv
21. How can the processor ignore other interrupts when it is servicing one ___________
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
d) All of the mentioned
22. When dealing with multiple devices interrupts, which mechanism is easy to implement?
a) Polling method
b) Vectored interrupts
c) Interrupt nesting
d) None of the mentioned

Explanation: In this method, the processor checks the IRQ bits of all the devices, whichever is enabled first that
device is serviced.

23. The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be
serviced is ___________
a) Polling
b) Vectored interrupts
c) Interrupt nesting
d) Simultaneous requesting

24. In vectored interrupts, how does the device identify itself to the processor?
a) By sending its device id
b) By sending the machine code for the interrupt service routine
c) By sending the starting address of the service routine
d) None of the mentioned

Explanation: By sending the starting address of the routine the device ids the routine required and thereby
identifying itself.

25. The code sent by the device in vectored interrupt is _____ long.
a) upto 16 bits
b) upto 32 bits
c) upto 24 bits
d) 4-8 bits
.

26. The starting address sent by the device in vectored interrupt is called as __________
a) Location id
b) Interrupt vector
c) Service location
d) Service id

27. The processor indicates to the devices that it is ready to receive interrupts ________
a) By enabling the interrupt request line
b) By enabling the IRQ bits
c) By activating the interrupt acknowledge line
d) None of the mentioned

Explanation: When the processor activates the acknowledge line the devices send their interrupts to the
processor.

28. We describe a protocol of input device communication below:

i) Each device has a distinct address.
ii) The BUS controller scans each device in a sequence of increasing address value to determine if the entity
wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following.
a) Programmed mode of data transfer
b) DMA
c) Interrupt mode
d) Polling

Explanation: In polling, the processor checks each of the devices if they wish to perform data transfer and if
they do it performs the particular operation.

29. Which one of the following is true with regard to a CPU having a single interrupt request line and single
interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices are possible.
a) iii
b) i, iv
c) ii, iii
d) iii, iv

30. Which table handle stores the addresses of the interrupt handling sub-routines?
a) Interrupt-vector table
b) Vector table
c) Symbol link table
d) None of the mentioned

31. _________ method is used to establish priority by serially connecting all devices that request an interrupt.
a) Vectored-interrupting
b) Daisy chain
c) Priority
d) Polling

Explanation: In the Daisy chain mechanism, all the devices are connected using a single request line and
they’re serviced based on the interrupting device’s priority.

32. In daisy chaining device 0 will pass the signal only if it has _______
a) Interrupt request
b) No interrupt request
c) Both No interrupt and Interrupt request
d) None of the mentioned

Explanation: In daisy chaining since there is only one request line and only one acknowledges line, the
acknowledge signal passes from device to device until the one with the interrupt is found.
33. ______ interrupt method uses register whose bits are set separately by interrupt signal for each device.
a) Parallel priority interrupt
b) Serial priority interrupt
c) Daisy chaining
d) None of the mentioned

34. ______________ register is used for the purpose of controlling the status of each interrupt request in
parallel priority interrupt.
a) Mass
b) Mark
c) Make
d) Mask

35. The added output of the bits of the interrupt register and the mask register is set as an input of
______________
a) Priority decoder
b) Priority encoder
c) Process id encoder
d) Multiplexer

Explanation: In a parallel priority system, the priority of the device is obtained by adding the contents of the
interrupt register and the mask register.

36. Interrupts initiated by an instruction is called as _______

a) Internal
b) External
c) Hardware
d) Software
“Exceptions”
37. If during the execution of an instruction an exception is raised then __________
a) The instruction is executed and the exception is handled
b) The instruction is halted and the exception is handled
c) The processor completes the execution and saves the data and then handle the exception
d) None of the mentioned

Explanation: Since the interrupt was raised during the execution of the instruction, the instruction cannot be
executed and the exception is served immediately.

38. _____ is/are types of exceptions.

a) Trap
b) Interrupt
c) System calls
d) All of the mentioned

39. The program used to find out errors is called __________

a) Debugger
b) Compiler
c) Assembler
d) Scanner

Explanation: Debugger is a program used to detect and correct errors in the program.

40. The two facilities provided by the debugger is __________

a) Trace points
b) Break points
c) Compile
d) Both Trace and Break points

Explanation: The debugger provides us with the two facilities to improve the checking of errors.

41. In trace mode of operation is ________

a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without rectification of errors
d) The program is halted only at specific points

Explanation: In trace mode, the program is checked line by line and if errors are detected then exceptions are
raised right away.
42. What is the operation in Breakpoint mode?
a) The program is interrupted after each detection
b) The program will not be stopped and the errors are sorted out after the complete program is scanned
c) There is no effect on the program, i.e the program is executed without rectification of errors
d) The program is halted only at specific points

Explanation: The Breakpoint mode of operation allows the program to be halted at only specific locations.

43. What are the different modes of operation of a computer?

a) User and System mode
b) User and Supervisor mode
c) Supervisor and Trace mode
d) Supervisor, User and Trace mode

Explanation: The user programs are in the user mode and the system crucial programs are in the supervisor
mode.

44. The instructions which can be run only supervisor mode are?
a) Non-privileged instructions
b) System instructions
c) Privileged instructions
d) Exception instructions

Explanation: These instructions are those which can are crucial for the system’s performance and hence
cannot be adultered by user programs, so is run only in supervisor mode.

45. A privilege exception is raised __________

a) When a process tries to change the mode of the system
b) When a process tries to change the priority level of the other processes
c) When a process tries to access the memory allocated to other users
d) All of the mentioned

46. How is a privilege exception dealt with?

a) The program is halted and the system switches into supervisor mode and restarts the program execution
b) The Program is stopped and removed from the queue
c) The system switches the mode and starts the execution of a new process
d) The system switches mode and runs the debugger
“Direct Memory Access”.
47. The DMA differs from the interrupt mode by __________
a) The involvement of the processor for the operation
b) The method of accessing the I/O devices
c) The amount of data transfer possible
d) None of the mentioned

Explanation: DMA is an approach of performing data transfers in bulk between memory and the external device
without the intervention of the processor.

48. The DMA transfers are performed by a control circuit called as __________
a) Device interface
b) DMA controller
c) Data controller
d) Overlooker

Explanation: The Controller performs the functions that would normally be carried out by the processor.

49. In DMA transfers, the required signals and addresses are given by the __________
a) Processor
b) Device drivers
c) DMA controllers
d) The program itself

Explanation: The DMA controller acts as a processor for DMA transfers and overlooks the entire process.

50. After the completion of the DMA transfer, the processor is notified by __________
a) Acknowledge signal
b) Interrupt signal
c) WMFC signal
d) None of the mentioned

Explanation: The controller raises an interrupt signal to notify the processor that the transfer was complete.
51. The DMA controller has _______ registers.
a) 4
b) 2
c) 3
d) 1

Explanation: The Controller uses the registers to store the starting address, word count and the status of the
operation.

52. When the R/W bit of the status register of the DMA controller is set to 1.
a) Read operation is performed
b) Write operation is performed
c) Read & Write operation is performed
d) None of the mentioned

53. The controller is connected to the ____

a) Processor BUS
b) System BUS
c) External BUS
d) None of the mentioned

Explanation: The controller is directly connected to the system BUS to provide faster transfer of data.

54. Can a single DMA controller perform operations on two different disks simultaneously?
a) True
b) False

Explanation: The DMA controller can perform operations on two different disks if the appropriate details are
known.

55. The technique whereby the DMA controller steals the access cycles of the processor to operate is called
__________
a) Fast conning
b) Memory Con
c) Cycle stealing
d) Memory stealing

Explanation: The controller takes over the processor’s access cycles and performs memory operations.

56. The technique where the controller is given complete access to main memory is __________
a) Cycle stealing
b) Memory stealing
c) Memory Con
d) Burst mode

Explanation: The controller is given full control of the memory access cycles and can transfer blocks at a faster
rate.

57. The controller uses _____ to help with the transfers when handling network interfaces.
a) Input Buffer storage
b) Signal enhancers
c) Bridge circuits
d) All of the mentioned

Explanation: The controller stores the data to transfer in the buffer and then transfers it.

58. To overcome the conflict over the possession of the BUS we use ______
a) Optimizers
b) BUS arbitrators
c) Multiple BUS structure
d) None of the mentioned

Explanation: The BUS arbitrator is used to overcome the contention over the BUS possession.

59. The registers of the controller are ______

a) 64 bits
b) 24 bits
c) 32 bits
d) 16 bits
60. When the process requests for a DMA transfer?
a) Then the process is temporarily suspended
b) The process continues execution
c) Another process gets executed
d) process is temporarily suspended & Another process gets executed

Explanation: The process requesting the transfer is paused and the operation is performed, meanwhile another
process is run on the processor.

61. The DMA transfer is initiated by _____

a) Processor
b) The process being executed
c) I/O devices
d) OS

Explanation: The transfer can only be initiated by an instruction of a program being executed.

“Bus Arbitration”
62. To resolve the clash over the access of the system BUS we use ______
a) Multiple BUS
b) BUS arbitrator
c) Priority access
d) None of the mentioned

Explanation: The BUS arbitrator is used to allow a device to access the BUS based on certain
parameters.

63. The device which is allowed to initiate data transfers on the BUS at any time is called _____
a) BUS master
b) Processor
c) BUS arbitrator
d) Controller

Explanation: The device which is currently accessing the BUS is called as the BUS master.

64. ______ BUS arbitration approach uses the involvement of the processor.
a) Centralised arbitration
b) Distributed arbitration
c) Random arbitration
d) All of the mentioned

Explanation: In this approach, the processor takes into account the various parameters and
assigns the BUS to that device.

65. The circuit used for the request line is a _________

a) Open-collector
b) EX-OR circuit
c) Open-drain
d) Nand circuit

66. The Centralised BUS arbitration is similar to ______ interrupt circuit.

a) Priority
b) Parallel
c) Single
d) Daisy chain
67. When the processor receives the request from a device, it responds by sending _____
a) Acknowledge signal
b) BUS grant signal
c) Response signal
d) None of the mentioned
Explanation: The Grant signal is passed from one device to the other until the device that has
requested is found.

68. In Centralised Arbitration ______ is/are is the BUS master.

a) Processor
b) DMA controller
c) Device
d) Both Processor and DMA controller

Explanation: The BUS master is the one that decides which will get the BUS.

69. Once the BUS is granted to a device ___________

a) It activates the BUS busy line
b) Performs the required operation
c) Raises an interrupt
d) All of the mentioned

Explanation: The BUS busy activated indicates that the BUS is already allocated to a device
and is being used.

70. The BUS busy line is made of ________

a) Open-drain circuit
b) Open-collector circuit
c) EX-Or circuit
d) Nor circuit
.

71. After the device completes its operation _____ assumes the control of the BUS.
a) Another device
b) Processor
c) Controller
d) None of the mentioned

Explanation: After the device completes the operation it releases the BUS and the processor
takes over it.

72. The BUS busy line is used __________

a) To indicate the processor is busy
b) To indicate that the BUS master is busy
c) To indicate the BUS is already allocated
d) None of the mentioned

73. Distributed arbitration makes use of ______

a) BUS master
b) Processor
c) Arbitrator
d) 4-bit ID

Explanation: The device uses a 4bit ID number and based on this the BUS is allocated.

74. In Distributed arbitration, the device requesting the BUS ______

a) Asserts the Start arbitration signal
b) Sends an interrupt signal
c) Sends an acknowledge signal
d) None of the mentioned

75. How is a device selected in Distributed arbitration?

a) By NANDing the signals passed on all the 4 lines
b) By ANDing the signals passed on all the 4 lines
c) By ORing the signals passed on all the 4 lines
d) None of the mentioned

Explanation: The OR output of all the 4 lines is obtained and the device with the larger value is
assigned the BUS.

76. If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device
gets the BUS based on the Distributed arbitration.
a) Device A
b) Device B
c) Insufficient information
d) None of the mentioned

Explanation: The device Id’s of both the devices are passed on the lines and since the value of
B is greater after the Or operation it gets the BUS.

“Synchronous BUS”
77. The primary function of the BUS is __________
a) To connect the various devices to the cpu
b) To provide a path for communication between the processor and other devices
c) To facilitate data transfer between various devices
d) All of the mentioned

Explanation: The BUS is used to allow the passage of commands and data between cpu and
devices.

78. The classification of BUSes into synchronous and asynchronous is based on __________
a) The devices connected to them
b) The type of data transfer
c) The Timing of data transfers
d) None of the mentioned

Explanation: The BUS is classified into different types for the convenience of use and
depending on the device.

79. The device which starts data transfer is called __________

a) Master
b) Transactor
c) Distributor
d) Initiator

Explanation: The device which starts the data transfer is called an initiator.

80. The device which interacts with the initiator is __________

a) Slave
b) Master
c) Responder
d) Friend

Explanation: The device which receives the commands from the initiator for data transfer.

81. In synchronous BUS, the devices get the timing signals from __________
a) Timing generator in the device
b) A common clock line
c) Timing signals are not used at all
d) None of the mentioned

Explanation: The devices receive their timing signals from the clock line of the BUS.
82. The delays caused in the switching of the timing signals is due to __________
a) Memory access time
b) WMFC
c) Propagation delay
d) Processor delay

Explanation: The time taken for the signal to reach the BUS from the device or the circuit
accounts for this delay.

83. The time for which the data is to be on the BUS is affected by __________
a) Propagation delay of the circuit
b) Setup time of the device
c) Memory access time
d) Propagation delay of the circuit & Setup time of the device

Explanation: The time for which the data is held is larger than the time taken for propagation
delay and setup time.

84. The Master strobes the slave at the end of each clock cycle in Synchronous BUS.
a) True
b) False

85. Which is fed into the BUS first by the initiator?

a) Data
b) Address
c) Commands or controls
d) Address, Commands or controls

86. _____________ signal is used as an acknowledgement signal by the slave in Multiple cycle
transfers.
a) Ack signal
b) Slave ready signal
c) Master ready signal
d) Slave received signal

Explanation: The slave once it receives the commands and address from the master strobes
the ready line indicating to the master that the commands are received.

“Asynchronous BUS”
87. The master indicates that the address is loaded onto the BUS, by activating _____ signal.
a) MSYN
b) SSYN
c) WMFC
d) INTR

Explanation: The signal activated by the master in the asynchronous mode of transmission is
used to intimate the slave the required data is on the BUS.

88. The devices with variable speeds are usually connected using asynchronous BUS.
a) True
b) False

Explanation: The devices with variable speeds are connected using asynchronous BUS, as the
devices share a master-slave relationship.

89. The MSYN signal is initiated __________

a) Soon after the address and commands are loaded
b) Soon after the decoding of the address
c) After the slave gets the commands
d) None of the mentioned

Explanation: This signal is activated by the master to tell the slave that the required
commands are on the BUS.

90. In IBM’s S360/370 systems _____ lines are used to select the I/O devices.
a) SCAN in and out
b) Connect
c) Search
d) Peripheral

Explanation: The signal is used to scan and connect to input or output devices.

91. The meter in and out lines are used for __________
a) Monitoring the usage of devices
b) Monitoring the amount of data transferred
c) Measure the CPU usage
d) None of the mentioned

Explanation: The line is used to monitor the usage of the device for a process.

92. MRDC stands for _______

a) Memory Read Enable
b) Memory Ready Command
c) Memory Re-direct Command
d) None of the mentioned

Explanation: The command is used to initiate a read from memory operation.

93. The BUS that allows I/O, memory and Processor to coexist is _______
a) Attributed BUS
b) Processor BUS
c) Backplane BUS
d) External BUS

94. The transmission on the asynchronous BUS is also called _____

a) Switch mode transmission
b) Variable transfer
c) Bulk transfer
d) Hand-Shake transmission

Explanation: The asynchronous transmission is termed as Hand-Shake transfer because the

master intimates the slave after each step of the transfer.

95. Asynchronous mode of transmission is suitable for systems with multiple peripheral
devices.
a) True
b) False

Explanation: This mode of transmission is suitable for multiple device situation as it supports
variable speed transfer.

96. The asynchronous BUS mode of transmission allows for a faster mode of data transfer.
a) True
b) False
 “Interface Circuits”
97. ______ serves as an intermediary between the device and the BUSes.
a) Interface circuits
b) Device drivers
c) Buffers
d) None of the mentioned

Explanation: The interface circuits act as a hardware interface between the device and the
software side.

98. The side of the interface circuits, that has the data path and the control signals to transfer
data between interface and device is _____
a) BUS side
b) Port side
c) Hardwell side
d) Software side

Explanation: This side connects the device to the motherboard.

99. What is the interface circuit?

a) Helps in installing of the software driver for the device
b) Houses the buffer that helps in data transfer
c) Helps in the decoding of the address on the address BUS
d) None of the mentioned

Explanation: Once the address is put on the BUS the interface circuit decodes the address and
uses the buffer space to transfer data.

100. The conversion from parallel to serial data transmission and vice versa takes place inside
the interface circuits.
a) True
b) False

Explanation: By doing this the interface circuits provide a better interconnection between
devices.

101. The parallel mode of communication is not suitable for long devices because of ______
a) Timing skew
b) Memory access delay
c) Latency
d) None of the mentioned

102. The Interface circuits generate the appropriate timing signals required by the BUS control
scheme.
a) True
b) False

Explanation: The interface circuits generate the required clock signal for the synchronous
mode of transfer.

103. The status flags required for data transfer is present in _____
a) Device
b) Device driver
c) Interface circuit
d) None of the mentioned

Explanation: The circuit holds the flags which are required for data transfers.

104. User programmable terminals that combine VDT hardware with built-in microprocessor is
_____
a) KIPs
b) Pc
c) Mainframe
d) Intelligent terminals

105. Which most popular input device is used today for interactive processing and for the one
line entry of data for batch processing?
a) Mouse
b) Magnetic disk
c) Visual display terminal
d) Card punch

Explanation: In batch processing systems the processes are grouped into batches and they’re
executed in batches.

106. The use of spooler programs or _______ Hardware allows PC operators to do the
processing work at the same time a printing operation is in progress.
a) Registers
b) Memory
c) Buffer
d) CPU

Explanation: When the processor is busy with the process the data to be printed is stored in
the buffer.

“Standard I/O Interfaces”

107. ______ is used as an intermediate to extend the processor BUS.
a) Bridge
b) Router
c) Connector
d) Gateway

Explanation: The bridge circuit is basically used to extend the processor BUS to connect
devices.

108. ________ is an extension of the processor BUS.

a) SCSI BUS
b) USB
c) PCI BUS
d) None of the mentioned

Explanation: The PCI BUS is used as an extension of the processor BUS and devices
connected to it, is like connected to the Processor itself.

109. What is the full form of ISA?

a) International American Standard
b) Industry Standard Architecture
c) International Standard Architecture
d) None of the mentioned

Explanation: The ISA is an architectural standard developed by IBM for its PC’s.

110. The video devices are connected to ______ BUS.

a) PCI
b) USB
c) HDMI
d) SCSI

Explanation: The SCSI BUS is used to connect the video devices to a processor by providing a
parallel BUS.
111. SCSI stands for ___________
a) Signal Computer System Interface
b) Small Computer System Interface
c) Small Coding System Interface
d) Signal Coding System Interface

Explanation: The SCSI BUS is used to connect disks and video controllers.

112. ISO stands for __________

a) International Standards Organisation
b) International Software Organisation
c) Industrial Standards Organisation
d) Industrial Software Organisation

Explanation: The ISO is yet another architectural standard, used to design systems.

113. The system developed by IBM with ISA architecture is ______

a) SPARC
b) SUN-SPARC
c) PC-AT
d) None of the mentioned

114. IDE disk is connected to the PCI BUS using ______ interface.
a) ISA
b) ISO
c) ANSI
d) IEEE

115. IDE stands for _________

a) Integrated Device Electronics
b) International Device Encoding
c) Industrial Decoder Electronics
d) International Decoder Encoder

Explanation: The IDE interface is used to connect the hard disk to the processor in most of the
Pentium processors.

“Parallel Port”
116. The _____ circuit enables the generation of the ASCII code when the key is pressed.
a) Generator
b) Debouncing
c) Encoder
d) Logger

Explanation: The signal generated upon the pressing of a button is encoded by the encoder
circuit into the corresponding ASCII value.

117. To overcome multiple signals being generated upon a single press of the button, we make
use of ______
a) Generator circuit
b) Debouncing circuit
c) Multiplexer
d) XOR circuit

Explanation: When the button is pressed, the contact surfaces bounce and hence it might lead
to the generation of multiple signals. In order to overcome this, we use Debouncing circuits.

118. The best mode of connection between devices which need to send or receive large
amounts of data over a short distance is _____
a) BUS
b) Serial port
c) Parallel port
d) Isochronous port

Explanation: The parallel port transfers around 8 to 16 bits of data simultaneously over the
lines, hence increasing transfer rates.

119. The output of the encoder circuit is/are ______

a) ASCII code
b) ASCII code and the valid signal
c) Encoded signal
d) None of the mentioned

Explanation: The encoder outputs the ASCII value along with the valid signal which indicates
that a key was pressed.

120. The disadvantage of using a parallel mode of communication is ______

a) It is costly
b) Leads to erroneous data transfer
c) Security of data
d) All of the mentioned

Explanation: The parallel mode of data transfer is costly as it involves data being sent over
parallel lines.

121. In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel
port interface.
a) Valid bit
b) Idle bit
c) Interrupt enable bit
d) Status or data register
.

122. The Status flag circuit is implemented using _____

a) RS flip flop
b) D flip flop
c) JK flip flop
d) Xor circuit

Explanation: The circuit is implemented using the edge triggered D flip flop, that is triggered
on the rising edge of the valid signal.

123. In the output interface of the parallel port, along with the valid signal ______ is also sent.
a) Data
b) Idle signal
c) Interrupt
d) Acknowledge signal

Explanation: The idle signal is used to check if the device is idle and ready to receive data.

124. DDR stands for __________

a) Data Direction Register
b) Data Decoding Register
c) Data Decoding Rate
d) None of the mentioned

Explanation: This register is used to control the flow of data from the DATAOUT register.

125. In a general 8-bit parallel interface, the INTR line is connected to _______
a) Status and Control unit
b) DDR
c) Register select
d) None of the mentioned

“Serial Port”
126. The mode of transmission of data, where one bit is sent for each clock cycle is ______
a) Asynchronous
b) Parallel
c) Serial
d) Isochronous

Explanation: In the isochronous mode of transmission, each bit of the data is sent per each
cycle.

127. The transformation between the Parallel and serial ports is done with the help of ______
a) Flip flops
b) Logic circuits
c) Shift registers
d) None of the mentioned

Explanation: The Shift registers are used to output the data in the desired format based on the
need.

128. The serial port is used to connect basically _____ and processor.
a) I/O devices
b) Speakers
c) Printer
d) Monitor

Explanation: The serial port is used to connect the keyboard and other devices which input or
output one bit at a time.

129. The double buffer is used for _________

a) Enabling retrieval of multiple bits of input
b) Combining the input and output operations
c) Extending the buffer capacity
d) None of the mentioned

130. ______ to increase the flexibility of the serial ports.

a) The wires used for ports is changed
b) The ports are made to allow different clock signals for input and output
c) The drivers are modified
d) All of the mentioned

Explanation: The ports are made more flexible by enabling the input or output of different
clock signals for different devices.

131. UART stands for ________

a) Universal Asynchronous Relay Transmission
b) Universal Accumulator Register Transfer
c) Universal Asynchronous Receiver Transmitter
d) None of the mentioned

Explanation: The UART is a standard developed for designing serial ports.

132. The key feature of UART is _________

a) Its architectural design
b) Its simple implementation
c) Its general purpose usage
d) Its enhancement of connecting low speed devices
133. The data transfer in UART is done in ______
a) Asynchronous start stop format
b) Synchronous start stop format
c) Isochronous format
d) EBDIC format

Explanation: This basically means that the data transfer is done in asynchronous mode.

134. The standard used in serial ports to facilitate communication is _____

a) RS-246
b) RS-LNK
c) RS-232-C
d) Both RS-246 and RS-LNK

Explanation: This is a standard that acts as a protocol for message communication involving
serial ports.

135. In a serial port interface, the INTR line is connected to _____

a) Status register
b) Shift register
c) Chip select
d) None of the mentioned

“PCI BUS”
136. The PCI follows a set of standards primarily used in _____ PC’s.
a) Intel
b) Motorola
c) IBM
d) SUN

Explanation: The PCI BUS has a closer resemblance to IBM architecture.

137. The ______ is the BUS used in Macintosh PC’s.

a) NuBUS
b) EISA
c) PCI
d) None of the mentioned

Explanation: The NuBUS is an extension of the processor BUS in Macintosh PC’s.

138. The key feature of the PCI BUS is _________

a) Low cost connectivity
b) Plug and Play capability
c) Expansion of Bandwidth
d) None of the mentioned

Explanation: The PCI BUS was the first to introduce plug and play interface for I/O devices.

139. PCI stands for _______

a) Peripheral Component Interconnect
b) Peripheral Computer Internet
c) Processor Computer Interconnect
d) Processor Cable Interconnect

Explanation: The PCI BUS is used as an extension for the processor BUS.

140. The PCI BUS supports _____ address space/s.

a) I/O
b) Memory
c) Configuration
d) All of the mentioned

Explanation: The PCI BUS is mainly built to provide a wide range of connectivity for devices.

141. ______ address space gives the PCI its plug and plays capability.
a) Configuration
b) I/O
c) Memory
d) All of the mentioned

Explanation: The configuration address space is used to store the details of the connected
device.

142. _____ provides a separate physical connection to the memory.

a) PCI BUS
b) PCI interface
c) PCI bridge
d) Switch circuit

Explanation: The PCI bridge is a circuit that acts as a bridge between the BUS and the
memory.

143. When transferring data over the PCI BUS, the master as to hold the address until the
completion of the transfer to the slave.
a) True
b) False

Explanation: The address is stored by the slave in a buffer and hence it is not required by the
master to hold it.

144. The master is also called as _____ in PCI terminology.

a) Initiator
b) Commander
c) Chief
d) Starter

Explanation: The Master is also called as an initiator in PCI terminology as it is the one that
initiates a data transfer.

145. Signals whose names end in ____ are asserted in the low voltage state.
a) $
b) #
c) *
d) !
146. A complete transfer operation over the BUS, involving the address and a burst of data is
called _____
a) Transaction
b) Transfer
c) Move
d) Procedure

147. The device connected to the BUS are given addresses of ____ bit.
a) 24
b) 64
c) 32
d) 16

Explanation: Each of the devices connected to the BUS will be allocated an address during the
initialization phase.
148. The PCI BUS has _____ interrupt request lines.
a) 6
b) 1
c) 4
d) 3

Explanation: The interrupt request lines are used by the devices connected to raise the
interrupts.

149. _____ signal is sent by the initiator to indicate the duration of the transaction.
a) FRAME#
b) IRDY#
c) TMY#
d) SELD#

Explanation: The FRAME signal is used to indicate the time required by the device.

150. ______ signal is used to enable commands.

a) FRAME#
b) IRDY#
c) TMY#
d) c/BE#

Explanation: The signal is used to enable 4 command lines.

151. IRDY# signal is used for _______

a) Selecting the interrupt line
b) Sending an interrupt
c) Saying that the initiator is ready
d) None of the mentioned

Explanation: The initiator transmits this signal to tell the target that it is ready.

152. The signal used to indicate that the slave is ready is _____
a) SLRY#
b) TRDY#
c) DSDY#
d) None of the mentioned

153. DEVSEL# signal is used _________

a) To select the device
b) To list all the devices connected
c) By the device to indicate that it is ready for a transaction
d) None of the mentioned

Explanation: This is signal is activated by the device after it as recognized the address and
commands put on the BUS.

154. The signal used to initiate device select ________

a) IRDY#
b) S/BE
c) DEVSEL#
d) IDSEL#

Explanation: This signal is used to initialization of device select.

155. The PCi BUS allows us to connect _______ I/O devices.

a) 21
b) 13
c) 9
d) 11

Explanation: The PCI BUS allows only 21 devices to be connected as only the higher order 21
bits of the 32 bit address space is used to specify the device.

“SCSI BUS”
156. The key features of the SCSI BUS are _________
a) The cost effective connective media
b) The ability overlap data transfer requests
c) The highly efficient data transmission
d) None of the mentioned

Explanation: The SCSI BUS can overlap various data transfer requests by the devices.

157. In a data transfer operation involving SCSI BUS, the control is with ______
a) Initiator
b) Target
c) SCSI controller
d) Target Controller
View Answer
Answer: d
Explanation: The initiator involves in the arbitration process and after winning the BUS it’ll
hand over the control to the target controller.

158. In SCSI transfers the processor is not aware of the data being transferred.
a) True
b) False

Explanation: The processor or the controller is unaware of the data being transferred.

159. What is DB(P) line?

a) That the data line is carrying the device information
b) That the data line is carrying the parity information
c) That the data line is partly closed
d) That the data line is temporarily occupied

160. The BSY signal signifies _________

a) The BUs is busy
b) The controller is busy
c) The Initiator is busy
d) The Target is Busy

Explanation: This signal is generally initiated when the BUS is currently occupied in an
operation.

161. The SEL signal signifies _________

a) The initiator is selected
b) The device for BUS control is selected
c) That the target is being selected
d) None of the mentioned

Explanation: This signal is usually asserted during the selection or reselection process.

162. ________ signal is asserted when the initiator wishes to send a message to the target.
a) MSG
b) APP
c) SMS
d) ATN
Explanation: The ATN signal is short for attention, which is used to intimate the target that the
initiator sent a message to it.

163. The MSG signal is used _________

a) To send a message to the target
b) To receive a message from the mailbox
c) To tell that the information being sent is a message
d) None of the mentioned
View Answer
Answer: c
Explanation: None.

164. _____ is used to reset all the device controls to their startup state.
a) SRT
b) RST
c) ATN
d) None of the mentioned

165. The SCSI BUS uses ______ arbitration.

a) Distributed
b) Centralised
c) Daisy chain
d) Hybrid

Explanation: The SCSI uses distributed arbitration to select the device to give the BUS control.

166. SCSI stands for ________

a) Small Computer System Interface
b) Switch Computer system Interface
c) Small Component System Interface
d) None of the mentioned

Explanation: The SCSI BUS is one of the expansion BUSes used in a system..

167. A narrow SCSI BUS has _____ data lines.

a) 6
b) 8
c) 16
d) 4

Explanation: The SCSI BUS which is narrow is capable of transferring 8 bits of data at a time.

168. Single ended transmission means _________

a) That all the signals have a similar bit pattern
b) That the signals have a common source
c) That the signals have a common ground return
d) That the signals have a similar voltage signature

Explanation: These type of signals are a common feature of the SCSI BUS.

169. HVD stands for _________

a) High Voltage Differential
b) High Voltage Density
c) High Video Definition
d) None of the mentioned

Explanation: This is a type of signaling which uses 5v of current.

170. For better transfer rates on the SCSI BUS the length of the cable is limited to ______
a) 2m
b) 4m
c) 1.3m
d) 1.6m

Explanation: To increase the transmission rate in SCSI in SE mode of transfer the wire length
is restricted to 1.6m.

171. The maximum number of devices that can be connected to SCSI BUS is ______
a) 12
b) 10
c) 16
d) 8

172. The SCSI BUS is connected to the processor through _____

a) SCSI Controller
b) Bridge
c) Switch
d) None of the mentioned

Explanation: This is used to coordinate and monitor the data transfer over the BUS.

173. The mode of data transfer used by the controller is _____

a) Interrupt
b) DMA
c) Asynchronous
d) Synchronous

174. The data is stored on the disk in the form of blocks called _____
a) Pages
b) Frames
c) Sectors
d) Tables

Explanation: The data is stored on the disk in the form of a collection of blocks called as
sectors.

“USB ”
175. The transfer rate, when the USB is operating in low-speed of operation is _____
a) 5 Mb/s
b) 12 Mb/s
c) 2.5 Mb/s
d) 1.5 Mb/s

Explanation: The USB has two rates of operation the low-speed and the full-speed one.

176. The high speed mode of operation of the USB was introduced by _____
a) ISA
b) USB 3.0
c) USB 2.0
d) ANSI

Explanation: The high-speed mode of operation was introduced with USB 2.0, which enabled
the USB to operate at 480 Mb/s.

177. The sampling process in speaker output is a ________ process.

a) Asynchronous
b) Synchronous
c) Isochronous
d) None of the mentioned

Explanation: The isochronous process means each bit of data is separated by a time interval.
178. The USB device follows _______ structure.
a) List
b) Huffman
c) Hash
d) Tree

Explanation: The USB has a tree structure with the root hub at the centre.

179. The I/O devices form the _____ of the tree structure.
a) Leaves
b) Subordinate roots
c) Left subtrees
d) Right subtrees

Explanation: The I/o devices form the leaves of the structure.

180. USB is a parallel mode of transmission of data and this enables for the fast speeds of data
transfers.
a) True
b) False

Explanation: The USB does a serial mode of data transfer.

181. In USB the devices can communicate with each other.

a) True
b) False

Explanation: It allows only the host to communicate with the devices and not between
themselves.

182. The device can send a message to the host by taking part in _____ for the communication
path.
a) Arbitration
b) Polling
c) Prioritizing
d) None of the mentioned

183. When the USB is connected to a system, its root hub is connected to the ________
a) PCI BUS
b) SCSI BUS
c) Processor BUS
d) IDE

Explanation: The USB’s root is connected to the processor directly using the BUS.

184. The devices connected to USB is assigned a ____ address.

a) 9 bit
b) 16 bit
c) 4 bit
d) 7 bit

Explanation: To make it easier for recognition the devices are given 7 bit addresses.

185. The USB address space can be shared by the user’s memory space.
a) True
b) False

Explanation: The USB memory space is not under any address spaces and cannot be
accessed.
186. The initial address of a device just connected to the HUB is ________
a) AHFG890
b) 0000000
c) FFFFFFF
d) 0101010

Explanation: By standard, the usual address of a new device is zero.

187. Locations in the device to or from which data transfers can take place is called ________
a) End points
b) Hosts
c) Source
d) None of the mentioned

188. A USB pipe is a ______ channel.

a) Simplex
b) Half-Duplex
c) Full-Duplex
d) Both Simplex and Full-Duplex

Explanation: This means that the pipe is bi-directional in sending messages or information.

189. The type/s of packets sent by the USB is/are _______

a) Data
b) Address
c) Control
d) Both Data and Control

Explanation: This means that the USB gets both data and control signals required for the
transfer operation.

190. The first field of any packet is _____

a) PID
b) ADDR
c) ENDP
d) CRC16

Explanation: The PID is the field that is used to identify the device (the device id).

191. The 4 bit PID’s are transmitted twice.

a) True
b) False

Explanation: The fields are transmitted twice, once with the true values and the second time
with the complemented values.

192. The last field in the packet is ______

a) PID
b) ADDR
c) ENDP
d) CRC

Explanation: The last 5 bits of the packet is used for error checking, that is cyclic redundancy
check.

193. The CRC bits are computed based on the values of the _____
a) PID
b) ADDR
c) ENDP
d) Both ADDR and ENDP
Explanation: The CRC bits are calculated based on the values of the address and endp.

194. The data packets can contain data upto ______

a) 512 bytes
b) 256 bytes
c) 1024 bytes
d) 2 KB

195. The most important objective of the USB is to provide ______

a) Isochronous transmission
b) Plug and play
c) Easy device connection
d) All of the mentioned

Explanation: The above are all the common features of the USB.

196. The transmission over the USB is divided into ____

a) Frames
b) Pages
c) Packets
d) Tokens

Explanation: To support the isochronous mode of operation the usb transmission is divided
into frames.

197. The _____ signal is used to indicate the beginning of a new frame.
a) Start
b) SOF
c) BEG
d) None of the mentioned

Explanation: The SOF(State Of Frame) is used to indicate the beginning of a new frame.

198. The SOF is transmitted every ______

a) 1s
b) 5s
c) 1ms
d) 1Us

199. The power specification of usb is _____

a) 5v
b) 10v
c) 24v
d) 10v

2marks questions
1. what is memory mapped I/O?
When the I/O devices share the same address space,the arrangement is called
memory mapped I/O.
2. What is program controlled I/O?
In program controlled I/O , the processor repeatedly checks a status flag to achieve
the required synchronization between the processor and an input and output device
3. what are the various mechanisms for implementing I/O operations?
• Program controlled I/O
• Interrupts
• DMA
4. what are vectored interrupts?
To reduce the time involved in the polling process, a device requesting an interrupt
may identify itself directly to the processor. Then the , processor can immediately
 start executing the corresponding ISR. The schemes based on this approach is
called vectored interrupts.
5. when the privilege exception arises?
An attempt to execute a privileged instruction while in the user mode leads to a
special type of interrupt called a privilege exception.
6. what are the 2 independent mechanisms for controlling interrupt request?
• At the device end, an interrupt enable bit in a control register determines whether
the device is allowed to generate an interrupt request.
• At the processor end, either an interrupt enable bit in the PS or a priority structure
determines whether a given interrupt request will be accepted.
7. what is time slicing?
With this technique each program runs for a short period called a time slice,then
another program runs for its time slice and so on.
8. What is DMA?
Transfer of a block of data directly between an external device and main memory,
with out continuous intervention by the processor is called DMA.
9. What is DMA controller?
DMA transfers are performed by a control circuit that is part of the I/O device
interface. This cuircuit is known as DMA controller.
10. What is cycle stealing?
The processor originates most memory access cycles and the DMA controller can be
said to stael memory cyckles from the processor.This technique is known as cycle
stealing.
11. What is bus arbitration?
It is the process by which the next device becomes the bus master is selected and
bus master ship is transferred to it.
12. what are the three types of buses?
• Address bus
• Data bus
• Control bus
13. What are the objectives of USB?
• Simple
• Low cost
• Easy to use
• Supports wide range of data transfer characteristics.
• Plug and play mode of operation
14. what is synchronous bus?
In this, all devices derive timing information from a common clock line.
15. what is asynchronous bus?
In this, all devices do not derive timing information from a common clock line. It uses
handshake between the master and the slave.
16. What is DMA? Mention its advantages.
To transfer large blocks of data at high Speed, between EXTERNAL devices & Main
Memory, without intervention of processor is called DMA approach.
Advantages:- i) high speed of data transfer
ii)Large block of data can be transferred.
iii) processor performance will be better
17. Mention the advantage of USB.
• Simple
• Low cost
• Easy to use
 • Supports wide range of data transfer characteristics.
• Plug and play mode of operation

18. What does isochronous data stream means?

Isochronous Transfers are used for transmitting real-time information such as audio and
video data, and must be sent at a constant rate. USB isochronous data streams are
allocated a dedicated portion of USB bandwidth to ensure that data can be delivered at
the desired rate.
19. What is distributed arbitration?
All devices waiting to use the bus has to carry out the arbitration process-no central arbiter.
Each device on the bus is assigned with a 4-bit identification number identification number.
One or more devices request the bus by asserting the start-arbitration signal and place their
identification number on the four open collector lines. One among the four is selected using
the code on the lines and one with the highest ID number
20. How interrupt requests from multiple devices can be handled?
When more than one device raises an interrupt request signal, then additional
information is needed to decide which device to be considered first. The following
methods are used to decide which device to select: Polling, Vectored Interrupts, and
Interrupt Nesting.
21. Define an interrupt. ?
An interrupt is a signal sent to the processor that interrupts the current process. It may
be generated by a hardware device or a software program. A hardware interrupt is often
created by an input device such as a mouse or keyboard.
22. What are the possible data transfer modes available with peripherals. ?
Data transfer to and from the peripherals may be done in any of the three
possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).

23. Name and give the purpose of widely used bus standard?
ISA - Industry Standard Architecture
EISA - Extended Industry Standard Architecture
MCA - Micro Channel Architecture
VESA - Video Electronics Standards Association
PCI - Peripheral Component Interconnect
PCI Express (PCI-X)
PCMCIA - Personal Computer Memory Card Industry Association (Also called PC
bus)
AGP - Accelerated Graphics Port
SCSI - Small Computer Systems Interface
24. What is priority interrupt?
A priority interrupt is a system which decides the priority at which various devices, which
generates the interrupt signal at the same time, will be serviced by the CPU. The system has
authority to decide which conditions are allowed to interrupt the CPU, while some other
interrupt is being serviced.
25. Why does DMA have priority over the CPU when both request a memory transfer?
DMA seems to have priority because when the DMA transfer is not happening, the CPU has
the memory bus all the time. DMA works by “cycle stealing” bus cycles from the CPU’s
access to memory bus. On modern processors, this has to do with transferring data between
the cache and memory via the memory controller. The CPU cores can continue to process
instructions and access cache.
DMA needs priority to prevent overrun and under run. DMA is used primarily for input and
output.

26. What is the Advantage of using interrupt initiated data transfer over transfer under
program control without interrupt?
The main advantage is reduced latency. The processor has to temporarily halt it's work
in programmed I/O, whereas in interrupt I/O, the processor continues to perform and
only halts when interrupt is received.
27. Why we need DMA?
Advantages of DMA include:
high transfer rates, fewer CPU cycles for each transfer.
CPU and DMA run concurrently under cache mode.

28. What is interrupt service routine?

An ISR (also called an interrupt handler) is a software process invoked by

an interrupt request from a hardware device. It handles the request and sends it to the CPU,
interrupting the active process. When the ISR is complete, the process is resumed.

29. What is bus master and slave master?

During one BCLK, one and only one of the components connected the bus is the bus master,
each of the other devices is either a slave or inactive. The bus master initiates a bus transfer,
while the slave is passive because it can only wait for a request from the bus master.

30. What are the uses of interrupts?

Recovery from errors

Debugging
Communication between programs
Use of interrupts in operating system
31. Define vectored interrupts.

In order to reduce the overhead involved in the polling process, a device requesting an
interrupt may identify itself directly to the CPU. Then, the CPU can immediately start
 executing the corresponding interrupt-service routine. The term vectored interrupts refers
to all interrupt-handling schemes base on this approach.
32. Name any three of the standard I/O interface.

1. SCSI (small computer system interface),bus standards

2. Back plane bus standards
3. IEEE 796 bus (multibus signals)
4. NUBUS
5. IEEE 488 bus standard
33. why program controlled I/O is unsuitable for high-speed data transfer?

1. in program controlled i/o considerable overhead is incurred.. because several program

instruction have to be executed for each data word transferred between the external
devices and MM.

2. many high speed peripheral; devices have a synchronous modes of operation. that is data
transfer are controlled by a clock of fixed frequency, independent of the cpu.

34. what is the function of i/o interface?

The function is to coordinate the transfer of data between the cpu and external devices.

35. .what is NUBUS?

A NUBUS is a processor independent, synchronous bus standard intended for use in 32 bit
micro processor system. It defines a backplane into which upto 16 devices may be plugged
each in the form of circuit board of standard dimensions.
36. Define interface.

The word interface refers to the boundary between two circuits or devices.

37. What is programmed I/O?

Data transfer to and from peripherals may be handled using this mode. Programmed I/O
operations are the result of I/O instructions written in the computer program.

38. Describe different speed of operation of USB?

The USB supports two speeds of operation called low The USB supports two speeds
of operation, called low speed (1.5 megabits/s) and full-speed (12 megabits/s).
The most recent revision of the bus specification (USB 2.0) introduced a third speed
of operation, called high-speed (480 megabits/s).
39. Types of SCSI
SCSI1(Narrow SCSI)
SCSI2(wide SCSI)
SCSI3(ultra wide SCSI)
40. Advantages of SCSI over IDE
The modern SCSI can even perform serial communication with an improved data rates,
better fault association, enhanced cable connections and longer reach. The other advantage
of SCSI drives over IDE is, it can deactivate the device that is still working
 41. Advantages and dis advantages of parallel port.
Parallel offers the advantage of transferring 8 data bits per I/O clock cycle, but at the disadvantage
of many more pins required on the devices. Overall, the parallel mode offers the advantage of faster
loading of the registers, but with the disadvantage of requiring more interconnect traces. On some
of the DDS devices (AD9852/54/58) the parallel port offers the advantage of addressing single bytes
in the device register set

42. What is the key feature of PCI bus ?

The PCI BUS was the first to introduce plug and play interface for I/O devices.
43. The PCI BUS supports which address space/s.
The PCI BUS is mainly built to provide a wide range of connectivity for devices.
It supports i/o,memory, configuaration