Structure of von Neumann machine

4.0 Assembly Language Programming

• On completing this chapter, the students should be

able to;
• Explain Number systems.
• Perform Integer arithmetic
• Discuss hardware schemes that are used to perform
addition, subtraction, multiplication and division.
• Explain floating-point representation, operation and
floating-point hardware schemes.

1.8
 4.1 Number Systems

• A number system uses a specific radix (base).

• Radices that are power of 2 are widely used in
digital systems.
• These radices include
– binary (base 2),
– quaternary (base 4),
– octagonal (base 8), and
– hexagonal (base 16).
• An unsigned integer number A can be
represented using n digits in base b as follows:
1.9
 4.1 Number Systems

1.10
 4.1 Number Systems

• Consider the use of n digits to represent a real

number X in radix b such that the most
significant k digits represents the integral part
while the least significant m digits represents
the fraction part.
• The value of X is given by:

• Represent X=27.475 with k=5 and m=3

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 4.1 Number Systems

Radix Conversion Algorithm

– A radix conversion algorithm is used to convert a number
representation in a given radix, r1, into another
representation in a different radix, r2.
• Dividing Xint by r2 will result in a quotient and a remainder
Xrem
• Repeating the division process on the quotient and
retaining the remainders as the required digits until a zero
quotient is obtained will result in the required
representation of Xint in the new radix r2.
• Convert 506 to base 3

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 4.1 Number Systems

Radix Conversion Algorithm

– A repeated multiplication of the fractional part of X (Xf) by
r2 retaining the obtained integers as the required digits, will
result in the required representation of the fractional part in
the new radix.
– However, the fractional part conversion may not terminate
after a finite number of repeated multiplications.
• Convert 45.475 to binary
• Convert 45.475 to base 4
Example Consider the conversion of the decimal number
67.575 into binary. Here r1=10, r2=2, Xint=67, and
Xf=0.575.
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 4.1 Number Systems

• Negative Integer Representation

– There exists a number of methods for representation of
negative integers:
• The sign-magnitude,
• Radix complement, and
• Diminished radix complement.

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 4.1 Number Systems

• Sign-Magnitude
– The most significant bit (out of the n bits used to represent
the number) is used to represent the sign of the number
such that a “1’’ in the most significant bit position indicates
a negative number while a "0" in the most significant bit
position indicates a positive number.
– Remaining (n-1) bits are used to represent the magnitude.
– Although simple, the sign-magnitude representation is
complicated when performing arithmetic operations.
– In particular, the sign bit has to be dealt with separately from
the magnitude bits.
• Represent -18 and 25 and add them
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 4.1 Number Systems

• Radix Complement
– A positive number is represented the same way as in
the sign magnitude.
– However, a negative number is represented using the
b’s complement (for base b numbers).
• Examples
• Represent -18 and 25 and add them
• Represent -20 and 19 and add them

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 4.1 Number Systems

• Diminished Radix Complement

– This representation is similar to the radix complement
except for the fact that no “1” is added to the least
significant bit after complementing the digits of the
number, as is done in the radix complement.
– The main disadvantage of the diminished radix
representation is the need for a correction factor
whenever a carry is obtained from the most
significant bit while performing arithmetic operations.
• Represent -6 and 19 with 6 digits and add them

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 4.1 Number Systems

1.18
 4.2 Integer Arithmetic

1.19
 4.2 Integer Arithmetic

1.20
 4.2 Integer Arithmetic

• Two's Complement Arithmetic

– Addition:
• Addition of two n-bit numbers in 2's complement can
be performed using an n-bit adder.
• Any carry-out bit can be ignored without affecting the
correctness of the results, as long as the results of
the addition is in the range -2n-1 to +2n-1 – 1
• Consider the addition of the two 2’s complement
numbers (-7) and (+4). This addition can be carried
out as (-7) + (+4) = -3, that is, 1001 + (0100) = 1101,
a (-3) in 2’s complement.

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 4.2 Integer Arithmetic

• Example Consider adding the two 2’s complement numbers

(-7) and (-6). The addition can be done as (+7) + (+6) =
+13, that is, 0111 + (0110) = 1101, a wrong result. This is
because the result exceeds the largest value (+7).
• Example add the two 2’s complement numbers (-7) and (-
4). The addition can be done as (-7)+(-4) = -11, that is,
1001+ (1100) = 0101, a wrong result. This is because the
result is less than the smallest value (-8). Notice that the
original numbers are negative while the result is positive.
• From above, we can make the following observation: when
two numbers (both positive or both negative) are added,
then overflow can be detected if and only if the result has
1.22an opposite sign to the added numbers.
 4.2 Integer Arithmetic

1.23
 4.2 Integer Arithmetic

• Hardware Structures for Addition and Subtraction of

Signed Numbers:
• The addition of two n-bit numbers A and B requires a basic
hardware circuit that accepts three inputs, i.e., ai, bi and ci-1
• These three bits represent respectively the two
current bits of the numbers A and B (at position i)
and the carry bit from the previous bit position (at
position i-1).
• The circuit should produce two outputs, i.e.,
representing respectively the sum and the carry.
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 4.2 Integer Arithmetic

• The circuit should produce two outputs, that is,

si and ci representing respectively the sum and
the carry, according to the following truth-
table..

1.25
 4.2 Integer Arithmetic

• Two's Complement Arithmetic

– Hardware Structures for Addition and Subtraction of Signed
Numbers:
• The output logic functions are given by
And
• The circuit used to implement these two functions is called
a fulladder (FA).

1.26
 4.2 Integer Arithmetic

1.27
 4.2 Integer Arithmetic

1.28
 4.2 Integer Arithmetic

1.29
 4.2 Integer Arithmetic

• One of the main drawbacks of the CRT circuit is the

expected long delay between the time the inputs are
presented to the circuit until the final output is
obtained.
• This is because of the dependence of each stage on
the carry output produced by the previous stage.
• This chain of dependence makes the CRT adder’s
delay O(n), where n is the number of stages in the
adder.

1.30
 4.2 Integer Arithmetic

• To speed up the addition process, we introduce

addition circuits in which the chain of dependence
among the adder stages must be broken.
• A number of fast addition circuits exist, among these
is the carry-look-ahead (CLA).
• Consider the CRT adder circuit. The two logic
functions realized are and

1.31
 4.2 Integer Arithmetic

• The functions can be rewritten in

terms of two new subfunctions, the carry generate, Gi = aibi
and the carry propagate, Pi = ai + bi.
• Using these two new subfunctions, ci = Gi + Pici-1.
• Now we can write the series of carry outputs from the
different stages as follows.

1.32
 4.2 Integer Arithmetic

• sequence of carry outputs shows total independence

among the diff carries (broken carry chain).
• Below is the overall architecture of a 4-bit CLA
adder.
• The first one is used to generate the Gis and the Pis,
with one gate delay.
• The second is used to create all the carry output,
with two gate delay.
• The third block is used to generate all the sum
outputs, with equivalent one gate delay.
1.33
 4.2 Integer Arithmetic

1.34
 4.2 Integer Arithmetic

Two's Complement Arithmetic

– Multiplication:
• The two input arguments are the multiplier Q given by:
and the multiplicand M given by:
.
• No of methods exist for performing multiplication.
– The paper and Pencil Method (for unsigned numbers)
» This is the simplest method for two unsigned numbers.
» The above multiplication can be performed using an
array of cells each consisting of a FA and an AND.
» Each cell computes a given partial product.

1.35
 4.2 Integer Arithmetic

Multiplication - The paper and Pencil Method

1.36
 4.2 Integer Arithmetic

• What characterizes this method is the need for

adding n partial products regardless of the values of
the multiplier bits.
• If a bit of the multiplier is 0, then there should be no
need for computing the corresponding partial product.

1.37
 4.2 Integer Arithmetic

• Multiplication: The Add-Shift Method

• Multiplication is performed as a series of (n) conditional
addition and shift operations such that if the given bit of the
multiplier is 0 then only a shift operation is performed,
• While if the given bit of the multiplier is 1 then addition of
the partial product and a shift operation are performed.
• Multiply two unsigned numbers 11 and 13.
• A is a 4-bit register and is initialized to 0s and C is the
carry bit from the most significant bit position.
• The process is repeated n = 4 times (the number of bits in
the multiplier Q).

1.38
 4.2 Integer Arithmetic

• The process is repeated n = 4 times (the number of

bits in the multiplier Q).
• If the bit of the multiplier is “1”, then A A+M
and the concatenation of AQ is shifted one bit
position to the right.
• If, on the other hand, the bit is “0”, then only a shift
operation is performed on AQ. The structure
required to perform such an operation is shown
below

1.39
 4.2 Integer Arithmetic

1.40
 4.2 Integer Arithmetic

1.41
 4.2 Integer Arithmetic

– Multiplication: The Booth’s Algorithm

– two bits of the multiplier, Q(i)Q(i-1), (0 ≤ i ≤ n −1), are
inspected at a time.
– The action taken depends on the binary values of the
two bits, such that:
» if the two values are respectively 01, then A← A + M
» if the two values are 10, then A← A−M
» No action is needed if the values are 00 or 11.
- In all four cases, an arithmetic shift right operation
on the concatenation of AQ is performed.
• Consider multiplying two positive numbers M = 0111
(7) and Q = 0011 (3) and assuming that n = 4.
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 4.2 Integer Arithmetic

– Multiplication: The Booth’s Algorithm

1.43
 4.2 Integer Arithmetic

– Multiplication of 7 and 3: The Booth’s Algorithm

1.44
 4.2 Integer Arithmetic

– Multiplication of 7 and -3: The Booth’s Algorithm

1.45
 4.2 Integer Arithmetic

• The hardware structure shown below can be used to

perform the operations required by the Booth’s
algorithm.
• It consists of an ALU that can perform the add/sub
operation depending on the two bits Q(0)Q(-1).
• A control circuitry is also required to perform the
ASR (AQ) and to issue the appropriate signals
needed to control the number of cycles.

1.46
 4.2 Integer Arithmetic

1.47
 4.2 Integer Arithmetic

• The main drawbacks of the Booth’s algorithm are

the variability in the number of add/sub operations
and the inefficiency of the algorithm when the bit
pattern in Q becomes a repeated pair of a 0 (1)
followed by a 1(0).
• This last situation can be improved if three rather
than two bits are inspected at a time.

1.48
 Game
Start at the bottom left square and move up, down, left or
right until you reach the finish. Add the numbers as you
go, can you make exactly 53?

4 9 7 7 4 Finish
8 9 4 5 7
6 6 4 9 9
7 8 8 8 6
Start 5 5 6 5 5
2.2
 4.2 Integer Arithmetic

– Division:
• Among the four basic arithmetic operations, division is
considered the most complex and most time
consuming.
• An integer division operation takes two arguments, the
dividend X and the divisor D.
• It produces two outputs, the quotient Q and the
remainder R.
• The four quantities satisfy the relation X = Q× D + R
where R < D

1.50
 4.2 Integer Arithmetic

– A number of complications arise when dealing with

division:
–D=0
– the requirement that the resulting quotient should not
exceed the capacity of the register holding it.
» This can be satisfied if Q < 2n−1 , where n is the
number of bits in the register holding the quotient.
This implies that the relation X < 2n−1D must also be
satisfied. Failure to satisfy any of the above
conditions will lead to an overflow condition.

1.51
 4.2 Integer Arithmetic

• The division algorithm assumes that all values

involved, that is, divided, divisor, quotient, and
remainder are interpreted as fractions.
• In order to obtain a positive fractional quotient Q =
0q1q2…qn-1 , the division operation is performed as a
sequence of repeated subtractions and shifts.
• In each step, the remainder should be compared
with the divisor D. If the remainder is larger, then
the quotient bit is set to “1”; otherwise the quotient
bit is set to “0”.
1.52
 4.2 Integer Arithmetic

• This can be represented by the following equation

• ri = 2ri-1 - qi x D where ri and ri-1 are the current and
the previous remainder, respectively, with r0 = X and i
= 1, 2, . . . , (n-1).
• Example Consider the division of a dividend X = 0.5 =
(0.100000) and a divisor D = 0.75 = (0.1100). The
process is illustrated in the following table.

1.53
 4.2 Integer Arithmetic

Resultant quotient Q=(0.101)=(5/8) and remainder R = (1/32).

These values are correct since X = QD + R = (5/8)(3/4) +1/32
= 1/2.
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 4.2 Integer Arithmetic

1.55
 4.2 Integer Arithmetic

1.56
 4.2 Integer Arithmetic

1.57
 4.2 Integer Arithmetic

1.58
 4.2 Integer Arithmetic

• Now we show the validity of the above process in the

case of integer values. In this case, the equation
• X = QD+R can be rewritten as 22n-2Xf = 2n-1Qf x 2n-1Df
+ 2n-1Rf , leading to Xf = Qf x Df + 2-(n-1)Rf where Xf, Df,
Qf and Rf are fractions.
• Example Consider the division of a dividend X = 32 =
(0100000) and a divisor D = 6 = (0110). The process
is illustrated in the following table.

1.59
 4.2 Integer Arithmetic

• The resultant quotient is Q = 0101 = (5) and

the remainder R = 0010 (2).
• These are correct values.
1.60
 4.2 Integer Arithmetic

• A hardware structure for binary division is shown in

the figure below,
• The divisor (D) and the contents of register A are
added using an (n+1)-bit adder.
• A control logic is used to perform the required shift left
operation.
• The comparison between the remainder and the
divisor is considered to be the most difficult step in
the division process.
• The way used above is to subtract D from 2ri-1 and if
result is negative, we set qi = 0. Hence restoring the
previous value by adding back the subtracted value.
1.61
 4.2 Integer Arithmetic

• The alternative is to use a non-restoring division

algorithm:
• Step #1: Do the following n times
• 1. If the sign of A is 0, shift left AQ and subtract D
from A; otherwise shift left AQ and add D to A.
• 2. If the sign of A is 0, set q0 = 1; otherwise set q0=0.
• Step #2: If the sign of A is 1, add D to A.
• Example Consider the division of a dividend X = 8 =
(1000) and a divisor D = 3 = (0011) using the non-
restoring algorithm. The process is illustrated in the
following table.

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 4.2 Integer Arithmetic

1.63
 4.2 Integer Arithmetic

– Division – Binary division structure.

1.64
 4.3 Floating-Point Arithmetic

• Floating-Point Representation (Scientific Notation)

• – A floating-point (FP) number can be represented in
the following form: ± m * be
• where m, called the mantissa, represents the fraction
part of the number and is normally represented as a
signed binary fraction,
• e represents the exponent, and
• b represents the base (radix) of the exponent..

1.65
 4.3 Floating-Point Arithmetic

• Floating-Point Representation (Scientific Notation)

– Steps required to add/subtract two floating-point
numbers:
– Compare the magnitude of the two exponents and
make suitable alignment to the number with the
smaller magnitude of exponent.
– Perform the addition/subtraction
– Perform normalization by shifting the resulting
mantissa and adjusting the resulting exponent.

1.66
 4.3 Floating-Point Arithmetic

• Floating-Point Representation (Scientific Notation)

1.67
 4.3 Floating-Point Arithmetic

• Floating-Point Representation (Scientific Notation)

– Steps required to multiply two floating-point numbers:
• Compute the exponent of the product by adding the
exponents together,
• Multiply the two mantissas, and
• Normalize and round the final product.

1.68
 4.3 Floating-Point Arithmetic

• Floating-Point Representation (Scientific Notation)

1.69
 4.3 Floating-Point Arithmetic

• Floating-Point Representation (Scientific Notation)

– Steps required to divide two floating-point numbers:
• Compute the exponent of the result by subtracting the
exponents,
• Divide the mantissa & determine the sign of the result,
and
• Normalize and round the resulting value, if necessary.

1.70
 4.3 Floating-Point Arithmetic

• Floating-Point Representation (Scientific Notation)

1.71
 4.3 Floating-Point Arithmetic

• The IEEE Floating-Point Standard

– There are basically two IEEE standard floating-point
formats:
• These are the basic and the extended formats.
• In each of these, IEEE defines two formats:
– the single-precision and
– the double-precision.
• The single-precision format is 32-bit and the double-
precision is 64-bit.
• The single extended format should have at least 44 bits
and the double extended format should have at least
80 bits.
1.72
 4.3 Floating-Point Arithmetic

• The IEEE Floating-Point Standard

– The IEEE single-precision representation:

– In the single-precision format, base 2 is used, thus

allowing the use of a hidden bit. The exponent field is
8 bits.

1.73
 4.3 Floating-Point Arithmetic

– The 8-bit exponent allows for any of 256 combinations.

Among these, two combinations are reserved for special
values. These are:
• e=0 is reserved for zero (with fraction m = 0) and
denormalized numbers (with fraction m≠0).
• e=255 is reserved for ±∞ (with fraction m=0) and not a
number (NaN) (with fraction m≠0).
– The single extended IEEE format extends the exponent field
from 8 to 11 bits and the mantissa field from 23+1 to 32
resulting in a total length of at least 44 bits.
– The single extended format is used in calculating
intermediate results.
1.74
 4.3 Floating-Point Arithmetic

• Double-precision IEEE Format

– The exponent field is 11 bits and the significant field is
52 bits.
– The format is:

1.75
 4.3 Floating-Point Arithmetic

• Characteristics of the IEEE single and double

floating-point formats

1.76
 4.4 Summary

• The last topic discussed in the chapter was floating-

point representation and arithmetic.
• We have also shown the basic architectures needed
to perform basic floating-point operations.
• We ended our discussion in the chapter with the
IEEE floating-point number representation.

1.77