DESIGN OF CODE CONVERTERS USING QCA

A PROJECT REPORT

Submitted by

E.JEEVAKARUNYA -921618106025
A.MONISHA -921618106045
P.T.SUGIRTHA KALAIVANI -921618106074
M.SNEKA -921618106085

in partial fulfillment for the award of the degree of

BATCHLER OF ENGINEERING
in
ELECTRONICS AND COMMUNICATION ENGINEERING

SBM COLLEGE OF ENGINEERING AND TECHNOLOGY,

DINDIGUL-624 005

ANNA UNIVERSITY: CHENNAI 600 025

JUNE 2022

i
 BONAFIDE CERTIFICATE

Certified that this Project titled “DESIGN OF CODE CONVERTERS USING

QCA” is the bonafide work of “E.JEEVAKARUNYA-921618106025, A.MONISHA
-921618106045, P.T.SUGIRTHAKALAIVANI-921618106074 M.SNEKA-
921618106085," who carried out the work under my supervision. Certified further, that to the
best of my knowledge and belief, the work reported herein does not form part of any other
thesis or dissertation on the basis of which a degree or an award was conferred on an earlier
occasion.

SIGNATURE SIGNATURE
Mr.R.SANKARANARAYANAN,M.E., Mr.V.RAJESH,M.E.,
HEAD OF THE DEPARTMENT, SUPERVISOR,
ASSISTANT PROFESSOR/ECE, ASSISTANT PROFESSOR/ECE,
Department of Electronics and Department of Electronics and
Communication Engineering, Communication Engineering,
SBM College of SBM College of
Engineering and Technology, Engineering and Technology,
Dindigul-624005. Dindigul-624005.

Submitted for the Project Viva Voce Examination held on

INTERNAL EXAMINER EXTERNAL EXAMINER

ii
 ACKNOWLEDGEMENT

We are grateful to our Almighty for His divine blessing and for our well-being
which was necessary to accomplish this project work successfully. We would also like to
thank our Parents for their support and encouragement.

We express our sincere gratitude to our beloved and Esteemed Chairman,

Dr.N.Jayaraj., MJF,D.Lit.,Ph.D.,D.Hons for his support towards this project.

We extend our sincere gratitude to our Principal Dr.G.Vijay

Chakravarthy.,M.E.,Ph.D., and our for his enthusiasm and support towards this project.

We wish to convey our acknowledgements to our CEO, Mr.J.Jaya

Simhaa.,M.E.,(Ph.D) for his support and inspiration towards this project.

We express our heartfelt appreciation to Mr.R.Sankaranarayanan,M.E., Assistant

Professor and Head, Department of Electronics and Communication Engineering,
for his constant care, motivation, reassurance and for being a source of inspiration
throughout this project and during the course of this semester.

We are much thankful to our Project Supervisor Mr.V.Rajesh,M.E., for his

valuable ideas which makes us to finish our work in a most successful manner.

We duly acknowledge the help extended by and Ms.A.Rosariyo,M.E., Tutor and

Project Co- ordinator for his timely guidance in the documentation and presentations
related to the project work.

We also take this opportunity to thank all the Teaching and Non-teaching faculty
members of Department of Electronics and Communication Engineering for their constant
support

iii
 ABSTRACT

Quantum dot Cellular Automata (QCA) is a new direction in creating logic circuits
based on nano technology. It is a promising alternative to CMOS technology with many
appealing features such as high speed, low power consumption and higher switching
frequency than transistor based technology. The code converters are the basic unit for
altering of data to perform arithmetic processes. In this work ,a novel configurable XOR
gate based binary to gray and 4-bitbinary to gray code converter, with a minimum number
of cells, has been proposed. The simulations are completed using QCA Designer.

iv
 TABLE OF CONTENTS

CHAPTER PAGE
TITLE
NO NO

ABSTRACT iv
LIST OF FIGURES viii
LIST OF TABLES ix
LIST OF ABBREVIATIONS x
1 INTRODUCTION 1
1.1 Background of QCA 1
1.2 Clocking in QCA 3
1.3 Basic QCA elements and gates 5
1.3.1 Non inverter gate or binary wire 5
1.3.2 Inverter gate 7
1.3.3 QCA majority voter 8

2 LITERATURE SURVEY 13

3 EXISTING SYSTEM 17

A Novel Design “Binary to Gray Converter” 17

3.1
with QCA Nanotechnology

3.2 CODE CONVERTERS 17

v
4 PROPOSED SYSTEM 20

4.1 Implementation of XOR/XNOR Designs

20
4.2 PROPOSED XOR/XNOR GATE 21

4.3 The Novel XOR/XNOR Design 21

4.4 Physical Verification 22

5 5.1 ELEMENTS OF QCA 25

5.1.1 Quantum Dot 25

5.1.2 Cell Structure 26
5.1.3 Clocking Scheme 28
5.1.4` QCA Wire 28
5.1.5 Memory Loop 28
5.1.6 Majority Logic Synthesis 30
5.2 Fundamental Logic Gates In QCA 31
5.3 Signal Routing 32
5.3.1 In plane Crossing 32
5.3.2` Multi-Layer Crossover 33
5.4 Software Tool 34
5.4.1 Key Features 34
5.4.2 Design Engines 35
5.4.3 Editing Features 35

6 CONCLUSION 37

REFERENCES 38

vi
 LIST OF FIGURES
PAGE
CHAPTER FIGURE
TITLE NO
NO NO

1 1.1 Basic QCA cell. 2

Operations of a QCA wire propagation by

1.2 application of Logic 0 and logic 1 1 to a QCA cell 3
at the input

1.3 Four phases of QCA clock zones. 4

1.4 Schematic of inter dot barriers in QCA clock 5

Binary wire, (a) representation, (b) QCA layout,
and (c) simulation results
1.5 6
Inverter gate, (a) representation, (b) QCA layout,
1.6 and (c) simulation results 7
Majority voter (MV) gate, (a) QCA representation,
1.7 (b) QCA layout, and (c) simulation results 9

OR gate, (a) QCA representation, (b) QCA layout,

1.8 10
and (c) simulation results.
AND gate, (a) QCA representation, (b) QCA
1.9 layout, and (c) simulation results 11

existing layout of exiting

3 3.1 19
21
4 4.1 The novel XOR/XNOR logic gate

vii
5 5.1 Quantum Dot 25

5.2 QCA cell 26

5.3 Clock Phase 27

5.4 QCA wire 28

QCA Memory Loop

5.5 29

5.6 QCA Memory Loop in a large layout 30

5.7 Majority voter 31

5.8 AND gate in QCA 31

5.9 OR gate in QCA 32

5.10 QCA inverter 32

5.11 In plane crossing of two QCA wires 33

5.12 Multi-layer crossing 34

5.13 QCA cell styles 36

viii
 LIST OF TABLES

CHAPTER TABLE PAGE

TITLE
NO NO NO

`1 1.1 Operation of QCA clock phases 4

2 3.2.1 TRUTH TABLE OF 3-BIT BINARY TO 18

GRAY CODE CONVERTER

TRUTH TABLE OF 4-BIT BINARY TO

3.2.2 18
GRAY CODE CONVERTER

4 4.4 Binary to Gray code converter 24

ix
 LIST OF ABBREVIATIONS

QCA Quantum dot Cellular Automata

CMOS Complementary Metal Oxide Semiconductor
CNT Carbon nano tubes
VLSI Very Large-Scale Integration
QCAD Quad Citians Affirming Diversity
ALU Arithmetic Logic Unit
NSA National Security Agency
EPS Encapsulated PostScript

x
 CHAPTER-1

INTRODUCTION

In recent years, the use of CMOS technology is limited by high

consumption, low speed, and density beyond 10 nm. To overcome these
problems, a number of researchers have been ascertained to find the solution for
this classical CMOS technology which is quantum-dot cellular automata (QCA)
used for high-speed application.

Nowadays, QCA transistor-less technology, single electron transistor

(SET), and carbon nano tube (CNT) are being used as an alternative to CMOS
technology. The use of QCA on the nano scale has a promising future because
of its ability to achieve high performance in terms of clock frequency, device
density, and power consumption if it is compared to similar implementations
with conventional VLSI technology. These advantages make the proposed QCA
technology useful for high-performance electronic applications applied on
mobile or autonomous devices where power consumption and real-time
processing low are needed.

Recently, using QCA technology for electronic modules design has

become widely used. The memory circuits have been proposed. The reversible
full adder/subtractor and multiplier has been designed. A sequential circuits
based on QCA technology has been proposed. Adecoder circuit based on QCA
technology has been developed.

1.1 Background of QCA

In 1993, Craig Lent proposed a new concept called quantum-dot cellular

automata (QCA). This emerging technology has made a direct deviation to
replace conventional CMOS technology based on silicon. QCA generally uses
arrays of coupled quantum dots in order to implement different Boolean logic
1
functions. QCA or quantum-dot cellular automata as its name is pronounced
uses the quantum mechanical phenomena for the physical implementation of
cellular automata. In the general case, conventional digital technologies require
a range of voltages or currents to have logical values, whereas in QCA
technology, the position of the electrons gives an idea of the binary values. The
advantages of this technology are especially given in terms of speed (range of
terahertz), density (50 Gbits/cm2) and in terms of energy or power dissipation
(100 W/cm2).

QCA is based essentially on a cell. Each cell represents a bit by a suitable

charge configuration as shown in Figure 1. It consists of four quantum dots and
two electrons charge. Under the effect of the force of Colombian repulsion, the
two electrons can be placed only in two quantum sites diametrically opposite.

Figure 1.1Basic QCA cell.

A QCA cell is composed of four points with one electron each in two of
the four points occupying diametrically opposite locations. The question that
arises in this case is why do electrons occupy quantum dots of opposite or
diagonal corner To answer this question, it is enough to have an idea about the
principle of the repulsion of Coulomb, which is less effective with respect to the

2
electrons when they are in adjacent quantum dots. The points are coupled to one
another by tunnel junctions.

Thus, the internal effect of the cell highlights two configurations possible;
each one will be used to represent a binary state “0” or “1.” A topology of QCA
is a paving of cells QCA. The interaction between the cells makes it possible to
transmit information which gives the possibility of replacing physical
interconnection of the devices. The information (logic 0 or logic 1) can
propagate from input to the output of the QCA cell only by taking advantage of
the force of repulsion as shown in Figure 2.

Figure1. 2.Operations of a QCA wire propagation by application of logic 0 and

logic 1 1 to a QCA cell at the input.

1.2 Clocking in QCA

Clocking is an important term in QCA design. In order to propagate the

information through QCA without any random adjustments of QCA cells, it is
necessary to make a clock to guarantee the same data putting from input to the
output. According to Figure 3, timing in QCA is obtained by clocking in four
distinct periodic phases namely Switch, Release, Relax, and Hold.

3
 Figure 1.3.Four phases of QCA clock zones.

Based on the position of the potential barrier, the arrays of QCA cells in
each phase have different polarizations. There are four phases, and every phase
has its own polarizations as shown in Table 1.

Clock phase Potential barrier Polarization state of the cells

Hold Held high Polarized

Switch Low to high Polarized

Relax Low Un polarized

Release Lowered Un polarized

Table 1.1 Operation of QCA clock phases.

From Table 1, during the “Switch” phase of the clock, the QCA cell
begins without polarization and switches to polarized state while the potential
barrier has been raised from low to high. In the “‘Hold” phase, the polarization
state is preserved as the preceding phase and the potential barrier is high. From
the “‘Release” phase, the potential barrier is lowered and the cells become un
polarized. In “Relax” phase, the potential barrier remains lowered and the cells

4
keep at non polarized state. This phase, the cells are ready to switch again. This
way information is propagated in QCA circuits by keeping the ground-state
polarization all the time. Figure 4 illustrates the polarizations and inter dot
barriers of the QCA cells in each of the QCA clock zones.

Figure 1.4. Schematic of inter dot barriers in QCA clock.

1.3 Basic QCA elements and gates

Many architectures of logic devices can be designed by using adequate

arranging of QCA cells. The biggest advantage of this wireless technology is
that the logic is carried by the cells themselves. The fundamental QCA logic is
binary wire, inverter, and majority voter. These QCA logic gates are evaluated
and simulated using the QCA Designer tool version 2.0.3.

1.3.1. Non inverter gate or binary wire

The great advantage of cell QCA is that all the close cells are aligned on a
specific polarization, which depends on the input cell or the driver cell. Hence,
by arranging the cells side-by-side according to the type “0” or “1” applied to
the input cell, any logic can be transferred. Consequently, this gate can play the
role of a wire or binary interconnection or non inverter gate as shown

5
in Figure 5(a). The layout of each cell given by binary wire is represented
in Figure 5(b).

Figure 1.5 Binary wire, (a) representation, (b) QCA layout, and (c) simulation
results.

The simulation results of the non inverter gate are presented

in Figure 1.5(c). One waveform with one frequency is applied to the input (In),
one waveform for the first clock (Clk 0), and one waveform for the binary wire
outputs (Out). From simulation results of binary wire given by Figure 1.5(c), the
expression from the output pulses of the non inverter gate can be deduced,
which is given by Eq. (1):

Out =In.Clk¯ 0 (1)

6
1.3.2. Inverter gate

Thanks to the columbic interaction between electrons in neighboring

cells, different types of the inverter gates in QCA were proposed. The principle
operation of this gate is to invert the input signal applied. If the applied input is
low then the output becomes high and vice versa, as shown
in Figure 1.6(a) and 1.6(b). The input “In” is given to one of the ends and the
output reversed will be obtained at the output “Out.” The position of the
electrons and the layout of each cell are represented in Figure 1.6(b). The
principle of operation of this gate is based on the wire of input, which will be
prolonged in two parallel wires and will polarize the cell placed at the end of
these two wires, which implies the opposite polarization of this cell due to the
Coulomb repulsion.

Figure 1.6 Inverter gate, (a) representation, (b) QCA layout, and (c) simulation
results.

7
 According to Figure 1.6(c), the simulation results of the inverter gate are
presented. One waveform with one frequency is applied to the input (In), one
waveform for the clock 0 (Clk 0), and one waveform for the inverter gate
outputs (Out).

From simulation results of the output pulses inverter gate (Out) given
by Figure 1.6(c), the expression of the inverter gate can be deduced as
expressed in Eq. (2):

Out=In¯¯¯¯.Clk¯¯¯¯¯¯ 0 (2)

1.3.3. QCA majority voter

In QCA circuits, the majority voter (MV) plays an important role for
logic gates. It is only composed of five cells: three input cell, one output cell,
and a center cell, which is the decision-making cell. These cells are arranged
like a cross with three inputs (a, b, and c) and one output (Out). This gate is
based on the majority logic value given at its input as shown in Figure 1.7(a).
The layout of each cell given by MV is represented in Figure 1.7(b).

8
Figure 1.7Majority voter (MV) gate, (a) QCA representation, (b) QCA layout,
and (c) simulation results.

According to Figure 1.7(c), the simulation results of the majority voter

(MV) gate are presented. Three waveforms with different frequencies are
applied to the inputs (a, b, and c), one waveform for the clock 0 (Clk 0), and one
waveform for the MV outputs (Out). From simulation results of the output
pulses of MV gate given by Figure 1.7(c), the expression of the MV gate can be
given by Eq. (3):

Out=a . b+b . c+c . a (3)

From the majority voter gate, depending on the input fixed to 0 or 1, other
logical gates can be deduced such as AND/OR gates.

9
 On the one hand, when one of the inputs of MV is fixed to 1, the logical
function of OR gate is obtained and can be expressed in Eq. (4):

Out=a+bwhenc=1 (4)

Figure 8 shows the representation, QCA layout, and simulation of OR gate.

Figure 1.8.OR gate, (a) QCA representation, (b) QCA layout, and (c) simulation
results.

According to Figure 1.8(c), the simulation results of the OR gate are

presented. Two waveforms with one frequency are applied to the inputs (a and
b), one waveform for the clock 0 (Clk 0), and one waveform for the OR gate
outputs (Out).

From simulation results of the output pulses OR gate (yellow) given

by Figure 1.8(c), the expression of the inverter gate can be deduced as
expressed in Eq. (5):

Out=(a+b).Clk¯¯¯¯¯¯ 0 (5)

10
 On the other hand, when one of the inputs of MV is fixed to 0, the logical
function of AND gate is obtained (Figure 1.9) and can be expressed in Eq. (6):

Out=a . bwhenc=0 (6)

Figure 1.9.AND gate, (a) QCA representation, (b) QCA layout, and (c)
simulation results.

Figure 1.9 shows the representation, QCA layout, and simulation of AND
gate. According to Figure 1.9(c), the simulation results of the AND gate are
presented. When there are two waveforms, with one frequency is applied to the
inputs (a and b), one waveform given for the clock 0 (Clk 0), and one waveform
for the AND gate outputs (Out).

11
 From simulation results of the output pulses AND gate (yellow) given
by Figure 1.9(c), the expression of the inverter gate can be deduced as
expressed in Eq. (7):

Out=(a . b).Clk¯¯¯¯¯¯ 0 (7)

In conventional digital VLSI design, it is assumed that a circuit/system

should function perfectly to provide accurate results. In non-digital world, ideal
operations are seldom needed e.g. “analog computation” that provides “good
enough” results instead of totally accurate results may in fact be acceptable. For
many digital systems, the data already contained errors e.g. in a communication
system errors may occur everywhere. In communication system, the analog
signal out coming from the outer world must first be sampled before being
transformed to digital data at the frontend of the system. The digital data are
then processed and transmitted in a noisy channel before convert back to an
analog signal at the back end of the system. Errors may take place anywhere
during this process. Due to the advance in transistor size scaling, factors such as
noise and process variations which are previously not important are becoming
important in today’s digital IC design.

12
 CHAPTER-2

LITERATURE SURVEY

[1] Design of novel inverter and buffer in Quantum-dot Cellular Automata

(QCA)
Ahmad et al (2015) presented at the design of a programmable
inverter/buffer using proposed XOR gate. The proposed circuit can be used as
an inverter (NOT gate) or a buffer (pass gate). The programmable
inverter/buffer has been designed and simulated based on intensive discrete
arithmetic analysis. In addition, 2-bit and 3-bit programmable inverter/buffer
has also been designed and implemented in this paper. The proposed design
enjoys the features of small area, superior performance factors in respect of
speed and circuit stability.

[2] Efficient realization of digital logic circuit using QCA multiplexer

Goswami et al (2014) targeted design of efficient logic circuits based on
QCA multiplexer. The design capability of the multiplexer in QCA is
investigated implementing XOR, XNOR logic gate and arithmetic logic unit.
Further, efficient sequential circuits like D latch, T latch, D flip-flop, Scan flip-
flop, shift registers are designed using QCA multiplexer. Results obtained
supports the fact that the proposed designs achieve significant improvement in
terms of device density, cell count as well as clock delay than that of the other
previous designs.

[3] Design and analysis of odd- and even-parity generators and checkers
using Quantum-dot Cellular Automata (QCA)
Ahmad et al (2015) presented novel 3-bit odd- and even-parity generators
and checkers using QCA nanotechnology. The proposed techniques can be used
to detect and check errors during information communication (message word).
The parity generators and checkers have been designed based on QCA-
XOR/XNOR gates. The circuits present a simple design using homogenous
13
layer of cells and effective technique to find errors in data transmission
systems.

[4] QCA Designer: A simulation and Design Layout Tool for QCA based
Nano Domain Computing Architectures
Aralikatti et al (2020) presented a QCA designer is a simulation with
layout development tool for QCA, it is the notable Nano-technology
replacement to current CMOS IC technology and it provides the ability to
manufacture even denser integrated circuits, which can consume low power and
operate at high frequencies. Later a little attention is given to design rules for
better QCA digital circuit design using this tool. In QCA technology, the signal
transmission happens due to electrostatic interaction among the placed electrons
in QCA cell, as opposed to flowing to the electrons in a QCA wire, so
crossovers available in designs is discussed.

[5] Synthesis of reversible universal QCA gate structure for energy efficient
digital design
Sen et al (2011) investigated a novel approach to synthesis a reversible
universal QCA logic gate (RUG) structure with the target to reduce the garbage
outputs as well as the logic gates of a design. This design addresses the
fundamental issues of realizing reversible gates in nanotechnology and also its
reliability and performance trade-off. The experimental designs establish that
the RUG can ensure an energy saving, cost effective realization of QCA logic
circuits that may not be possible with the conventional reversible logic gates.

[6] Stubby delay comparator in QCA: The C-Gate

Babu et al (2015) explained the C-Gate and check its efficiency. The
proposed gate can be extended for a lot many bits depending on the usage. The
regular counter parts in QCA give very high delay as to C-Gate. This paper
totally is opus of the C-Gate both theoretically and simulated version of it.

14
[7] A Simple Synthesis Process for Combinational QCA Circuits:
QSynthesizer
Dhare et al (2019) presented a simple but novel synthesis method for
combinational QCA circuit "QSynthesizer". The authors do neither claim an
optimized method of synthesis nor a very high level of research in the field of
QCA synthesis tool development. Still, this paper definitely contains a frugal
innovation for synthesizing QCA circuit in absence of rarely available, low cost
QCA synthesizers. The proposed synthesis method comprises logic reduction
algorithm implemented in C++, Perl scripts and widely used synthesis tools like
Leonardo Spectrum for digital design. The results on Microelectronics Centre of
North Carolina (MCNC) benchmark circuits using proposed QSynthesizer show
the effectiveness of the proposed method.

[8] Design and Analysis of Digital Circuits using Quantum Cellular

Automata and Verilog
Nanditha et al (2020) concentrated on simulate design and comparison of
digital circuits using QCA Designer and Verilog Code, more specifically
multiplexers and demultiplexers. The simulation results of these two digital
circuits using QCA Designer and Verilog code are shown separately along with
a performance comparison table. It was observed that they seem to be the same.
But., while we consider other parameters like time, space, speed and
sensitivity., we truly get to know that QCA design is more reliable when
compared to Verilog Code Design. QCAD is a free computer-aided design
software application for 2-Dimensional design and drafting. Multiplexers are
used in telephone networking, computer memory, and transmission from the
computer system of a satellite and in many more fields. Demultiplexers are used
in Communication Systems, ALU (Arithmetic Logic Unit) and many other
fields.

15
[9] A New Robust Design of Dual-Rail Checker in QCA Technology,
Capable of Testing of Digital Electronics Circuit
Kumar et al (2019) devoted to the robust architecture of dual-rail checker
using the co-planar technique in QCA Designer tool. These designs are of
concern to modern testing approach. These circuits are also included a modern
approach for physical implementation such as Quantum-Dot cellular automata.
The main concern of this article is on the synthesis of nano computing testing
circuit in QCA. The interest of this article is not only synthesis aspects it covers
the physical implementation aspect also. Dual-rail checker is an inherent
module of the testing digital logic circuit. High device density happens to be an
important factor in the synthesis of the Dual-rail checker. The article proposed a
robust architecture of Dual-rail checker using QCA Technology, which
consumes a less number of quantum cell and latency.

[10] Simplification of master power expression and effective power

detection of QCA device (Wave nature tunneling of electron in QCA
device)
Roy et al (2016) presented the power and the tunneling rate computation
methodology of the QCA devices in wave nature of electrons, in terms of some
mathematical expressions. The computed and simplified expressions provide a
congenial way to detect the device power instantaneously at a precise position
inside the tunneling junction. The most significant factors for tunneling are
tunneling power, dissipated power and the total power of a QCA cell at
tunneling time is computed do with Schrödinger wave equations. This paper
summarizes on the QCA device power computational technique, by the help of
Schrödinger wave equations.

16
 CHAPTER-3

EXISTINIG SYSTEM

3.1 A Novel Design “Binary to Gray Converter” with QCA Nanotechnology

Ali H. Majeed et al presented QCA based3-bit binary to gray and 4-bit
binary to gray code converter, with a minimum number of cells, has
beenproposed.The simulations are completed using QCA Designer. This paper
presented the QCA implementation of 4- bit binary to gray code converter using
the fundamental elements of QCA technology that is majority gate and inverter.
In this design we use 3 EX-OR gates for designing the 4 bit binary to gray code
converter. Here we also proposed QCA design for EX-OR gate. A. EX-OR gate
implementation in QCA EX-OR gate using QCA technology is designed by
using 1 OR gate, 2 AND gates, and 1 inverter. The AND gate and OR gate is
implemented using majority gate. This EX-OR gate is used in implementation
of 4-bit converter. The schematic design is presented below in fig. From the
figure given below, for the inputs A, B and C the output is ‘out’.

3.2 Code Converters

The wide variety of codes to represent discrete elements of information,
lead them, being used by different digital systems. However, in some cases, the
need to connect the output of one digital system to the input of another digital
system arises. Between these two systems, the conversion circuit must be
inserted if each uses different codes for the same information. Therefore a code
converter is a circuit that makes both systems compatible even though each uses
different codes. Without a doubt, the effectiveness of code converters was
proven by the National Security Agency (NSA), since they utilized them while
creating and breaking codes. Code converters can be very helpful for protecting
sensitive data from spies. Code converters are also useful for enhancing
tractability and portability of the data. Code converters have also found
applications in communication and algorithm generation. Binary to gray code
17
converter shown in Table 1 is one of the most important converters used in
digital systems.

Table 3.2.1 TRUTH TABLE OF 3-BIT BINARY TO GRAY CODE

CONVERTER

Table3.2.2 TRUTH TABLE OF 4-BIT BINARY TO GRAY CODE

CONVERTER

18
 Figure 3.1existing layout of exiting

The above figure is designed based on XOR gate, the qca layout is
shown. The code converters circuit are performed using this layout have been
designed using QCA Designer 2.0.3. in this layout, it consists of three fixed
input which is indicated in the orange colour qca cell. This design and
simulation of a QCA binary to gray code converter circuits has been presented.
The operation of these converters has been analyzed using QCA designer bi-
stable vector simulation. The designs are efficient where it contains less number
of cells, use minimum clock phases and have significantly minimum wire length
which causes to trouble-free operation at higher temperature.

19
 CHAPTER-4

PROPOSED SYSTEM

In this section, the proposed system of binary to grey code is described

with its layout model. In this project, a novel XOR/XNOR-function logic gate
with two inputs, two enable inputs and one output is proposed and designed in
Quantum-dot Cellular Automata (QCA) nanotechnology. In order to
demonstrate the functionality and capabilities of the proposed QCA based
XOR/XNOR architecture, performance is evaluated and analysed. The proposed
XOR/XNOR logic gate has a superb performance in terms of area, complexity,
power consumption and cost function in comparison to some existing QCA-
based XOR architectures which has three enable inputs. Moreover, some
efficient circuits based on the proposed XOR/XNOR gate are designed in QCA.

4.1 Implementation of XOR/XNOR Designs

So far, we have encountered inverter, 3-input majority, and AND/OR
gates as the basic elements from which logic circuits can be constructed. In
XOR/XNOR are also very useful in practice, particularly for building circuits
that perform arithmetic operations and communication. In the study of QCA
circuit design, XOR/XNOR gate function can be expresses as shown in Eq.
(4.1).

(4.1)

Various design of XOR/XNOR have been presented previously studies.

Since their outputs are inverts of each other, one of the logical outputs can be
followed by an inverter to get the other. Most of these designs are based on
inverter and 3- input majority gates by using different equations. A XOR

20
designs are built with 5-input majority gates and 3- input majority gate. In
addition, two 3-input XOR design.

4.2 PROPOSED XOR/XNOR GATE

After use for reference to current integrated circuits design experiences,
the XOR/XNOR logic gate are adopted serving for the large size circuit, which
can reduce the complexity and area.

4.3 The Novel XOR/XNOR Design

Traditionally, QCA circuits regarding their logical function are
implemented by majority and inverter gates. However, this paper presents the
XOR/XNOR logic gate design based on cell level methodology, the expected
output would be achieved by influence of the cell to each other. Fig. 2
demonstrates the novel XOR/XNOR gate. In contrast to previous XOR/XNOR
designs, our proposed gate are not majority and inverter based. The schematic
of proposed QCA based circuit of XOR/XNOR gate is given in Fig. 2(a). As
shown in Fig. 2(a), a andb represent input cells, e1 and e2 represent enable
input cells, while f is output cell. The layout of XOR/XNOR gate is in Fig 2(b)
that consists of 13 QCA normal cells, occupies 0.01 μm2 area and
has delay of 0.25 cycle. When polarization value of enable inputs (e1e2) is ‘-
1+1’, it performs XOR logic operation. The QCA layout of XOR gate is
depicted in Fig. 2(c).

Figure 4.1. The novel XOR/XNOR logic gate

21
4.4 Physical Verification
The physical verification of the novel logic gate is offered in this section.
The proposed design possesses 8 driver cells. In order to proof the output of the
novel structure under XOR/XNOR logic gate, generous radius of effect should
be considered in an account. In order to get the most accurate result, we
consider that the output cell is affected by all other cells in this letter.
In order to calculate the kink energy of any cell, the electrostatic energies
of different electrons in every cell are calculated when the state of the 13th cell
is unpolarized during the input (a, b, e1, e2) = (1, 1, -1, 1), which only two types
of outcomes are possible (i.g. ‘1’ and ‘0’). Table 1 gives the calculated results
by using Eq. (4.2-4.3). The electrostatic energy between two different electrons
can be obtained through equation (4.2). The total electrostatic energy UT can be
obtained from Eq. (4.3).

(4.2)

(4.3)

The simulation results of XOR logic function are seen from front half in
Fig (i.e. enable inputs (e1e2) is ‘01’ in binary) that when a = 0, b = 0, the
output will be f = 0. When a = 0, b = 1, the output will be f = 1. Thus, all the
values of output bit f are in accordance with inputs a and b. This result satisfies
the theoretical values of XOR gate, which indicates the accuracy of the design.

It is worth mentioning that in constructing large circuits using the smaller

designs, complexity and delay of the small building blocks are of much
importance and hence, we can use the proposed XOR/XNOR logic gate as a
22
module to implement large and complex logic circuits (such as adder,
comparator, multiplexer, etc.). In this way, it is theoretically possible to design
efficient circuits.

In this work , a novel configurable XOR gate based binary to gray and
4-bit binary to gray code converter, with a minimum number of cells, has been
proposed. The simulations are completed using QCA DesignerThe wide variety
of codes to represent discrete elements of information, lead them, being used by
different digital systems. However, in some cases, the need to connect the
output of one digital system to the input of another digital system
arises..Between these two systems, the conversion circuit must be inserted if
each uses different codes for the same information. Therefore a code converter
is a circuit that makes both systems compatible even though each uses different
codes. Without a doubt, the effectiveness of code converters was proven by the
National Security Agency(NSA), since they utilized them while creating and
breaking codes. Code converters can be very helpful for protecting sensitive
data from spies. Code converters are also useful for enhancing tractability and
portability of the data. Code converters have also found applications in
communication and algorithm generation. Binary to gray code converter shown
in Table 1 is one of the most important converters used in digital systems

23
Table 4.4 Binary to Gray code converter

24
 CHAPTER-5
ELEMENTS OF QCA
Quantum dot cellular automata emerged as a new paradigm, beyond
current switches to encode binary information.
5.1.1 Quantum Dot

Quantum dots are nanostructures created from standard semi conductive

materials such as Si/SiO. These structures can be modeled as quantum wells
during real time manufacture. In order to implement a system that encodes
information in the form of electron position it becomes necessary to construct a
vessel in which an electron can be trapped and counted as there or not there.
A quantum dot acts a vessel and stores logic states not as voltage levels,
but based on the position of individual electron. Electrons, once trapped inside
the dot, do not alone possess the energy required to escape. We can use
quantum physics to our advantage because the smaller a quantum dot is
physically, the higher the potential energy necessary for an electron to escape.
Techniques for fabricating quantum dots are electron-beam lithography, self-
organization, and formation of depletion bubbles

Fig.5.1 Quantum Dot

5.1.2 Cell Structure

The cell is charged with two free electrons, which are able to tunnel
between adjacent dots. These electrons tend to occupy antipodal sites as a result
of their mutual electrostatic repulsion. Thus, there exist two equivalent
25
energetically minimal arrangements of the two electrons in the QCA cell. These
two arrangements are denoted as cell polarization. Binary information is
encoded in the charge configuration of the QCA cell to represent logic 1 and 0.
Coulomb repulsion causes the electrons to occupy antipodal sites; the
ground state charge distribution may have the electrons aligned along either of
the two diagonal axes. The cell polarization has been defined as a quantity
which measures the extent to which the charge distribution is aligned along one
of these axes. The electrons exactly localized on sites two and four will result in
P = + 1, while electrons on sites one and three yield P = -1.

Fig.5.2 QCA cell

5.1.3 Clocking Scheme

The signal flow in a QCA wire is controlled by clocks. To achieve

controllable data directions, the cells within a QCA design are partitioned into
the so-called clock zones that are progressively associated to four clock signals,
each phase shifted by 90°.This clock scheme, named the zone clocking scheme,
makes the QCA designs intrinsically pipelined. As the main source of the
synchronization, a clock plays a key role in the QCA circuit. QCA circuit areas
are organized into four clock zones.

26
 QCA circuits use clock signals for transmission of signals and clock
signals control the QCA circuits. It has four different phases. The four different
phases are switch, hold, release and relax. Due to the tunnel barrier between the
dots the clock signal stops tunnelling and at the same time allowing the
electrons to tunnel in the other clock phase shows the clocking scheme when an
individual cell is affected with clock signal.

Fig.5.3. Clock Phases

During the switch phase electron tunnelling is stopped as the tunnel

barrier between the dots rising, electrons thus tunnelling is stopped and due to
the polarization of its input the electron in the cell become localized Switching
occurs by refreshing its state. During the hold phase as the barrier remains high
thus no electron tunnelling takes place. The polarized cells are latched. The cell
is refreshed every cycle.
During Release phase the electrons becomes free and the cell starts to
lose its polarization due to the lowering of electron barrier. During the relax
phase, the barriers are low, the electrons are free to tunnel and delocalize. There
is a 900 phase shift from one clock zone to the next. In each clock zone, the
clock signal has four states: high-to-low, low, low-to-high, and high. The cells
in each clock zone behave like a single latch.

27
 The cell begins computing during the high-to-low state and holds the
value during the low state. The cell is released when the clock is in the low-to-
high state and inactive during the high state. This allows information to be
pumped through the circuit as a result of the successive latching and unlatching
in cells attached to different clock cycles. These four clocking zones named as
clock zone 0, clock zone 1, clock zone 2, clock zone 3; are implemented in
QCA Designer tool. Each cell can be independently attached to any one of the
four clocking zones.
5.1.4 QCA Wire
A series of QCA cells act like a wire. Adjacent QCA cells interact in an
attempt to settle to a ground state determined by the current state of the inputs.
Columbic forces will cause adjacent cells to interact. The state of the cells will
always tend to the lowest energy. Transmitting information through a “wire” is
done by forcing the polarization of a cell at one end. The polarization of the
input cell is propagated down the wire. Any cells along the wire that are anti-
polarized transmit the information.

Fig.5.4 QCA wire

5.1.5 Memory Loop
The clocking mechanism of QCA systems allows each clock zone to act
as a memory cell, for one quarter clock period, so connecting four subsequent
clock zones will produce a memory effect during one clock period. Given the
basic memory cell construct, a value has to be inserted into the loop and read
from it, in order to make it useful. Unlike CMOS memory, QCA has no
equivalent for “static memory”. Memory storage in this design is based on

28
circulating memory model. The memory loop is divided into four consecutive
clocking zones each latching in succession.

Fig.5.5 QCA Memory Loop

The stored memory continuously circulates in the loop. This means that
information is transmitted through each cell and not retained. Each cell erases
its own state every cycle of the clock. As a result, memory units must be created
using loops of cells that continuously circulate the stored information. To be
used as a memory cell, a loop of the cells is needed, in which a series of clock
zones are used. The different shades of grey represent the different clocking
zones to which cells are attached.
Each shade of gray represents a different clocking zone. The darkest shaded
cells are attached to clock 0, and the others are represented by successively
lighter shades. The cells which have polarizations, shown directly above them,
are fixed to that polarization by denoting them as -1.00 and 1.00. Fixed
polarization cells are required since the fundamental logic gate in QCA is the
majority gate, by fixing one of its inputs to either a 1 or 0 we can generate the
standard AND, OR operations.

29
 Fig.5.6 QCA Memory Loop in a large layout

5.1.6 Majority Logic Synthesis

The Majority Gate (MG) is a result of majority logic synthesis. Given
three inputs a, b, and c, the MG performs the logic function provided that all
input cells are associated to the same clock signal clkx (with x ranging from 0 to
3), whereas the remaining cells of the MG are associated to the clock signal
clkx+1. The output cell will polarize to the majority polarization of the input
cells. The majority gate performs a three-input logic function. Assuming the
inputs are A, B and C, the logic function of the majority gate is
m(A, B,C) = A . B + B . C + A . C
A separation of at least two cells between signal interconnect wherever
the possibility for cross-talk exists; an example is the gap between the memory
loop and some of the fixed polarization cells. There are some areas in the design
where this was not necessary; e.g., interconnect attached to clocks 0 and clock
30
2. In this case, there is no problem with cross-talk because the two interconnects
do not simultaneously transmit.

Fig.5.7 Majority voter

Using this technique, minimal majority expression and an optimal QCA
layout can be obtained. Furthermore, this method removes all the redundancies
that are produced in the process of converting a decomposed network into a
majority network.

5.2. Fundamental Logic Gates In QCA

Large digital circuits using quantum-dot cellular automata (QCA) cells

can be designed by means of basic design of AND, OR and NOT gates.When
any one of the three inputs is fixed to one, it performs OR operation; while any
one of the three inputs is fixed to “0”, it performs AND operation. By fixing the
polarization of one input as logic “0”, we obtain AND gate.

Fig.5.8 AND gate in QCA

By fixing the polarization of one input as logic “1”, we can obtain an OR gate.
31
 Fig.5.9. OR gate in QCA
NOT gate or a QCA inverter can also be designed by arranging the cells as
shown in a layout shown in Figure 5.10

Fig.5.10. QCA inverter

5.3. Signal Routing

5.3.1. In plane Crossing

Two ways have been proposed to solve wire crossing conflicts: in plane
crossing and multi- layer crossing. By observing the ‘in plane crossing’, it
should be noticed that the vertical wire has all the cells rotated by 45 degrees,
relative to the cells in the horizontal wire. With such organization there is no
interference, as two cells with a 45 degree rotation relative to each other have
no energy associated to their polarizations. But a problem may arise from the
increase in distance between the cells of the horizontal wire, right in the
32
crossing point, since the energy is lower than with the normal spacing, and
transmission error may occur. The cells can be rotated easily using an option
‘Rotate’ in the QCA Designer tool.
The coplanar crossing of two wires is achieved by physically passing one
wire over the other with an insulator placed between them. Such a non-planar
crossing would also work for two QCA wires, but the cellular nature of such
wires allows us to cross them using an entirely coplanar arrangement of cells. In
this example, the horizontal line is transmitting a ‘one’ and the vertical line is
transmitting a ‘zero’. In order to cross the lines, the horizontal wire must be
converted from standard cells to translated cells. The signal on the horizontal
line is transmitted through cells undisturbed using this technique.

Fig.5.11. In plane crossing of two QCA wires

5.3.2. Multi-Layer Crossover
Multi-layer crossover gives better simulation results (seems safer), it may
not be as easily fabricated as in plane crossovers, thus a compromise between
the best (in theory) and the possible must be assumed. And regarding multi-
layer crossover, it should be noticed that for an even number of separation
layers the via connection will act as an inverter.

33
 Fig.5.12.Multi-layer crossing
5.4.Software Tool
During the initial analysing of the state of the art in QCA, the need for
automatic layout generation tools was needed, and as a consequence a software
tool is developed to generate a QCA layout of a given logic circuit. The
development of such a tool was considered and carried out, and the resulting
tool is named QCA Designer.
QCA designer tool is a rapid Design and Simulation Tool for Quantum-
Dot Cellular Automata to create a design and simulation for Quantum Dot
Cellular Automata (QCA). This tool facilitates rapid design, layout and
simulation of QCA circuits by providing powerful CAD like features available
in more complex circuit design tools.
QCA logic and circuit designers require a rapid and accurate simulation
and design layout tool to determine the functionality of QCA circuits. QCA
Designer gives the designer the ability to quickly layout a QCA design. Two
simulation engines facilitate rapid and accurate simulation.
5.4.1.Key Features
a) Intuitive CAD-like user interface
b) Easy drag-and-drop circuit design
c) Encapsulated PostScript (EPS) printing
d) Support for multiple layers (for signal crossover)

34
5.4.2. Design Engines
A QCAD Designer is a well-known simulation tool used to create QCA
circuits and verifying its functionality. This tool provides two simulation
engines they are bistable engine and coherence vector engine. By performing
simulation, the bistable is more favourable than the coherence vector engine
usually produces the results. Four clocking zones are implemented in QCA
Designer tool and each cell can be independently attached to any one of the four
clocking zones.
The QCA cells are 18-nm wide and 18-nm high; the cells are placed on a
grid with a cell center-to-center distance of 20 nm; there is at least one cell
spacing between adjacent wires; the quantum-dot diameter is 5 nm; the
multilayer wire crossing structure is exploited; a maximum of 16 cascaded cells
and a minimum of two cascaded cells per clock zone are assumed. The bistable
engine is used for simulations with the options shown. QCA Designer is the
“state of the art” QCA layout editor and simulator.

5.4.3. Editing Features

a) Drawing QCA cells individually or in arrays, optionally aligned to a grid

with a default spacing (20 nm) equal to the default cell size (18 nm) plus
the default inter cell spacing (2 nm).
b) Setting clock signal for each QCA cell is required to have synchronous

circuits working properly. In Multi-layer QCA layout design is required

to have multi-layer signal crossing. Drawing QCA cells with 90 degrees
rotation is required to have in plane signal crossing.
c) Graphical marking of special cells (on via and crossover layers) is

possible. Although cell in via and crossover structures may look different
in the layout, they are regular QCA cells and no distinction is made
during simulation.

35
d) Cells acting as vertical via interconnections between layers are

represented by a square with a circle inside, and cells in crossover layers

are represented by a square with a cross inside, the normal cells are
represented as a square with four little circles inside and the arrangement
of those circles depend on the rotation of the cell.

Fig.5.13. QCA cell styles

e) Importing and exporting layout blocks to files, which allow, for example,

to easily importing QCA layout blocks produced by the developed QCA

Designer tool. The simulation can be performed with an exhaustive set of
input vectors, or alternatively with a user-defined set of input vectors.
QCA Designer simulation inputs window has the option to specify a set
of user defined input vectors, or alternatively choose an exhaustive
simulation.

36
 CHAPTER-6
CONCLUSION
In this project , we will design and simulate a QCA binary to gray code
converter circuits. The operation of these converters will be analyzed using
QCA designer bi-stable vector simulation. The designs will be
efficient where it will contain less number of cells, use minimum clock phases
and have significantly minimum wire length which causes to trouble-free
operation at higher temperature. The proposed converter will have an advantage
in terms of number of cells and delay from an earlier circuit proposed.

37
 REFERENCES

[1] F. Ahmad and G. M. din Bhat, "Design of novel inverter and buffer in
Quantum-dot Cellular Automata (QCA)," 2015 2nd International Conference on
Computing for Sustainable Global Development (INDIACom), New Delhi,
2015, pp. 67-72.

[2] M. Goswami, B. Kumar, H. Tibrewal and S. Mazumdar, "Efficient

realization of digital logic circuit using QCA multiplexer," 2014 2nd
International Conference on Business and Information Management (ICBIM),
Durgapur, 2014, pp. 165-170, doi: 10.1109/ICBIM.2014.6970972.

[3] F. Ahmad, P. Z. Ahmad and G. M. din Bhat, "Design and analysis of odd-
and even-parity generators and checkers using Quantum-dot Cellular Automata
(QCA)," 2015 2nd International Conference on Computing for Sustainable
Global Development (INDIACom), New Delhi, 2015, pp. 187-194

[4] S. Aralikatti, "QCA Designer: A simulation and Design Layout Tool for
QCA based Nano Domain Computing Architectures," 2020 Second
International Conference on Inventive Research in Computing Applications
(ICIRCA), Coimbatore, India, 2020, pp. 1042-1046, doi:
10.1109/ICIRCA48905.2020.9183046

[5]B. Sen, T. Adak, A. S. Anand and B. K. Sikdar, "Synthesis of reversible

universal QCA gate structure for energy efficient digital design," TENCON
2011 - 2011 IEEE Region 10 Conference, Bali, 2011, pp. 806-810, doi:
10.1109/TENCON.2011.6129222.

[6]B. M. Babu, P. V. S. R. Bharadwaja and K. Neelima, "Stubby delay

comparator in QCA: The C-Gate," 2015 International Conference on Circuits,
Power and Computing Technologies [ICCPCT-2015], Nagercoil, 2015, pp. 1-5,
doi: 10.1109/ICCPCT.2015.7159282.

38
 [7] V. Dhare and U. Mehta, "A Simple Synthesis Process for
Combinational QCA Circuits: QSynthesizer," 2019 32nd International
Conference on VLSI Design and 2019 18th International Conference on
Embedded Systems (VLSID), Delhi, NCR, India, 2019, pp. 498-499, doi:
10.1109/VLSID.2019.00105.

[8] V. M. Nanditha, U. Sanath Rao, M. Murali, R. Swathi and K.

Chethana, "Design and Analysis of Digital Circuits using Quantum Cellular
Automata and Verilog," 2020 7th International Conference on Computing for
Sustainable Global Development (INDIACom), New Delhi, India, 2020, pp.
205-210, doi: 10.23919/INDIACom49435.2020.9083709.

[9]D. K. Kumar, V. Shankar and K. Vittal, "A New Robust Design of

Dual-Rail Checker in QCA Technology, Capable of Testing of Digital
Electronics Circuit," 2019 International Conference on Smart Systems and
Inventive Technology (ICSSIT), Tirunelveli, India, 2019, pp. 759-763, doi:
10.1109/ICSSIT46314.2019.8987797.

[10] S. S. Roy, "Simplification of master power expression and effective

power detection of QCA device (Wave nature tunneling of electron in QCA
device)," 2016 IEEE Students’ Technology Symposium (TechSym), Kharagpur,
2016, pp. 272-277, doi: 10.1109/TechSym.2016.7872695.

39