MICRO 1

REMOTE TERMINAL UNIT

TECHNICAL MANUAL

ClOOO-AAA-00000

REV. "B"

PRINTED IN THE U.S.A. BY CAMCO, INC. OCT. 1984

PREVIOUS EDITION JANUARY 1986

PRESENT EDITION APRIL 1986
 TABLE OF CONTENTS

1.0 GENERAL DESCRIPTION ••••••••• ••••••••• ••••••••• ••••••••• ••• !

2.0 CIRCUIT BOARD DESCRIPTIONS ••••••••• ••••••••• ••••••••• ••••• 3

2.1 CPU Card (ClOOl) ••••••••• ••••••••• ••••••••• ••••••••• •••••• 3

2 .1.1 Descripti on ......... ....•...• ......... •........ ...•..... •. 3
2 .1.2 Programming Informati on ••••••••• •.•••••• ..•••••.• •. ••• 4
2.1.3 System Flow Diagram ••••••••• ••••••••• ••••••••• ••••••••• • 7
2.1.4 Circuit Descripti on ••••••••• ••• ,.... • ••••••••• •••••••• 8
2.2 Micro/! Communic ations Card (Cl002) ••• ••••••••• ••••••••• 8
2.2.1 Descripti on and Block Diagram ••••••••• ••••••••• •••••••• • 8
2.2.2 Switch es....... .......... .......... .......... .......... .9
2.2.3 Lamps • ••••••••• ••••••••• ••••••••• • ... 9
2.2.4 Serial Ports ••••••••• ••••••••• •••• .......... ......••• • 9
2.2.5 Modem ••••••••• ••••••••• ••••••••• ••••••••• ••••••••• •••••••• 9
2.2.6 Programming Informati on ••••••••• ••••••••. ••••••••• ••••••• 11
2.2.1 Circuit Descripti on (Cl002) ••••••••• ••••••••• ••••••••• ••• 12
2.2.8 LED Lamps on Communic ations Board Definitio n ••••••••• •••• 13
2.3 Base I/0 Board (Cl003) ••••••••• ••••••••• ••••••••• ••••••• .14
2.3.1
2.3.2
Descripti on and Block Diagram •••••••
Power Supply •••.•••..• ••••••••
..................
.14
. .........• .••..•.• 14
2.3.3 Status Input ......... .....•... ......... ........• ......••• 14
2.3.4 Analog Input ......... ......... ......•.. ....••... .......•. 16
2.3.5 Relay Output ••..••••. •••••••.• .••..•••• •.••••••• ••••.•••. 16
2.3.6 Configura tion ••••••••• ••••••••• ••••••••• ••••••••• •••••••• 16
2.3.7 Modem Interface .•••..•..• .•••••••• • t ••••••••• ••••••••• ••• 16
2.3.8 Base I/0 Board Circuit Descripti ons ••••••••• ••••••••• •••• 17
2.3.8.1 Power Supply ••••••••• ••••••••• ••••••• • ••••••••• ••••••• 1 7
2.3.8.2 Address Decode ••••••••• ••••••••• ••••• ..•...•..• ..••.•. l 7
2.3.8.3 Re 1 ay • ......... ......... ......... • • 17
2.3.8.4 Configura tion ••••••••. ••••••••• •. ••••••••• ••••••••• •• 1 7
2.3.8.5 Status ......•••. ••.•.••.. .•..•••.. •.•.•..•• .•.••.••• • •• 18
2.3.8.6 Analog ......... ......... ......... ......... ...... ~········1 8
2.3.9 Programming Informati on ••••••••• ••• .19
2.4 Expansion Boards ••••••••• ••••••••• ••••••.•• ••••••••• •• .21
2.4.1 Relay Expansion Board (Cl004) ••••••••• ••••••••• ••••• ••• 21
2.4.2 Status Expansion Board (ClOOS) ••••••••• ••••••••• •••••••• .21
2.4.3 Analog Expansion Board (Cl006) ••••••.• ....•...•. ..•.... •• 21

3.0 MICRO 1 FIRMWARE ••••••••• ••••••••• ••••••••• ••••••••• ••••• 25

3.1 Overview .•••••••• •••••••..• • ••••••••• • 2 5

3.2 Interrupt Structure •.••••.•• .. 25
3.3 Power Up Sequen ce........ ........... .. • •••... .25
3.4 ~eal Time Clock Interrup t..... • ••••••••• •••••••. •• 25
3.5 Message Processin g Task •••••••• •••••••• ••••• .. 26
3.6 Communic ations Interrup t.... . •......... ..•..•..• .•. .. 26
3.7
3.8
Analog Processin g ••••••••• ••••••••
Status Processin g ••••••••• •••••••.
................. ..26
••••••• • ••••••••• 2 6
3.9 Control Processin g ••.••••.•• •••••• .•••••••• •••••••.. •• 2 7
 TABLE OF CONTENTS (Cont.)

4.0 JUMPER OPTIONS AND SWITCH SETTINGS ••••••••••••••••••••••• 28

4 .1 Jumper Options ••••••••••••••••••••••••••••••••••••••••••• 28

4.1.1 CPU Card (ClOOl) .••..••••••••••••••. ~ .••••••••••••••••••• 28
4.1.2 Communications Card (Cl002) •••••••••••••••••••••••••••••• 29
4.1.3 Base I/0 Board (C1003) ••••••••••••••••••••••••••••••••••• 30
4.1.4 Relay Expansion Board (C1004) •••••••••••••••••••••••••••• 31
4 .1. 5 Status Expansion Board (Cl005) ••••••••••••••••••••••••••• 32
4.1.6 Analog Expansion Board (C1006) ••••••••••••••••••••••••••• 33
4.2 Switch Settings •••••••••••••••••••••••••••••••••••••••••• 34
4.2.1 Communications Board (C1002) ••••••••••••••••••••••••••••• 34
4.2.2 Base I/0 Board (Cl003) ••••••••••••••••••••••••••••••••••• 36

5.0 TECHNICAL SPECIFICATIONS ••••••••••••••••••••••••••••••••• 37

5.1 CPU Card (ClOOl) •••••••••••••••••••••••.••••••••••••••••• 37

5.2 Communications Card (Cl002) •••••••••••••••••••••••••••••• 38
5.3 Base I/0 Board (Cl003) ••••••••••••••••••••••••••••••••••• 39
5.4 Relay Expansion Board (Cl004) •••••••••••••••••••••••••••• 42
5.5 Status Expansion Board (Cl005) ••••••••••••••••••••••••••• 43
5.6 Analog Expansion Board (Cl006) ••••••••••••••••••••••••••• 44

6.0 CALIBRATION ••••• ••••.•••••••••••••••••••• , ••••••••••••••• 45

6.1 Test and Calibrate Mode •••••••••••••••••••••••••••••••••• 45

6 .1.1 Test and Calibration Functions ••••••••••••••••••••••••••• 45
6 .1. 2 Test, Calibrate Switch Settings on Comm. Board (Cl002) ••• 46
6.1.3 Programming Information for Monitoring, Input Power, etc.47
6.2 Communication Card Modem (Cl002) Calibration ••••••••••••• 48
6.3 Base I/0 Board (Cl003) Calibration ••••••••••••••••••••••• 50
6.3.1 Power Supply Adjustment •••••••••••••••••••••••••••••••••• 50
6.3.2 Analog Calibration .........................•......••....• 51

Appendix A Series V Communications Protocol •• , •••••••••••••••••••••• 53

A.1 Introduction ............................................ . 54
A.2 Character Structure •••••••••••••••••••••••••••••••••••.•• 54
A.3 Security Coding ................•.•.•..........•••.......• 55
A.4 Message Organization, Master to Remote ••••••••••••••••••• 56
A.S Message Organization, Remote To Master ••••••••••••••••••• 57
A.6 Opcode Summary . .••.•.••...••••......•••......••.•.•..••.• 5 9
A. 7 Response Byte Count Summary ••.•••••••.•.••.•••••••• ·••.••• 74
 TABLE OF CONTENTS (Cont.)

Appendix B Schematic and Assembly Diagrams •• ~·••••••••••••• •••••••••75

B.l Table of Contents ••••••• 1 ••••••••••••••• ••••••••••••••• •• 76
PART NUMBER DESCRIPTION gry SHEETS
c1001-002-ooooo Micro/I CPU Board 1
ClOOl-AOO-QOOOO Micro/I CPU Board, PCA 1
c1002-002-ooooo Micro/I Comm Board 1
c1002-ooo-xxxxo Micro/I Comm Board, PCA 1
Cl003-002-00000 Micro/I I/0 Board 4
Cl003-000-XXOXO Micro/I I/0 Board, PCA 1
Cl004-002-00000 Micro/I Relay Expansion Board 1
Cl004-000-00XXX Micro/I Relay Expansion Board, PCA 1
ClOOS-002-00000 Micro/I Status Expansion Board 1
ClOOS-000-0000X Micro/I Status Expansion Board, PCA 1
Cl006-002-00000 Micro/I Analog Expansion Board 1
Cl006-000-0000X Micro/I Analog Expansion Board, PCA 1
1.0 GENERAL DESCRIPTION

I
The Tejas Controls Inc. Micro/1 is a low end, high performance Scada device.
The unit is modular in constructio n to minimize field repair and maximize
versatility . It includes a high performance 8 bit microproces sor card to
provide for a computation al capability in addition to the standard Scada
requirement s. The unit contains a man-machine interface card that can include
modem, serial port, printer port, LED indicators, and dip switches. Field I/0
is provided on the base I/0 card and includes digital and analog I/0 capable
of operation in hostile environment .

The CPU card contains microproces sor, memory, watchdog timer, and real time
clock. All memory access is located on this card with only buffered lines
going off of the card. Only the I/0 page access is off board. The card may
contain up to 64K of memory to insure ample space for program and data
storage. A real time clock is generated for the microproces sor based on the
microproces sor crystal. A watchdog timer that generates a complete reset is
also based upon this crystal.

The Man Machine interface card contains the interconnec tions to system and
local human access devices such as terminals, printers and test sets. The
card also contains LED display indicators and configuratio n switches for
programming and status indication.

The base I/0 card contains all field interfaces, digital and analog I/0
circuitry is located on this card. Field wiring connects to removable
terminal blocks. This will allow replacement of the complete unit without the
disconnectin g of individual field wires. All surge protection is located on
the base I/0 card. All field I/0 circuitry is on the base I/0 card.

The I/0 is expandable for the different data types on specially designed
medium speed buses. The entire unit uses high speed CMOS to improve noise
immunity and to minimize power consumption without degrading performance . The
Micro/ 1 card set may be powered by one single DC supply voltage powering
status and analog loops, or separate supplies may be used for isolation of the
loops. Since only one supply voltage is necessary, standard supplies from
many vendors may be used in the RTU rather than a custom power supply.

Microproces sor busing is broken into 3 sections for noise immunity. Memory
access for program and data is restricted to the microproces sor card. No
signal's lines associated with the memory access are run off board without
buffering. The I/0 bus goes off board in a buffered fashion to the man
machine interface card and the base I/0 card. This is a high speed micro-
processor bus which is disengaged during memory accesses. For access to off
board expansion, special medium speed buses are used where specific points are
selected, allowed to settle and then written or read. This combined with CMOS
provides the Micro/1 with improved noise immunity from internal and external
noise sources.

1
The Micro/I allows for a variety of enclosures. Dust tight, oil tight, and
explosion proof enclosures may be specified. The Micro/I has been designed
to cut down on the enclosure space required, yet allow front access to all
of the adjustments and terminations. The unit may also be packaged on a
panel for integration into racks or enclosures containing additional equip-
ment.

2
2.0 CIRCUIT BOARD DESCRIPTIONS

2.1 CPU Card (ClOOl)

2.1.l Description

The Micro/1 CPU card is a high performance, low power unit. It contains all
of the memory for program and data storage, a CMOS 8085 8 bit mi'croprocessor
and the real time clock/watchdog timer system. The card is fully buffered
from off board signals and uses high speed CMOS logic for low power and high
noise immunity. An optional battery backup card may be added to the CPU card
to provide nonvolatile data storage. The card plugs into the master side of
the base I/0 board.

The CPU card utilizes a CMOS version of the Intel 8085 microprocessor. It is
directly compatible in both hardware and software to the NMOS device. The
unit 1s run at an internal clock speed of 3.072 MHz with a 6.144 MHz
crystal. This provides fifty percent more processing speed than the Intel
8080 running 2MHz.

The CPU allows for a large amount of memory. Four sockets are provided for
prom and ram. Each socket will access 16K bytes of memory which will allow
the CPU to have up to 64K bytes. One socket is dedicated to prom, one is
dedicated to ram, and two are jumper selectable. There are jumper options to
allow memory chip sizes of 2K bytes, 4K bytes and 8K bytes. Normal RTU
functions may be run with 4 to 8 bytes of prom and 2K bytes of ram while
special functions may be allowed 32K to 48K bytes of prom and 8K to 16K bytes
of ram.

The microprocessor clock provides the system timing. The real time clock is
generated by an onboard divider circuit. The watchdog timer is generated from
the divider circuit as well. The watchdog timer is reset by an output to the
lower quarter page of I/0. Jumper options are available to select the real
time clock interrupt period from 130 microseconds to 66 milliseconds. The
nominal interrupt period will be 1.04 or 2.08 milliseconds. The RTC utilizes
the processor interrupt 7 .5 which is an edge triggered input. Accuracy for
time of day clocks will only depend on the crystal accuracy and the ability
of the software to handle interrupts. The watchdog timer provides a reset
signal to the processor. It will continually attempt to reset the processor
until the watchdog timer begins rece1v1ng its own reset commands.

The Micro/1 CPU card utilizes the high speed CMOS logic family. The 74HC
family provides the noise immunity and power requirements of CMOS with the
speed and drive capability of 74LS TTL logic.

3
The off board interconnects provide clocks, controlling and I/0 access to the
rest of the Micro/1. These signals are all buffered to provide the maximum
amount of noise immunity. Only the I/0 data access is available off board
since the memory access has been restricted on board for noise immunity. The
top three quarters of the I/0 page is available for accessing the rest of the
Micro/1. The use of the I /O page provides additional security from the
accidental access of field devices.
I
2.1.2 Programming Information

The CPU card contains all memory locations for the Micro/ 1. Four sockets
divide the memory into four 16K byte sections with fixed addresses. These
addresses are fixed and independent of memory size, when using a smaller prom
or ram, the memory will be multiple addressed to fill the entire 16K block
where it is installed. When two contiguous memory chips are required that are
not 16K bytes in size, the two may be made contiguous by software addressing
them in the two blocks which are adjacent to the 16K boundary. For program
memory, the interrupt table must appear at Address O while the rest of the
program may start further up in the memory to allow continuity to the next
prom. Prom always starts in U7 which is the lowest memory. Ram should always
start in UlO which is the highest to memory section. UlO is where the battery
backed up ram must go if present. The 8K byte ram must be used for battery
backup.

The watchdog timer provides a reset when tripped. It is generated from the
bottom of the timing chain of the real time clock. The timer will continually
attempt to reset the CPU and system every quarter of a second unless it
receives a stream of strobe pulses generated by the software. The strobes are
generated by wr1t1ng to any of the lower 64 I/0 port addresses. These
addresses are not normally used for any Micro/ 1 I /O devices. The watchdog-
timer must be strobed at least as frequently as the cycle time for the slowest
realtime clock. For the normal strapping option, this amounts to once about
every 130 milliseconds. It does not hurt to strobe the unit much more
frequently than this. To achieve an optimum protection from the timer, a
scheme of WDT reset that requires realtime clock interrupts, background task
execution and memory integrity may be devised. By using a counter in memory
to be decremented during the realtime clock interrupt one can strobe the WDT
on the condition that the timer is non zero. Sufficient time may be allowed
for critical tasks or background tasks to be run and used to set the counter
in memory. Failure of the processor to accept interrupts or run background
programs will result in the triggering of the WDT and the reseting of the
processor.

4
 A16-A8 A16-AO 1/0 BUS
XTAL l -l 80C85 BUFFER ....
I A01-AOOrE
A7-AO

WOT I I I I

BUFFER ~7~0
07-00

CONTROL
I ATC
I I
I BUFFER r-0.!'"ROL

U1

TEJAS MICR0/ 1 CPU CARD

All Micro/I I/0 is accessed through the I/0 page. The top 192 addresses of
this page are allocated to I/0. The use of the I/0 page for I/0 access offers
two major benefits, the first and foremost is security of controls. Only two
instructions can access them for a select or an execute with the particular
I/0 address information residing in memory. The second benefit is a memory
map dedicated to program and data memory rather them be split between I/0 and
memory.

Memory Addressing:

IC

0 - 3FFFh U7
4000h - 7FFFh U8
8000h - BFFFh U9
COOOh - FFFFh UlO

I/0 Addressing:

IC

0 - 3Fh Watchdog timer reset

40h - FFh Offboard r/o access

6
2.1.3 System Flow Diagram

START
_ t__
INITIALIZATION

_l-- BACKGROUND
LOOP

CLOCKINT

t
UPDATE CLOCKj COMINT

NO
V
TEST AND
CALIBRATE?

V
Yes
----->
Yes
TEST

I
&
C
------->
COLLECT I
.-1
RX
RXtX l_t
TX

I A/D TIME 1-------> A/D DATA RECEIVE BYTE TRANSMIT BYTE

~ - - - Y e s _____ STATUS
I
_t
RETURN
t
RETURN
!STATUS TIMEl------->1 READ

N~----------- ---

SELECT TASK COS TASK

MSG TASK

1~-RITURN I <--------------------

7
2.1.4 Circuit Description

The microprocessor clock uses a 6.144 MHz crystal yl and the internal clock
generator of the 80C85, U6. The clock out, U6-37 provides a 3. 072 MHz clock
frequency to the dividing circuit. Ul5 a 74HC390 dual BCD counter, is used to
divide the signal by 2. This is then buffered through Ul2 to provide a 1.536
MHz signal to the rest of the Micro/1 system. This is the signal HICLK. Ul5
provides jumper outputs Wl7, 16, and 15 to generate the RTU timing chain. The
jumpers, Wl7, 16 and 15 provide clock speed of 3.072 MHz, 30,720Hz, and 307.2
KHz respectively. A 307 .2KHz signal is also buffered through U2 and made
available to the Micro/ l signal as LOCLK. The rte timing signals from the
jumpers goes into Ul6-10, a 74HC4040. Outputs QO through QlO may be jumpered
for the realtime clock output via jumpers W28 through Wl8. A nominal setting
of l.04lms is available at W24. The real time clock output proceeds to U6-
7. The RST 7 .5 interrupt input of the 80C85. Qll is run to Ul 7, a 74HC74.
If Qll has two positive transitions without Ul7 being reset, a watchdog timer
reset will occur. This will reset the processor and all Micro/1 hardware tied
to reset. An external power on reset circuit exists with CR!, R2, and C20
tied to Ull.

U6, the 80C85 uses U3, a 74HC373 latch, to latch the lower address lines.
Ull,a 74HC14 schmidt trigger, buffers the external interrupt requests RST5.5
RST6.5 and INTRQ, SID and SOD are buffered by Ul, a 74HC04.

The Micro/1 memory is composed of U7, 8, 9, and 10. These are 28 pin sockets
capable of handling 2K x 8 devices up through 16K x 8 devices. U7 is
dedicated to the lower quarter of memory and has jumpers Wl and W2 to select
Al3 or +5v. U8 is the second quarter of the memory map. It can be prom or
ram. Jumpers W3, 4, 5, and 6 determine Al3, + 5V, /wr, and All. U9 maps into
the third quarter of memory. It may be dedicated to either prom or ram.
Jumpers associated with U9 are W7, 8, 9, and 10. UlO is dedicated to ram. It
is in the top quarter of the memory map.

The off board interconnect consists of Pl and P2 connectors. The data address
bus, power, and control signals are carried on these connectors. All signals
are buffered on incoming and outgoing signals. U4 is a 74HC245, a
bidirectional bus driver. It is used to buffer I/0 writes, I/0 reads, and
interrupt acknowledge vector reads from off board. Ul4 is a 74HC244. It is
used to buffer address bits AO through A7 for offboard use. Individual
signals are buffered by a variety of gates.

2.2 MICR0/1 COMMUNICATIONS CARD (Cl002)

2.2.1 Description and Block Diagram

The communications card provides two serial communications ports, a Bell 202
compatible modem, indicator lamps, and program switches for setup. The card
is a 6 x 6 inch printed circuit board. It connects to the Micro/1 via two 20
pin connectors and is held in place by four standoffs. The board uses all
CMOS digital integrated circuitry for high noise immunity and low power. A
printer port is provided for more sophisticated applications.

8
2.2.2 Switc hes
unicat ions card. One bank
Three banks of dip switc hes are provid ed on the comm
usart s. Four switc hes are
is used to pass the baud rate clock signa ls to the
may be enabl ed at one
dedic ated to each usart and only one of each four baud. One bank
time. The switc hes selec t baud rates from 300 baud to 4800
by the Micro /1 CPU for
is compo sed of eight switc hes whose state s are read
confi gurat ion inform ation. The usage of these switc hes is defin ed by the
switc hes. The first seven
progra m. The third bank consi sts of a group of ten
are for confi gurat ion inform ation only. The eight h switc h may only be used
not being used. The ninth
for confi gurat ion when the local print er optio n is
indic ator lamps on the
switch is used to provi de switc hable power to all
board . This optio n provi des a savin gs in power .

2.2.3 Lamps
provi des indic ator lamps for servi ce and
The comm unicat ions card
ions lines and
maint enanc e. Six dedic ated lamps are used for the comm unicat in
ation s progra mmab le
eight progra mmab le lamps are avail able for indic receiv e line,
softw are. Each comm unica tion's line has indic ators on its
transm it line, and clear to send line. The eight progra mmab le lamps are
print er port. These two
driven by the same latch that drive s the paral lel the outpu t of
ed with
funct ions may coexi st becau se of the short time involv no usart s and
print chara cters. In speci al appli catio ns where there are
of the eight outpu ts may
seria l comm unicat ions is done by the Micro /1 CPU. Two
optio ns.
have to be dedic ated to modem contr ol throug h jumpe r

2.2.4 Seria l Ports

aces. These are based
The comm unicat ions card provi des for two seria l interf will allow for
The hardw are
on the CMOS versio n of the 8251 usart chip. devic es which
with most
opera tion with most all byte orien ted proto cols and is tied to
seria l port
are interf aceab le with RS232 seria l ports . The first to a stand ard
conne cts
the onboa rd Bell 202 comp atible modem. The secon d port can opera te with
that
RS232 comp atible DB25S conne ctor throug h buffe r chips secon d port may
n. This
TTL level or RS232 level s depen ding on the card optio contr ols.
run with modern
be run with a simpl e three wire interf ace or may be
baud and are indep enden tly
The seria l ports may run from 300 baud up to 4800
selec table in baud rate. The onboa rd modem is limite d to the baud rates of
provid ed from the maste r
300, 600, or 1200. Baud rate gener ation is norma lly
chip for 300 baud or
CPU clock or may be optio nally provid ed from the modem
Both usart s may be stoppe d for CPU inter rupts . An opto- isola ted
1200 baud.
radio keyer is provid ed for the first seria l port.

2.2.5 Modem
for Bell 202 opera tion or
The onboa rd modem is a TI TCM3101. It can provi de
rates up to 12_00 baud may be
some of the CCITT V.23 modes of opera tion. Baud
A sixtee n pin ribbo n conne ctor is used to bring the
run using this modem.
A test set interf ace card may
modem tones and digit al signa ls off the card. broug ht to the
The tones and radio keyer are
be inser ted for test purpo ses. conne ctions .
, and field wirin g
base, I/0 board for isola tion surge prote ction

9
 110 BUS COMM

.... ..., BUFFER

DATA USART (1) ....-. MODEM
202
00-07

[:J- 1
SWITCH (1)

1-----------~--U S_A_.,R_T-(2 _)_1.---j RS232C r±:

1 ::== 1=== ~~::1
AO-A7

______
._ ..
DECODE _ _ SWITCH 1 i
rr11-:<rr 2
SWITCH (2)

.....
0
CONTROi.
....
_,;o•rno1 BUFFER j LATCH (8)
PARALLEL ..._

It

LAMPS

MICR0/ 1 COMMUNICATIONS CARD

2.2.6 Programming Information

Card Addressing:

Address Install Jumpers (W22, 23, 24, 25)

80h-8Fh~'r W22, 25
90H-9Fh W23, 25
AOh-AFh W22, 24
BOh-BFh W23, 24

* standard address

Onboard Addresses (base address 80h-factory standard)

Address Function Access

80h Usart l(UlO) Data register I/0
81h Usart l(UlO) Control register I/0
82h Usart 2(U2) Data register I/0
83h Usart 2(U2) Control register I/0
84h, 85h Read Switch Sl I
86h, 87h Read Switch S2 I
88h, 89h Write parallel port (printer & lamps) 0
8Ah, 8Bh Write strobe for printer output 0
8Ch-8Fh Not used

11
2.2.7 Circuit Description (Cl002)

The communications card is an I/0 mapped card. Ul7 and Ul8 along with jumpers
W22-W25 decode the board addressing. A buffer chip, U3, is enabled by any
access to the board as detected by Ul9. Read and write options are qualified
for the simple devices by Ul4. Jumper Wl6 - W21 allow selection of a
receive/transmit interrupt from each USART or a combined interrupt from both
USARTS for assignment to restart 5.5 and 6.5.

The modem section is composed of UlO, Ull, Yl, U12, Ul5 and U9, Jumpers W4
through WlS are associated with the circuit. Ull is the modem. Tones are
buffered through the op amp Ul5 and run to the connector P3. There are three
adjustments associated with this circuit. One is the carrier output level.
The two others are a receive bias adjustment and the carrier detect level. P3
includes power supplies and digital level signals to allow for a test card
connection for checkout purposes. In normal operation only the transmit and
receive tones and the radio keyer signals are utilized offboard. A special
+Sv power regulatory Ql, 1s provided to power the modem chip since the
adjustments are voltage sens1t1ve. Three lamps; DS1, DS10, and D89 are
provided to indicate data transfer signals. Ul6 and Q2 provide the transmit
keyer for use in radio applications. UlO is the usart.

The second serial port is composed of Ul, U2, and U7. U2 1s the usart. U7 is
the output buffer. Ul 1s the input buffer. Wl, 2, and 3 select the
appropriate driver voltages for U7 in RS232 or TTL level applications.
Connector P4 provides an R8232 compatible DB25-S connection to the outside.
Lamps D812, 13 and 14 provide indications for the serial port activity.
Pullups are provided for incoming control signals to allow for 3 wire operator
default as well as full modem control operation.

Baud rate for both serial ports is provided by 83 and U8. The 302.?KHz LOCLK
signal from the micro/1 CPU is divided down by 48 to provide suitable x 16 and
x 64 rates for the usart baud rates. The modem clock output may also be used
to run the usarts at the 300 baud and 1200 baud data rates.

Programmable lamps and the printer port are composed of U6, DSl-8, and PS.
The 8 bits of parallel data may be used to indicate software status and may
be used to output characters to an external printer or device. A write strobe
line provides a latch signal while one of the dip switch inputs is run to PS
from US to allow for a status bit input. Data bits 6 and 7 may also be
strapped by jumper WS and W3 to provide carrier turn on and radio keyer turn
on in the event that UlO is not used.

Sl, 82, U4, and US provide up to 16 program readable configuration bits.

Closing of a switch provides a logic low input to the processor. Bit O of 82
may be used for the parallel port status input if switch 82 position 8 is left
in the open position.

The Cl002 utilizes input voltage of +Sv, and +/- 15v. Onboard regulators
provide the necessary 12 volts for the RS232 levels. A +Sv regulator 1s
provided for a stable voltage for the modem Ull. This allows the board to
be ca1ibrated and be independent of the base I/0 board power supply.

12
2.2.8 LED Lamps on Communications Board Definition

0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
Heart Clk Cint Ren Rxst Cinit Cintl n/u

DSl Heart- Heartbeat on 500 msec, off 500 msec.

DS2 Clk- Turned on at begin of Clock interrupt, off upon return.
DS3 Cint- Turned on at begin of Comm interrupt, off upon return.
DS4 Ren- Re-entrancy alarm, comes on if programmer puts too much code
in the clock routine and it re-enters clock before it exits.
This should never happen (this alarm reset only by RESET).
DSS Rxst- Receive Start (test point for oscilloscope while debugging comm
errors) pulses everytime routine "Rxstrt' sets executed. If
watched on dual trace concurrently with "RXRDY", coincidence
with the 5th RXRDY pulse means bad LRC or message is for other
RTU.

Coincidence with other RXRDY means message does not meet

standards for good message (e.g. parity error), so set up for
first byte of message. When no RX data coming in, this signal
pulses every 25 msec, constantly getting ready for new message.

DS6 CINIT- r,/ TURNED ON WHEN COMMUNICATION WITH MTU rs LOST FOR MORE THAN 10
vJT-SEC. AND OFF WHEN COMMUNICATION IS RESTORED. Toe/~
I ,,
v ~/) '),/}f '; -,-
~ O~,;-J y~~->
CINTL- TURNED ON WITH CINIT ABOVE AND OFF WHEN CPU RESET OCCURS.

DS8 NOT USED,

13
2.3 BASE I/0 BOARD (Cl003)

2.3.1 Description and Block Diagram

The base I/0 board is the field interface section of the Micro/1. Power and
field wiring are brought into the Micro/1 through the base I/0 board. Power
to run the Micro/1 is brought in as a single voltage and used to generate all
of the required levels. Optically isolated status inputs provide for the
digital input monitoring. Analog inputs are available for monitoring of field
signals. Momentary relays provide control capabilities. Configuration
switches al low implementation of various configurations and software
options. A modem termination allows for the isolated field interface of the
communication card. Field I/0 has expansion capabilities as well as on board
capabilities. I/0 has surge protection and the board has ground planes to
minimize effects of noise and destructive surges. All field connections are
removable terminal blocks.

2.3.2 Power Supply

The base board power system is driven by 24vdc nominal input. In minimal
configurations, all of the Micro/1 may be run from this single input,
including analog current loops and status loops. The 24vdc is used to switch
relays and generate the analog and logic voltages for the operation of the
Micro/1. Analog loops and status loops may be optionally powered from this
source or from external sources. The base board uses switching regulators to
generate the +5 volts and the -15 volts required by the circuitry. A linear
regulator is used to generate +15volts. A zener diode and fuse protects the
+5v power line from over voltage. Input voltage is protected by gas tubes and
transzorbs. The sections of the 24v lines are decoupled from each other by
low value resistors and decoupling capacitors. A switch 1s provided to
disable relay controls.

2.3.3 Status Input

The status section is composed of 16 optoisolated form A inputs. Expansion

cards may be added to bring the unit up to 64 form A input. Both gas tube and
transzorb surge protection may be used. Inputs are polled by the processor
and options such as form C inputs, sequence of events, and accumulation are
handled in software. The status loops may be powered from 24vdc or 48vdc loop
supplies with no change in componentry. Larger loop voltages are optional.
The status circuitry provides a great deal of surge protection even without
the use of the transzorbs and gas tubes. LED indicators provide the user with
immediate indications of the state of each input without causing additional
power drains on low power systems. Debounce is handled in software.

14
 DATA BUS

STATUS EXP ANSION

MODEM M
ISOLATION STATUS
SIGNALS I
STATUS
--
STATUS INPU TS ( 18)
SWITCH (1)

sELECT
ADDRESS - - { : : y E C O D E
AO-A7
! TATUS
'4Al00S
S ELAYS
ANALOGS ,_ CONVERTER
ANALOG EXP ANSION

i't'ITCHES
1/0 READ .
1/0 WRITE

,_. I
Vt

I SWITCH (2)

I
MUX -

ANAL( G INPUTS (8)

- i2 EXPA NSION
4 voe RELAY
24 voe •111 voe CONTROLS
.!f•voe
voe
~
RELAYS
CONTROL 01. TPUT (8)

MICR0/ 1 BASE 1/0 BLOCK DIAGRAM

2.3.4 Analog Input

The analog circuitry allows for eight differential inputs. Up to 64 inputs

may be implemented by use of expansion cards. The A/D offers 11 bi ts plus
sign resolution and 10 bits of accuracy for voltage and current inputs of+/-
Sv, 1 to Sv, +/- 1 ma, and ~ o 20 ma. Conversion times of 25 microseconds,
typical, allow for analog acquisition rates of up to 1 point per
millisecond. Individual front end op amps allow for higher common mode
operating ranges and for pre-multiplex or filtering of noise. On board
current loop resistors are provided for current loop applications and inputs
are not restricted to the lowest loop resistor on the chain to maintain
accuracy. Gas tubes are optional for surge protection.

A voltage reference and monitoring section is provided. Precision voltage

references are provided for+/- 90% of full scale. These may be calibrated in
a narrow area around 90% ful 1 scale and used to verify the accuracy of the
analog to digital converter and the final opamp stage. In addition to the
precision references and ground, the major power supplies of the Micro/1 may
be measured. Precision resistor ratios allow the monitoring of +24v, +Sv,
+lSv, and -Sv. These do not take up any of the field inputs.

2.3.S Relay Output

The relay section provides for four trip close momentary relay points (eight
form C relays). Expansion cards may be used to bring the count to 24 trip
close points. The relays are organized in a matrix of rows and columns. The
on board relays provide the first bank of eight. The other banks are decoded
on the board and brought out to the expansion connector. The CPU may select
up to 8 relays in a bank. Single relay activation may be implemented in
software with protection from accidental relay trips, even with single
component failures. A relay power switch allows the disconnecting of relay
controls with a detectable error condition for software.

2.3.6 Configuration

The base board has two eight pos1t1on dip switches for configuration. Each
switch may be read by the processor. These switches are intended to contain
the I/0 configuration information such as form A, or form C status, number of
accumulators, and number of expansion modules. The information is software
definable.

2.3.7 Modem Interface

The Modem interface provides the field interconnects for the modem located on
the communications card. Transformer isolation for the tone lines is provided
by 600 ohm 1 ine transformers. Both transzorb and gas tube protection are
provided for the tone lines. The terminal block provides shield and local
ground plane connections for special noise sensitive environments. The radio
keyer is provided with transzorb protection at the same terminal block.
Jumpers for full and half duplex operation are provided on the P. C. board.

16
2.3.8 Base I/0 Board Circuit Descriptions

The Base I/0 Board has pin headers for the mounting for the CPU,
communications card and the field I/0. Power is brought in and regulated down
to the appropriate voltages for the logic circuitry. Address select
circuits address all of the I/0 sections on the card. These include the
configuration, states, analogs, and relay sections.

2.3.8.1 Power Supply

The power supply section takes 24VDC and generates +5 and +15V for the rest of
the circuitry. +SV and -15V are created by switching regulators. +15V is
generated by the linear regulator VR2. Ml3,R93, and Ll form the basic
elements for the SV regulator. Ml2,R85,Q5, and L2 form the basic elements of
the -15V regulator. Both the +SV and -15V are adjustable while the +15V
supply is fixed.

2.3.8.2 Address Decode

The address decoding section consists of M39,U37 and U34. M39 selects when
the address bits AB7 through AB3 are all high. AB2/l and O feed the input of
decoder chips U37 and U34. M37 in enabled for I/0 reads for the address range
F8h to FFh and U34 is enabled for I/0 writes for same address range.

2.3.8.3 Relay

The relay section provides control and monitoring of the relay coils. The
coils are arranged in multiple fashion for 8 select lines and up to 6 banks,
with the first bank being the one on board. U29, U30, U27, U28, U41, and U42
provide the select latch and drive current sink for the relay coils. DS17
through DS25 provide visible indications for the presence of the state of the
select lines. U36, U38, and Ql through Q6 provide execute signals for bank 1
through 6. The execute line source current by relay bank. Relay coils that
are provided simultaneous sink and source paths are energized. U33 provides a
read back to the CPU of the condition of the execute lines. The lamp DS2 l
provides an indication of the state of bank and the on board relay bank. S5
offers a local disconnect of the relay voltage source.

2.3.8.4 Configuration

The configuration section of the board consists of two 8 pos1t1on DIP

switches. These are Sl and S2. The switch positions are read by CPU through
the buffer chips UlO and Ull.

17
2.3.8.S Status

The status section includes 16 on board points and expansion for 48 offboard
points. The status inputs are organized as 8 bit bytes that may be read by
the CPU through the buffer U20. Ul9 and U21 are latch and decoder used to
select the desired status byte to be read. There are two onboard status bytes
that may be read and upto six off board bytes for the total of 8 bytes ( 64
points). Ul8 and U22 are the buffer for the onboard status bytes. The dual
opto isolators Ul4-Ul7 and U23-U26 provide the isolation for the status
inputs. The lamps DSl through DS16 provide visual information as to the state
of each contact loop. The front end protection includes optional gastubes and
transzorbs, carbon slug resistors and high voltage capacitors.

2.3.8.6 Analog

The analog section includes 8 onboard inputs and up to 56 offboard inputs.

Point selection is achieved through US and U6. U6 is an octal latch which
stores the encoded point number and the input voltage reference select flag.
US decodes the selection of which 8 point multiplexor is to be used. Each 8
point multiplexor point is selected by the least three address bits latched by
U6. The onboard multiplexor is U4 which accepts 8 single ended opamps. Field
signals come into the opamps as differential inputs. The inputs are
attenuated and converted to single ended signals before being fed to the
multiplexor chip. A simple RC filter is provided for each input prior to
multiplexing. A voltage monitoring and reference section is also provided for
the monitoring of precision references and for the monitoring of the Micro/1
power supply levels. The precision references are Q4 and Q3. These are
adjustable to+ 90% of full scale by R65 and R66. The Micro/1 power supplies
which are monitored are +24V input, +SV, +lSV, -lSV and -SV. Each analog
signal, when selected, is fed into Ul, the restoring opamps. Ul compensates
for offset for 1 to SV inputs (such as 4-20ma loops). R58 provides the gain
adjustment. RS 7 provides an off set adjustment only when Wl8 is installed.
The output of Ul is fed to U44, the A/D converter. R59 and R60 provide the
adjustments of gain and offset for the A/D. The conversion occurs when the
A/D convert command is received from the addressed decode circuitry. U40 and
U43 provide the buffering to the data bus. The conversion in process flag is
fed to U40 as the MS data bit to indicate to the CPU that the conversion is
not finished.

18
2.3.9 Programm ing Informa tion

Section Function (Operati on) Data Address

Status

Select byte to read (write) XXXXlnnn F8h

I I
don't care byte N=0-7

Read byte of status (read) ssssssss F8h

I I
MS bit LS bit

byte N = 0 - LS byte
byte N = 7 - MS byte

Analog

Select point to convert (write) VrXPPPPPP FDh

I
- point Oto 63
Vr = 1 analog
Vr = 0 referenc e

Start conversi on (after

settling delay) ( write) xxxxxxxx FCh

Read low data (read) DDDDDDDD FCh

I I
bit 7 - bit 0

Read high data (read) SXXXDDDD FDh

I
S = 1
I
- bit 8
bit 11
convert in process
S = 0
convert complete

19
 Section Function (Operatio n) Data Address
Relay
Select relay'" (write) NNNNNNNN F9h
I I
K8 - - Kl
Verify select (read) NNNNNNNN F9h
I I
K8 - - Kl
Execute (write) XXNNNNNN FAh
I I
Bank 6 - - Bank 1
Verify Execute (read) XXNNNNNN FAh
I I
. Bank 6 - - Bank 1
Cancel (write) xxxxxxxx FBh

Configura tion Switches

Read Sl (read) ssssssss FFh

I I
Bit 7 - - Bit 0
1 = open
0 = closed
Read S2 (read) ssssssss FEh
I I
Bit 7 - - Bit 0

*Automat ically cancels any existing execute as does a master reset.

20
2.4 Expansion Boards

2.4.1 Relay Expansion Board (Cl004)

The relay expansion board provides up to 4 momentary or 8 latching controls.

All current sinking and sourcing for controls is performed on the base I/0
board. The board can be configured to run all latching relays or a
combination of momentary and latching relays. In the first case up to 8
latching relays can be used. In a combination configuration momentary relays
can be used or one latching relay can be used in place of two momentary
relays.

Several jumpers determine addressing and operating configuration on the

board. Each relay is provided with a LED which lights up to show that a relay
is being operated. Connectors Jl, J2 or J3 connects the board to the base
board and other relay expansion boards.

2.4.2 Status Expansion Board (ClOOS)

The status expansion board consists of 16 digital inputs. These inputs are
organized as 8 bit bytes that may be read by the CPU through the buffer U3 on
the base I/0 board. U3 and US are the on board buffer for status bytes. The
dual optoisolators Ul-UlO provide the isolation for the status inputs. The
LED's DSl through DS16 indicat~ the state of each status input. The front end
protection includes carbon slug resistors, high voltage capacitors, and
optional transzorbs and gas tubes.

Jumpers Wl-Wl2 select the address of the expansion board. Only one jumper is
used out of each pair of consecutive jumpers like Wl and W2. Each jumper
defines one byte of status inputs. The card is connected to the base I/0
board or other status expansion boards through connector Jl, J2 and JS.
Connectors TBS and TB6 are used to power status inputs.

2.4.3 Analog Expansion Board (Cl006)

The analog expansion board contains 8 differential inputs. U3 is an octal

latch which stores the encoded point number. 03 accepts 8 single ended op
amps. Field signals come into the op amps as differential inputs. The inputs
are attenuated and converted to single ended signals before being fed to the
multiplexor chip. A simple RC filter is provided for each input prior to
multiplexing.

The jumpers on the board select the address of the card. The analog expansion
board derives its power from the base I /O board. Connectors Jl, J2 or J3
connect the board·to the base board or other analog expansion boards.

21
 RELAY OUTPUT POI~T

EXECUTE

FOR}! C OUTPUT
SELECT

22
 STATUS INPUT POINT 24v/48v

EXTER...~AL A C
STATUS
POWER+
~ 0 o.-------•ii ,, INTERNAL 24v STATUS POWER+
+SV
B

+ CONTACT '
_J WS

lOOK

INDICATOR
LED O?TO ISOLATOR

3. 9K* 1W STAT:
- CONTACT -·Po IN~

** .02vf IN4001 or
GASTUBE TRA.'f'.JSZORB
OPTIONAL soov (OPTIONAL)

W4
.d
•EXTER.i.~AL
"STATUS 41~--oA Q~-----_ .ri.
\.,
INTERNAL 24v STATUS POWER -
POWER -

* RESISTOR IS CARBON COMPOSITIONS LUG. VALUE IS FOR 24v/48v STATUS.

**
m GUARD RING.

23
 A.."'IALOG INPUT PO INT

200K*

499K*
ANALOG -

ANALOG
POrnT

Ai.'iALOG +
499K*

200K*

* RESISTORS ARE MATCHED TO .01% ACCURACY FOR HIGH COMMON MODE REJECTION.
** LOOP RESISTOR SK .02% FOR ±1 Xa LOOP, 250 OHM FOR 4-20 Ma LOOP
*** 177 r,uARD RING

24
3.0 MICRO 1 FIRMWARE

3.1 Overview

The Micro/1 software provides remote functions and a communications protocol

compatible with the existing line of CAM/DAC remotes. It is based on the
CAM/DAC RTU software package. All real time tasks are interrupt based. A
realtime clock interrupt provides 960 ticks per second to generate the timing
for the unit. A test and calibrate mode, TAC. is provided for calibration and
checkout of the unit. Status and accumulator inputs are processed for
debounce and counting by the program. An analog section provides the timing
and control for analog acquisition. The Relay Control section operates and
monitors the relay hardware. A watchdog timer routine is executed when the
software is operating properly to prevent the watchdog timer from resetting
the RTU.

3.2 Interrupt Structure

The Micro/1 utilizes two basic interrupts. In normal operation the CPU
executes an idle loop routine. The only operation performed is to keep the
watchdog timer reset. All operations are performed as a result of an
interrupt request. The top priority interrupt is RST7.5. It is reserved for
the realtime clock. All CPU timing, field I/0 control and monitoring are
initiated from the clock routine. The other interrupt 1s for
communications. This interrupt ,RST6.5, flags the processor on communication
matters. Both transmit and receive interrupts are shared by this priority
level.

3.3 Power Up Sequence

On power-up or watchdog timer trip, the CPU is forced into the reset mode.
This mode also provides reset signals to other programmable IC's in the
unit. When reset mode ends, the CPU begins the initialization sequence.
Programmable IC's are programmed, certain values are set to predefined
states.Configuration switches are read. A security code located in memory
is tested for validity to distinguish between a watchdog time trip and a power
outage.

3.4 Real Time Clock Interrupt

The realtime clock interrupt, RST7.5, is run at 960 Hz. This provides an
interrupt period of 1.041 milliseconds. Timing of 6.25 ms may be generated by
6 periods while 25ms timing is accomplished by 24 periods. The RTC provides
timing for the analog acquisition and 60Hz filtering. Status data is read
every 15.6 ms. Relay control timers and request to send timers are also
incremented by the RTC. Various tasks associated with change of state, and
message transmissions are set up in the RTC.

25
3.5 Message Processing Task

The Message Task is entered from the RTC task when setup from the
communication interrupt. This occurs when a valid message has been received
through the receive interrupt. The message task decodes the received message
and builds a response. When the response is built, the USART is switched to
the transmit sequence and will commence transmission after the clear to send
delay.

3.6 Communications Interrupt

The transmit and receive interrupt, RST6.5, is engaged in the normal

"quiescent" state of the RTU. The processor is interrupted on a byte by byte
basis for incoming data. When a complete message has been received and
verified as being a valid message for this RTU, the program sets a request for
the clock interrupt routine to schedule the message task.The transmit
interrupt is entered when the USART transmitter has been enabled and the USART
output buffer is empty. The transmitter is turned on at the end of the
request to send-clear to send delay time. A byte of data is loaded into the
USART and the interrupt is exited. When the last byte has been shifted from
the USART, the transmitter enable is shut off and the USART is placed in the
receive mode.

3.7 Analog Processing

The Analog acquisition software provides for the reading of a new analog point
every 6.25 ms. The conversion requires about 25 microseconds to complete and
is made for the point selected in the previous execution of the routine. This
conversion is started by an output to address OFCH. On conversion complete
bit D07 of the A/D high byte will go low indicating that the 12 bits from the
A/D high and low bytes are valid. The software reads each input twice, 25
milliseconds apart. This provides two readings which are 180 degrees out of
phase for any 60Hz noise. The two readings are averaged together to eliminate
the 60Hz component prior to storing in the RTU data base. The A/D databytes
are read at OFDH and OFCH. After a conversion has been made, the analog
multiplexor is set to the next input point and the program is exited to allow
another 6.25ms settling time.

3.8 Status Processing

The status input program reads 1n points every 15 milliseconds. If the

processor recognizes a change, it will verify the data 5 ms later to allow for
settling, status bytes are read through port OF8h. The byte is selected by
writing the status bank select to port OF8h with the status bank enable bit
(bit 08h) set. Banks 1 through 8 are enabled by selecting enable O through
7. The bytes correspond to 08h through OFH with the enable bit set. The
configuration switches determine whether the status inputs are treated as
status, form A accumulators or form C accumulators. Form C accumulators are
composed of two adjacent status points, Form A accumulators are single status
points. The configuration switches specify the number of status input cards
and the number of accumulators in the system.

26
Accumulators are maintained as 12 bit registers which are incremented once per
cycle of the field input point. On form C accumulators both inputs must cycle
to cause an increment of the count. Accumulators are the last N status points
in the unit. Form C accumulators use adjacent status points. The last status
input is the first accumulator. The second to the last 1s the second
accumulator (form A), and so on.

3.9 Control Processing

The relay control operation is composed of three steps. First, the point must
be selected. This is done as a response to the communications reception of a
control select command. The coil will be tied to the relay current sink.
Four controls may be selected, each control having two coils. For momentary
control relays, this is eight form C relays. For magnetic latching relays
this is four relays. The control points are paired together in trip-close
pairs of coils. Even bit numbers (7-0) correspond to close relay coils. Odd
numbered coils correspond to the trip coils. Relay Kl corresponds to bit O, a
close coil for point one. The second step is the checkback function. If any
coil other than the one to be selected has been selected, a cancel command
will be generated. The third function is the execute or operate command. The
source current to a bank of relays is engaged on operate. The selected relay
coil will be energized. The CPU will read back the bank execute port to
verify that only the appropriate bank will be powered up. In the event that
multiple banks or the wrong bank has been powered up, the CPU will cancel the
command before the relay has been completely energized. The CPU decrements
the relay execution timer in the clock routine, so that it will be deenergized
at the appropriate time defined by the control message.

27
4.0 JUMPER OPTIONS AND SWITCH SETTINGS

4.1 Jumper Options

4.1.1 CPU Card (ClOOl)

The Micro/1 has thirty jumper options. These options may be divided into two
functions. These are memory selection and real time clock interval
selection. Jumper options Wl through Wl2 and W29 and 30 are associated with
the memory while Wl5 through W28 select the rte options. There are fourteen
real time clock selections and six prom/ram type of selections.

The Jumper descriptions are:

state
Wl select Al3 for memory chip U7-26 install for 27128 prom (or 2764)
W2 select +5v for memory chip U7-26 install for 2732
W3 select write for memory chip U8-23 install for 6116 ram chip
W4 select All for memory chip U8-23 install if not 6116
W5 select Al3 for memory chip U8-26 install for 27128, 2764, 6264
W6 select 5v for memory chip U8-26 install for 2732 or 6116
W7 select write for memory chip U9-23 install for 6116 ram chip
W8 select All for memory chip U9-23 install if not 6116 ram chip
W9 select Al3 for memory chip U9-23 install for 27128, 2764, 6264
WlO select 5v for memory chip U9-26 install for 2732 or 6116
Wll select write for memory chip Ul0-23 install for 6116
Wl2 select All for memory chip Ul0-23 install if not 6116
Wl3 select Al3 for memory chip Ul0-26 (not used for present chips)
Wl4 select 5v for memory chip Ul0-26 use for 6116 or 6264 no B.B.
W29 select power down for chip Ul0-26 use for 6264 with B.B. option
W30 AB select 5v for chip Ul0-28 use for 6264 no B.B.
W30 BC select B+ for chip UlO use for 6264 with B.B.
Wl5 + 10 provides 307,200 Hz to counter chain (special use only)
Wl6 + 100 standard 30,720 Hz to counter chain
Wl7 + 1 provide 3.072MHz to counter chain (special use only)
Wl8 + 2048
Wl9 + 1024
W20 + 512
W21 + 256
W22 + 128
W23 + 64
W24 + 32 l.046ms standard setting provides (3.072mHz/l00)/32 = 960Hz
W25 + 16
W26 + 8
W27 + 4
W28 + 2

Jumper state: x = jumper 1n

blank= jumper out

28
 4.1.2 Communications Card (Cl002)

state
Wl Provide -12v for RS232 driver chip in U7
W2 Provide +12v for RS232 driver chip in U7
W3 Provide +5v for TTL driver chip in U7
/ X W4 UlO (usart 1) provides RTS for modem transmit enable
W5 U6 8 bit latch provides RTS for modem transmit enable
X W6 UlO (usart 1) provides transmit data to modem
W7 CPU SOD signal provides transmit data to modem
X W81( Modem - Bell 202 option strapping
W9>'( Modem - Bell 202 option strapping
Wl01( Modem V23 option strapping
z .i:._ wll ,'( Modem Bell 202 option strapping
Wl2 1( Modem V23 option strapping
Wl3 U6 8 bit latch control of radio keyer
X Wl4 UlO usart 1 DTR control of radio keyer
Wl5 Connection of Tx data to Micro/1 cpu SID input
X: Wl6 UlO (usart 1) interrupt request to RST 6.5
Wl 7 UlO (usart 1) interrupt request to RST 5.5
Ul8 UlO and U2 (usarts 1 & 2) or'ed interrupt request to RST 6.5
Ul9 UlO and U2 (usarts 1 & 2) or'ed interrupt request to RST 5.5
U20 U2 (usart 2) interrupt request to RST 6.5
U21 U2 (usart 2) interrupt request to RST 5.5
X U22 Address select AB4 low
U23 Address select AB4 high
U24 Address select AB6 high
X U25 Address select AB6 low

*see Tl TCM 3101 data sheets for detailed strapping information

Jumper state: x = jumper in

blank= jumper out

29
4.1.3 Base I/0 Board (Cl003)

lxl Wl
W2 A-B, C-D
Ties modem gas tube grounds to guard ring
Ties modem lines for half duplex mode

W3 A-C Ties shield at modem transformer to terminal block

connection
1=1 W3 BC Ties shield at modem transformer to digital ground

W4 A-B Provides status loop power externally

ws AB

I'='I ws
W4 BC Provides status loop power externally
BC

Wl8 Include analog offset for 1 to Sv operation

Jumper state: x = Jumper 1n

blank= Jumper out

30
 4.1.4 Relay Expansion Board (Cl004)

Relay Type Select Jumpers:

W4 Momentary or Momentary/Latch ing combo

Wll Momentary or Momentary/Latch ing combo
Wl8 Momentary or Momentary/Latch ing combo
W24 Momentary or Momentary/Latch ing combo
W22 Momentary or Momentary/Latch ing combo
-
W3 Latching only
ws Latching only
WlO Latching only
Wl2 Latching only
Wl7 Latching only
Wl9 Latching only
W23 Latching only
W25 Latching only

Address Jumpers:

Select one jumper out of one of the pairs for momentary or momentary/latch ing
combination operations. The selection of either jumper out of the pair is
transparent to the CPU. Select two jumpers, one each from a different pa1 r
for latching only operation. In this case first Jumper selects relays on
connectors TBS - TB8, whereas the second one selects TB1 - TB4.

Selects relay bank 0

I /I ~! Selects relay bank 0

I /I ~; Selects relay bank 1

Selects relay bank 1

I , I ~~ Selects relay bank 2

Selects relay bank 2

Wl3 Selects relay bank 3

YI I Wl4 Selects relay bank 3

,=, WlS
Wl6
Selects relay bank 4
Selects relay bank 4

W20 Selects relay bank 5

II W21 Selects relay bank 5

31
4.1.5 Status Expansion Board (C1005)

Jumpers on status expansion board define the address of the board. Each pair
defines one status by~e. Only one jumper needs be selected out of a pair and
only two jumpers are required on the entire board. Fist jumper in each pair
defines status inputs on connectors TB1 and TB2, whereas the second jumper
defines TB3 and TB4.

Wl Selects byte in
W2 Selects byte 113
W3 Selects byte 114
W4 Selects byte il4
W5 Selects byte 115
W6 Selects byte lf.5
W7 Selects byte lf.6
W8 Selects byte il6
W9 Selects byte in
WlO Selects byte ill
Wll Selects byte il8
W12 Selects byte if.8

NOTE: Bytes 1 and 2 are used for status inputs on the base I/0 board.

Jumper state= X = jumper 1n

blank= jumper out

32
4.1.6 Analog Expansion Board (Cl006)

Only one of the jumpers Wl-W7 should be selected to define the address of the
analog expansion board.

Wl Selects expansion card 117

W2 Selects expansion card 116
W3 Selects expansion card 115
W4 Selects expansion card 114
ws Selects expansion card 113
W6 Selects expansion card 112
W7 Selects expansion card Ill
11
NOTE: Base I/0 board is assigned to card 0 11 •

Jumper state X = Jumper in

blank= Jumper out

33
4.2 Switch Settings

4.2.l Communic ations Board (Cl002)

SWITCH 1

I 1 I 2 3 I 4 I s I 6 I 7 I a
\~_! \ I
SPARE SWITCHES

On selects the radio mode. RTS/CTS

delays specified below are
multiplie d by 6

Select RTS/CTS delay as follows:

SP2 SP3 DELAY

OFF OFF 10 M.S.
OFF ON 30 M.S.
ON OFF 60 M.S.
ON ON 200 M.S.

On Selects the baud rate multiplye r.

----- ----- ----- 8au d rates on page % are multiplie d
by
4.
SWITCH 2 (RTU MODE)

I 1 2 3 4 s 6 1 a 9 I
\ I
------ ,,----- --- LED power switch. ON supplies power to
the onboard LED's.

RTU ADDRESS. A number from 1 to 127

be selected. Switch position 2 is the
MSB, 8 the LSB, ON is a 1, OFF is a O.

RTU mode selection switch. On selects

the normal mode. Off selects the test
and calibrate mode. The test and
calibrate mode redefines the meaning of
Switch 1 and 2, Position 1 through 8 as
defined below.

34
SWITCH 3

Switch 3 selects the baud rates for the two USARTS on the MICRO 1, only one
switch position can be on at a time for each USART. The baud rates listed
below are multiplied by 4 when baud rate multiplier switch is on.

1 I 2 I 3 I 4 I s I 6 I 7 I 8 I
I_ USART 1, 300 baud (use modem clock)

USART 1, 300 baud (use internal clock)

USART 1, 600 baud (use internal clock)

USART 1, 1200 baud (use internal clock)

USART 2, 300 baud (use modem clock)

USART 2, 300 baud (use internal clocK)

USART 2, 600 baud (use internal clock)

-----
USART 2, 1200 baud (use internal clock)

Dedicated Switches:

Switch 2 position 9 power to on board lamps

Switch 3 eosition Function

1 usart 2(U2) 4800/ 1200 baud"(

2 usart 2(U2) 2400 / 600 baud>'<'
3 usart 2(U2) 1200 / 300 baud"(
4 usart 2(U2) 1200/300 baud>'d(
5 usart l(UlO) 4800/1200 baud*
6 usart l(UlO) 2400/600 baud>'(
7 usart 1(UlO) 1200/300 baud"(
8 usart 1 (UlO) 1200/300 baud>'(>'(

* usart is programmed internally by software to select which of the two baud

rates listed will be used
** baud rate generated by modem

35
4.2.2 Base I/0 Board (Cl003)

SWITCH 1

I i 2 3 4 5 6 7 a I
Number of accumulator s. --,
A maximum of 31 accumulator s
can be selected they begin
physically at the end' of the status
inputs. Switch position 6 is the MSB
8 the LSB, ON is a 1, OFF is a O.

ON selects form~ accumulator s

OFF selects~ C.

Number of status expansion boards.

A maximum of 3 boards can be selected
switch position 1 is the MSB, 2 the LSB
ON is a 1, OFF is a O.

SWITCH 2

I i 2 3 4 5 6 7 a I
Number of analog expansion boards. A
maximum of 7 boards can be selected
switch position 6 is the MSB 8 is the
LSB, ON is a 1, OFF is a

~~~~~~~~~~~lects two reference analogs as

values 1 and 2. This reduces useful
points on baseboard to 6 values
(points 3-8).

~~~~~~~~~~~~ enables analog processing, OFF

disables all analogs.

Spare switches

36
5.0 TECHNICAL SPECIFICATIONS

5.1 CPU Card (ClOOl)

Microprocessor 80C85
Speed 3.072 MHz (6.144 MHz crystal)
Realtime clock intervals 65 usec, 130 usec, 260 usec,
520 usec, l.04ms, 2.08ms, 4.16ms
8.33ms, 16.66ms, 33.3ms, 66.6ms

RTC interrupt RST 7.5 edge triggered

WDT interval 133ms nominal (function of timing

chain)

WDT reset output to I/0 port 0-3Fh

Memory 4 sockets (28 pin)
Prom
Number of Ics 1 to 3 (24 pin or 28 pin)
Allowable type 2732, 2764, 27128, 27C32, 27C64
Prom storage area 4K bytes to 48K bytes

Ram
Number of Ics 1 to 3 (24 pin or 28 pin)
Allowable types 6116, 6264
Ram storage area 2K byte to 24K bytes

Power requirement 5v +/- 10% 30 mils nominal

(without proms)
Board size 5 11 X 611
Bus Micro/! Master bus - dual 20 pin
connector
Environment -20c to +70 C 0-95% humidity non-
condensing
ESD Sensitive to electrostatic dis-
charge - handle with care.

37
5.2 Communications Card (Cl002)

I/0

Modem channel 1 Bell 202 or CCITT V,23 compatible

Baud rate 300, 600, or 1200 baud
Format byte oriented protocols
Connection 16 pin ribbon cable
Output adjustable Oto -15 dB
Input range 0 to -40 dB

Carrier detect threshold adjustable - 43 dB to - 48 dB

Carrier detect delay 15 ms nominal, 19 ms worst case

Isolation & protection external

Clear to send delay software programmable

Radio keyer opto isolated open collector

Serial Channel 2 RS232 or TTL Level compatible as options

baud rates 300, 600, 1200, 2400, or 4800 baud
Format byte oriented protocols

Connector RS232 compatible DB25-S

Signals out Tx data, RTS, DTR

Signals in Rx data, CTS, DSR

Operation Full modem control or 3 wire data only

Parallel port

Psuedo centronics 8 latched data bits

interface 1 400ns negative going output strobe
1 status level input
Logic family high speed CMOS
Connector 14 pin ribbon

Board
Size 6 x 6 inch pcb
Environment -20 to +70'C 0-95% humidity non-condensing
Interface dual 20 pin .l" connectors -Micro/1 slave bus
Power +5v 100 ma nominal
+/- 12v, 30 ma nominal

38
5.3 Base I/0 Board (Cl003)

General

Board 11" x 14" double sided PCB

.093" thickness
2 oz. copper plate

Mounting 6 stand offs

Field Connectors Pluggable compression fitting terminal blocks

12 to 28 ga standard wire

Power 24v DC@ 120 ma nominal including CPU &

Communications

Environment -20'C to +70'C 0-95% humidity non-condensing

Special Features Heavily ground planed for noise immunity

uses HCMOS logic for noise immunity and low
power guard ring surrounding entire board for
surge protection and grounding.

Supports Micro/1 Master and slave buses

Power Regulators

Input 24vdc nominal@ 120 ma typical excluding current

loops and relay coil power 18v to 30vdc (current
varies with Range input voltage, power
consumption stays unchanged)

On board voltage +5v adjustable +/-5% 0-.5A

-15v adjustable +/-5% 0-.5A
+15 fixed +l-5% 0-.5A
Protection 24v input - gas tube + tranzorb
+5v zener diode OVP

Status

Inputs 16 form A inputs expandable to 64 off board

Max Input Rate 10 Pulses/Sec

Isolation Opto isolated to 1500v m1n1mum

Indicators LED lamp on each input loop

Protection Carbon slug resistor and ceramic capacitor

combines with opto isolator to handle large
transients (passes IEEE surge with stand
test)

39
 Trans zorbs (optio nal)
Gas Tubes (optio nal)

Conta ct Loop Volta ges Jumpe rable to intern al 24v or exter nal volta ge
exter nal 24vdc or 48vdc
129 vdc (optio nal)

Conta ct Curre nt 24vdc 5 ma nomin al

48vdc 10 ma nomin al
129vd c 10 ma nomin al

Softw are defin able (norm ally 20 ms)

Filte ring

Analo gs

Input s 8 diffe renti al offbo ard expan sion to 64 point s

Common mode range s +/-24 v

Common mode rejec tion 60dB

Input imped ance SOOK ohm exclu ding loop resis tor

Resol ution 12 bits for+ /- 5v

11 bits for 1 to 5v

Accur acy 10 bits long term

Input range s +/-Sv , 1 to 5v, +/- 1 ma, 0 to lma, 4 to 20 ma,

10 to 50 ma

A/D conve rsion time 35 usec typic al

Multi plexo r settli ng time lms

Refer ence voltag es + 90% f. s.

- 90% f.s. (not used for 1 to 5v input )
groun d

Monit or volta ges + 24v input

avail able to cpu +15v suppl y volta ge
-5v suppl y voltag e
-15v suppl y voltag e

Prote ction Very high input imped ance( > 1/2 megoh m)
trigua rds (optio nal)

Relay s

Outpu ts 8 form C conta cts (expa ndabl e to 48 total coils )

40
Momentary Control
Duration Software programmable

Contact Rating 0-220VAC lOA

0-30 VDC lOA

Continuous Controls Offboard expansion only

Protection Direct monitoring of relay coils

allows for security single component
failure I/0 mapped to prevent accidental
selects and executes

Modem Interconnect

Protection Gas tube and transzorb

Mode Half or full duplex

Isolation 600 ohm transformer to 1500v

41
5.4 Relay Expansion Board (Cl004)

General

Board 6.5 x 8" double sided PCB

.093" thickness
2 oz. copper plate

Mounting 4 stand offs

Field Connectors Pluggable compression fitting terminal blocks

12 to 28 ga standard wire

Environment -20°C to +70°C 0-95% humidity non-condensing

Special Features Heavily ground planed for noise immunity

Low power guard ring surrounding entire board for
surge protection and grounding.

Features

Outputs 8 x 2 form C contacts

Momentary Control
Duration Software programmable

Contact Rating 0-240 VAC lOA

0-30 VDC lOA

Protection Direct monitoring of relay coils

allows for security single component
failure I/0 mapped to prevent accidental
selects and executes

42
5.5 Status Expansion Board (Cl005)

General

Board 5 11 x 8 11 double sided PCB

.093" thickness
2 oz. copper plate

Mounting 6 stand offs

Field Connectors Pluggable compression fitting terminal blocks

12 to 28 ga standard wire

Environment -20°C to +70°C 0-95% humidity non-condensing

Special Features Heavily ground planed for noise immunity

HCMOS logic for noise immunity
Low power guard ring surrounding entire board for
surge
protection and grounding.

Features

Inputs 16 form A inputs

Max Input Rate 10 Pulses/Sec

Isolation Opto isolated to 1500v m1n1mum

Indicators LED lamp on each input loop

Protection Carbon slug resistor and ceramic capacitor

combines with opto isolator to handle large
transients (passes IEEE surge withstand test)

Transzorbs (optional)
Gas Tubes (optional)

Contact Loop Voltages External 24vdc or 48vdc

129 vdc (optional)

Contact Current 24vdc 5 ma nominal

48vdc 10 ma nominal
129 vdc 10 ma nominal

Filtering Software definable (normally 20 ms)

43
5.6 Analog Expansion Board (Cl006)

General

Board 5 x 8" double sided PCB

.093" thickness
2 oz. copper plate

Mounting 4 stand offs

Field Connectors Pluggable compression fitting terminal blocks

12 to 28 ga standard wire

Environment -20,c to +70,c 0-95% humidity non-condensing

Special Features Heavily ground planed for noise immunity

HCMOS logic for noise immunity
Low power guard ring surrounding entire board for
surge protection and grounding.

Features

Inputs 8 differential inputs

Common mode ranges ± 24 VDC

Common mode rejection 60dB

Input impedance SOOK ohm excluding loop resistor

Resolution 12 bits for+/- 5v

11 bits for 1 to 5v

Accuracy 10 bits long term

Input ranges +/-5v, 1 to Sv, +/-lma, 0 to lma, 4 to 20 ma,

10 to 50 ma

A/D conversion time 35 usec typical

Multiplexor settling time lms

Protection Very high input imedance (> 1/2 megohm)

triguards (optional)

44
6.0 CALIBRATION

6.1 Test and Calibrate Mode

The Test and Calibrate mode, TAC, allows the user to perform initial
installation, scheduled and repair maintenance on the unit with a minimum of
equipment and difficulty. The Micro/1 has one switch dedicated to selecting
this function or the normal RTU operation function. The TAC function changes
the switch definition to allow the calibration of modem transmit level, adjust
or monitor analog inputs using the programmable lamp on the communications
card, and to verify power supply levels and voltage reference levels.

The TAC mode is entered by setting the TAC switch to off. , The program RTU
address switches and other configuration switches are redefined to their TAC
meanings. Each message in TAC consists of a high and a low byte. The lamps
display the appropriate bytes according to the position of hi/lo byte switch,
as defined in the TAC mode. Refer to the following figures for the switch
definitions. Refer to the function list for the TAC function code operation.

6.1.1 Test and Calibration Functions

The following functions support tests and calibrations. To select these

functions and points refer to switch select section.

Functions Point Description

0 NA Display RTU program number and revision.

Select high byte for program number (hexadecimal)
Select low byte for revision (ASCII)

2 N Set analog input to reference input N, (N=l, ••• ,8),

convert and display results.

3 N Set analog input to input N, (N=l, ••• ,64)

convert and display results

4 N Display status by test N, (N=O for base board;

N= 1, 2, or 3 for extension boards 1, 2, or 3)
Select high byte to display status point 9 through 16
Select low byte to display status point l through 8

5 NA Not Defined

6 NA Display bytes 3 and 4 of last received message

Select High byte for byte 4
Select Low byte for byte 3

7 N Display last transmitted message starting from byte

4. Select point 1 to display byte 4 for high and
byte 5 for low byte. Then keep incrementing the
point select for next two bytes until the whole
message is displayed.

45
6.1.2 Test and Calibrate Switch Settings on Communications Board (C1002)

SWITCH 1

Point number for processing and display

in the test and calibrate mode. Switch
pos1t1on 2 is the MSB, 8 the LSB, ON is
a 1, OFF is a O.

This switch has no meaning 1n the test

and calibrate mode.

SWITCH 2

I 1 2 I 3 I 4 I s I 6 I 7 I 8 I 9
\ I I_ LED power switch. ON supplies power to
the onboard LED's.

Test and calibrate function number.

Switch position 3 is the MSB, 8 the LSB,
ON is a 1, OFF is a O. (For detailed
explanation of the function selected see
Test and Calibrate section)

ON selects low byte result of T.A.C

function for display on LED's, OFF
selects high byte.

RTU mode selection switch. ON selects

the normal mode, OFF selects the test
and calibrate mode.

46
6.1.3 Programming Information For Monitoring, Input Power, On Board Power
Supply and Analog Reference Voltages

A/D values are read in the Led' s display in function 2 of the Test and
Calibrate mode. Use point number switch Sl to display the various voltage
inputs.

Reference Voltages
Point Input A/D Value(+/- Sv) A/D Value (1 to Sv)
0 gnd 800h SFFh
1 ref+ adjustable adjustable
2 ref- adjustable not used
3 +24v C8Eh (20mv/ct) BB2h (16mv/ct)
4 +lSv D73h (lOmv/ ct) CD0h (8.6 mv/ct)
s +Sv 9D3h (lOmv/ ct) 845h (8.6mv/ct)
6 -lSv 28Bh (lOmv/ ct) 0 (under range)
7 -Sv 62Eh (lOmv/ ct) 36Ah (8.6 mv/ct)
HOW TO READ LED DISPLAY

LED DISPLAY
MSB X X LSB
Low byte 0 0 0 olo 0 0 0 X = Hex value digit
enabled DSl DS8

MSB Not Used' X LSB

High byte 0 0 0 0 0 0 0 0
enabled DSl DS8

Example of display:

for FOO Hex (1111 1101 0000) display below,

~ o 1 lo = ON LED
0 1
Low byte 1 0 0 0 2 = OFF LED
enabled DSl DS8

not used' F
High byte 0 0 0 0 1 1 l l
enabled DSl DS8

47
 6.2 Communicati on Card Modem (C1002) Calibration

Equipment required:

Wavetek Model 171 function generator, or equivalent

Fluke Model 8810A 5 1/2 DIGIT DMM, or equivalent
600 ohm 0.1% Resistor
Micro/I unit

Introductio n:

There are adjustments to be made on the modem circuitry. One adjustment is

associated with the output while the other two are ass~ciated with the
input. The output adjustment is the transmit level and is normally set to
-lOdB. This adjustment is application dependent and may be set from OdB down
to -20dB. The receive adjustment consists of a bias adjustment which is not
application dependent, and a carrier detect threshold adjustment which may be
application dependent.

Procedure:

Output Level

(Refer to Test and Calibrate mode switch settings for modem output level
adjustments ) (r~ <lb) SCT
1 1

1. Set the Micro I to Test and Calibrate mode. Set all switches
on ~I to "off" position except ,~ech~9 for Led power.
11
II
2. Enable function 1 of the Test and Calibrate mode.

3. Install a 600 ohm resistor across the TX tone signals on the

baseboard. Disconnect any field wiring from this terminal block to
prevent interference to the system.

4. Connect the DVM to the TX tone signal (across the 600 ohm resistor)
on the baseboard. Set DVM to 1-2 volt AC rms scale. A scale reading
in DB is desirable.

5. Adjust R13 (TX level) pot on the communicati ons board for reading of
.2449 vrms or -lOdB.

6. Return all switches to normal positions.

Carrier Detect

1. Input 1700Hz to the Rx tone input on the base I/0 board. Adjust tone
generator to measure -40dB at UlS-14. In systems strapped for two-
wire on the base I/0 board remove U7 on CPU board. If different
carrier detect threshold is required, inject the required level.

2. Adjust the CDLVL pot, RB, until pin 3 of Ull goes to a logic high.

48
 3. Back off of the adjustment until pin 3 returns low. Slowly change
the level until pin 3 returns high.

Receive Bias

1. Adjust the RBias pot, R7, so that there is 2.8vdc at pin 7 of Ull pin
8 of Ull should read logic 1 (Sv).

2. Decrease the voltage at pin 7 by .02v decrements until pin 8 goes low
(Ov).

3. Carefully increase the voltage at pin 7 until pin 8 returns high

again.

49
 6.3 Base I/0 Board (Cl003) Calibration

6.3.1 Power Supply Adjustment

Equipment:

DVM

Introductio n:

The power supply generates two adjustable outputs. The first is +SV. The
second is -15V. Note that voltage magnitude increases with the adjustment pot
being turned counter clockwise.

Procedure:

+SV Adjustment

1. Set up the DVM to a DC voltage scale capable of accurately reading +5.00

volts.

2. Attach the DVM leads to test points TP6 (negative lead) and TP3 (cathode
end of CR47 positive lead).

3. Turn R93 to full clockwise (minimum voltage adjustment) (note: step 3 may
be skipped for minor adjustments ).

4. Power up the board with 24VDC.

5. Adjust R93 counter clockwise until the DVM reads +5.0 volts.

-lSV Adjustment

1. Set up the DVM to a DC voltage scale capable of accurately reading +15.0V.

2. Attach the DVM leads to test points TP6 (negative lead) and TPS (positive
lead).

3. Measure and note voltage reading for use 1n -!Sv adjustment. It should be
in the range (14.25v - 15.75v).

4. Attach the DVM leads to test points TP6 (positive lead) and TP4 (negative
lead).

5. Turn R85 to full clockwise (minimum voltage adjustment) (note: step 3 may
be skipped for minor adjustments ).

6. Power up the board with 24VDC.

7. Adjust R85 counter clockwise until the DVM reads the previously noted
voltage for +lSV.

50
 6.3.2 Analog Calibration

Introduction

The Micro I analog calibration procedure requires knowledge of the test and
calibrate software operation. Refer to the switch definitions for details on
using the test and calibration mode. Note that bipolar adjustments are done
differently from offset single polar.

A/D CONVERTER CHIP CALIBRATION

1. Set the Micro I to test and calibrate mode.

2. Set point number switch= 1, set the test and calibration function to 3.

3. Connect a precision voltage source to first analog ( +) and (-) input.

TB1-Al on baseboard.

4. Connect DVM across TP-1(-) and TP-2(+) on baseboard.

5. Adjust input voltage until DVM reads Ov.

6. Check LED's display for (1000 0000 0000) 800 Hex. If the display does not
read 800 Hex adjust R60 on the baseboard for correct reading.

NOTE: Use high and low byte switch on S2 of the communication board to
read full display.

7. Adjust input voltage until DVM reads 5.000 volts.

8. Check LED display for a reading of FFE - FFF Hex. Adjust R59 for correct
reading. The LED's should toggle between the two readings.

(1111 1111 lllO)FFE Hex (1111 1111 llll)FFF Hex

9. Repeat steps 4-8 until no further adjustments are necessary.

ANALOG INPUT CALIBRATION: (4-20ma, 10-SOma, or 1 to Sv input with Wl8 Jumper

installed)

1. Set Micro I to test and calibrate mode.

2. Set point number switch= 1, set test and calibration function to 3.

3. Inject a l.OOOv (or 4ma) signal into the first analog(+) and(-) input on
baseboard (TB1-Al).

4. Adjust R57 for an LED display of 800 Hex (1000 0000 0000). (Use high and
low byte switch to read the full display.)

5. Inject a full scale voltage or current (Sv or 20ma) into the first analog
input.

6. Adjust R58 for an LED display of FOO Hex (1111 1101 0000). (Use high and
low byte switch to read the full display.)

7. Repeat steps 3 - 6 until no further adjustments are necessary.

51
8. Increase point number switch by 1 to read the second analog input, etc.
Only one adjustment procedure is required for all analog inputs.

ANALOG INPUT CALIBRATION: (.:!:_lma, 0-lma, 0-5v, .:!:_5v with Wl8 jumper out, R57
not used)

1. Set Micro I to test and calibrate mode, set test and calibration function
to 3.

2. Set point number switch= 1.

3. Short the first analog(+) and(-) inputs on TBl-Al of the baseboard.

4. Check LED display for a reading of (1000 0000 0000) 800 Hex.

5. Inject a full scale voltage or current (5. OOOv or lma) into the first
analog(+) and(-) input on TBl-Al.

6. Adjust R58 for LED display of (1111 1101 0000) FDO Hex. (Use high and low
byte switch to read full display.)

7. Reverse the input leads to inject and full negative scale (-5. OOOv or
-lma) into the first analog(+) and(-) input.

8. Check LED display for a reading of (0000 0011 0000) 030 Hex.

9. Increase the point number switch to read the next analog input until all
analog inputs have been read.

ANALOG REFERENCE CALIBRATION:

1. Set Micro I to test and calibrate mode.

2. Set function to 2, set point number to 1.

3. Attach the DVM to test points TP-1 (-) and TP-7 (+) on baseboard.

4. Adjust R65 until DVM reads 1.9800 volts.

5. Check LED display for a reading of (1111 1101 0000) FDO Hex.

6. Set point number switch to 2.

7. Attach the DVM to test points TPl and TP8 on baseboard.

8. Adjust R66 until DVM reads -1.9910 volts.

9. Check LED display for a reading of (0000 0011 0000) 030 Hex. (Does not
apply for 1 to 5v or 4-20ma analogs.)

52
 APPENDIX A

SERIES V COMMUNICATIONS PROTOCOL

53
A.1 Introduction

The Series V communications protocol allows partyline operation of many RTU's

using a master-remote polling scheme. The protocol accommodates "select
before operate" control over field devices and allows retrieval of field
status, sequence of events, analog, and accumulator data. It includes
provisions for scanning analog and status data on a direct scan or by
exception basis.

All messages have the following structure:

MASTER TO REMOTE

Each master-to-remo te message consists of 5-bytes:

Station ID 1 Byte
OPCODE 1 Byte
Data 2 Bytes
LRC 1 Byte

REMOTE TO MASTER

The RTU being addressed (and only that RTU) responds to the master by sending
a multi-byte message consisting of:

Station ID 1 Byte
RTU Status 1 Byte
COS Counter 1 Byte
Data (Varies with command)
LRC 1 Byte

A.2 Character Structure

All data transfers between the master and the RTU's are organized into multi-
byte blocks, where each byte contains one START BIT, 8 bi ts of data, one
PARITY bit (ODD) and one STOP bit. The START bit is transmitted first.

MSB LSB
STOP p

where:

D7: Most significant data bit

DO: Least significant data bit
P: ODD PARITY bit

The data 1s generated by the master or RTU software; the START, STOP, and
PARITY bits are added to the data byte by the communications hardware,
implemented with a UART (Universal Asynchronous Receiver-Trans mitter)
interface.

54
A.S Message Organization, Remote To Master

All RTU responses are multi-byte blocks structured as follows:

REMOTE TO MASTER MESSAGE STRUCTURE

Byte No. 7 6 s 4 3 2 1 0 Function

1 0 R6 RS R4 R3 R2 Rl Rl Station ID
2 D7 D6 DS D4 D3 D2 Dl DO RTU Status
3 D7 D6 DS D4 D3 D2 Dl DO COS Counter
4 to (N-1) D7 D6 DS D4 D3 D2 Dl DO Data
N E7 E6 ES E4 E3 E2 El EO LRC

Byte No. 1 contains the following information:

BIT NO FUNCTION
7 DIRECTION bit: Always set to "O"

RO to R6 Station ID

Byte No. 2 contains the RTU STATUS. This indicates to the master various
conditions detected at the RTU, as follows.

BIT NO. FUNCTION

D7,D6 Future
DS=l Control selection failure
D4=1 RTU malfunction detected
D3=1 Accumulators were FROZEN and/or RESET
02=1 RTU configuration questionable
(switches on CPU board set incorrectly)
Dl=l Request from MTU is questionable
(MTU-RTU message passes security code check but OPCODE
is invalid or data requested does not exist)
DO=l Power failure has occurred.

The RTU STATUS byte is sent with each response. The MTU resets the individual
tits using OPCODE 11 which also requests more detailed information related to
the error bit appearing in the RTU STATUS byte. (cf. OPCODE 11)

57
In the event of the occurrence of a CONTROL SELECTION FAILURE, a QUESTIONABLE
CONFIGURATION, or a QUESTIONABLE REQUEST (bits DS, D2, Dl), the RTU response
to the message which "caused" the problem will consist of the following 4
bytes only:

* Remote Reply*

0 R6 RS R4 R3 R2 Rl RO Station ID
DS D2 Dl RTU Status
COS QUEUE
E7 E6 ES E4 E3 E2 El EO LRC

-:drNote that DS (CONTROL SELECTION FAILURE) and Dl (QUESTIONABLE REQUEST) are

set in response to certain MTU to RTU messages (as compared, for example, to
D4 or DO which may occur independently of MTU-RTU communications). D2
(QUESTIONABLE CONFIGURATION) will be set if the RTU has been configured
incorrectly and this case, the message shown above will be sent in response to
any MTU to RTU message.

Byte No. 3 contains the following information:

BIT NO. FUNCTION

D6 - DO CHANGE OF STATE (COS) Counter: The value of DO to D6
indicates the number of sequential status changes pre-
sently in the COS QUEUE. All "1' s" (including bit D7)
in an overflow state. (more than 63 changes have
occurred).

Byte No. 4 to (N-1): contains the data requested by the master. this 1s a
variable length field.

Byte N: contains the LRC security code.

58
A.6 Opcode Summary

The following OPCODES are supported by the Series V protocol.

OPCODE FUNCTION

0 - not used
1 Scan - Analogs
2 - Accumulators
3 - Status
4 Control - Select
5 - Operate
6* - Direct Control (Select & Operate)
7 Accumulator - Freeze
8 - Reset
9 - Freeze and Reset
10 - COS Queue Dump
11 - Remote Status Clear
12 - Remote Configuration Request
13 Analog by Exception - Dead Band Load
14 - Change of State Queue Dump
15 - Analog Change Queue Dump

*Requires special version of PROM for implementation.

59
 ANALOG SCAN, OP CODE . 1

An ANALOG SC~J~~mmand returns the analog values for the requested number of
points frol}lJt:he RTU.
/'
/
* Mast~r Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 0 0 0 0 1 OPCODE
N7 N6 NS N4 N3 N2 Nl NO Starting Point Number**
N7 N6 NS N4 N3 N2 Nl NO Number Points to Return
E7 E6 ES E4 E3 E2 El EO LRC
,•: Remote Reply•':

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS QUEUE
0 0 0 0 Dll DlO D9 D8 1st Point
D7 D6 DS D4 D3 D2 Dl DO

0 0 0 0 Dll DlO D9 D8 Nth Point

D7 D6 DS D4 D3 D2 Dl DO
E7 E6 ES E4 E3 E2 El EO LRC
Analogs are coded in 2's complement with resolution of 11 bits (DO-D10) plus
sign (Dll). The sign bit is O if the value is zero or positive; it, and the
four unused high order bits are set to 1, if negative.

EXAMPLE:

COUNT BINARY VALUE (MSB) BINARY VALUE (LSB)

+2000 0000 0111 1101 0000
0 0000 0000 0000 0000
-1 1111 1111 1111 1111
-2 1111 1111 1111 1110
-2000 1111 1000 0011 0000
NOTE: Full Scale: 2 12 -1 = 2045

**First point number 1n RTU 1s zero (not one) for AlO.

60
ACCUMULATOR SCAN, OPCODE 2

An ACCUMULATOR SCAN command returns the contents of the accumulator FREEZE

registers for the requested number of points from the RTU. Refer to OPCODES
7, 8, and 9.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 0 0 0 1 0 OPCODE
N7 NO Starting Point Number**
N7 NO NO. of Points to Return
E7 EO LRC

,., Remote Reply>'<

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS QUEUE
0 0 0 0 Dll DlO D9 DB 1st Point
D7 D6 D5 D4 D3 D2 Dl DO

0 0 0 0 Dll D10 D9 D8 Nth Point

D7 D6 D5 D4 D3 D2 Dl DO
E7 EO LRC

Accumulators range from Oto 4095 and are coded as 12 bits binary.

>'<>'<First point number 1n RTU 1s zero (not one) for accumulators.

61
STATUS SCAN, OPCODE 3

A STATUS SCAN command returns the present status values for the requested
number of points from the RTU. The number of points returned and the number
of the starting point are integer multiples of 8.

* Master Request*

1 R6 RS R4 .. R3 R2 Rl RO Station ID
Rst RA 0 0 0 0 1 1 OPCODE
N7 NO Starting Point Number
N7 NO Number Points to Return
E7 EO LRC

,., Remote Reply>':

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS QUEUE
S7 s s s s s s so 1st 8 Points

SN(7) s s s s s s SN(O) Nth 8 Points

E7 EO LRC

Each bit corresponds to one status point 1n the RTU data base. S = 1 is
closed, S = 0 is open, unless the status inputs are inverted on the input
boards.

62
 CONTROL POINT SELECT, OPCODE= 4

The CONTROL POINT SELECT command selects the requested control point
at the RTU for a subsequent control operation (OPEN or CLOSE).

The SELECT TIMER is equal to its binary value times 0.2 seconds (up to 30
seconds). If a valid CONTROL POINT OPERATE command is not received before
the SELECT TIMER times out, the RTU resets the control point.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 0 0 1 0 0 OPCODE
T7 T6 TS T4 T3 T2 Tl TO Select Timer
P7 P6 PS P4 P3 P2 Pl s Point no. & desired state
E7 EO LRC

Note: S = O: for CLOSE; S = 1: for OPEN

PO - P6: Control Point Number (0 to 127)

* Remote Reply*

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS QUEUE
T7 T8 Select Timer
P7 PO s Point no. & desired state
E7 EO LRC

CONTROL POINT OPERATE, OPCODE= 5

The CONTROL POINT OPERATE command instructs the selected control point
to operate for a time duration equal to the OPERATE TIMER. The OPERATE
TIMER is equal to its binary value times SO milliseconds (up to 7.5 seconds).
The maximum binary value is 10010110 or 150 decimal.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO
Rst RA 0 0 0 1 0 1 OPCODE
T7 T6 TS T4 T3 T2 Tl TO Operate Timer
P7 P6 PS P4 P3 P2 Pl s Point no. & desired state
E7 EO LRC
,·, Remote Reply>',·

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS QUEUE
T7 TO Operate Timer
P7 Pl s Point no. & desired state
LRC

63
DIRECT CONTROL (SELECT AND OPERATE), OPCODE= 6

This Command is functionally identical to an OPCODE 4 and 5 in succession.

This OPCODE requires a special version of PROM for implementation.

64
ACCUMULATOR COMMANDS; OPCODE= 7 ACCUMULATOR FREEZE
OPCODE= 8 ACCUMULATOR RESET
OPCODE= 9 ACCUMULATOR FREEZE & RESET

The ACCUMULATOR FREEZE command transfers the data from the individual
accumulator registers to a FREEZE buffer for subsequent transfer back to the
MTU. The individual counting registers are not reset.

The ACCUMULATOR RESET command resets both the requested accumulator registers
and "freeze" buffers to zero.

The ACCUMULATOR FREEZE AND RESET command first transfers the individual
accumulator registers to the FREEZE buffer for subsequent transfer back to the
MTU, and then resets the individual accumulator counting registers to zero.

GLOBAL address O (all stations) is applicable for all accumulator commands.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst 0 0 0 D3 D2 Dl DO OPCODE: 7-0111,8-1000, 9-1001
N7 NO Starting Point Number
N7 NO Number of Points
E7 EO LRC

Note: If number of points= O, the command 1s applied to all points 1n the

RTU.

* Remote Reply*

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS QUEUE
D7 D6 DS D4 D3 D2 Dl DO Starting Pt .ii
D7 D6 DS D4 D3 D2 Dl DO ii of Points
E7 EO LRC

Note: No reply is returned for a GLOBAL O Station ID.

Note on Accumulator Commands: OPCODES 7, 8 and 9 do not cause desired action

unless OPCODE 11 had previously been sent resetting bit D3 of the RTU status
byte (refer to byte No. 2 in section A.S).

65
COS QUEUE DUMP, OPCODE= 10

A COS QUEUE DUMP returns the changes reported in the COS QUEUE byte where the
number of changes to report are requested by the master station.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst 0 0 0 1 0 1 0 OPCODE
0 0 NS N4 N3 N2 Nl NO # of changes to report
0 0 0 0 0 0 0 0 Not used
E7 EO LRC

Remote Reply~·(

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS QUEUE
P7 PO Pt.#, 1st Change
0 0 0 0 0 0 0 s State

P7 PO Pt .ff, Nth Change

0 0 0 0 0 0 0 s State
E7 EO LRC

Note: P7 - PO Point Number (0-255)

S = State (1 = CLOSED; 0 = OPEN), unless inverted on the STATUS board)

66
REMOTE STATUS CLEAR, OPCODE = 11

The REMOTE STATUS CLEAR command instructs the RTU to clear previously set
STATUS bit(s). This command is normally sent automatically if an RTU error
condition is detected at the MTU. The RTU responds to the command with a
diagnostic message describing the RTU STATUS.

This OPCODE also clears the COS QUEUE count, if it has overflowed.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 0 1 0 1 1 OPCODE
D7 D6 DS D4 D3 D2 Dl DO 1 to clear corres. bit
Spare
E7 EO LRC

* Remote Reply*

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS Queue
Not used
D7 D6 DS D4 D3 D2 Dl DO QUESTIONABLE REQUEST
D7 D6 DS D4 D3 D2 Dl DO QUESTIONABLE CONFIGURATION
D7 D6 DS D4 D3 D2 Dl DO RTU MALFUNCTION
D7 D6 DS D4 D3 D2 Dl DO CONTROL FAILURE
E7 EO LRC

THE QUESTIONABLE REQUEST byte contains the following information:

Bit No.= 1 Function
DO Data type does not exist.
Dl Invalid starting point number.
D2 Invalid number of points.
D3 Invalid OPCODE.
D4 Reply too large.
DS Invalid COS queue change request.
D6 Spare.
D7 Spare.

THE QUESTIONABLE CONFIGURATION byte contains the following information.

Bit No.= 1 Function
DO Questionable number of analog cards selected.
Dl Questionable number of accumulator cards selected.
D2 Questionable number of status cards selected.
D3 Questionable number of D/A cards selected.
D4 Spare.
DS Questionable total number of cards.
D6 Spare.
D7 Spare.

67
THE RTU MALFUNCTION byte contains the following information :
Bit No.= 1 Function
DO Level 3 interrupt occurred.
Dl Level 7 interrupt occurred.
D2 Control error count high.
D3 A/D converter interrupt failure.
D4 Status card interrupt failure.
DS Accumulator card interrupt failure.
D6 Status card COS failure.
D7 D/A card failure.

THE CONTROL FAILURE byte contains the following information :

Bit No.= 1 Function
DO Arm timer too high.
Dl Execution timer too high.
D2 Control already in progress.
D3 Operate point not pre-selecte d.
D4 Invalid control check-back.
DS D/A set-point not pre-selecte d.
D6 Invalid set-point check back.
D7 D/A set-point not operated.

68
REMOTE CONFIGURATION REQUEST, OPCODE 12

A REMOTE CONFIGURATION command returns the number of analogs, stat us and

accumulators on the RTU.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 0 1 1 0 0 OPCODE
Not used
Not Used
E7 EO LRC

·k Remote Reply'>':

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU Status
COS Queue
D7 DO # of Analogs Points
D7 DO # of Status Points
D7 DO # of Accumulators
D7 DO LRC

69
 ANALOG BY EXCEPTION, OPCODE 13-15

Opcodes 13-15 are used to load the analog DEADBAND, display the number of
analog and status changes since the last scan, and dump the ANALOG CHANGE
QUEUE including analog point number and current value.

Note that in OPCODES 13 and 15, the first analog point is considered to be
point number 1, whereas in other analog related OPCODES point O is the first
point.

LOAD DEADBAND, OPCODE 13

The LOAD DEADBAND command instructs the RTU to load the analog DEADBAND for a
given point. A point number= 0 loads the same DEADBAND for all the points in
the RTU.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 0 1 1 0 1 OPCODE
D7 D6 DS D4 D3 D2 Dl DO Point Number (0 for all points)**
D7 D6 DS D4 D3 D2 Dl DO DEADBAND
E7 ED LRC
,•: Remote Reply>'<'

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU status
COS queue
D7 DO Point number
D7 DO DEADBAND
E7 ED LRC

**Note: The starting point for point number 1s 1, for OPCODES 13-15.

70
COS QUEUE and ANALOG CHANGE QUEUE SCAN, OPCODE 14

This opcode requests the COS queue and the ANALOG CHANGE queue

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 0 1 1 1 0 OPCODE
Not used
Not used
E7 EO LRC

-/( Remote Reply-I(

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU status
COS queue
ANALOG CHANGE QUEUE
E7 EO LRC

ANALOG CHANGE QUEUE DUMP, OPCODE 15

An ANALOG CHANGE QUEUE DUMP requests the current values of the analog point in
the analog change queue. Setting the RA bit in the next message from the
master station resets the ANALOG CHANGE queue.

* Master Request*

1 R6 RS R4 R3 R2 Rl RO Stat ion ID
Rst RA 0 0 1 1 1 1 OPCODE
Not used
0 N6 NS N4 N3 N2 Nl NO # of changes to report
E7 EO LRC

* Remote Reply*

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU status
COS queue
P7 P6 PS P4 P3 P2 Pl PO Point#, first change
0 0 0 0 Dll Dlo' D9 DB High byte
D7 D6 DS D4 D3 D2i Dl DO 1 Low byte
]
P7 P6 PS P4 P3 P2 Pl PO Point#, Nth point
0 0 0 0 Dll DlO D9 DB High byte
D7 D6 DS D4 D3 D2 Dl DO Low byte
E7 EO LRC character

71
STATUS TIME TAGGING, OPCODES 29-30

These OPCODES are used to perform TIME SYNCH and COS QUEUE DUMP in RTU's which
are equipped with the optional ±6.25 msec STATUS TIME TAGGING.

TIME SYNCH, OPCODE= 24

* Master Request

1 R6 RS R4 R3 R2 Rl RO Station ID
Rst RA 0 1 1 1 0 1 OPCODE
Cl5 Cl4 Cl3 Cl2 Cll ClO C9 CB COUNTER HIGH
C7 C6 cs C4 C3 C2 Cl co COUNTER LOW
E7 EO LRC
The RTU maintains an internal 16-bi t counter where each count = 6. 25 msec.
This counter is used to time tag status changes as they are detected. The
COUNTER HIGH byte and COUNTER LOW byte make up the 16-bit value to which the
RTU' s counter is to be set as a result of the TIME SYNCH command. This
command is ordinarily sent to RTU address O.

* Remote Reply*

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU STATUS
COS QUEUE
Cl5 Cl4 Cl3 Cl2 Cll ClO C9 C8 COUNTER HIGH
C7 C6 cs C4 C3 C2 Cl co COUNTER LOW
E7 EO LRC

72
TIME TAGGED COS QUEUE DUMP, OPCODE= 30

An OPCODE 30 COS QUEUE request returns the status changes along with their
associated timer values.

* Master Request

1 R6 RO Station ID
Rst RA 0 1 1 1 1 0 OPCODE
0 0 NS N4 N3 N2 Nl NO # of Changes to report
0 0 0 0 0 0 0 0 Not used
E7 EO LRC

1': Remote Reply -::

0 R6 RS R4 R3 R2 Rl RO Station ID
RTU STATUS
COS QUEUE
ClS C14 Cl3 C12 C11 ClO C9 CB COUNTER HIGH
C7 C6 cs C4 C3 C2 Cl co COUNTER LOW
P7 PO PT .:/I
0 0 0 0 0 0 0 s State
[ l
ClS C14 C13 C12 C11 ClO C9 CB COUNTER HIGH
C7 C6 cs C4 C3 C2 Cl co COUNTER LOW
P7 PO PT.#
0 0 0 0 0 0 0 s State
E7 EO LRC

P7-PO is the point number (0-2SS) and S is the state (1 = closed, 0 = open).
The RTU will not begin to update the TIMER values, after it first initializes,
until it has received a TIME SYNCH command from the master station.

73
A. 7 Response Byte Count Summary

OPCODE EXPECTED BYTE COUNT*

1 ANA. SCAN 4 + 2 x no. analog points requested

2 ACC. SCAN 4 + 2 x no. acc. points requested

3 ST. SCAN 4 + no. status points requested /8

4 SELECT 6

s OPERATE 6

6 EXECUTE>'<>'.- 6

7 FREEZE 6

8 RESET 6

9 FREEZE & RESET 6

10 cos QUEUE DUMP 4 + 2 x no. of changes requested

11 RTU STATUS CLEAR 9

12 CONFIG. REQUEST 7

13 DEAD BAND LOAD 6

14 ANALOG CHANGE QUEUE s

SCAN

15 ANALOG CHANGE QUEUE

DUMP 4 + 3 x no. of changes requested

29 TIME TAGGED STATUS 6

TIME SYNCH

30 TIME TAGGED STATUS

COST QUEUE DUMP 4 + 4 x no. of changes requested

>':Ifthe second byte of RTU response contains bi ts DS, D2 or Dl = 1, the

response will be only 4 bytes long.

**Requires special version of PROM for implementation.

74
 APPENDIX B

SCHEMATIC AND ASSEMBLY DIAGRAMS

75
8.1 Table of Contents

PART NUMBER DESCRIPTION QTY SHEETS

c1001-002-o oooo Micro/I CPU Board 1
ClOOl-A00-0 0000 Micro/I CPU Board, PCA 1

c1002-002-o oooo Micro/I Comm Board 1

Cl002-000-XXXXO Micro/I Comm Board, PCA 1

Cl003-002-0 0000 Micro/I I/0 Board 4
Cl003-000-XXOXO Micro/I I/0 Board, PCA 1
Cl004-002-0 0000 Micro/I Relay Expansion Board 1

Cl004-000-00 XXX Micro/I Relay Expansion Board, PCA 1

c1oos-002-oo ooo Micro/I Status Expansion Board 1

C!OOS-000-0000X Micro/I Status Expansion Board, PCA 1

Cl006-002-0 0000 Micro/I Analog Expansion Board 1
Cl006-000-00 00X Micro/I Analog Expansion Board, PCA 1

76
 C8 + 5V A8- A 15 A8-A15

Pl
U\2 Ul5-9 - 30.72 KHZ D + 5V
R2
il
r<) + 5V
WR
r<) +5V !:'.l + ~1V -- !:'.l
WR
+ sv
+ 5V 74HC04
II
. - - - - - - - - - - - - - - - - ,-,,-;i HOLD
39
!OK
"'< 0
C\.16
"'<
L() U)i n
"'<
(J) 0~ I'-
~b "'<
t2 'Jl
~15 00 t 5V
3 3 3 3 3 3
393! 393
LO CLK 6.144mHZ 2 XI 39 31

--~~--1-·~:r _
C2 YI
JW30
~
13
HJ CLK
," C5
lUF t 5V
T 5V + 5V
213
-t 5V
28
27
213
B ~VBB
I
WR 27
I WR 27
I

RESET OUT
13 ~I 3/3 _ci ~_!3
7.c"CT'3 2 ,4,12 2
Al2 Al3 26
2
Al2 Al3
WR
2
A!2 Al3
26
W29
PWR OW'J
.___ _ _ _ _ _ _ _-C;.3:..:.0c..7.:c.2'""M'-'-HZ"-------"3'-17 CLK OUT -- 20
3 3 A 7 A5 25 3 A? 25 3 A7 A8 25

.I'
READY UI 3 30 11 A7 A8
4 I 24 KEY
GND
74HC04 ' - - - - - + - - - - - - - - - - - - - - - - - - - < l l ' ---t RESET OUT ALE•-~ - - - EN 4
6 '19 24 4
6 j9
24
6 \9
Ul7 . 29 3 D, 5 5 5 All 23 5 5 23 t 5V +5Y

,~
5 5 All 5 A 11
74HC74 + 5V UG 33 113
6 22
GND
t 5V
8 16 G
4
6
4
22
oc 6 4 6E 4 OE VBB VBB
·-
- 10 II 10 130Cil5 4
17
Is ?
3 AlO
7
i3 AIO
7
3 AIO
21 7
13 AIO
21
GND
Ul2 12 p 2 p '4 8 5 8 20 8 20
?I
Q
UIG
74HC4040
01
i'.\
74HC04
ii
D Q 9
8 3
D
36
rF---+-niRESET IN AD 7
19
IG 18
7
14
13

13 12
9
10
AO
I~ CE
D7
IG
i9
15
9 12
10 1'
AO
CE
07
19
15 10
9

AO
1~ CE
07
6
19
15
9
10
AO
GE
07
19
18

--
0 9 !O 11

7.5HZ
17
16
!5
13
! ! 3
•2 ll
11
I'
11
c'.
90
I:
17
i5
11 DO
12 I
11
17
16
1:IA 1I
I
I:
DO
12 1 I
5
4
16
17 II
12
DO
1
16

I
17
16
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4. MARK BOARD EDGE WITH ASSY P/N, REVISION LEVEL AND SERIAL NO. MICRO/ 1
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Bcro2 142 <XXfX) RES CC 5o/o IW 30K ,,.,.,,.. 1m /02 !04,Jrv; JO(JJJO /12 2 73 Bero/ 1392 CXXIX) POT CM IT 5K o.5W R55, R93 I 3 BCC()f -647 O'.XX)/3 ICD 74HC08 AND GATE U31
,, ,, N ,.. SEE NOTE 10 R 116.118.120 122 124 l?fi./28,130 I 74 BCDOI -9oa-cxxro POT CM ldT 50K 0.5W R56 I 4 aooor-047-00030 lCD 74HC30 NANO GATE UJ9
6 75 acro2- 175 CXXXX) RES CC 5°t.. 0.25W a.2 K R49, 52,140.143, /47, 1:s..c.o_ _-ll--'4-+--5'--+B~cro~_I---=.04_;_;_7_--=-0-=-0-'13C..C8'-f-'l-"C:=;D_c.74"'-'H-'-C=-l--=3-=-8_3=---,8'--"'LJ='-N-"E'-'D"'E"'CC..CO'-CDE'-C-'R'---+'U-=-5:...:,U"'l9::.,,..=U.:e34.:..z.:::Uc:,3c:_7_ _ _ _ _-'I
I, 6 8CXX)l-847-00174 ICD 74HCl74HE>< D FF WICLEAR U36
H-ANALOG 8 - 106
Jctr!J-656 <XXfX) RES WW 0.025°/, 0.12W 250A R2.6,I0.!6 29,.'!4..40.44
25
I
76 aax:o-671-CXXXX)
77 80001 -256-<XlXO
LED RED CYL /.7V T/.75
CAP-P £L 50V 470MF !OP RL
DSJ-DS25
C44 SEE NOTE 5 3 7 80001-1347-00175 ICD 74HCl75 QUAD D-LATCH U2t.U29,U30
Jctr!J -566- 00000 RES WW 0.025°!~ 0.J2W 5K
107 R2,6.IO /6.29.34 40,44 I 713 80001-696-COXO CAP-PEL 6.3V 3300MF 20P AL C45 SEE NOTE 5 2 6 BCXX!l-847-00240 ICD 74HC240 BUFFER UIO,U22
BC(X)2-l50-00JOJ JUMPER MIN/ 0./00 JR 2P
II I IW/d I 79 80001 -897-CXXXX) CAP-P EL 16V 2200MF ><><P AL C 36 SEE NOTE 5 5 9 8000/ -tM-7-00244 lCD 74HC244 BUFFER ORNER U/0, U/1, U20,U40,U43
/ 80 J0204-062-<XXXXJ CAP-N MI 500V /OOPF 5% RL C23 I 10 BCXX!I 047 00374 JCD 74HC374 D-LATCH U6
N-CONIROL.S U32
CO--I_M_F-'-5°"'"'Yo,_·c..:Rc:cL_-;.::C.:c2cc2_ _ _ _ _ _ _ _ _11-'l--+_l,..c./ ~ I -846-00240 ICD 74HCT240 BUFFER 3-STAT£
'--'l--1----...c.:IO:..=dc...-i=BCm="-'''---=8:.:::0c:..l_--=OOOOO==-,i-=SN:.:..:.c..lccTCccH.;.....::$c...PST=-=-"-M"'IN--l_ _ _ _ _ _-+-=-$-=-5----------+--'--l-+-'O'-'-l-+8=-0'.XX>=-=----9c..7-'3c..-...:cx:tXX>::.::.:=-;..:CAP:.:....;___-'-N-M-'--'-1-I--O-'-O-V_O_.__ --------
109 acro, -900-C:XXX:,5 CONN PCB PC 5 M SEE NOTE 7 (J 82 JO::t:t) -!566 -<XXXX) CAP-N CE IOOV 0,00/5MF 5% PJ.. C5.C6,CIO.C/I C25-C28 I 12 BOCOI - 648-00244 [CD 74HCT244 BUFFER 3-STATE U33
/10 IRrm? -150-00JOO JUMPER MINI .JOO 2P SEP NOTE 7 2 83 Bctr!J -638-()(XIX) CAP-N CE 50V 0,0022MF 20°1o RL C38 C46 2 13 aax:o OQ6-C<XXX) ICD 405/B CMOS I OF O MU>< U4,U9
-
24 84 87093-003-caxx> CAP-N C£ 500V 0.02MF )()(p RL CI-C4 Cl7-CJ9,C24C51-56C64-7J 4 14 EnX>l -673-00XlO JCD DS3634 DRIVER CMOS DUAL U27,U26,U41,U42
6 135 BCCOI - B70-axt:XJ CAP-N CE 50V IMF 20% RL C9 C/3 C39 C4l C42 C48 I 15 E!IXXJl -876 -CXXXXJ ICD AD574A AID CONV 12 BIT U44
35 86 800C0-79B-OOOCO CAP-N CE 50V Q.IJ,IF 20% RL Cl,8,12 /4-16,20,24,29-35,37, 2 16 80001-Bll-CXXXXJ JCD 7BS40 SW REG U/2,U/3
Bl ,, ,, ,, ,, C4l495059-63.72-8/40 I 17 JOOC0-531-C<XXXl lCD 7406 INVERTER H£>< 0 C U30
2 68 80::tX)- 839-00CX:O SNITCH DIP OPOS $1,$2 4 18 BCXX)l-874-CXXXXJ ICL LF442 OPER AMPL DUAL U2,U3,U7,U6
89 BOOOl-8tJO-a::tm SWITCH MOMENTARY N/0 S3 / /9 8CXX)I-075-CXXXXJ ICL LF44IA OP£R AMPL DUAL UI
90 scro2- 0?6-R/60A CABLE ASSY FLAT W/STR 16 C 11N Jf (LOCATION) I 20 BCXX)I -B05-00000 ]CL 79L05ACZ V-REG-5V IOOMA . VRI
91 B(Xt)J -879-CXX)/6 CONN PCB PC 2xB M JI I 21 B<XX>l -866-CXXXJO !CL 7815 V-R£G +l5V 1A VR2
3 92 8CIX)J -079-0J020 CONN PCB PC 2xl0 M J2,J3,J4 8 22 BIOOCJ-216-00000 ]CL MCT6 OPTO-ISOLATOR DUAL Ur4-Ul7 U23-U26
4 93 BOOOI - 900-00020 CONN PCB HOR STRIP M XAIJI ><AJJ2 ><A2JI.XA2J2 t 23 JCIXXJ -245-00CXX) TSTR. 2N4036 P 5W 90V 40H Q5
ll-'.8:c-t-94--1Fscm~~l----=B-::-82--VH006-=-~-cON~N-H-£~A--D-£~R-P-=-c-B~0-6-PO-=--c-$,:--,V---Tc"-B~l=-""TB~4~.T='s=,~,-~Tc",8'-/~4~~-----6-""2~4-BC(X)--J----"866"-'---_--'C<XXX)-"-'-'-'-I-TS"'T'-R.:._;2::.:N_;_3.:...90=5'-'-P--=0.-"2'-A=5.:...V...c40c=cV-----+=Q"'1-Q-2-Q-6---Q9-----· -
6 95 8CXX)J-8B2-VH(X)BCONN H£ADERPCBO(J POSV T85-TBIO 24 25 J/160-016-CIXXX) Dl0DE1N4004 RS400V IA CR23-CR46
tl 96 BCtX!I - 711-000<X) SOCKET RELAY dPIN RECT PC IOA Kl-KB 2 26 J0000-666-00:X:0 DIODE tN4933 HS 50V IA CA4 CR.5
I 97 BCtX!I - (137-000:X, SOCKET JC 28PIN DIP CLSD BOT U44 2 27 BOOC0-603-000CO DIODE Z 39V 5W 81,5KE39A CR.I CR6
98 7
Bax:o - 740 -OCIXXJ TERM/ NAL PIN TUARET~H;-.,O:.~L:-":"L'::O:'cWc---+::T:::P-:-l--:T:;:P:-;;6-------jt-=,-+-'::2:-::-a-t=s""'oococ.=.=.cc____.::;(3;:c/6=---C<XXX)-===-t=D:CC/.=;OD""£=-=Z'-=6=-:.2V'-'"'o'-'-.'-,5w-.:;.;a==1=Nc=:523:...:4.,.,B--1-"c'-'Rc:.J4C:,7::..!..:'--------~
8
STATUS YQLrAGE CONTROLS
3 99 BCtX!l -900-CXX:o'!S CONN PCB PC 5 M W2,W4,W5Wl6 SEE NOT£ 9 2 29 BCXXJI -BltJ-00000 D/0lJ£ Z 2.5V R£FRNC LM336BZ Q3,Q4
-XXOOO-RELAY POWE.R SNITCH ON BOAAD. 4 100 Bet::02-150-00U:,o JUMPER MINI 0.100 1R 2P W2,W4,W5 SEE NOTE 6 I 30 87019 -002-CXX:OO TRANSISTOR. PADS 7717-22N T0-5 Q5
-3XO.XO. -:-Z.4. V... ,- XJOX0-4--20 m.A LOCAL CONTROL. Is 1 IN Is 1wm I 8 101 BOOCO- 012 -CIX/X} NUT H£>< 6-32 SM PAT ss----+-=:'.::_~-----~--1t--,,6c-l--=37/-+B,c-cOX)~/,---2-=-4""'7=-_-axro7'C"'C~r'C7'P.ANS-'--'-,=E-N=T-'-s=-u~P='PR~Z=£~'N=ER-B=-.~2~v--1-=c'-R-7--C-R-2~'2-----·-
-4xaxo. =129.v. . ... -x4oxo - :1: 1mA -XXOIO - RE.LAY POWER SNITCH REMO/ED. 6 102 Jro::JJ-346-00CDJ WASHER P...AT NYL N05x.375x.03/ - 2 !32 BC(X)J-349-000CO TRAN.$1£NTSUPPR SSIOBV 8/PLR CR.2 CR.3
1s lw II R 1£ !M 1 _ _~ - - - = - - - - - - - - - 1 1 - ' 9
~a~_I0_3~J_6_0_2._'2_-_0_12_-~ooxo~~S~A_l<IC~£R~_o_.5_8~R_H_M_F_TD_6_-~32 33 Bcr:J02-IOJ -co::m SUR.GE SUPPR G4S 230/ INY DUTY £(-£19
RE.MOTE. CONTROL.
_L 34 BCXXJI -e,9e,-axro INDUCTOR fMH IHA-105 AXIAL Lt

1· ~ ~!~~-i;;=~ ~~C::0~~£5:~£::~;~o:~~ .
SEE NOTE 6
NOTES.' .,_L_T:-.-T2---------.
I 37 JaX)') -360-caxx> FU$£ ·0.5AMP SUB-MINI PICO Ft S££ NOTE 4
/. - SCHEMATIC C/(X)3-CXJ2-0:X.X:O. 2 .38 acro2 -149 -<XXXX) RECEPTACLE COMP 0.-0/6-0.040 rl .c::r: Fl
2. - ~ CMOS ]C's ASSEMBLE AT GROUNDED 'WJRK $TA710/I/. 2 39 BcaJI -891-CO<XX> RES \IVW 1% 0.75W 30.a Re.6 R94
3. - MARK BOAAD EDG£ WITH ASS/ P/N, f/J:YISI0/1/ LEVEL Al'O SERIAL I 40 BCXX)I -009 -COOOO RES NTWK 09 /OK SIP /OP R/36
NO •. AFTER FINAL ASS(. 4 41 BroJI - 544 -'10400 RES NTWK 09 IOOK SIP PULLUP RBS.RM R/14.Rl/5
4. - PJCQ_ElJSE F/ (ITEM 37) TO 8£ INSTALLED IN UNIT TEST AFTER 42 BCXX)l -695- OO'XO RES NTWK 09 22K SIP !OP 2% Rl37 -
43 BCXXJ2-206 -COOOO RES NTWK O(J IOOK DIP 16P U35
+.~V JiEG/.4.ATOR N)JLJSTME.NT.
3 44 BcaJI -1'193-COOOO RES CC 5°/o /,OW 3.9.a R95-R97
5. -<;tlJI!Sl:Jj CAPACITOfl.S C36,C44,C4-5 (ITEMS 79, 77, 78) MUST
45 89400-020-oro:::D RES CC 5% o.25W fOO.o. RB7
8.E.JI.O!.JNIED AFTER Fl..fNI SOLDER ID IMJJD CONTAMINATION 8Y 46 J6022-007-(XXX)() RES CC 5% 0,25W 220 .a. R{j(j
<13LORJNATED SOIYE.NTS. I 47 89400-022-COOOO RES CC 5% 0.25W 390A R14.2
6. - F O R . ~ MA!J~At;TIJP.ING. CJ>l'!EJ!JJJPATION INSTALL ITEM f(X) 2 48 BeJOO I - 030- a:1JOO RES CC 5% 0.25-W 560 .Q R.tJt .R(:)2
(Q.IY.4) To W2 CA-a & c-o), W4(ka), W5(A-a). (HALF DU- 22 49 H9402-034-00000 RES CC 5% 0.25W 020.a iOOOIQLJ{llJD!il()7./09/ll 113.ll7.
50 ,, " ,, n R/19.121,123.125.IZT.129./31.155-/60
PLEX, EXTERNAL STATUS P<:JNERl
8 5/ 81002 -036-COOOO RES CC 5% 0.25W IK R/32-135,139,/44,/53-/54
7. - FOA. REMOTE CONTROL OF R.f.lA' POHER (VARIANCE .• XXO!O) 2 52 B/007-013-COOOO RES CC 5% 0.25W J.2K R09,R91
2 5.3 89/03-003-00000 RES CC 5% 0.25W 2.2K R76,RB-O
S5
lS._Rf.fV.CEtJ Bf :,CON.~~EMKJ9(2OF 5).

~~~::s: -
SNJTC~H.
., RES CC 5% 0,5W 2,2K

--~~
I 54 J0209-035-00000 R.136
I 55 B/007-006-COOOO RES CC 5% 0.25W 3K RSIZ
I 56 .J6022- 005-CXX:OO RES CC 5% 0,25W 12K R90
5 RES CC 5% 0.25W 15K R47.FfSO,Rl46.Rl49.R.l52
. f . ~® 3
57 81007-011-CXX:XX,
~/3 BOX>/ - 904 -00000 RES MF 1% 0,12W 4.99K R75,R71. R79
4 59 Bet:0/ -903 -00000 RES MF 0.1% 0.12W !OK R67,R69,R7!./U3
I 60 BCXXD -/75 - cxxxt) RES MF 1% 0,12W /OK R56
ITEM-110 P£MCNE.D IF EXlE.RNAL SNITCH WIRED TO PIN I& PIN~ AT 2 61 8CIXt) -/73 - oct:JX) RES MF /°Ir, 0,12W. 20K R36,R37
I 62 BT.!13 -004-COOOO RES MF 1% 0.12W 49.9K R!S4
RTU ASSEM8/.Y LEVEL.
I 63 J4005-021-COOOO R.£S MF 1% 0.25W 56.2K RIS3
B. - CHOICE. OE. EXTERNAL OR INTE.P./'l,AI... STATUS PON£.R DE.TERM /NED Bf R6a,R"l0,R72.R74 R76
5 64 BCXX)/-905- COOOO RES MF 0.1°1,, 0.12W IOOK·
..,JUMPEF.S.. W4 & W5. ~-a' EXTEFWfJ!. ·: INTERNAL. ~B-c" 14 65 8CXXXJ 174 OCX::OO RES MF /% 0.12W IOOK Rl7,/9,2J.2448,51fif-64 /41.145./48./51
9. -INSTALL PIN STRIPS. (/TEM 99) FOP. W2-2+2 PINS, W4-3 PINS, I 66 BODO/ -5&1 -00000 RES MF 1% 0./2W 150K R55
_ W5-3 PINS, W/8-2 PINS, 16 67 BCXXJI - 808 - oro:::D RES MF 0.1% 0,/2 W ,200K RJ 7 11 /4 /8,20-22~5-28.3/,35.A/.45
/0. -JNSfALL llE.M 105 (p/N BCXX)2-/42-a:x:x:x)) 0.25# OFF 16 613 Bet::01 -887-COOOO RES MF 0.1% O.J2W499K Rf.4.5.8.9./2.13.15.30,32.33.JB.3!1.42.43:4/i
ti. 69 8CJXIJ - 602 - co:XXl CONN PLUG IN FCB 00 POS Jii5::ri3IO -
fDAAI) SURFACE. a 70 BCa)j - 662- C00'.)6 CONN PWGIN PCB 06 .PO$ Ta,::7'94·,-T-B-,-,---TB--,4·--------<
/.I.-~ DENOTES ITEMS Of.TE/WINED BY VARIANCE CHAF{TS.

SEE. NOTE 7

N 6468 7·28·&5 GW ..,..,_

6453 7-1·45 GW
I,/ '"-"".
N M06 6-;lf-1',5 tlW .1',I.,
SYM E:CO NO '"T!: a, .'.HJoi
 TB4

(?) q) (p $ ~ '4;J
4Y~, ~~
WI W2
EXEC 9)
W6 W7 CRl3 CR 14 CRl8 CRl9
EXEC I CR3 CR4 CR 8 CR9
wa W9
EXEC 2
JI J2 J3 Wl3
B 8 B 8 B 8 B 8
EXEC 3 Kl K2 K3 K4
EXEC 4 · CR2
W20 W21 OSI CR5 CRIO DS3 CRl2 CRl5 os4 CRl7 CR20
EXEC5
W22
A 5 A 5 A 5 A 5

SEL 7

SEL 6
SEL 5
SEL 4
SEL 3
SEL 2
SEL I

SEL 0

W3 W4 W5 WIO WII W12 Wl7 Wl8 Wl9 W23 W24 W25

A A A 5 A 5

DS5 DSG DS7 DS8

CR34 CR39
CR24 CR21 CR29 CR2G CR31 CR3G
R5 K5 KG K7 K8
B 8 B 8 B 8 B 8

CR23 CR22 CR28 CR27 CR33 CR32 CR38 CR37

RES1STORSRI-R8 - 2.7K
DIODES CRI -CR40 - IN4004
RELAYS KI - KB - p &. B KUP / KUL
LED'S OS I -DS8- Tl L220
1-1~ r1~ fi~ H~ i-Hf~ r-1~
@@0@©© TBS
@@0@©©
TB7
@@0@©© TB8

00 NOT SCALE DRAWING

HOUSTON. TEXAS
TOLERANCES UNLESS OTHERWISE SPECIF I ED
DECIMAL !:,.,015 FRACTION.AL :!_1/64 ANGLE!, 1/2° 1--+--,c----+--+-1------------1 MICR0/1
REHOVE ALL BURRS - BREAK ALL SHARP CORNERS

t---+-+--+---+--+-------------1 RELAY EXPANSION BOARD

DAT<2·21 ·84 ac,L&

MATERIAL HEAT TREAT PLATWG OR COATING

 OTY ITEM PAliH NUMBER DESCRIPTION DESIGNATION
; I CI004-AOO -00000 PCA MiCR0/1 RLY EXP BD --
i 2
;3 BOOO 1-084 - 00000 RLY PWR 2FC 48VDC IOA PLUG IN
4 BOOOl-719-00024 RLY PWR I FX MB IOA 150V 24VDC
·5 BOOOl-083-00000 RLY BIS 2FC 24VDC IOA PLUG IN

~· ~. ~·
__
2 6 61027-024 - 00000 WI RE BUS 18 G SXSN BARE
.·.~~. BCXXJ2 - 150- 00100 JUMPER MINI 0.100 IR 2P W3,57, 6,10,12.
TIil r:;;:- Tl!2 r::;:- Tl3 r:;;:- TB4 r.;;:- 10 .7
~___., . ~ ,. 0 ,o ~ ,o '8 II II IJ
17,19,23,25
. 9'

•• •• •• ••• •• •• •• •• •• •• ••
NOTE 9 80001 - 075 - _00000 SPRING RELAY FOR 1.9Hx1.4W RLY K1-K8

..:: .
p•
"•.

:: ~· Io
•• ~I · ~ :c~
. . . . . . . . ...
• •

14
•

R3
~· 19
•

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•

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.. " ~~ ~ 'o
t4
•

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~f ~,. ... :~:f::
o I·~
CM ec
• •

14
•

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•
•• •

14
•

QCJ/10
.::
n
J2
NOTE 9
NOTE 9
10
II
12
13
14
'80001 - 111 - 00000
80001 - 07 6 - 00000
SPRING RELAY FOR 2.2Hx1.5W RLY K1-K8
RIVET POP OP 5 - 32 D OM HD .250G

!:.;
n- "'°:-·•
••
R1
OS 1~ 14 CR4
IS Olt2
DS2Q
0.
H
..
C.M
CR10 llll

•
OS 3 Q
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•
14
"4
CRJ.4
GCR15 . .
OS 4Q
re.,
14
..
OCJl;f'P
ecno • I 15
0 •• ~;t £i;' c,,._
~~
COOi 0-N I') ... Ol'ltO ,.._«;Jct 0 •••
0

• • ..
•••••••

• •••••••••• ,1111.
3'~ J:~~
·3:·i<· ,1.;..3:. ~ 1t ~ .: ~ 1t •• o.- N M1".t)

•
0
,6-
1
; ; am
c~~~e 114 9
...c.::t.
-Cos ~Cll'l6EI···
C1tV 114
..&'::,.
~OS6~CR32
':c•3,~e ~ •,t!.~·~
°"Uos10CR37
M
•••~ '1B "'1 4l) S&o
:
,:: : : • olr.- : : fa ~:!!. : r:.; ~:!: : ra NOTES:
:: .
• • cau
. - ..,. V O ca30 ..,. · ol V . CA35 V
...
.. • 'W ~
. .-----~----
O cR•o .. e ~ 8

-ii • • • • • • • • I. SCHEMATIC : C1004 - 002 - 00000.

-~-. .. . ... . . . .. . ..
.
J3 • • • • • • • • • • • • 2. MARK BOARD EDGES WITH ASS{ PART NO., ~EV. LEVEL AND SERIAL NO.
I • • • • • • • • • 8 • • AFTER FINAL ASSY.
3: FOR MOMENTARY RE;LAYS OR A COMBINATION OF MOMENTARY AND LATOilNG
~-
0 K7 • _ RB.AYS INSTALL -JUMPERS W4,Wll,W18,W22,W24.
~~7.rt~ 4. FOR LATCHING RELAYS INSTALL JUMPERS W3,W51 WIO,Wl2,Wl7,'Nl91 W23,W25.
.~ 'llilll'll!VW'illll181
"-ill'-' __. 5._ FOR TEST PURPOSES INSTALL JUMPERS W7 & W8. ',

6. _ FOR ~ATCHING ONLY_ USE, FILI:- ~OCKETS KJ- K8 IN ASCB\IDING ORDER.

7. _ FOR MOM.ENTARY ONLY USE, FILL Kl,K5,K2,KG,K3,K7,K41 K6.
8. _ FOR COMBINATION USE , FILL MOMENTARY AS Af3CNf. , FILL LATCHING IN NEXf
.. AVAILABLE OF K2,K3 OR K4.
9. QTY OF SPRINGS AND RIVETS DEPENDS UPON QTY OF RELAYS.

CI 004 - OOO-OOXXX

t= O.TY MOM RELA'fS

TYPE MOM RELAYS { A= KUP (iJEM 3)
B= KUEP En'EM 4}
0.1'< LATCHING RELAYS (tTEM 5)

PICA I I I I I I

--
HOUSTON.TEXAS

11---t---+--+----l--+-------------·- MICRO /1
- per_W_6_repl-ace-d-'M'-th-W-7-.8--11.
1t::6-;:;659~E::-r.-:11:-:21~55::t-=GW-:-:--rv1..,,_.,,---t:N-OT-E:c-5---iUTi·
1
RELAY EX PANS ION BOARD
6516 D 8-15-85 GW w<-"" ADDED ITEMS 9, 10, 11 & NOTE 9 PCA
5435 C 7-11-85 OW l;~ A»c./) 175M 7 OWN GW OATlli3-16-84 I •cAU: f: I
~ B 5-10-84 GW MVI ADDED NOTES 5-8. MM
,__ _ _ _ _ _..
_A_:r..
ERIAL
_ _ _ _HEA_:r_r_REA
__:r.....P...L_ATIN_G_o_R_c_o_AT_IN...,G...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,_:l1::i., LET OATE BY CH~ -ff-E.-IIS-IOl-l------------1-,.-,...-1---'~:..:.~i..:.:M.;__--1cioo4-ooo-ooxxx
CHM
 TB I TB2 TB3 TB4
/ /
5 G
TB5 TBG
STATUS PWR +
+
m SHIELD GROUND
STATUS PWR -

R3 R7 R29 3.9K IW x 16

CR4 CR8 CR12 IN4004

OR X 16
P6KE 8.2

.02µF 500 V x 16

DS4 DS8 DSl2 DSIG Tl L220 X 16

820.a. X 16
3 3 3 4 2 3 3 4 3 4

~
:-'\£>- o-6~ (TYP) ;, ,; MCT6 x8
U2 U4 U5 UG U7 U9 UIO
6 8 7 5 B 7 5 6 8 7 5 6 B 7 5 6 B 7 5 ~
{, 8 7 5 6 B 7 5 6
'::" '::" -7 /
'::" -- -7 '::"

+ 5V
+5V 19
l,
17 3
B W2 W4 WG W8 WIO Wl2 5 I 15 5
6
13 7 WI W3 W5 W7j W9 WJJ , 16 2 11-4'----l&-+---!-+-+--l-_;4.JV\A,-41

II
5
9
18 3 U8 n-2----~--i---1--=-2J\/\1 R 18
12 8
RI? 17
U3 4
3
4 74HC a-:=--~----4111-+-+--l-...::BJV\/\r-CII IOOK
IOOK .3 14 5 240 6 6 SIP
15 74HC
SIP 5
240 2 7 6 • a-:-'3=-------_.__-i-..!..7..1\/\
4 16
~
2
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SD¢-SD7 soi - soi
9 SD 7 11-1_1--------411>--='9.JV\/\r-411
~
10 +5V
+ 5V
C9
,lfJF 7 +5V
JI JI

Cl91
22).JFI J2

00 NOT SCALE DRAWING HOUSTON.TEXAS

TOLERANCES UNLESS OTHERWISE SPECIF I ED
J3
DECIMAL .!..015 FRACTIONAL .:!:..1/64 ANGLE! l/2" 11---t--1--+--+-1----------1 MICRO/ 1
REMOVE All BURRS ~ BREAK ALL SHARP CORNERS 0
z
0
z
>-
w
0 - (\J r<) <r \/) (j) ,._ > > 1 - - - - 1 - - i - - + - - + - f - - - - - - - - - ~ STATUS EXPANSION BOARD
0 0 0 0 0 0 0 0 l!) l!)
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MATERIAL HEAT TREAT PLATING OR COATING "46 tET OAT£ &Y (HK ltfVISIQN APP KNflUE C1005-002-CCXXX)
 PART NUMBER DESCRIPTION DESIGNATION QTY

CI005-00I- REV-l> PCB MICR0/1 STAnJS EXP BD -- I I I I .

2
3 BOOO I - B4 7 :_ 00240 ICD 74HC240 BUFFER U3,U8 2. 2 2 2
4 81080-.216-0000 0 lCL MCT6 OPTO-ISOLATOR DUAL Ul-2,4-7, 9-10. 8 8 8 8
5
6 B<XX)I- 884 - OCf.XX) RES CC 5% IW 3.9 K Rl-8,27-34 16 - 16 -
7 69402- 034 - CIXJX) RES CC 5% 0.25W .820..a. R9-l~,19-24 .16 16. 16 16 1
8 BOOO I -544 - 104·00 RES NTWK SIP 9 PULWP lOOK R17-18 2 2 2 2
9
10 BOOOl-729 - OCXXX) CAP-P. TA 15V 22).JF 20% RL Cl9 I I I I
II 67093-003 - OCXXX) CAP-N CE 500V O,OZ,UF 20% RL CI-C8,CI I-Cl8 16 16 16 16
12 B0000 - 798 - <JXXX) CAP-N CE 50V O. I )JF 20% RL C9-CIO 2 2 2 2
13 Ba:JJ2- 23 7 - 10036 CONN HEADfR PCB S.l(X) 36 .150 WI -Wl2 •v• J I I l
..
14 B<XX) I - 24 7 - OCXXX) TRANSIENT SUFiPR ZENER 8,2V CRI-CRl6 - - 16 16
15 80002- 181 - ct:XXX) • SURGE .SUPPR.. GAS 2SOV H'N 'l>UT'I EI-E8 - - 8 8
IG B0000-871 - (JX[JJ LED .RED D LC R DS!-DS16 16 16 16 16
17 Ba:1)2 -237 - ICfD3 CONN .H£f,D£R PCB SJOO 0.3 .150 Wl-Wl2 ·1" '6 6 :6 6
18 BOOOl-879 - CfJJ20 CONN PCB PC 2xl0 M JI-J3 3 3 3 3
19 aooo1-aa2.- cocoa CONN PLUGIN PCB 06 POS TBI-TB4 4 4" 4 4
20 80001-882- CC003 CONN PLUG!N PCB 03 POS TB5-TB6 2· 2 2 2
21 BCXJJ/- 662-VHCXXJ CONN HEADER PCB 06 POS V TBJ-T84 4 4 4 4
22 B<XXJI- d62-VHOJ3 CONN HEADER PCB 03 POS V T85-TB6 2 2 2 2 '

23 Ba:JJ2 - 150 - 00 J(X) JUMPER MINI 0.100 JR 2P Wl,4 2 2 2 2

24
25
26
27
28

VARIANCE / 2 3 4 5

INPUT VARIANCE DEFLNITON

NOTE: c1oos- a:n - axnx

--
I. SCEMATIC; C/(X)5-(X)2-0XXXJ
2. INSTALL JUMPERS W/ AND W4
FOR TEST PURPOSES:
3. MARK BOARD EDGES WITH ASSY PART NO., REV.LEVEL -DOOD4 - - - . 1 2· g V Ci T
-00003 2 4. / 4 8 V & T
ANO SERIAL NO AFTER FINAL ASSY,
·-00002 1 2 9 V N B T
, - 00001 2 4 / 4 8 V MG T

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SU8SIDIARY OF . . . . .

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HOUSTON.TEXAS

5943 D I0·24 ·&4 liW (I+ AllDEl) ITEM 17 i0002 • 185" · 15006 PCA RE v- (;
5654 C 5·11°11'1 GW ,t,:"' Ablt.11 vAR'tAMCli l>HCAlPTION GW DATll:3-17-84 I •CALI! I : I
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MM OWG. NO
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MATERIAL HEAT TREAT PLATING OR COATING Al'P I CI005-000-0000X
 200K
X8
200K 499K 0.02),JF
1500PF · IOOK RII * xB xl6 500V GS
X 8 X 8 xB
RIO*
TBI·
JI J2 J3
R3
SHIELD
A GND
Rl2
ANALOG OUT C7
*
+
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7 S!-llELD
A GND

+ 5V + 5V R2 +
- 5V -5v
CG RIG
+15V +15V
3 *
-15V. -15V RIB*
OUT TB2
D GND
9 RI
A SEL 3 C
A SEL 2 10
B
U3 SHIELD
4051 B
A SEL I II
A C5 * +
WI 13
A CARD 7 (/)
A CARD 6
W2 14 SHIELD
W3 +
~
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15 R4
A CARD 4
W4 12
3
A CARD 3
W5 4 C8
A CARD 2
WG 5
5
R27-x-
A CARD I
W7 G INH 2
6
D GND 7
4 R45 R41
SHIELD
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C II +
VDD vss VEE
16 8 7
CONNECTION BETWEEN DIGITAL SHIELD
AND ANALOG GROUNDS. +5V -5V

C9l
, I/JF *CIO
• l)JF
Cl4
R48
R32-1t-
+

-5V +5V -15V +15V

R35*

l l l l
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IJJF
C20 C21
l)JF
C22 Cl2
R4G
SHIELD

+
1/JF IJJF

SHIELD
R47 +
Cl3 R40*
-15V

NOTES: SUiJSU)M,R'IOF •

00 NOT SCALE DRAWING * - I. MATCHED SET TO ,QI% HOUSTON. TEXAS

TOLERANCES UNLESS OTHERWISE SPECIF I ED
DECIAAL .!..015 FRACTIONAL :t_l/64 ANGLE!. 1/2• ** - 2. LOOP RESISTORS DEPEND ON APPLICATION:
11---+-+-----+-1---+----------1 MICRO / 1
REHOVE All BURRS - BREAK ALL SHARP CORNERS 250.LL FOR 4-20 mA
5 K FOR± I mA ANALOG EXPANSION BQi\RD
REV-A
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3·26-84 GW -..,.;· CHECKED PT TO PT AGAINST AR1'1-.0RK CHK

MATERIAL HEAT TREAT PLATING OR COATING Nd lf! O~Tf BY CHK REVISION
 QTY ci~ DESCRIPTION DESIGNATION
NOTES: l-=-:t...,,..-:==='l"l-l-r-':"I- , - - , - . , - - , , - ~ PCB MICRO / 1 ANA EXP BO
1

2 I
I. SCEMATIC: CIOOG-CD2-CXX:X::O I I I 3 00000-806 - 00000 ICD 4051B CMOS 1 OF 8 MUX U3
2. INSTALL JUMPER W7 FOR TEST PURPOSE. 4 4 4 4 4 4 4 $0001 -874 - 00000 ICL LF442A OPER AMPL DUAL UI-U2, U4-U5
3. MARK BOARD EDGES WITH ASSY PART NO., REV. LEVEL 5 I
8 B 8 8 8 8 6 (:l(XX)O - 174 - 00000 RES MF 1°1o 0.12W IOOK RI-R4, R45-R48
AND SERIAL NO. AFTER FINAL ASSY.
- - 8 8 - 7 ~COO) - 566 - 00000 RES WW 0.025,, 0.12W SK R5-R8,R41-R44
16 16 16 16 16 16 8 eooor - 888 - 00000 RES MF 0.l°k 0.12W 200K RI I, 12, 15, 16,19,20,23-25,
9 l // // // 28,29,31,33,36,37, 39.
16 16 16 16 16 16 I JO e<XX)I 887. 00000 RES MF 0.1 % 0.12W 499K R9,10,13,14,17,18,21,22,26,
11 / It II II 27,30,32,34,35,38,40.

- I
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8
I
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12
13
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B<X1J2-J50-: 00100 JUMPER. MINI 0.100 JR 2P
R5-R8, R41-R44
W7
2 2 2 2 2 2 6<XXX) - 798 - 00000 CAP-N CE 00V 0.1,.UF 20% RL
14 C9-CIO
4 4 4 4 4 4 15 800'.)I -870 -C/:XXXJ CAP-N CE 50V VJF 20% RL Cl9-C22
8 8 8 8 8 8 16 JCXXX>-586-00000 CAP-N CE IOOV 1500PF 5% RL C5-C8, CI I -Cl4
8 8 8 8 8 8 17 ~7093-003 - OCl:ro CAP-N CE 500V 0.02,.uF 200/o RL CI-C4, Cl5-Cl8
I I I I I I 18 B(XX)2 -237-10036 CONN HEADER PCB S.100 36 .150 WI-W7 · 'V'
-+---+--+--+---+_...;;.-++-----
8 - 8 8 - - 19 S0002 -181 - CJJ:tfJ SURGE SUPPR GAS 230V HVY DUTY EI-E8
7 7 7 7 7 7 20 ~<X1J2-237-JCX1J2 CONN HEADER PCB S.100 02 .150 WI-W7 •1•
J 3 3 3 3 3 21 B<XX>I- 879-00020 CONN PCB PC 2xlO M JI-J3
4 4 4 4 4 4 22 l3(XX) I - 882 -C0006 CONN PLUG IN PCB 06 POS ... TBI-TB4
4 4 .f. 4 4 4 Z3 8CXXJJ -(j(j2 -VH(f)f. CONN HEADER PCB 06 POS V TBI'"' TB4

5/5 4 3 2/1 -VARlt,NCE

A1 + /71 - "+ rn - A2 A3 + m - 11
+ m - A4

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00002 + / ... i M A N G T
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t! 10·94·i.'4 GW ~.2': Amlfll m:M 2'!1 l!IOOD2-U55·1500& GW DATll:5-9-64 I 111cAU1. I: I
B 5-9-84 GW 1v1.1v1 AID::D VARIANCE DESCRIPTION
MATERIAL HEAT TREAT
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PLATING OR COATING LET DATE i BY (HK REVISION