3

CIRCUIT DESCRIPTION

3. Circuit Description

• Main B’D

3-1 Main PBA

3-1-1 SUMMARY
The main circuit that consists of CPU, MFP controller (built-in 32bit RISC processor core: ARM7TDMI) including various I/O
device drivers, system memory, scanner, printer, motor driver, PC I/F, and FAX transceiver controls the whole system. The
entire structure of the main circuit is as follows :

PROGRAM DATA RAM

OSC SRAM
PLL ROM (DRAM)
20 MHz ARM7TDMI 256K
Cache 8KB 1MB x 4EA 8MB x 2EA
POWER Reset & WDT
ON RESET Generation
/CS,/RD,/WR

A/D BUS
ROM/SRAM/
FLASH ROM
IMCS
Control
(4 Bank)
/MIR0,

I/O EDO/FPM MA
/RD,/WR CPU BUS
Control MD
MODEM IOCS (5 Bank) Interface Block
DRAM
Control
RAS
D0~D7 CAS
(4 Bank)

A0~A4

GPIO
GEU
RST_OUT

RTC
/RST_OUT Interrupt
/XDACK
Control
(4 External) PVC
/XDREQ SYSTEM BUS
Interface Block PARALLEL
/SDIP CS [Arbiter]
Timer
(3 CH)
INTERFACE
CIP3 /RD,/WR PPI
D0~D15

A0~A5 Tone
Generator

UART DMAC
OSC.(Video) (3 CH) (2 CH)
VIS
45.3928 MHz
OPE PANEL
INTERFACE
JBIG HCT
Engine
Comm. I/F USB
OSC. INTERFACE IC USB
ADC LRAM:1296B
CXRAM:256B
48 MHz (UNICON)
LIU HPVC

RAM : 512B

RAM
512B+512B

<Block Diagram>

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2 Circuit Operation

3-2-1 CLOCK
1) System Clock
Device Oscillator
Frequency 20MHz±%

• KS32C61200 RISC PROCESSOR: drives PLL internally and uses 60MHz.

2) Video Clock
Device Oscillator
Frequency 45.3928 MHz±%

• Fvd =((PAPER 1SCAN LINE sending time * SCAN effective late /1SCAN LINE DOT #)*4
=(600dpi*600dpi*58.208mm/s*216mm*4)/(25.4mm*25.4mm*76.1%)=28.697MHz
•PAPER 1SCAN LINE sending time=SCAN LINE interval/DOCUMENT SPEED (58.208mm/S)
•1SCAN LINE DOT #=MAZ SCAN distance(216mm)*DOT# per 1mm

3)USB Clock
Device Oscillator
Frequency 48MHz±%

3-2-2 POWER ON/OFF RESET

1) Signal Operation

Input Signal +5V Power Line (VCC)

Output Signal KS32C61200 nRESET 29F800B nRESET

• POWER ON/OFF DETECT VCC RISING/FALLING 4.5°≠4.6V

RESET TIME (Td) 1.48~1.52ms

• Td=(Ct*V sensing)/I charge (...Ct=33µF, Is=100µA)

2) TIMING CHART

V CC and SENSE

Threahold Voltage
VV
CCCC 3.6V
VCC 2V

RESET td td

Output Output
Undefined Undefined

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-3 RISC MICROPROCESSOR

1) RISC MICROPROCESSOR PIN & INTERFACE

No Pin Name I/O Reset Value Description PAD

1 DATA0 I/O Input CPU Data Bus 0 PHBTT8, 8 mA
2 DATA1 I/O " CPU Data Bus 1 "
3 DATA2 I/O " CPU Data Bus 2 "
4 DATA3 I/O " CPU Data Bus 3 "
5 Vsso Vss - 5 V Gnd
6 DATA4 I/O Input CPU Data Bus 4 PHBTT8, 8 mA

7 Vddo Vdd - 5 V

8 DATA5 I/O Input CPU Data Bus 5 PHBTT8, 8 mA

9 DATA6 I/O " CPU Data Bus 6 "
10 DATA7 I/O " CPU Data Bus 7 "
11 DATA8 I/O " CPU Data Bus 8 "
12 Vssi Vss - 3.3 V Gnd
13 DATA9 I/O Input CPU Data Bus 9 PHBTT8, 8 mA
14 Vddi Vdd 3.3 V
15 DATA10 I/O Input CPU Data Bus 10 PHBTT8, 8 mA
16 DATA11 I/O " CPU Data Bus 11 "
17 DATA12 I/O " CPU Data Bus 12 "
18 DATA13 I/O " CPU Data Bus 13 "
19 Vsso Vss - 5 V Gnd
20 DATA14 I/O Input CPU Data Bus 14 PHBTT8, 8 mA
21 DATA15 I/O " CPU Data Bus 15 "
22 DATA16 I/O " CPU Data Bus 16 "
23 DATA17 I/O " CPU Data Bus 17 "
24 Vsso Vss - 5 V Gnd
25 DATA18 I/O Input CPU Data Bus 18 PHBTT8, 8 mA
26 DATA19 I/O " CPU Data Bus 19 "
27 DATA20 I/O " CPU Data Bus 20 "
28 DATA21 I/O " CPU Data Bus 21 "
29 Vddi Vdd - 3.3 V
30 DATA22 I/O Input CPU Data Bus 22 PHBTT8, 8 mA

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Samsung Electronics
 CIRCUIT DESCRIPTION

No Pin Name I/O Reset Value Description PAD

31 Vssi Vss - 3.3 V Gnd
32 DATA23 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
33 DATA24 I/O " CPU Data Bus 23 "
34 Vddp Vdd - 5V
35 DATA25 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
36 Vssp Vss - 5 V Gnd
37 DATA26 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
38 DATA27 I/O " CPU Data Bus 23 "
39 Vddo Vdd - 5V
40 DATA28 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
41 Vsso Vss - 5 V Gnd
42 DATA29 I/O Input CPU Data Bus 23 PHBTT8, 8 mA
43 DATA30 I/O " CPU Data Bus 23 "
44 DATA31 I/O " CPU Data Bus 23 "
45 Vssi Vss - 3.3 V Gnd
46 LFIA0 / OP4 O H Line Feed Motor Phase A PHOB4, 4mA
47 Vddi Vdd - 3.3 V
48 LFIA1 / OP5 O H Line Feed Motor Phase /A PHOB4, 4mA
49 LFIB0 / OP6 O " Line Feed Motor Phase B "
50 LFIB1 / OP7 O " Line Feed Motor Phase /B "
51 TnRST I TAP Controller Reset PHIT
52 TMS I TAP Controller Mode Sel PHIT
53 TDI I TAP Controller Data In "
54 TCK I TAP Controller Clock "
55 TDO O TAP Controller Data Out PHOB4
56 AVdd Vcca - Analog 3.3 V
57 AVin[0] I - Analog Input 0 PICA
58 AVin[1] I - Analog Input 1 "
59 AVss Vssa - Analog Gnd
60 AVssAVin[2] I - Analog Input 2 PICA

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Samsung Electronics
 CIRCUIT DESCRIPTION

No Pin Name I/O Reset Value Description PAD

61 AVref I - Analog Positve Reference PICA
62 nIOCS0 O H IO Chipselect 0 PHOB4, 4 mA
63 nIOCS2/ToneOut O " IO Chipselect 2 / ToneOut "
64 nIOCS3/BufferSel O " IO Chipselect 2 / BufferSel "
65 Vssi Vss - 3.3 V Gnd
66 nSELECTIN I - Select Input PHIL, ST
67 nFAULT O H Fault for Error Condition PHOB8, 8 mA
68 nAUTOFD I - Auto Feed PHIL, ST
69 nINIT I - Initialization "
70 SELECT O L Parallel Port Select PHOB8, 8 mA
71 Vddp Vdd - 5 V
72 PERROR O L Paper Error PHOB8, 8 mA
73 BUSY O " Parallel Port Busy PHOB8, 8 mA
74 nACK O H Parallel Port Acknowledge PHOB8, 8 mA
75 Vssp Vss - 5 V Gnd
76 PD0 I/O Input Parallel Port Data 0 PHBTT8, 8 mA
77 PD1 I/O " Parallel Port Data "

78 Vddi Vcca - 3.3 V for Ring OSC

79 PD2 I/O Input Parallel Port Data PHBTT8, 8 mA

80 PD3 I/O " Parallel Port Data "
81 Vssi Vssa - 3.3 V Gnd for Ring OSC
82 PD4 I/O Input Parallel Port Data PHBTT8, 8 mA
83 PD5 I/O " Parallel Port Data "
84 Vddo Vdd - 5 V
85 PD6 I/O Input Parallel Port Data PHBTT8, 8 mA
86 PD7 I/O " Parallel Port Data "
87 nSTROBE I - Data Strobe PHIL, ST
88 Vsso Vss - 5 V Gnd
89 RxD1 / CTin[2] I - Uart 1 Rx Data PHIL, ST
90 TxD1 O H Uart 1 Tx Data PHOB4, 4 mA

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Samsung Electronics
 CIRCUIT DESCRIPTION

No Pin Name I/O Reset Value Description PAD

91 nDREQ1/RxD2/CTin[1] I - DMA Request1/Uart 2 RxD PHIL, ST
92 nDMACK1 / TxD2 O H DMA Ack1/Uart 2 TxD PHOB4, 4 mA
93 nIOCS1 / nIOCS5 O " IO CS1 / DMA IO1 CS "
94 Vddi Vdd - 3.3 V
95 nDREQ0 /IP1/CTin[0] I - DMA Request0 / Input Port PHIL, ST
96 nDMACK0 / OP1 O H DMA Ack1 / Out Port PHOB4, 4 mA
97 nIOCS4 / OP2 O " DMA IO0 CS / Out Port "
98 EIRQ0 I - External Interrupt 0 PHILU50, ST
99 EIRQ1 I - External Interrupt 1 "
100 EIRQ2 I - External Interrupt 2 "
101 nWait / EIRQ3 I - Wait Request / Ex. IRQ 3 "
102 Vssi Vss - 3.3 V Gnd
103 VCLK I - Video Clock Input PHIC
104 Vddi Vdd - 3.3 V
105 IP[7] / nFSYNC I - Input Port / Frame Sync PHIL, ST
106 nLSYNC I - Line Sync "
107 OP[8] / nPRINT O H Out Port / Print Start PHOB4, 4 mA
108 Vssi Vss - 3.3 V Gnd
109 VDO O H Video Data Output PHOB16, 16mA
110 Vsso Vss - 5 V Gnd
111 CCLK / PWM[0] O H Com. Clock / PWM [0] PHOB4, 4 mA
Engine Power Ready
112 nEPRDY / RxD0 I - PHIL, ST
/ Uart 0 Rx Data
Command Busy
113 nCBSY / TxD0 O H PHOB4, 4 mA
/ Uart 0 Tx Data
114 nEMSG / PWM[1] I/O Input Eng. Message / PWM [1] PHBLT4,ST,4mA
115 nEBSY / nLsuReady I - Eng. Busy / LSU Ready PHIL, ST
116 nCMSG / PWM[2] O H Com. Busy / PWM [2] PHOB4, 4 mA
117 Vddo Vdd - 5 V
118 nDRAMCAS0 O L DRAM Cas Strobe 0 PHOB8, 8 mA
119 nDRAMCAS1 O " DRAM Cas Strobe 1 "
120 nDRAMCAS2 O " DRAM Cas Strobe 2 "

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Samsung Electronics
 CIRCUIT DESCRIPTION

No Pin Name I/O Reset Value Description PAD

121 nDRAMCAS3 O L DRAM Cas Strobe 3 PHOB8, 8 mA
122 Vsso Vss - 5 V Gnd
123 nDRAMOE O H DRAM Data Out Enable "
124 nDRAMWE O H DRAM Data Write Enable "
125 Vssi Vss - 3.3 V Gnd
126 nDRAMRAS0 O L DRAM Ras Strobe 0 PHOB8, 8 mA
127 Vddi Vdd - 3.3 V
128 nDRAMRAS1 O L DRAM Ras Strobe 1 PHOB8, 8 mA
129 nDRAMRAS2 O " DRAM Ras Strobe 2 "
130 nDRAMRAS3 O " DRAM Ras Strobe 3 "
131 Vsso Vss - 5 V Gnd
132 DRAMD0 I/O Input DRAM Data Bus 0 PHBTT12, 12mA
133 Vddo Vdd - 5 V
134 DRAMD1 I/O Input DRAM Data Bus 1 PHBTT12, 12mA
135 DRAMD2 I/O " DRAM Data Bus 2 "
136 DRAMD3 I/O " DRAM Data Bus 3 "
137 DRAMD4 I/O " DRAM Data Bus 4 "
138 Vsso Vss - 5 V Gnd
139 DRAMD5 I/O Input DRAM Data Bus 5 PHBTT12, 12mA
140 DRAMD6 I/O " DRAM Data Bus 6 "
141 DRAMD7 I/O " DRAM Data Bus 7 "
142 Vssi Vss - 3.3 V Gnd
143 DRAMD8 I/O Input DRAM Data Bus 8 PHBTT12, 12mA
144 Vddi Vdd - 3.3 V
145 DRAMD9 I/O Input DRAM Data Bus 9 PHBTT12, 12mA
146 DRAMD10 I/O " DRAM Data Bus 10 "
147 DRAMD11 I/O " DRAM Data Bus 11 "
148 Vssp Vss - 5 V Gnd
149 DRAMD12 I/O Input DRAM Data Bus 12 PHBTT12, 12mA
150 Vddp Vdd - 5 V

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

No Pin Name I/O Reset Value Description PAD

151 DRAMD13 I/O Input DRAM Data Bus 13 PHBTT12, 12mA
152 DRAMD14 I/O " DRAM Data Bus 14 "
153 DRAMD15 I/O " DRAM Data Bus 15 "
154 DRAMD16 I/O " DRAM Data Bus 16 "
155 Vsso Vss - 5 V Gnd
156 DRAMD17 I/O Input DRAM Data Bus 17 PHBTT12, 12mA
157 Vddo Vdd - 5 V
158 DRAMD18 I/O Input DRAM Data Bus 18 PHBTT12, 12mA
159 DRAMD19 I/O " DRAM Data Bus 19 "
160 DRAMD20 I/O " DRAM Data Bus 20 "
161 DRAMD21 I/O " DRAM Data Bus 21 "
162 Vssi Vss - 3.3 V Gnd
163 DRAMD22 I/O Input DRAM Data Bus 22 PHBTT12, 12mA
164 Vddi Vdd - 3.3 V
165 DRAMD23 I/O Input DRAM Data Bus 23 PHBTT12, 12mA
166 DRAMD24 I/O " DRAM Data Bus 24 "
167 DRAMD25 I/O " DRAM Data Bus 25 "
168 DRAMD26 I/O " DRAM Data Bus 26 "
169 Vsso Vss - 5 V Gnd
170 DRAMD27 I/O Input DRAM Data Bus 27 PHBTT12, 12mA
171 Vddo Vdd - 5 V
172 DRAMD28 I/O Input DRAM Data Bus 28 PHBTT12, 12mA
173 DRAMD29 I/O " DRAM Data Bus 29 "
174 DRAMD30 I/O " DRAM Data Bus 30 "
175 DRAMD31 I/O " DRAM Data Bus 31 "
176 Vsso Vss - 5 V Gnd
177 DRAMA0 O L DRAM Address Bus 0 PHOB8, 8 mA
178 DRAMA1 O " DRAM Address Bus 1 "
179 DRAMA2 O " DRAM Address Bus 2 "
180 DRAMA3 O " DRAM Address Bus 3 "

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

No Pin Name I/O Reset Value Description PAD

181 DRAMA4 O L DRAM Address Bus 4 PHOB8, 8 mA
182 Vsso Vss - 5 V Gnd
183 DRAMA5 O " DRAM Address Bus 5 "
184 DRAMA6 O " DRAM Address Bus 6 "
185 DRAMA7 O " DRAM Address Bus 7 "
186 Vddo Vdd - 5 V
187 DRAMA8 O L DRAM Address Bus 8 PHOB8, 8 mA
188 Vsso Vss - 5 V Gnd
189 DRAMA9 O L DRAM Address Bus 9 PHOB8, 8 mA
190 DRAMA10 O " DRAM Address Bus 10 "
191 DRAMA11 O " DRAM Address Bus 11 "
192 Vssi Vss - 3.3 V Gnd
193 nROMCS0 O H ROM Chip Select 0 PHOB4, 4 mA
194 Vddi Vdd - 3.3 V
195 nROMCS1 O H ROM Chip Select 1 PHOB4, 4 mA
196 nROMCS2 O " ROM Chip Select 2 "
197 nROMCS3 O " ROM Chip Select 3 "
198 nROMRD O " ROM or IO Read PHOB8, 8 mA
199 Vssp Vss - 5 V Gnd
200 nROMWR O H ROM or IO Write PHOB8, 8 mA
201 Vddp Vdd - 5 V
202 ADDR2 O L Address Bus 2 for ROM PHOB8, 8 mA
203 ADDR3 O " Address Bus 3 for ROM "
204 ADDR4 O " Address Bus 4 for ROM "
205 Vsso Vss - 5 V Gnd
206 ADDR5 O L Address Bus 5 for ROM PHOB8, 8 mA
207 ADDR6 O " Address Bus 6 for ROM "
208 ADDR7 O " Address Bus 7 for ROM "
209 Vssi Vss - 3.3 V Gnd
210 ADDR8 O L Address Bus 8 for ROM PHOB8, 8 mA

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

No Pin Name I/O Reset Value Description PAD

211 ADDR9 O L Address Bus 9 for ROM PHOB8, 8 mA

212 Vddo Vdd - 5 V

213 ADDR10 O L Address Bus 10 for ROM PHOB8, 8 mA

214 Vsso Vss - 5 V Gnd

215 ADDR11 O L Address Bus 11 for ROM PHOB8, 8 mA

216 ADDR12 O " Address Bus 12 for ROM "

217 ADDR13 O " Address Bus 13 for ROM "

218 ADDR14 O " Address Bus 14 for ROM "

219 Vsso Vss - 5 V Gnd

220 ADDR15/CTOut[0] O L Address Bus 15 for ROM PHOB8, 8 mA

221 ADDR16/CTOut[1] O " Address Bus 16 for ROM "

222 ADDR17/CTOut[2] O " Address Bus 17 for ROM "

223 ADDR18/CTOut[3] O " Address Bus 18 for ROM "

224 Vsso Vss - 5 V Gnd

225 ADDR19/CTOut[4] O L Address Bus 19 for ROM PHOB8, 8 mA

226 ADDR20/CTOut[5] O " Address Bus 20 for ROM "

227 ADDR21/CTOut[6] O " Address Bus 21 for ROM "

228 ADDR22/CTOut[7] O " Address Bus 22 for ROM "

229 Vddo Vdd - 5 V

230 ADDR23/PTOut O L Address Bus 23 for ROM PHOB8, 8 mA

231 Vsso Vss - 5 V Gnd

232 TESTSE I - Scan Enable :Tied to Gnd PHILD50, ST

233 TM I - Test Mode :Tied to Gnd "

234 Vddi Vcca - 3.3 V for PLL

235 MCLK I - Master Clock PHIC

236 Vssi Vssa - 3.3 V Gnd for PLL

Charge Pump Out :

237 FILTER O - POBA
Capacitor is connected
CPU Test Mode :
238 CPUTEST I - PHILD50, ST
Tied to Gnd
239 nRESET I - Reset Input PHIL, ST

240 nRSTOUT O L Reset Output PHOB8, 8 mA

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-4 PROGRAM ROM (FLASH MEMORY) CONTROL

1) DEVICE

TYPE No...................................AM29F800B
CAPACITY................................4 MBYTE (512K * 16BITS * 4)

2) PROGRAMMING

BEFORE ASS’Y.......................EPROM PROGRAMMER or PROGRAMMING at the factory

AFTER ASS’Y ..........................DOWNLOAD from PC

3) OPERATING PRINCIPLE

When the RCSO(ROM CHIP SELECT)signal is activated from the CPU after the POWER is ON, it activates RD SIGNAL
and reads the DATA(HIGH/LOW) stored in the FLASH MEMORY to control the overall system.
The FLASH MEMORY may also write. When turning the power on, press and hold the key(power switch) for 2 - 3 seconds,
then the LED will scroll and the PROGRAM DOWNLOAD MODE will be activated. In this mode, you can download the pro-
gram through the parallel port.

Tr Ta Tw Tw Tw Tw Tw Tw Tw Td Tr Tr Tr Tr

MCLK

nWR

A23-2

nROMCS

nTA

SETUP ACC+1 HOLD

<Write Timing Diagram for Two Beat Burst Cycle>

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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-5 DRAM CONTROL

1) DEVICE

TYPE NO..................................K4E6411D EDO TYPE

CAPACITY................................4MBYTES (1M*16BITS*2)

2) OPERATING PRINCIPLE

DRAM can either read or write. The data can be stored in the DRAM only when the power is on. It stores data white the CPU
processes data. The address to read and write the data is specified by RAS SIGNAL and CAS SIGNAL. DRAMWE*SIGNAL
is activated when writing data and DRAMOE*SIGNAL, when reading. You can expand up to 64MBYTE of DRAM in this sys-
tem.

0xf f f f f f f

bank3 Next

bank3 Base

bank2 Next

bank2 Base

bank1 Next

bank1 Base

bank0 Next

bank0 Base

0x0000000

<DRAM Bank Configuration>

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-5-1 Fpm DRAM reading Timing

Fast Page Mode DRAM can access the page mode. It can read consecutive cells by accessing the page mode while access-
ing the burst. For FPM DRAM, the data are valid only when the nCAS is active.

While configuring the software, you must set the timing register of SFR considering the clock speed and the DRAM spec.

addr wait dat a wait dat a

5Mhz

MCLK

nRAS

nCAS

DRAMA r ow address column address column address

nOE

nWE

DRAMD dat a 0 dat a 1

Trp Trc Tcas Tcas

<FPM Read Timing Diagram>

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-5-2 fpm DRAM write timing

addr wait dat a wait dat a

5Mhz

MCLK

nRAS

nCAS

DRAMA r ow address column address column address

nOE

nWE

DRAMD dat a 0 dat a 1

Trp Trc Tcas Tcas

<FPM Write Timing Diagram>

Trp Trc Tcas

clock type
cycle # register cycle # register cycle # register
40 ns FPM 2 0x1 2 0x1 1 0x0
50 ns FPM 2 0x1 2 0x1 1 0x0
58Mhz
60 ns FPM 3 0x2 2 0x1 2 0x1
70 ns FPM 3 0x2 2 0x1 2 0x1

<SFR Values Example for FPM>

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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-5-3 EDO DRAM read timing

Basically the Extended Data Out DRAM is similar to Fast Page Mode DRAM. For FPM, the data are valid only when the
nCAS is active while reading the internal data, however, it has a latch that the data will be
continuously outputted even after the nCAS is inactivated.
While configuring the software, you must set the timing register of SFR considering the clock speed and the DRAM spec.

addr wait dat a wait dat a

5Mhz

MCLK
nRAS

nCAS

DRAMA r ow address column column

nOE

nWE

DRAMD data 0 data 1

Trp Trc Tcas Tcas

<EDO Read Timing Diagram>

Repair Manual
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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-5-4 edo DRAM write timing

addr wait dat a wait dat a

5Mhz
MCLK

nRAS

nCAS

DRAMA r ow address column column

nOE

nWE

DRAMD dat a 0 dat a 1

Trp Trc Tcas Tcas

<FPM Write Timing Diagram>

Trp Trc Tcas

clock type
cycle # register cycle # register cycle # register
40 ns EDO 2 0x1 2 0x1 1 0x0
50 ns EDO 2 0x1 2 0x1 1 0x0
58Mhz
60 ns EDO 3 0x2 2 0x1 1 0x0
70 ns EDO 3 0x2 2 0x1 2 0x1
<SFR Values Example for FPM>

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Samsung Electronics
 CIRCUIT DESCRIPTION

3-2-6 FS781 (FREQUENCY ATTENUATOR)

This system used FS781 for the main clock for EMI SUPPRESSION.
It spreads the source clock in a consistent bandwidth to disperse the energy gathered in order to attenuate the energy.
The capacitor value of the loop filter(PIN 4) is set depending on the source clock used or the spread bandwidth. Refer to
FS781 Spec. for detail.

3-2-7 USB (UNIVERSAL SERIAL BUS)

NS’s USBN9602 is used as the interface IC and 48MHz clock is used.
When the data is received through the USB port, EIRQ1 SIGNAL is activated to send interrupt to CPU, then it directly sends
the data to DRAM by IOCS4*&DRAMA(11) SIGNAL through DRAMD (24;31).

3-2-8 SRAM; 32KB SRAM

It stores a variety of option data.

3-2-9 FAX TRANSCEIVER (Only SCX-5312F)

3-2-9-1. GENERAL
This circuit processes transmission signals of modem and between LIU and modem.

3-2-9-2. MODEM (u44)

FM336 is a single ship fax modem. It has functions of DTMF detection and DTMF signal production as well as functions of
modem. TX A1, 2 is transmission output port and RX IN is received data input port. / POR signal controlled by MFP controller
(U36:KS32C61200) can initialize modem (nMODEM_RST) without turning off the system.
D0-D7 are 8-bit data buses. RS0-RS4 signals to select the register in modem chips. /RS and /WR signals control READ and
WRITE respectively. /IRQ is a signal for modem interrupt.

Transmission speed of FM336 is supported up to 33.6k. The modem is connected to LINE through transformer directly.

< FAX TRANSCEIVER >

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Samsung Electronics
 CIRCUIT DESCRIPTION

3-3 Scanner

3-3-1 SUMMARY
This flat-bed type device to read manuscripts has 600dpi CCD as an image sensor. There is one optical sensor for detecting
CCD home position and Scan-end position. The home position is detected by a optical sensor which is attached to the CCD
Module. The Scan-end position is calculated by number of motor step.

CCD : Charge Coupled Device improves productivity and allows a compact design.

This machine uses a color CCD.

• Minimum Scan Line Time for One Color : 5mS

• Light Source Power : +12V
• Maximum Pixel frequency : 6 MHz
• Effective Sensor Element : 5340 X 3
• Clamp Level : 0.7~0.8V
• Bright Output : MIN 0.8V

R_L ED,
G _LE D,
AIN PI_TG B _LE D
EXT SRAM
AD C_REF T PI1 PI2
ADC _REFB

[ AFE] Sen so r Shadi ng

12-bit Interfac e Ac qu isitio n
A/ D c onv erter

Vertic al
Shadi ng D ec im ation
C orrec tio n

SRAM
1 024 x 8
Gam ma SRAM_A[ 15:0]
( R/G/ B) SRAM_D[ 15: 0]
C orrec tio n SRAM_nRD
SRAM_nWR

Imag e SRAM
Proc es s ing 256 x 8
SRAM
Enlarge men t Mo dule
8 192 x 8
/ Redu c t ion
( 2l ine) SRAM
4 09 6 x16
(2 line )

IRQ Interrupt Vp eak

Cont ro l Contro l TX_A, B
Mo to r
n TX_A, B
Con tro l
TX_EN1, EN2

D MA

CPU I/F CIP3 Interfac e

SRAM
Mod ule Regis ter
1 024 x 8

n CS n RD n WR A [ 5 : 0] D [ 15 : 0] n XDREQ n XDACK

<Block Diagram>

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Samsung Electronics
 CIRCUIT DESCRIPTION

3-3-2 KEY FEATURES

Overview

(1) 0.5µm C-MOS process(TLM), 208-PIN QFP, STD85 library

(2) Frequency : 50 MHz
(3) On-Chip oscillator
(4) Method : Raster scanning method
(5) Image Sauce : 300/400/600dpi CIS & CCD
(6) Scanning Mode
• color gray image : each 8 bits / RGB
• mono gray image : 8 bits / pixel
• binary image : 1 bit / pixel (for text/photo/mixed mode)
(7) Maximum scanning width : A3, 600dpi (8K effective pixels)
(8) Ideal MSLT (A4, 600/300dpi)
• color gray image : 3x5Kx80nsec = 1.2msec (7/28 CPM)
• mono gray image : 1x5Kx80nsec = 0.4msec (21/84 CPM)
• binary image : 1x5Kx80nsec = 0.4msec (21/84 CPM)
(9) A/D conversion depth : 12bits

Pixel processing structure

• Minimum pixel processing time : 4 system clocks

• High speed pipelined processing method
(Shading correction, Gamma correction, Enlargement/Reducement, and Binarization)

Shading Correction

(1) White shading correction support for each R/G/B

(2) White shading data memory : 3x8Kx12bits = 288Kbits 384Kbits (external)
(3) Black shading data memory : 3x8Kx12bits = 288Kbits 384Kbits (external)

Gamma Correction

(1) Independent Gamma table for each RGB component

(2) Gamma table data memory : 3x1Kx8bits = 24Kbits (internal)

Binarization (mono)

(1) 256 Gray’s halftone representation for Photo document : 3x5 EDF(Error DifFusion) method proposed by Stuck.
(2) LAT(Local Adaptive Thresholding) for Text document :
• use of 5x5 LOCAL WINDOW (TIP ALGORITHM)
• ABC(Automatic Background Control) :Tmin Automatic change
(3) Mixed mode processing for text/photo mixed document
(4) EDF data memory : 2x4Kx16bits = 128Kbits (internal)
(5) LAT data memory : 4x4Kx16bits = 256Kbits (external)

Scaling of input image

(1) Scaling factor

• Horizontal direction : 25 ~ 800% by 1% unit
• Vertical direction : 25 ~ 100% by 1% unit
(2) Scaling data memory : 2x8Kx8bits = 128Kbits (internal)

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 CIRCUIT DESCRIPTION

Intelligent scan motor controller

(1) Automatic acceleration/deceleration/uniform velocity

(2) Data memory : 256x16bits = 4Kbits (internal)

Auto-Run

Automatic CLK_LINE (line processing start control) and •’TG (line scan start control) signal generation|

(1) Available resynchronization of øTG signal

(2) programmable øTG’s period & CLK_LINE’s occurrence number

Processed data output format in DTM(Data Transfer Module)

(1) DMA mode : Burst/On-demand mode

(2) CDIP I/F : LINE_SYNC, PIXEL_SYSNC, PIXEL_DATA[7:0]

• 36 General Purpose Input/Output : 8(GPO), 28(GPIO)

• Black/White reversion, and Image Mirroring support

ADD R BU S
DMA Controller
DATA MEMORY DATA BUS 1M bit
(Jupiter)
SRAM

T T
CLK_LINE R R
D D
CLK_PIX M M
L IN E_PERIOD A A Image
_
_

IW IN A R
C
K
E
Q Processor

Scan/Motor
CPU ADC _CLK

Driver CD S2 _CLK
AFE
(Jupiter) AFE Co ntro l
12b it ADC
Sig na l

12 b it (R/ G/ B)
ADD R- BUS ADDR- BUS Ana lo g Si gn al
PI_TG
PI1 , PI2
Scanner
Tx_A, Tx_B,
DAT A- BUS DAT A- BUS
n Tx_A, nTx_B

CIP3 D OCU MENT IMAGE

<External interface with CIP3>

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 CIRCUIT DESCRIPTION

R_LED,
G _LED,
AIN PI_TG B_LED
EXT SRAM
ADC_REFT PI1 PI2
ADC_REFB

[ AFE] Sen so r Shadi ng

12-bit Interface Acqu isitio n
A/ D converter

Vertical
Shadi ng Decimation
Correctio n

SRAM
1 024 x 8
Gamma SRAM_A[ 15:0]
( R/G/ B) SRAM_D[ 15: 0]
Correctio n SRAM_nRD
SRAM_nWR

Imag e SRAM
Processing 256 x 8
SRAM
Enlarge men t Mo dule
8 192 x8
/ Redu ction
( 2l ine) SRAM
4096 x16
(2 line )

IRQ Interrupt Vp eak

Contro l Contro l TX_A, B
Mo to r
nTX_A, B
Con tro l
TX_EN1, EN2

DMA

CPU I/F CIP3 Interface

SRAM
Mod ule Register
1 024 x 8

nCS nRD nWR A[5:0] D [15:0] nXDREQ nXDACK

<Block diagram of CIP3>

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 CIRCUIT DESCRIPTION

3-4 HOST INTERFACE:

Referred to IEEE 1284 standard.

3-4-1. HOST INTERFACE

PARALLEL PORT INTERFACE PART KS32C61200 has the Parallel Port Interface Part that enables Parallel Interface with
PC. This part is connected to PC through Centronics connector. It generates major control signals that are used to actuate
parallel communication. It is comprised of/ERROR, PE, BUSY, /ACK, SLCT, /INIT, /SLCTIN, /AUTOFD and /STB. This part
and the PC data transmission method support the method specified in IEEE P1283 Parallel Port Standard
(http://www.fapo.com/ieee1284.html). In other words, it supports both compatibility mode (basic print data transmitting
method), the nibble mode (4bit data; supports data uploading to PC) and ECP (enhanced capabilities port: 8bits data - high
speed two-way data transmission with PC). Compatibility mode is generally referred to as the Centronics mode and this is
the protocol used by most PC to transmit data to the printer. ECP mode is an improved protocol for the communication
between PC and peripherals such as printer and scanner, and it provides high speed two-way data communication. ECP
mode provides two cycles in the two-way data transmission; data cycle and command cycle. The command cycle has two
formats; Run-Length Count and Channel Addressing. RLE (Run-Length Count) has high compression rate (64x) and it
allows real-time data compression that it is useful for the printer and scanner that need to transmit large raster image that has
a series of same data. Channel Addressing was designed to address multiple devices with single structure. For example,
like this system, when the fax/printer/scanner have one structure, the parallel port can be used for other purposes while the
printer image is being processed.This system uses RLE for high speed data transmission. PC control signals and data
send/receive tasks such as PC data printing, high speed uploading of scanned data to PC, upload/download of the fax data
to send or receive and monitoring the system control signal and overall system from PC are all processed through this part.

PPD( 7: 0) DATA

BUSY

nSTROBE

nACK

<Compatibility Hardware Handshaking Timing>

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 CIRCUIT DESCRIPTION

1 2 3 4 5 6

nSTROBE

BUSY

PPD( 7: 0) BYTE0 BYTE1

nAUTOFD DATA BYTE COMMAND BYTE

<ECP Hardware Handshaking Timing (forward) >

1. The host places data on the data lines and indicates a data cycle by setting nAUTOFD
2. Host asserts nSTROBE low to indicate valid data
3. Peripheral acknowledges host by setting BUSY high
4. Host sets nSTROBE high. This is the edge that should be used to clock the data into the Peripheral
5. Peripheral sets BUSY low to indicate that it is ready for the next byte
6. The cycle repeats, but this time it is a command cycle because nAUTOFD is low

1 2 3 4 5 6 7 8

nACK

nAUTOFD

PPD( 7: 0) BYTE0 BYTE1

BUSY DATA BYTE COMMAND BYTE

nINI T

PE

<ECP Hardware Handshaking Timing (forward)

1. The host request a reverse channel transfer by setting nINIT low

2. The peripheral signals that it is OK to proceed by setting PE low
3. The peripheral places data on the data lines and indicates a data cycle by setting BUSY high
4. Peripheral asserts nACK low to indicate valid data
5. Host acknow ledges by setting nAUTOFD high
6. Peripheral sets nACK high. This is the edge that should be used to clock the data into the host
7. Host sets nAUTOFD low to indicate that it is ready for the next byte
8. The cycle repeats, but this time it is a command cycle because BUSY is low

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 CIRCUIT DESCRIPTION

3-4-2 USB INTERFACE

CS RD VVR A0/ALE D[7:0]/AD[7:0] INTR MODE[1:0]

RESET
Vcc
Microcontroller Interface
GND

Endpoint/Contol FIFOs XIN

48 MHz
XOUT
Control Status Oscillator

RX Clock CLKOUT

TX
Generator

SIE
Clock
Media Access Controller[MAC] Recovery

USB Event
Physical Layer interface[PHY]
Detect

V3.3

Trans ceiver VReg AGND

D+ D- Upstream Port

3-4-2-1 Features
• Full-Speed USB Node Device
• USB transceiver
• 3.3V signal voltage regulator
• 48 MHz oscillator circuit
• Programmable clock generator
• Serial Interface Engine consisting of Physical Layer In-terface (PHY) and Media
• Access Controller (MAC), USB Specification 1.0 compliant
• Control/Status Register File
• USB Function Controller with seven FIFO-based End-points :
• One bidirectional Control Endpoint 0 (8bytes) : Three Transmit Endpoints (2*32 and 1*64 bytes)
• Three Receive Endpoints (2*32 and 1*64 bytes)
• 8-bit parallel interface with two selectable modes : non-multiplexed
• multiplexed (Intel compatible)
• DMA support for parallel interface
• MICROWIRE/PLUS Interface
• 28-pin SO package

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 CIRCUIT DESCRIPTION

CS
DATA_IN 0x00
A0
DATA_IN
VVR
RD
DATA_OUT

DATA_OUT

D[7:0]

ADDR ADDRESS

0x3F

REGISTERFILE

<Non-Multiplexed Mode Interface Block Diagram>

cs

A0

RD

VVR

D[7:0] input out out

vvrte Address Read Data Burst Read Data

<Non-Multiplexed Mode Basic Timing Diagram>

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 CIRCUIT DESCRIPTION

3-5 Engine Controller

3-5-1. FUSER CONTROL / THERMISTOR CIRCUIT
This circuit controls the heat lamp temperature to fix the transferred toner on the paper. It is comprised of the thermistor that
has the negative resistance against the temperature and LM393 (voltage comparator) and transistor for switching.
The thermistor has the resistance value reverse proportional to the heat lamp surface temperature. The voltage value is read
by #60 pin(AVIN2) of CPU refering to the parallel combined resistance with the resistor(R43) connected parallel to it and the
voltage distribution of R29. The voltage read activates (inactivates) ‘fuser’ signal to high (or low) referring to the set tempera-
ture and when the ‘fuseron’ signal turns down(high) to low(high) by Q3 switching, the S21ME4 inside SMPS (PC3) turns
on(off) and this eventually turns two-way thyristor(THY501) on(off) to allow(shut) AC voltage to the heat lamp.

LM393 is a H/W designed to protect the system when the software heat lamp control does not run normal. When the ther-
mistor temperature goes up to 210°C, #1 pin’s level (LM393) will turn low to turn the ‘fuseron’ signal to high. (forcefully shuts
off Q3)In other words LM393 shuts off the heat lamp forcefully.

3-5-2. PAPER SENSING CIRCUIT

1) Cover Open Sensing
Cover Open Sensor is located on the right rear side of the printer. In case the right cover is open, it shuts +5V (LSU laser
unit) and +24V( polygon motor of fixer LSU and HVPS) that are supplied to each unit. It detects the cover opening through
CPU. In this case, the red LED of the OP Panel LED will turn on.

2) Paper Empty Sensing

The paper empty sensor (photo interrupter), located inside bottom of the bin cassette detects paper with the actuator con-
nected to it and informs the CPU of whether there is paper. When there is no paper in the cassette, the red LED of the OP
panel LED will turn on to tell the user to fill the cassette with papers.

3) Paper Feeding When the paper is fed into the set and passes through the actuator of the feed sensor unit, transistor inside
the photo interrupter will turn on, ‘nFEED’ signal will turn low and inform CPU that the paper is currently fed into the sys-
tem. CPU detects this signal and sprays video data after certain time (related to paper adjustment). If the paper does not
hit the feed sensor within certain time, CPU detects this and informs as “Paper Jam0” (red LED on the OP panel will turn
on).

4) Paper Exit Sensing

The system detects the paper going out of the set with the exit sensor assembled to the actuator attached to the frame. If
CPU does not turn back high a while after the paper hits the exit sensor, CPU detects this and inform as “Paper Jam2” (red
LEDs on the OP panel will turn on).

3-5-3. LSU CIRCUIT

1) Polygon Motor Unit (actuated by +24V)
The polygon motor inside LSU rotates by the ‘PMOTOR’ signal. When it reaches the motor constant velocity section through
the initial transient (transient response) section, it sends the ‘nLREADY’ signal to the CPU. The ‘clock’ pin is the pin that
receives clock of the required frequency when LSU uses external CLK as the motor rotational frequency. Currently the exter-
nal clock circuit is located in the HVPS and 1686Hz = 6.9083MHz (crystal frequency)÷4096(74HC4060N IC), is used as
the rotational frequency of the polygon motor.

2) Laser Unit (actuated by +5V)

After laser is turned on by ‘nLD_ON’ signal, it is reflected by 6 mirrors (polygon mirror) attached to the polygon motor and
performs scan in horizontal way.When the laser beam hits the corner of the polygon mirror, it generates ‘nHSYNC’ signal
(pulse) and the CPU forms the left margin of the image using this signal (horizontal synchronous signal).

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 CIRCUIT DESCRIPTION

3-5-4. FAN/SOLENOID ACTUATION CIRCUIT

The fan actuation circuit its power using NPN TR. When it receives ‘FAN’ signal from the CPU. The TR will turn on to make
the voltage supplied to the fan to 24V in order to actuate the fan.
The solenoid is actuated in the same way. When it receives control signal from the CPU, the solenoid for paper feeding is
actuated by switching circuit.
D29(1N4003) diode is applied to the both ends of the output terminal to protect Q22(KSC1008-Y) from noise pulse induced
while the solenoid is de-energized.

3-5-5. PTL ACTUATION CIRCUIT

PTL actuation circuit switches its power using NPN TR.

3-5-6. MOTOR ACTUATION CIRCUIT

Motor actuation circuit is determined while selecting the initial driver IC (provided by the vendor). This system uses
TEA3718(U57, U58), A2918(U59)’s motor driver IC. However, the sensing resistance (R273, R274, R292, R293) and refer-
ence resistance (R284, R289, R294, R295) can vary depending on the motor actuation current value.
It receives motor enable signal (2 phase) from CPU and generates bipolar pulse (constant-current) and sends its output to
stepping motor input.

3-5-7. HIGH VOLTAGE POWER SUPPLY

3-5-7-1. Summary
It is the high voltage power supply that has DC+24V/DC+5V (used for the image forming device in OA digital picture devel-
oping method) as the rated inputs. It supplies electrifying voltage (MHV), supply voltage (SUPPLY), developing voltage (DEV),
blade voltage(BLADE) and transferring voltage (THV).
Each high voltage supply shows the voltage required in each digital picture process.

3-5-7-2. Digital Picture Process

Digital picture developing method is widely used by copy machine, laser beam printer and fax paper.
The process is comprised of electrification, exposure, develop, transfer and fixing.
First, in the electrification process, retain constant charge at approx. -900V for the electric potential on the OPC surface by
electrifying OPC drum at approx. -1.4KV through the electrification roller.
The electrified surface of OPC is exposed responding to the video data by the LSU that received print command due to rota-
tion. The unexposed non-video section will retain the original electric potential of -900V, but the electric potential of the image
area exposed by LSU will be approx. -180V that it will form the electrostatic latent image. The surface of the photo-conduc-
tive drum where the electrostatic latent image is formed reaches the developer as the drum rotates. Then the electrostatic
latent image formed on the OPC drum is developed by the toner supplied to the developing roller by supplying roller and it is
transformed into visible image. It is the process to change the afterimage on the OPC drum surface formed by LSU into vis-
ible image by the toner particles.
While the supply roller energized with -450V by HVPS and the developer roller energized with -300V rotate in the same

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 CIRCUIT DESCRIPTION

BLADE
LSU SUPPLY
MHV DEV

SUPPLY ROLLER

DEVELOPER ROLLER
HEAT ROLLER

ELECTRIFICATION DIRECTION OF PAPER

ROLLER

THV
PRESSURE ROLLER

TRANSFER ROLLER

direction, it keeps the toner particles between two rollers supplied to OPC drum in negative state by the friction between two
rollers.
The toner supplied to the developer roller is biased to bias electric potential by the developer roller and transferred to the
developing area. After (-) toner is attached to the developer roller, it will move to the exposed high electric potential surface (-
180V) rather than to the unexposed low electric potential surface (-900V) of the developer roller and OPC drum. Eventually
the toner will not settle in the low electric potential surface to form the visible image.
Later, the OPC drum continues to rotate and reaches to transfer location in order to accomplish the transfer process.
This process transfers the (-)toner on the transfer roller to the printing paper by the transfer roller. The (-)toner attached to the
OPC drum will be energized to hundreds to thousands of the (+)transfer voltage by HVPS. The (+)electrostatic force of the
transfer roller generated has higher adhesiveness than the (-)toner OPC drum and thus it moves to the surface of the paper
passing through the transfer roller. The toner transferred to the paper with weak electrostatic force is fixed to the paper by the
pressure and heat of the fixer composed of pressure roller and heat roller. The toner attached to the paper is melted by apply-
ing the heat (approx. 180°C) from the heat roller and the pressure (approx. 4kg) from the pressure roller. After the fixing
process, the paper is sent out of the set to finish the printing process.

3-5-7-3. Organization of the Device

HVPS is comprised of electrification output unit, bias output unit and transfer output unit.

1) Input Unit
2) Electrification Output (Enable) Unit: MHV (Main High Voltage)
3) Bias Output (Enable) Unit: DEV (Development Voltage)/Supply(Supply Voltage)/BLADE(Blade Voltage)
4) Transfer ‘+’ Output (Enable) Unit: THV(+)(Transfer High Voltage(+))
5) Transfer ‘-’ Output (Enable) Unit: THV(-)(Transfer High Voltage(-))
6) Switching Unit
7) Feedback Unit
8) Regulation Unit
9) Output Unit

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 CIRCUIT DESCRIPTION

TRANS REGULATION OUTPUT

SWITCHING CIRCUIT
CONTROL UNIT CIRCUIT MHV

MHV-PWM

<Electrification Unit Block-Diagram>

THVPWM

PWM SWITCHING REGULATION

CONTROL UNIT CONTROL UNIT TRANS CIRCUIT
THV

FE E DBACK

THVEA
SWITCHING REGULATION
TRANS
CONTROL UNIT CIRCUIT

THVREAD
THV FEED BACK
ENVIRONMENT
RECOGNITION
CIRCUIT

<Transfer Output Unit Block Diagram>

MHV-PWM SWITCHING TRANS REGULATION MHV

PWM CONTROL UNIT CIRCUIT
CONTROL UNIT

OPC

FEEDBACK

<MHV Output unit Block Diagram>

BIAS-PWM
BLADE
PWM SWITCHING REGULATION
CONTROL UNIT CONTROL UNIT TRANS CIRCUIT

SUPPLY
FEEDBACK

DEV

<BIAS Output Unit Block Diagram>

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 CIRCUIT DESCRIPTION

3-5-7-4 MHV (Electrification Output Enable)

Electrification Output Enable is the electrification output control signal 'PWM-LOW ACTIVE'.
When MHV-PWM LOW signal is received, Q401 turns on and the steady voltage will be accepted to the non-inverting ter-
minal of OP-AMP 324. As the voltage higher than the inverting reference voltage of OP-AMP, which is set to R405 and
R406, OP-AMP output turns high. This output sends IB to the TRANS auxiliary wire through current-restricting resis-
tance Q402 via R408 and C403 and Q402 turns on. When the current is accepted to Q402, Ic increases to the current pro-
portional to time through the T401 primary coil, and when it reaches the Hfe limit of Q402, it will not retain the "on" state, but
will turn to "off". As Q402 turns 'off', TRANS N1 will have counter-electromotive force, discharge energy to the sec-
ondary unit, sends current to the load and outputs MHV voltage through the high voltage output enable, which is com-
prised of Regulation– circuit.

T401 MHV OUTPUT

24VS C404
3K/471
18V

D402 C406
4KV 3K/471

Q402
U103 7407 R405 220K R416 R413
MHV-PWM Q401 A708 D526
24VS 15M 12M
R412 2.2K
OPC
R417
R403 130K R408 R409 15M
+
47K 390
ZD401
R404 150V
R402 27K
_ KA324
82K C403
C407 333
R411 2K
104
R406
2.2K

3-5-7-5 BIAS (supply/dev/blade output unit)

BIAS (Electrification Output Enable)Electrification Output Enable is the electrification output control signal ‘PWM-LOW
ACTIVE’.When BIAS-PWM LOW signal is received, Q501 turns on and the steady voltage will be accepted to the non-invert-
ing terminal of OP-AMP 324. As the voltage higher than the inverting reference voltage of OP-AMP, which is set to R506
and R507, OP-AMP output turns high. This output sends IB to the TRANS auxiliary wire through current-restricting
resistance Q502 via R509 and C504 and Q502 turns on. When the current is accepted to Q502, Ic increases to the cur-
rent proportional to time through the T201 primary coil, and when it reaches the Hfe limit of Q502, it will not retain the “on”
state, but will turn to “off”. As Q502 turns ‘off’, TRANS N1 will have counter-electromotive force, discharge energy
to the secondary unit, sends current to the load and outputs DEV voltage through the high voltage output enable, which
is comprised of Regulation-circuit.

24VS

D502
T201 R514
KAB-007
4KV MGR1/2W 50K
7
1 BLADE
5V

C503 R508 Q502 5 6 C506 ZD501

R515
R520 R506 104 47K D526-Y 3KV 471 100V MGR1/2W 50K
R501 2
C505
26K Q501 86.6KF 2KV 680 SUPPLY
100
BIAS-PWM A708-Y
2 5
_ ZD501
7 4
100V
CON03-#24 U103-A R519 U1
7407 2.2K + R509 R510
6
R503 R504 C501 U101-B 47K 430
100KF 56.6KF 104 KA324 R512 DEV
MGR1/2W 12MF R516
C504 R511
R502 C502 MGR1/2W 50K
R507 333 1W 3
2K 222 12KF

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 CIRCUIT DESCRIPTION

3-5-7-6. THV(THV(+)/THV(-) Output Unit)

Transfer(+) output unit is the transfer output control signal 'PWM-LOW ACTIVE'.
When THV-PWM LOW signal is received, Q203 turns on and the steady voltage will be accepted to the non-inverting ter-
minal of OP-AMP 324. As the voltage is higher than the inverting reference voltage of OP-AMP, OP-AMP output turns high.
The 24V power adjusts the electric potential to ZD201 and ZD202, sends IB to TRANS auxiliary wire through current-
restricting resistance R215 via R212 and C204, and eventually Q204 will turn on. When the current is accepted to Q402,
Ic increases to the current proportional to time through the T201 primary coil, and when it reaches the Hfe limit of Q204, it will
not retain the "on" state, but will turn to "off". As Q402 turns 'off', TRANS N1 will have counter-electromotive force, dis-
charge energy to the secondary coil, sends current to the load and outputs THV voltage through the high voltage output
enable, which is comprised of Regulation– circuit. The output voltage is determined by the DUTY width. Q203 switches
with PWM DUTY cycle to fluctuate the output by fluctuating the OP-AMP non-inverting end VREF electric potential, and
the
maximum is output at 0% and the minimum, at 100%.Transfer(-) output unit is THV-EA 'L' enable.
When THV-EA is 'L', Q302 turns on and the VCE electric potential of Q302 will be formed and sends IB to TRANS auxil-
iary wire through R311, C305 and VR302 via current-restricting resistance R314, and eventually Q303 will turn on. When
the current is accepted to Q303, Q303's Ic increases to the current proportional to time through the T301 primary coil, and
when it reaches the Hfe limit of Q303, it will not retain the "on" state, but will turn to "off". As Q303 turns 'off', TRANS
N1 will have counter-electromotive force, discharge energy to the secondary coil, send current to load and output THV(-)
voltage through the high voltage output enable, which is comprised of Regulation– circuit.

5V

18V 24VS
R201
10K T201 C206 C208
U2 U2 KAB-007 6KV470pF
1 2 3 6KV
#7 TEV-PWM 1 7
R206
R205 100 D201 D206
C205 D204 D205 D207
1.8K 1N4148 6KV
2KV68pF 6KV 6KV 6KV
R208 C209
Q203 30K 6KV
A708Y 5 +
7 R213 5 6
U1 C207
R209 2.2K
_ 3KV470pF
100KF 6 Q204 2
R207 D526
24VS 2K C201 C202 D202 11 KA324
121 R210 R211
103 1N4148
VR201 845KF 1MF R216 R218
50K SBR306 MGR1/2W100KF
+ C101
35V47UF 4
C204 R215 R217
R212 C203 D203 ZD201 ZD202 R214
333Z 390 SBR207
680K 472 1N4148 5.65V 705V 2.2K

#17
5V
#19

18V
D301
5V 1N4148

R312
R309 1W56
202K KAB-006
C307 D304
T301
5 6 Q301 3KW470pF 4KV
#5 TEV-EA 1 6
U2 A708Y
R307 R313
7 7407
24VS 33K 1W56
C306 D303 C308 R315
2KV68pF 4KV 3KV470pF SBR306
18V

D-GND 5
C4 7
103
R310 Q303 2
2.2K D526
Q302
R308 A708Y
33K VR302
+ 10
8 2K
#24 TEV-READ U1
9 R302 R303 R304 4
_ R306
33K 100KF 389KF R311 C305 R314
KA324 26.1KF
100KF 333Z 1.7K
C302 D302 C303
R301 102 1N4148 103 R305
470K 10KF
C304
500V103Z
VR301
5K
C301
222

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 CIRCUIT DESCRIPTION

3-5-7-7. Environment Recognition

THV voltage recognizes changes in transfer roller environment and allows the voltage suitable for the environment in order
to realize optimum image output. The analog input is converted to digital output by the comparator that recognizes the
environmental changes of the transfer roller. It is to allow the right transfer voltage to perform appropriate environmental
response considering the environment and the type of paper depending on this digital output by the programs that can
be input to the engine controller ROM.

This environment recognition setting is organized as follows: First, set the THV(+) standard voltage.
Allow 200MΩ load to transfer output, enable output and set the standard voltage 800V using VR201.
Then set 56 (CPU's recognition index value) as the standard using VR302.
This standard value with CPU makes sure that the current feedback is 4µA when output voltage is 800V and load is 200MΩ.
If the load shows different resistance value when 800V is output, the current feedback will also be different and thus the
index value will also be different. according to the index value read by CPU, the transfer voltage output will differ according
to the preset transfer table.
The changes in transfer output required by each load is controlled by PWM-DUTY.

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 CIRCUIT DESCRIPTION

3-6 OPE PBA

3-6-1 SUMMARY
OPE Board is separated functionally from the main board and operated by the micom(Z8601) in the board. OPE and the main
use UART (universal asynchronous receiver/transmitter) channel to exchange information. OPE reset can be controlled by
the main. OPE micom controls key-scanning and LCD and LED display. If there occurs an event in OPE (such as key touch),
it sends specific codes to the main to respond to the situation and the main analyzes these codes and operates the system.
For example, it the main is to display messages in OPE, the main transmits data through UART line to OPE according to the
designated format and OPE displays this on LCD, LED. OPE’s sensing is also transmitted to the main through UART line
and then the main drives necessary operation.

OPE PBA consists of U1(MICOM, Z8601),LCD, key matrix, LED indicators. Refer to OPE Schematic Diagram and Wiring
Diagram sections of this manual.

• Signals from the key matrix are delivered to U1 input pin group (D1~D6)
• U1 pin 48 (TX DATA) is the UART code sent to MAIN PBA.

• Display from the controller is received at U1 pin 5(RX DATA).

• LCD drive signals are sent from U1 P2-x pin group, P3-4~P3-6 pins.
• Machine status LED drive signals are sent from U1 LED0~LED7.

RESONATOR
7.37 MHz

UART2 11
LCD
16 X 2 Line
Connector MICOM
Reset Z8601
7
X

Y 8 Key Matrix

LEDs

<OPE BLOCK DIAGRAM>

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 CIRCUIT DESCRIPTION

3-7 LIU PBA

3-7-1. SUMMARY
LIU WIRE CONNECTS Main B’D’s MODEM AND LINE PARTS, AND IMPEDANCE MATCHING (AC, DC), RING DETEC-
TION PART and LINE SEIZURE (DIALER).

3-7-2. DC MATCHING PART

Normal movement range of LIU is 12mA ~ 9mA.
Adapting CTR21 standard, the regulation limits to 60mA CURRENT flow through the terminal.
Therefore, select (*:for EU PIT) Option to connect necessary items then the current through LIU will not exceed 60mA.

• CTR21 Standard(Europe) : 12mA~60mA • OTHER Standard (U.S.) : 12mA~90mA

DC has a character to pass through the LINE. And with Q1 (VN2410) GATE section’s LINE INPUT corrent and Q1 Source
connection to R20, can be decided as follows :

• -VDCR = VL1 + ILINE X R20

(VDCR : Tip-Ring CD Voltage, ILINE : Current flow)VL1:Line Input Voltage, VL1=VBD1+VCE(Q2)+VDS(Q1)

3-7-3. AC MATCHING PART

Basic LIU’s AC IMPEDANCE is 600 and uses R47. 48. C36 to possibly control combined IMPEDANCE.

• U.S. Usage : A terminal IMPEDANCE Æ 600W(±30%)

• CTR21 : A Terminal IMPEDANCE Æ 270+750W//150nF

3-7-4. DIALER PART

*MF DIAL

DTMF Dialing is controlled by MODEM and should be selected by appropriate LEVEL and On-off Time output based on each
countries’ own National specification.

• Tolerance : ±1.5%
High Group : 1209, 1336, 1477, 1633Hz
Low Group : 697, 770, 852, 941 Hz

U.S. Usage CTR21

High Freq Level -9.0+2.0/-2.5 -7.0 +1.0/-2.0
Low Freq Level -9.0+1.0/-2.0 -11.0+2.5/-2.0

*DP DIAL

Controls from MAIN through / DP-Terminal.

for U.S.Usage, set time to DF signal of 40:60 M/B. DP signal is made of U6 (pcb817). The DC current which flows thru Q2
Base is regulated by On/Off switch and turns to DP dial signal with a COUPLER.
• CTR 21 does not have telephone capability but has the number 3 and 4 Line Connection. No DP condition but possibility
to get approval only on DTMF Dial based terminal.

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 CIRCUIT DESCRIPTION

3-7-5. RING DETECTION PART

RING SIGNALS from the LINE section (TIP, RING)are further passed through C5, R3, ZD1, and ZD2 and ends up at U9, (PC
814). U9 then detects above RING SIGNAL and passes the output to MAIN B’D. The wilre diagram’s C5 is RINGER CAPAC-
ITOR and it normally uses 1UF/250V.
A R3 limits AC current and controls upper and lower REN meter.

3-8 SMPS (Switching Mode Power Supply) Unit.

3-8-1 SMPS SPECIFICATIONS

The SMPS (Switching Mode Power Supply) Unit used here is a PWM (Pulse Width Modulation) type power supply unit that
supplies DC+5V to controller and control panel, and DC+5V, DC+24V and DC+12V to the engine. It also supplies AC power
to fixer heat lamp.

No. Output Channel Ch.1 Ch.2 Ch.3

1 Channel Name +5.1V +24.0V +12.0V
2 Rated Output Voltage +5.1V +24.0V +12.0V
3 Rate Output Current 2A 2.5A 1.0A
4 Maximum Load Current 3A Continued 3.5A Continued 1.0A Continued
and Load Pattern
5 Load Change Range 0.5~2.0A 0.3~2.5A 0.2~1.0A
6 Rate output voltage +5.1V±5% +24.0V±10% +12V±5%
(For rated I/O) (+4.84~+5.35V) (+21.60~+26.40V) (+11.40~+12.60V)
7 1) Total Output Voltage Including All Including All Including All
Deviation +5.1V±5% +24.0V±10% +12V±5%
(Input, Load, Temp., Aging) (+4.84~+5.35V) (+21.60~+26.40V) (+11.40~+12.60V)
2) Dynamic Input Change Including Set Error Including Set Error Including Set Error
3) Dynamic Load Change
8 Refer to ripple & noise 27) 150mVp-p or less 500mVp-p or less 150mVp-p or less
9 Refer to load short and Must not ignite or Output voltage must Must not ignite or
overload protection 23) generate smoke shutdown withing generate smoke
Refer to load short and when output shorted the range of when output shorted
overload protection 23) for 5 sec. 3.5A~6.5A for 5 sec.

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 CIRCUIT DESCRIPTION

3-8-2 AC INPUT STAGE

AC Input power path is consist of the Fase (F501) for AC current limit, the Varistor (TNR501) for by-passing high Voltage
Surge, the discharge resistor(R508), the AC Impalse Noise Filtering Circuit (C501, LF501, C503), the Common Mode
Grounding Circuit (C504, C505), the 2’nd noise filter (LF502), and the thermistor (TH501).
Wher power is turned on, TH 501 limits Inlush-Current by it’s high resistanle, and When it’s temperature rise, it’s resistance
become about Zero ohm.

3-8-3 SMC(SWITCHED MODE CONTROL)

The AC input voltage is rectified and filtered by BD552 and C507 to create the DC high voltage applied to the primary wind-
ing of T501. TR01 pin #1 is driven by the SMPS device U502. U502. auto-starts and chops the DC voltage. The U502 is PWM
SMPS IC and has internally a SMC(switched mode control) IC and a MOSFET output stage. The SMC IC has a Auto-restart
without a Power Supply for the IC and a Thermal Shutdown function and so on. C509, R512, C510, D505 clamp leading-
edge voltage spikes caused by transformer leakage inductance.
The power secondary winding(pim #11-12)is rectified and filtered by D507, C552, L551, and C554 to create the 5V output
voltage. The bias winding(pin #4-5)is rectified and filltered by D506 and C511 to create U502 bias voltage. The secondary
output 5V is regulated through the path of the voltage divide by R553, R556-U503 switching PC252-the bias voltage of U502-
U503 PWM duty cycle-T501 secondary voltage. C508 filters internal pin, determines the auto-restart frequency, and togeth-
er with R506, compensates the control loop. U552 of the secondary stage -12Vis the Low Power-loss Regulator with built-in
overcurrent protection function

3-8-4. FIXED TEMPERATURE CONTROL

3-8-4-1. Fixed Lamp Control Circui

AC Power Live
AC Neutral L501

R503
Zero crossing circuit
Logic Unit
C502 Fuser On
4
2
THY501

R505
1

6
R502 SMPS Unit
CON502 U501 DC Power

<Fixed Lamp Control Circuit>

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 CIRCUIT DESCRIPTION

3-8-4-2. The Concept of Fixed Lamp Control

For fixed lamp control, the logic unit "fuser on" control signal and SMPS unit DC power must be supplied. This circuit
turns on only when "fuser on" sends the signal and the DC power is supplied.
The following explains how the fixed lamp control circuit works.
logic unit "fuser on" sends trigger current to triac driver U501 LED, then the infrared ray is detected by U501 photo detector.
Next, U501 triac is conducted.
The conducted current sends trigger input to triac THY501 gate. At this point, THY501 is conducted and AC power is sup-
plied to fixed lamp. Lamp is turned on and temperature rises.
As this fixed lamp control circuit uses the AC voltage ("+" and "-" are repeated) as the power supply, it used two-way triac
(THY501), which has advantage over one-way SCR considering the price, size and reliability.
Triac's gate can be triggered by either forward or reverse signal. Once triac is turned on, it will not be controlled by gate sig-
nal, but will be continuously on until the current between major terminals decreases below the holding current. In other
words, you cannot turn it off with reverse signal unlike SCR. This property is called current-voltage threshold rise
rate (commutation: dv/dt). In AC power control
application, triac has to turn off conduction in each zero crossing or switch it twice in each cycle. This switching operation is
called commutation. It is possible to turn off the triac at the end of half cycle by eliminating the gate signal when the load cur-
rent (IL) is gained at the level equal to or lower than holding current. When triac commutes off-line, the direction of the
voltage of the both ends of triac will be reversed and increase up to the maximum value of line voltage (VAC). At this point,
the width of rise rate will be determined by dv/dt and overshoot voltage, by the circuit. When triac commutes off-line, the volt-
age of both ends of triac will have the same voltage as the line voltage.

IL

Inductive IL

VAC VT

<Inductive Circuit>

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