Individual Assignment

Instructions:
1. The figure numbers mentioned in the questions are from the Textbook (Computer System
Architecture, Author: Morris Mano)
2. Need to submit hand written assignments individually on or before 5.00(LT),
27/05/2019
3. Assignment should include both questions and answers.
4. Late submission will not be entertained.
5. Incorrect answers will result in deduction of marks.
6. Neatness and clarity of answers will have weightage for the marks.

Questions
1. A computer uses a memory unit with 128K words of 16 bits each. A binary instruction
code is stored in two word of memory. The instruction has four parts: an indirect bit. an
operation code, a register code part to specify one of 128 registers, and an address part.
a. How many bits are there in the operation code, the register code part, and the
address part?
b. Draw the instruction word format and indicate the number of bits in each part.
c. How many bits are there in the data and address inputs of the memory?

2. The following control inputs are active in the bus system shown in Fig. 5-4. For each case,
specify the register transfer that-will be executed during the next dock transition

Sl. No S2 S1 S0 LD of Register Memory Adder & Logic Circuit

1. 1 0 0 DR - -
2. 0 0 0 AC - AND
3. 1 1 1 TR Read -
4. 0 1 1 - Write -

3. The following register transfers are to be executed in the system of Fig. 5-4. For each
transfer, specify: (1) the binary value that must be applied to bus select inputs S2, S1 and
S0; (2) the register whose LD control input must be active (if any); (3) a memory read or
write operation (if needed); and (4) the operation in the adder and logic circuit (if any).
a. PC ← AR
b. M[AR] ← DR
c. TR ← M[AR]
d. DR ← AC

4. Explain why each of the following microoperations cannot be executed during a single
clock pulse in the system shown in Fig. 5-4. Specify a sequence of microoperations that
will perform the operation.
a. DR ← M[PC]
b. AC ← AC + IR
c. DR ← DR + AC (AC does not change)

5. Consider the instruction formats of the basic computer shown in Fig. 5-5 and the list of
instructions given in Table 5-2. For each of the following 16-bit instructions, give the
 equivalent four-digit hexadecimal code and explain in your own words what it is that the
instruction is going to perform.
a. 1001 0000 0010 0101
b. 0011 0001 0010 0101
c. 0111 0000 0010 0000
d. 1111 1000 0000 0000

6. Draw a timing diagram similar to Fig. 5-7 assuming that SC is cleared to 0 at time T3 if
control signal C7 is active.
C7 T3: SC ← 0
C7 is activated with the positive clock transition associated with T1

7. The content of AC in the basic computer is hexadecimal 1234 and the initial value of E is
1 . Determine the contents of AC, E, PC, AR, and IR in hexadecimal after the execution of
the CMA instruction. Repeat 11 more times, starting from each one of the register-
reference instructions. The initial value of PC is hexadecimal 020H

8. An instruction at address 021 in the basic computer has I = 0, an operation code of the
ADD instruction, and an address part equal to 083 (all numbers are in hexadecimal) The
memory word at address 083 contains the operand 18F2 and the content of AC is A937.
Go over the instruction cycle and determine the contents of the following registers at the
end of the execute phase: PC, AR, DR, AC, and lR. Repeat the problem six more times
starting with an operation code of another memory-reference instruction.

9. Show the contents in hexadecimal of registers PC, AR, DR, IR, and SC of the basic computer
when an ISZ indirect instruction is fetched from memory and executed. The initial content
of PC is 7FF. The content of memory at address 7FF is 6A9F. The content of memory at
address A9F is FFFE. The content of memory at address FFE is FFFF. Give the answer in a
table with five columns, one for each register and a row for each timing signal. Show the
contents of the registers after the positive transition of each clock pulse.

10. The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The
content of AC is 7EC3. The content of memory at address 3AF is 932E. The content of
memory at address 32E is 09AC. The content of memory at address 9AC is 8B9F.

a. What is the instruction that will be fetched and executed next?

b. Show the binary operation that will be performed in the AC when the instruction
is executed.
c. Give the contents of registers PC, AR, DR, AC, and IR in hexadecimal and the values
of E, I, and the sequence counter SC in binary at the end of the instruction cycle.

11. Assume that the first six memory-reference instructions in the basic computer listed in
Table 5-4 are to be changed to the instructions specified in the following table. EA is the
effective address that resides in AR during time T4. Assume that the adder and logic circuit
in Fig. 5-4 can perform the exclusive-OR operation AC ←AC ⊕ DR . Assume further that
the adder and logic circuit cannot perform subtraction directly. The subtraction must be
done using the 2' s complement of the subtrahend by complementing and incrementing
AC. Give the sequence of register transfer statements needed to execute each of the listed
instructions starting from timing T4. Note that the value in AC should not change unless
 the instruction specifies a change in its content. You can use TR to store the content of AC
temporary or you can exchange DR and AC.

Symbol Opcode Symbolic Designation Description

XNOR 000 AC←AC ⊕ M[EA] Exclusive NOR to AC
ADM 001 M[EA] ←M[EA] + AC Add AC to Memory
SUBM 010 M[EA] ← M[EA] - AC Subtract AC from Memory
XCHG 011 M[EA] ← AC , AC ← M[EA] Exchange AC and Memory
SNEQ 100 If M[EA] ≠ AC, then PC ← PC+1 Skip on Not Equal
BPA 101 If AC>0, then PC ← EA Branch if AC is positive & nonzero

12. Derive the control gate circuit associated with

a. TR register
b. Write control input of the memory
c. E flip flop

13. A computer uses a memory of 4 Giga words with eight bits in each word. It has the
following registers: PC, AR, TR (32 bits each), and AC, DR, IR (eight bits each). A memory-
reference instruction consists of five words: an 8-bit operation-code (one word) and a 32-
bit address (in the next four words). All operands are eight bits. There is no indirect bit.
a. Draw a block diagram of the computer showing the memory and registers as in
Fig. 5-3. (Do not use a common bus).
b. Draw a diagram showing the placement in memory of a typical five-word
instruction and the corresponding 8-bit operand.
c. List the sequence of microoperations for fetching a memory reference instruction
and then placing the operand in DR. Start from timing signal T0.