Microprocessor and Microcontroller

EG 2206 EE
Total: 5 hours /week
Year: II Lecture: 3 hours/week Semester: II Tutorial: hours/week
Practical: hours/week Lab: 2 hours/week

UNIT 1: Intel 8085 Microprocessor: Introduction [8]

1.1 Need for Microprocessors and its evolution
Need of Microprocessors is that these are general purpose electronic processing devices which
can be programmed to execute a number of tasks. So microprocessor offer reprogrammability,
includes all the necessary components of processing in single chip (System in Chip), processor
made up of discrete components (gates, registers) are slower and consumes large space on
printed board circuit (PCB). So Microprocessor replaces most of demerits of processing system
before it. These are used in personal computers as well as a number of other embedded
products.

Microprocessors were categorized into five generations: first, second, third, fourth, and fifth
generations. Their characteristics are described below:
First-generation
The microprocessors that were introduced in 1971 to 1972 were referred to as the first
generation systems. First-generation microprocessors processed their instructions serially—
they fetched the instruction, decoded it, then executed it. When an instruction was completed,
the microprocessor updated the instruction pointer and fetched the next instruction, performing
this sequential drill for each instruction in turn.
Second generation
By the late 1970s, enough transistors were available on the IC to usher in the second generation
of microprocessor sophistication: 16-bit arithmetic and pipelined instruction processing.
Motorola’s MC68000 microprocessor, introduced in 1979, is an example. Another example is
Intel’s 8080. This generation is defined by overlapped fetch, decode, and execute steps
(Computer 1996). As the first instruction is processed in the execution unit, the second
instruction is decoded and the third instruction is fetched.
The distinction between the first and second generation devices was primarily the use of newer
semiconductor technology to fabricate the chips. This new technology resulted in a five-fold
increase in instruction, execution, speed, and higher chip densities.
Third generation
The third generation, introduced in 1978, was represented by Intel’s 8086 and the Zilog Z8000,
which were 16-bit processors with minicomputer-like performance. The third generation came
about as IC transistor counts approached 250,000.
Motorola’s MC68020, for example, incorporated an on-chip cache for the first time and the
depth of the pipeline increased to five or more stages. This generation of microprocessors was
different from the previous ones in that all major workstation manufacturers began developing
their own RISC-based microprocessor architectures (Computer, 1996).
Fourth generation
As the workstation companies converted from commercial microprocessors to in-house
designs, microprocessors entered their fourth generation with designs surpassing a million
transistors.

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Leading-edge microprocessors such as Intel’s 80960CA and Motorola’s 88100 could issue and
retire more than one instruction per clock cycle.
Fifth generation
Microprocessors in their fifth generation, employed decoupled super scalar processing, and
their design soon surpassed 10 million transistors. In this generation, PCs are a low-margin,
high-volume-business dominated by a single microprocessor

1.2 Intel 8085 Hardware Architecture ,Pin description ,Internal Registers – Arithmetic
and Logic Unit, Control Unit
i. Intel 8085 Hardware Architecture

ii. Pin Description of 8085 Microprocessor

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iii. Internal Register

The 8085/8080A-programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and
the program counter. They are described briefly as follows.
The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified
as B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs - BC,
DE, and HL - to perform some 16-bit operations. The programmer can use these registers
to store or copy data into the registers by using
data copy instructions.
iv. Arithmetic and Logical Unit (ALU)
The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’,
‘AND’, ‘OR’, etc. Uses data from memory and from Accumulator to perform arithmetic.
Always stores result of operation in Accumulator.
v. Timing and Control Unit
Generates signals within uP to carry out the instruction, which has been decoded. In reality
causes certain connections between blocks of the uP to be opened or closed, so that data
goes where it is required, and so that ALU operations occur.

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It controls all the operations of microprocessor and peripheral devices. Depending upon
the machine cycles received from Instruction Decoder, it generates 12 control signals.

vi. Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This
register is used to store 8-bit data and to perform arithmetic and logical operations. The
result of an operation is stored in the accumulator. The accumulator is also identified as
register A.
vii. Flags
The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called, Zero(Z),
Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the
Table and their bit positions in the flag register are shown in the Figure below. The most
commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test
data conditions. The flags of 8085 is shown in 8bit format in below.

Figure: Flags of 8085

viii. Program Counter (PC)
This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the
next byte is to be fetched. When a byte (machine code) is being fetched, the program
counter is incremented by one to point to the next memory location
ix. Stack Pointer (SP)
The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by
loading 16-bit address in the stack pointer. The stack concept is explained in the chapter
"Stack and Subroutines."
x. Instruction Register/Decoder
Temporary store for the current instruction of a program. Latest instruction sent here
from memory prior to execution. Decoder then takes instruction and ‘decodes’ or
interprets the instruction. Decoded instruction then passed to next stage.
xi. Temporary Register
It is an 8-bit register. It is used to store temporary 8-bit operand from general purpose
register. It is also used to store intermediate results
xii. Increment/Decrement Register
This register is used to increment or decrement the value of Stack Pointer. During PUSH
operation, the value of Stack Pointer is incremented. During POP operation, the value of
Stack Pointer is decremented.

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xiii. Address Latch

It is group of 8 buffers. The upper-byte of 16-bit address is stored in this latch. And then
it is made available to the peripheral devices.
xiv. Address/Data Latch
The lower-byte of address and 8-bit of data are multiplexed. It holds either lower-byte of
address or 8-bits of data. This is decided by ALE (Address Latch Enable) signal.
 If ALE = 1 then Address/Data Latch contains lower-byte of address.
 If ALE = 0 then It contains 8-bit data.
xv. Serial I/O Controller
It is used to convert serial data into parallel and parallel data into serial.
 Microprocessor works with 8-bit parallel data.
 Serial I/O devices works with serial transfer of data. Therefore, this unit is the
interface between microprocessor and serial I/O devices.
xvi. Interrupt Controller
It is used to handle the interrupts. There are 5 interrupt signals in 8085: TRAP, RST 7.5,
RST 6.5, RST 5.5 and INTR.

1.3 Instruction word size, Addressing modes, Instruction Set, Assembly Language
Programming, Stacks and Subroutines, Timing Diagrams.

i. Instruction word size

An instruction is a command to the microprocessor to perform a given task on a
specified data. Each instruction has two parts: one is task to be performed, called the
operation code (opcode), and the second is the data to be operated on, called the operand.
The operand (or data) can be specified in various ways. It may include 8-bit (or 16-bit )
data, an internal register, a memory location, or 8-bit (or 16-bit) address. In some
instructions, the operand is implicit.
Instruction word size
The 8085 instruction set is classified into the following three groups according to
word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.
However, instructions are commonly referred to in terms of bytes rather than words.

One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s)
are internal register and are coded into the instruction.

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These instructions are 1-byte instructions performing three different tasks. In the first
instruction, both operand registers are specified. In the second instruction, the operand
B is specified and the accumulator is assumed. Similarly, in the third instruction, the
accumulator is assumed to be the implicit operand. These instructions are stored in 8-
bit binary format in memory; each requires one memory location.

Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second
byte specifies the operand. Source operand is a data byte immediately following the
opcode. For example:

Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two
bytes specify the 16-bit address. Note that the second byte is the low-order address
and the third byte is the high-order address.
opcode + data byte + data byte, for example:

This instruction would require three memory locations to store in memory.

Three byte instructions - opcode + data byte + data byte
Examples: LXI H,0520H and LDA 2134H.

ii. Addressing modes

The instructions MOV B, A or MVI A, 82H are to copy data from a source into a
destination. In these instructions the source can be a register, an input port, or an 8-bit

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number (00H to FFH). Similarly, a destination can be a register or an output port. The
sources and destination are operands. The various formats for specifying operands are
called the ADDRESSING MODES. For 8085, they are:
a. Immediate addressing.
Data is present in the instruction. Load the immediate data to the destination
provided.
Example: MVI R,data
b. Register addressing
Data is provided through the registers.
Example: MOV Rd, Rs
c. Direct addressing
Used to accept data from outside devices to store in the accumulator or send the data
stored in the accumulator to the outside device. Accept the data from the port 00H
and store them into the accumulator or Send the data from the accumulator to the
port 01H.
Example: IN 00H or OUT 01H
d. Indirect Addressing
This means that the Effective Address is calculated by the processor. And the
contents of the address (and the one following) is used to form a second address.
The second address is where the data is stored. Note that this requires several
memory accesses; two accesses to retrieve the 16-bit address and a further access
(or accesses) to retrieve the data which is to be loaded into the register.

iii. Instruction Set

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instructions, called the instruction set, determines what
functions the microprocessor can perform. These instructions can be classified into the
following five functional categories: data transfer (copy) operations, arithmetic operations,
logical operations, branching operations, and machine-control operations.

Data Transfer (Copy) Operations

This group of instructions copy data from a location called a source to another
location called a destination, without modifying the contents of the source. In
technical manuals, the term data transfer is used for this copying function. However,
the term transfer is misleading; it creates the impression that the contents of the
source are destroyed when, in fact, the contents are retained without any modification.

Arithmetic Operations
These instructions perform arithmetic operations such as addition, subtraction, increment,
and decrement.
Addition –
Any 8-bit number, or the contents of a register or the contents of a memory location
can be added to the contents of the accumulator and the sum is stored in the
accumulator. No two other 8-bit registers can be added directly (e.g., the contents
of register B cannot be added directly to the contents of the register C). The
instruction DAD is an exception; it adds 16-bit data directly in register pairs.

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Subtraction –
Any 8-bit number, or the contents of a register, or the contents of a memory location
can be subtracted from the contents of the accumulator and the results stored in the
accumulator. The subtraction is performed in 2's compliment, and the results if
negative, are expressed in 2's complement. No two other registers can be subtracted
directly.
Increment/Decrement –
The 8-bit contents of a register or a memory location can b incremented or
decrement by 1. Similarly, the 16-bit contents of a register pair (such as BC) can be
incremented or decrement by 1. These increment and decrement operations differ
from addition and subtraction in an important way; i.e., they can be performed in
any one of the registers or in a memory location.

Logical Operations
These instructions perform various logical operations with the contents of the accumulator.
AND, OR Exclusive-OR –
Any 8-bit number, or the contents of a register, or of
a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of
the accumulator. The results are stored in the accumulator.
Rotate-
Each bit in the accumulator can be shifted either left or right to the next position.
Compare-
Any 8-bit number, or the contents of a register, or a memory location can
be compared for equality, greater than, or less than, with the contents of the accumulator.
Complement –
The contents of the accumulator can be complemented. All 0s are replaced by 1s and all 1s
are replaced by 0s.

Branching Operations
This group of instructions alters the sequence of program execution either conditionally or
unconditionally.
Jump - Conditional jumps are an important aspect of the decision-making process in the
programming. These instructions test for a certain conditions (e.g., Zero or Carry flag) and
alter the program sequence when the condition is met. In addition, the instruction set
includes an instruction called unconditional jump.
Call, Return, and Restart - These instructions change the sequence of a program either by
calling a subroutine or returning from a subroutine. The conditional Call and
Return instructions also can test condition flags.

Machine Control Operations

These instructions control machine functions such as Halt, Interrupt, or do nothing.

iv. Assembly Language Programming

Assembly Level programs are low level programs which are written in Machine Level
codes called instruction sets. Assembly programs are easy to understand than Machine

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Level program but it need the assembler for creating machine level code from the assembly
programs.

Here are some examples of assembly programming:

Write an assembly program to add two numbers
MVI D, 8BH
MVI C, 6FH
MOV A, C
ADD D
OUT PORT1
HLT
Write an assembly program to multiply a number by 8
MVI A, 30H
RRC
RRC
RRC
OUT PORT1
HLT

v. Stacks and Subroutines

Stack
The stack is an area of memory identified by the programmer for
temporary storage of information. The stack is a LIFO structure.
Last In First Out. The stack normally grows backwards into
memory. In other words, the programmer defines the bottom of
the stack and the stack grows up into reducing address range.

Given that the stack grows backwards into memory, it is

customary to place the bottom of the stack at the end of memory
to keep it as far away from user programs as possible.

Information is saved on the stack by PUSHing it on. It is retrieved from the stack by POPing
it off.

Subroutines
A subroutine is a group of instructions that will be used repeatedly in different locations of
the program, rather than repeat the same instructions several times they can be grouped
into a subrouting that is called from the different locaitons. In asembly language , a
subroutin can exist anywhere in the code. However it is customary to place subroutines
separately from the main program.
The 8085 has two instructiions for dealing with subroutines: the CALL instructions is used
to redirect program execution to the subroutine and the RTE instruction is used to return
the execution to the calling routine. In Assembly Language data is passed to a subroutine
through registers.

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vi. Timing Diagrams

Timing diagram is the display of initiation of read/write and transfer of data operations
under the control of 3-status signals IO / M , S1, and S0. A machine may execute one
instruction in as many as 3-machine cycles while the other machine can take only one
machine cycle to execute the same instruction. Thus, the machine that has taken only one
machine cycle is efficient than the one taking 3-machine cycle. Each machine cycle is
composed of many clock cycle.

Instruction Cycle: The time taken by the processor to complete the execution of an
instruction. An instruction cycle consists of one to six machine cycles.
Machine Cycle: The time required to complete one operation; accessing either the memory
or I/O device. A machine cycle consists of three to six T-states.
T-State: Time corresponding to one clock period. It is the basic unit to calculate execution
of instructions or programs in a processor.

Fig. Machine cycle showing clock periods

Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC)

Fig. 3.2 (a) Processor cycle

UNIT 2: Intel 8085 Interrupts and DMA: [8]

2.1 8085 Interrupts – Software and Hardware Interrupts, 8259 Programmable Interrupt
Controller
Interrupt Structure:
Interrupt is the mechanism by which the processor is made to transfer control from its current
program execution to another program having higher priority. The interrupt signal may be given to
the processor by any external peripheral device. The program or the routine that is executed upon

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interrupt is called interrupt service routine (ISR). After execution of ISR, the processor must return to
the interrupted program. Key features in the interrupt structure of any microprocessor are as follows:
i. Number and types of interrupt signals available.
ii. The address of the memory where the ISR is located for a particular interrupt signal. This
address is called interrupt vector address (IVA).
iii. Masking and unmasking feature of the interrupt signals.
iv. Priority among the interrupts.
v. Timing of the interrupt signals.
vi. Handling and storing of information about the interrupt program (status information).
Types of Interrupts:
Interrupts are classified based on their maskability, IVA and source. They are classified as:

i. Vectored and Non-Vectored Interrupts

 Vectored interrupts require the IVA to be supplied by the external device that gives
the interrupt signal. This technique is vectoring, is implemented in number of ways.
 Non-vectored interrupts have fixed IVA for ISRs of different interrupt signals.
ii. Maskable and Non-Maskable Interrupts
 Maskable interrupts are interrupts that can be blocked. Masking can be done by
software or hardware means.
 Non-maskable interrupts are interrupts that are always recognized; the corresponding
ISRs are executed.
iii. Software and Hardware Interrupts
 Software interrupts are special instructions, after execution transfer the control to
predefined ISR.
Hardware interrupts are signals given to the processor, for recognition as an interrupt
and execution of the corresponding ISR.
Interrupt Handling Procedure: The following sequence of operations takes place when an interrupt
signal is recognized:
 Save the PC content and information about current state (flags, registers etc) in the stack.
 Load PC with the beginning address of an ISR and start to execute it.
 Finish ISR when the return instruction is executed.
 Return to the point in the interrupted program where execution was interrupted.

Interrupt Sources and Vector Addresses in 8085:

a. Software Interrupts:
8085 instruction set includes eight software interrupt instructions called Restart (RST) instructions.
These are one byte instructions that make the processor execute a subroutine at predefined
locations. Instructions and their vector addresses are given in Table 6.
Table 6 Software interrupts and their vector addresses

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The software interrupts can be treated as CALL instructions with default call locations. The concept
of priority does not apply to software interrupts as they are inserted into the program as instructions
by the programmer and executed by the processor when the respective program lines are read.

b. Hardware Interrupts and Priorities:

8085 have five hardware interrupts – INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP. Their IVA and
priorities are given in Table 7.
Table 7 Hardware interrupts of 8085

c. 8259 Programmable Interrupt Controller

INTEL 8259A Programmable Interrupt Controller
The 8259A is a programmable interrupt controller designed to work with Intel microprocessor
8080 A, 8085, 8086, 8088. The 8259 A interrupt controller can
1) Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the
processor in place of one INTR/INT pin.
2) Vector an interrupt request anywhere in the memory map. However, all the eight interrupt are
spaced at the interval of either four or eight location. This eliminates the major drawback, 8085
interrupt, in which all interrupts are vectored to memory location on page 00H.
3) Resolve eight levels of interrupt priorities in a variety of modes.
4) Mask each interrupt request individually.
5) Read the status of pending interrupts, in service interrupts, and masked interrupts.
6) Be set up to accept either the level triggered or edge triggered interrupt request.
7) Mine 8259 as can be cascade in a master slave configuration to handle 64 interrupt inputs.

Features:

 8 levels of interrupts.
 Can be cascaded in master-slave configuration to handle 64 levels of interrupts.
 Internal priority resolver.
 Fixed priority mode and rotating priority mode.
 Individually maskable interrupts.

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 Modes and masks can be changed dynamically.

 Accepts IRQ, determines priority, checks whether incoming priority > current level being
serviced, issues interrupt signal.
 In 8085 mode, provides 3 byte CALL instruction. In 8086 mode, provides 8 bit vector
number.
 Polled and vectored mode.
 Starting address of ISR or vector number is programmable.
 No clock required.

The 8259 A is contained in a 28-element in line package that requires only a compatible with 8259.
The main difference between the two is that the 8259 A can be used with Intel 8086/8088
processor. It also induces additional features such as level triggered mode, buffered mode and
automatic end of interrupt mode. The pin diagram and interval block diagram is shown below:

D0-D7 Bi-directional, tristated, buffered data lines. Connected to data bus directly or
through buffers
RD-bar Active low read control
WR-bar Active low write control
A0 Address input line, used to select control register
CS-bar Active low chip select

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CAS0-2 Bi-directional, 3 bit cascade lines. In master mode, PIC places slave ID no. on
these lines. In slave mode, the PIC reads slave ID no. from master on these lines.
It may be regarded as slave-select.
SP-bar / Slave program / enable. In non-buffered mode, it is SP-bar input, used to
EN-bar distinguish master/slave PIC. In buffered mode, it is output line used to enable
buffers
INT Interrupt line, connected to INTR of microprocessor
INTA-bar Interrupt ack, received active low from microprocessor
IR0-7 Asynchronous IRQ input lines, generated by peripherals.

Interrupt sequence (single PIC)

1. One or more of the IR lines goes high.
2. Corresponding IRR bit is set.
3. 8259 evaluates the request and sends INT to CPU.
4. CPU sends INTA-bar.
5. Highest priority ISR is set. IRR is reset.
6. 8259 releases CALL instruction on data bus.
7. CALL causes CPU to initiate two more INTA-bar's.
8. 8259 releases the subroutine address, first lowbyte then highbyte.
9. ISR bit is reset depending on mode.

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2.2 Data Transfer Techniques – Synchronous, Asynchronous and Direct Memory Access
(DMA) and 8237 DMA Controller- 8253 Programmable Interval Timer.

i. A wide variety of IO devices having wide range of speed and other different characteristics
are available .A slow responding IO device cannot transfer data when microprocessor issues
instruction for it as it takes some time to get Transfers ratesready. Of peripherals is usually
slower than the transfer rates of CPU. Operating modes of peripheral are different from each
other and each must be controlled so as not to disturb the operation of each other peripherals
connected to CPU. Different types of data transfer techniques are available which can be
broadly divided into two categories:-
 MICROPROCESSOR CONTROLLED
 DEVICE CONTROLLED
 Program data transfer scheme
 Synchronous Data Transfer
 Asynchronous mode of transfer
 Interrupt driven IO data transfer
 DMA Data Transfer
ii. Synchronous Data Transfer:- Synchronous means „at the same time‟. The device Which
sends data and the device which received data are synchronized with the same clock. When
the CPU and IO devices match in speed, Synchronous Data Transfer technique is employed.
The data transfer with IO devices is performed by executing IN and OUT instruction. The IN
instruction is used to read data from an input device or input port. The OUT instruction is
used to sends data from CPU to the output device or output port. As the CPU and the IO
devices match in speed, the I/O device is ready to transfer data when IN or OUT instruction is
executes. The status of the I/O device, whether it is ready or not, is not examined before the
data is transferred.
iii. Asynchronous mode of transfer:- Asynchronous means „at irregular intervals‟. In this
method data transfer is not based on predetermined timing pattern. This technique of data
transfer is used when the speed of an I/O device does not match the speed of the
microprocessor. In this technique the status of the I/O device i.e. whether the device is ready
or not, is checked by the microprocessor before the data are transferred. The microprocessor
initiates the I/O device to get ready and then continuously checks the status of I/O device till
the I/O device becomes ready to transfer data. When I/O device becomes ready, the
microprocessor executes instruction to transfer data.
This mode of data transfer is also called handshaking mode of data transfer because some
signals are exchanged between microprocessor and I/O devices before the actual data
transfer takes place. Such signals are called handshake signals. The microprocessor is too
busy. CPU is wasting time while checking the flag instead of doing some useful work.
The problem with programmed I/O is that CPU has to wait along time for the I/O device to be
ready for reception or transmission of data .The CPU while waiting, must repeatedly
interrogate the status of the I/O device. As a result the level of the performance of the entire
system is severely degraded.
iv. DMA Data Transfer: The transfer of data between the mass storage device and a system
memory is often limited by the speed of microprocessor. Removing the microprocessor
during such a transfer and letting the peripheral manage the transfer to or from memory

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would improve the speed of transfer and hence will make the system more efficient. This
transfer technique is called DMA Data Transfer. During DMA transfer microprocessor is idle,
so it has no longer control on the system buses. A DMA Controller takes over the buses and
manage the transfer directly between the peripheral and the memory It is fastest scheme
then Programmed Data Transfer Scheme and the microprocessor regains the control of buses
after data transfer.
v. 8237 DMA Controller:-
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest
rate. It allows the device to transfer the data directly to/from memory without any
interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data
transfer is initiated only after receiving HLDA signal from the CPU.

Following is the sequence of operations performed by a DMA −

 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU leaves the control over bus and acknowledges the HOLD request through
HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations
over buses between the CPU, memory, and I/O devices.

Features of 8257
Here is a list of some of the prominent features of 8257 −

 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It generates MARK signal to the peripheral device that 128 bytes have been
transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.

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Figure: 8257 Pin Description

DRQ0−DRQ3

These are the four individual channel DMA request inputs, which are used by the
peripheral devices for using DMA services. When the fixed priority mode is selected,
then DRQ0 has the highest priority and DRQ3 has the lowest priority among them.

DACKo − DACK3

These are the active-low DMA acknowledge lines, which updates the requesting
peripheral about the status of their request by the CPU. These lines can also act as strobe
lines for the requesting devices.

Do − D 7

These are bidirectional, data lines which are used to interface the system bus with the
internal data bus of DMA controller. In the Slave mode, it carries command words to
8257 and status word from 8257. In the master mode, these lines are used to send higher
byte of the generated address to the latch. This address is further latched using ADSTB
signal.

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IOR

It is an active-low bidirectional tri-state input line, which is used by the CPU to read
internal registers of 8257 in the Slave mode. In the master mode, it is used to read data
from the peripheral devices during a memory write cycle.

IOW

It is an active low bi-direction tri-state line, which is used to load the contents of the data
bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or
terminal count register. In the master mode, it is used to load the data to the peripheral
devices during DMA memory read cycle.

CLK

It is a clock frequency signal which is required for the internal operation of 8257.

RESET

This signal is used to RESET the DMA controller by disabling all the DMA channels.

Ao - A3

These are the four least significant address lines. In the slave mode, they act as an input,
which selects one of the registers to be read or written. In the master mode, they are the
four least significant memory address output lines generated by 8257.

CS

It is an active-low chip select line. In the Slave mode, it enables the read/write operations
to/from 8257. In the master mode, it disables the read/write operations to/from 8257.

A4 - A7

These are the higher nibble of the lower byte address generated by DMA in the master
mode.

READY

It is an active-high asynchronous input signal, which makes DMA ready by inserting wait
states.

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HRQ

This signal is used to receive the hold request signal from the output device. In the slave
mode, it is connected with a DRQ input line 8257. In Master mode, it is connected with
HOLD input of the CPU.

HLDA

It is the hold acknowledgement signal which indicates the DMA controller that the bus
has been granted to the requesting peripheral by the CPU when it is set to 1.

MEMR

It is the low memory read signal, which is used to read the data from the addressed
memory locations during DMA read cycles.

MEMW

It is the active-low three state signal which is used to write the data to the addressed
memory location during DMA write operation.

ADST

This signal is used to convert the higher byte of the memory address generated by the
DMA controller into the latches.

AEN

This signal is used to disable the address bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present
peripheral devices.

MARK

The mark will be activated after each 128 cycles or integral multiples of it from the
beginning. It indicates the current DMA cycle is the 128th cycle since the previous
MARK output to the selected peripheral device.

Vcc

It is the power signal which is required for the operation of the circuit.

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vi. 8253 Programmable Interval Timer:-

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for
microprocessors to perform timing and counting functions using three 16-bit registers.
Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate
a counter, a 16-bit count is loaded in its register. On command, it begins to decrement the
count until it reaches 0, then it generates a pulse that can be used to interrupt the CPU.
Features of 8253
Its operating frequency is 0 - 2.6 MHz
It uses N-MOS technology
Read-Back command is not available
Reads and writes of the same counter cannot be interleaved.
It has three independent 16-bit down counters.
It can handle inputs from DC to 10 MHz.
These three counters can be programmed for either binary or BCD count.
It is compatible with almost all microprocessors.

In the above figure, there are three counters, a data bus buffer, Read/Write control logic,
and a control register. Each counter has two input signals - CLOCK & GATE, and one
output signal - OUT.

Data Bus Buffer

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It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the
system data bus. It has three basic functions −

 Programming the modes of 8253/54.

 Loading the count registers.
 Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral
I/O mode, the RD and WR signals are connected to IOR and IOW, respectively. In the
memorymapped I/O mode, these are connected to MEMR and MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and
CS is tied to a decoded address. The control word register and counters are selected
according to the signals on lines A0 & A1.

A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection

Control Word Register

This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command
word, which specifies the counter to be used, its mode, and either a read or write
operation. Following table shows the result for various control inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation

Counters

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Each counter consists of a single, 16 bit-down counter, which can be operated in either
binary or BCD. Its input and output is configured by the selection of modes stored in the
control word register. The programmer can read the contents of any of the three counters
without disturbing the actual count in process.

UNIT 3: Memory & I/O Interfacing: [9]

3.1 Types of memory, Memory mapping and addressing, Concept of I/O map

The 8085 family can address 64K bytes of memory which is used for both code and data space.
Memory is accessed via 20 pins. 8 address high pins and 8 pins that are used both for the 8 address
low signals during the address setup phase and for the 8 data signals during the data transfer phase.
4 pins are used for control. A READY input line allows memory or I/O access to slow down the
data transfer. This allows slow memory or I/O hardware to be easily interfaced.
And a HOLD line allows peripheral hardware to take over the memory bus allowing DMA
transfers to be implemented.
a. Types of Memory: RAM & ROM (PROM,EPROM)

The programs and data that are executed by the microprocessor have to be stored in ROM/EPROM
and RAM, which are basically semiconductor memory chips. The programs and data that are
stored in ROM/EPROM are not erased even when power supply to the chip is removed. Hence,
they are called non-volatile memory. They can be used to store permanent programs.

In a RAM, stored programs and data are erased when the power supply to the chip is removed.
Hence, RAM is called volatile memory. RAM can be used to store programs and data that include,
programs written during software development for a microprocessor based system, program
written when one is learning assembly language programming and data enter while testing these
programs.

b. Memory Mapping and Addressing

The interfacing between the microprocessor and the memory device by connecting the data and address
bus is called memory mapping.
Memory mapping is a vitally important concept in computing because most devices are
interfaced to the microprocessor via a range of memory addresses. For example, the parallel to
serial conversion chip (UART) in a computer system has a number of internal registers. One of
the registers in the chip contains data that tells the device how to perform its function and
another register is used for incoming data and yet another for outgoing data. All these registers
are mapped, just as if they were normal system memory. The microprocessor communicates
with them as though they are normal memory locations, when in reality they are often part of
another special purpose chip or system.

The same memory mapping technique can be used to interface disk-drive controllers and
graphics controller cards to a microprocessor within a computer system. A range of memory
locations or registers in these devices are mapped into system memory as if they are normal
memory chips. The microprocessor moves data to and from them as though they are normal

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memory locations. The devices that are mapped onto the system use the data supplied by the
microprocessor to do their respective tasks. For example, the graphics controller card uses the
data provided by the microprocessor to create an image on a screen.

A typical example of memory mapping is as below.

Figure: memory mapping example

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Memory Addressing:
Memory address decoding is nothing but to assign an address for each location in the memory
chip. The data stored in the memory is accessed by specifying its address. Memory address can be
decoded in two ways:
i) Absolute or Fully decoding and ii) Linear Select or Partial decoding

There are many advantages in absolute address decoding.

i) Each memory location has only one address, there is no duplication in the address
ii) Memory can be placed contiguously in the address space of the microprocessor
iii) Future expansion can be made easily without disturbing the existing circuitry

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Fig. Memory Address

Fig. : The complete interfacing diagram

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Concept of I/O Mapping:

Input and output devices, which are interfaced with 8085, are essential in any microprocessor
based system. They can be interfaced using two schemes: I/O mapped I/O and memory-mapped
I/O. In the I/O mapped I/O scheme, the I/O devices are treated differently from memory. In the
memory-mapped I/O scheme, each I/O device is assumed to be a memory location.

PERIPHERAL MAPPED I/O INTERFACING

In this method, the I/O devices are treated differently from memory chips. The control
signals I/O read ( IOR ) and I/O write ( IOW), which are derived from the IO/M, RD and
WR signals of the 8085, are used to activate input and output devices, respectively.
Generation of these control signals is shown in Fig. 20. Table 11 shows the status of IO/M,
RD and WR signals during I/O read and I/O write operation.

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Figure:
IN instruction is used to access input device and OUT instruction is used to access output
device. Each I/O device is identified by a unique 8-bit address assigned to it. Since the
control signals used to access input and output devices are different, and all I/O device use
8-bit address, a maximum of 256 (2^8) input devices and 256 output devices can be
interfaced with 8085.

Ex: Interface an 8-bit DIP switch with the 8085 such that the address assigned to the DIP
switch if F0H.
IN instruction is used to get data from DIP switch and store it in accumulator. Steps
involved in the execution of this instruction are:
i. Address F0H is placed in the lines A0 – A7 and a copy of it in lines A8 – A15.
ii. The IOR signal is activated ( IOR = 0), which makes the selected input device to
place its data in the data bus.
iii. The data in the data bus is read and store in the accumulator.

Fig. shows the interfacing of DIP switch.

A0 – A7 lines are connected to a NAND gate decoder such that the output of NAND gate is
0. The output of NAND gate is ORed with the IOR signal and the output of OR gate is
connected to 1G and 2G of the 74LS244. When 74LS244 is enabled, data from the DIP
switch is placed on the data bus of the 8085. The 8085 read data and store in the
accumulator. Thus data from DIP switch is transferred to the accumulator.

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Fig. interfacing of 8-bit DIP switch with 8085

3.2 Types – I/O decode logic – Interfacing key switches and LEDs – 8279
Keyboard/Display Interface - 8255 Programmable Peripheral Interface –
Concept of Serial Communication – 8251 USART – RS232C Interface.

I/O decode logic

Interfacing I/O Using Decoders

Figure: Decode logic for a Dip-Switch Input Port

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First Step is to decode the address bus using 3x8 Decoder and 4-input NAND gate. A0 to A2 are
used as input and remaining A3 to A7 are used to enable decoder.
Second step is to decode address with appropriate control signal (IOR’/IOW’) output will generate
select pulse.
Third step is to use this pulse to enable I/O port (pulse enables LED latch with the output port
address F8H similarly input buffer is enable with address FAH).

Interfacing key switches and LEDs

Figure : 8085-8255 interfacing with Key Switch (Key Board)

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Figure : 8085-8255 interfacing with LED’s

8279 Keyboard/Display Interface

The INTEL 8279 is specially developed for interfacing keyboard and display devices to
8085/8086/8088 microprocessor based system. The important features of 8279 are,
• Simultaneous keyboard and display operations.
• Scanned keyboard mode.

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• Scanned sensor mode.

• 8-character keyboard FIFO.
• 1 6-character display.
• Right or left entry 1 6-byte display RAM.
• Programmable scan timing.
Functional Block diagram of 8279 is as follows:

The four major sections of 8279 are keyboard, scan, display and CPU interface.
Keyboard section:
• The keyboard section consists of eight return lines RL0 – RL7 that can be used to form
the columns of a keyboard matrix.
• It has two additional input : shift and control/strobe. The keys are automatically
debounced.
• The two operating modes of keyboard section are 2-key lockout and N-key rollover.
• In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is
recognized.
• In the N-key rollover mode simultaneous keys are recognized and their codes are stored
in FIFO.
• The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.
• The FIFO can store eight key codes in the scan keyboard mode. The status of the shift
key and control key are also stored along with key code. The 8279 generate an interrupt
signal when there is an entry in FIFO. The format of key code entry in FIFO for scan
keyboard mode is,

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• In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in
FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as
high to interrupt the processor.
Display section:
• The display section has eight output lines divided into two groups A0-A3 and B0-B3.
• The output lines can be used either as a single group of eight lines or as two groups of
four lines, in conjunction with the scan lines for a multiplexed display.
• The output lines are connected to the anodes through driver transistor in case of
common cathode 7-segment LEDs.
• The cathodes are connected to scan lines through driver transistors.
• The display can be blanked by BD (low) line.
• The display section consists of 16 x 8 display RAM. The CPU can read from or write
into any location of the display RAM.
Scan section:
• The scan section has a scan counter and four scan lines, SL0 to SL3.
• In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
• In encoded scan mode, the output of scan lines will be binary count, and so an external
decoder should be used to convert the binary count to decoded output.
• The scan lines are common for keyboard and display.
• The scan lines are used to form the rows of a matrix keyboard and also connected to
digit drivers of a multiplexed display, to turn ON/OFF.
CPU interface section:
• The CPU interface section takes care of data transfer between 8279 and the processor.
• This section has eight bidirectional data lines DB0 to DB7 for data transfer between
8279 and CPU.
• It requires two internal address A =0 for selecting data buffer and A = 1 for selecting
control register of8279.
• The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to
8279.
• It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
• The 8279 require an internal clock frequency of 100 kHz. This can be obtained by
dividing the input clock by an internal prescaler.
• The RESET signal sets the 8279 in 16-character display with two -key lockout
keyboard modes.

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Programming the 8279:

• The 8279 can be programmed to perform various functions through eight command
words.

8255- Programmable Peripheral Interface:

The 8255A is a general purpose programmable I/O device designed for use with Intel
microprocessors. It consists of three 8-bit bidirectional I/O ports (24I/O lines) that can be
configured to meet different system I/O needs. The three ports are PORT A, PORT B & PORT C.
Port A contains one 8-bit output latch/buffer and one 8-bit input buffer. Port B is same as PORT
A or PORT B. However, PORT C can be split into two parts PORT C lower (PC0-PC3) and PORT
C upper (PC7-PC4) by the control word. The three ports are divided in two groups Group A (PORT
A and upper PORT C) Group B (PORT B and lower PORT C).

The two groups can be programmed in three different modes. In the first mode (mode 0), each
group may be programmed in either input mode or output mode (PORT A, PORT B, PORT C
lower, PORT C upper). In mode 1, the second’s mode, each group may be programmed to have 8-
lines of input or output (PORT A or PORT B) of the remaining 4-lines (PORT C lower or PORT
C upper) 3-lines are used for hand shaking and interrupt control signals. The third mode of
operation (mode 2) is a bidirectional bus mode which uses 8-line (PORT A only for a bidirectional
bus and five lines (PORT C upper 4 lines and borrowing one from other group) for handshaking.
The 8255 is contained in a 40-pin package, whose pin out is shown below:

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Functional Description: This support chip is a general purpose I/O component to interface
peripheral equipment to the microcomputer system bus. It is programmed by the system software
so that normally no external logic is necessary to interface peripheral devices or structures.

Data Bus Buffer:

It is a tri-state 8-bit buffer used to interface the chip to the system data bus. Data is transmitted or
received by the buffer upon execution of input or output instructions by the CPU. Control words
and status information are also transferred through the data bus buffer. The data lines are connected
to BDB of MPU.
Read/Write and logic control: The function of this block is to control the internal operation of the
device and to control the transfer of data and control or status words. It accepts inputs from the
CPU address and control buses and in turn issues command to both the control groups.
CS Chip Select:
A low on this input selects the chip and enables the communication between the 8255 A & the
CPU. It is connected to the output of address decode circuitry to select the device when it (Read).
A low on this input enables the 8255 to send the data or status information to the CPU on the data
bus.

BSR Mode:
BSR means bit set reset mode for Port C.BSR mode mode is selected when bit D7=0 of the control word
register.
See lecture 14328 page 46

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Concept of Serial Communication:–

Serial communication is the process of sending/receiving data in one bit at a time.

Parallel communication is the process of sending/receiving multiple data bits at a

time through parallel channels.

Serial communication is used for all long-haul

communication and most computer networks, where the
cost of cable and synchronization difficulties make
parallel communication impractical. Serial computer
buses are becoming more common even at shorter
distances, as improved signal integrity and transmission
speeds in newer serial technologies have begun to
outweigh the parallel bus's advantage of simplicity (no
need for serializer and deserializer, or SerDes) and to outstrip its disadvantages (clock skew,
interconnect density).

8251 USART :–

8251 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER

(USART)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial
data communication. As a peripheral device of a microcomputer system, the 8251 receives

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parallel data from the CPU and transmits serial data after conversion. This device also receives
serial data from the outside and transmits parallel data to the CPU after conversion.

Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver

Transmitter)

The 8251 functional configuration is programed by software. Operation between the 8251 and a
CPU is executed by program control. Table 1 shows the operation between a CPU and the
device.

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Table 1 Operation between a CPU and 8251

Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait
for write" at either internal reset or external reset. That is, the writing of a control word after
resetting will be recognized as a "mode instruction."

Items set by mode instruction are as follows:

• Synchronous/asynchronous mode

• Stop bit length (asynchronous mode)

• Character length

• Parity bit

• Baud rate factor (asynchronous mode)

• Internal/external synchronization (synchronous mode)

• Number of synchronous characters (Synchronous mode)

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The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous
mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a
function will be set because the writing of sync characters constitutes part of mode instruction.

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2) Command

Command is used for setting the operation of the 8251. It is possible to write a command
whenever necessary after writing a mode instruction and sync characters.

Items to be set by command are as follows:

• Transmit Enable/Disable

• Receive Enable/Disable

• DTR, RTS Output of data.

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• Resetting of error flag.

• Sending to break characters

• Internal resetting

• Hunt mode (synchronous mode)

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Status Word

It is possible to see the internal status of the 8251 by reading a status word. The bit configuration
of status word is shown in Fig. 5.

Pin Description

D 0 to D 7 (l/O terminal)

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This is bidirectional data bus which receive control words and transmits data from the CPU and
sends status words and received data to CPU.

RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the writing of
"mode instruction." The min. reset width is six clock inputs during the operating status of CLK.

CLK (Input terminal)

CLK signal is used to generate internal device timing. CLK signal is independent of RXC or
TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at
Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at
Asynchronous "x16" and "x64" mode.

WR (Input terminal)

This is the "active low" input terminal which receives a signal for writing transmit data and
control words from the CPU into the 8251.

RD (Input terminal)

This is the "active low" input terminal which receives a signal for reading receive data and status
words from the 8251.

C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words and status
words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high,
command word or status word will be accessed.

CS (Input terminal)

This is the "active low" input terminal which selects the 8251 at low level when the CPU
accesses. Note: The device won’t be in "standby status"; only setting CS = High.

TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent out. The
device is in "mark status" (high level) after resetting or during a status when transmit is disabled.
It is also possible to set the device in "break status" (low level) by a command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251is ready to accept a transmitted data
character. But the terminal is always at low level if CTS = high or the device was set in "TX

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disable status" by a command. Note: TXRDY status word indicates that transmit data character is
receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be
reset by the leading edge or WR signal.

TXEMPTY (Output terminal)

This is an output terminal which indicates that the 8251 has transmitted all the characters and had
no data character. In "synchronous mode," the terminal is at high level, if transmit data
characters are no longer remaining and sync characters are automatically transmitted. If the CPU
writes a data character, TXEMPTY will be reset by the leading edge of WR signal. Note : As the
transmitter is disabled by setting CTS "High" or command, data written before disable will be
sent out. Then TXD and TXEMPTY will be "High". Even if a data is written after disable, that
data is not sent out and TXE will be "High".After the transmitter is enabled, it sent out. (Refer to
Timing Chart of Transmitter Control and Flag Timing)

TXC (Input terminal)

This is a clock input signal which determines the transfer speed of transmitted data. In
"synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous
mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64
the TXC. The falling edge of TXC sifts the serial data out of the 8251.

RXD (input terminal)

This is a terminal which receives serial data.

RXRDY (Output terminal)

This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the
CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the
CPU reads a data character before the next one is received completely, the preceding data will be
lost. In such a case, an overrun error flag status word will be set.

RXC (Input terminal)

This is a clock input signal which determines the transfer speed of received data. In
"synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous
mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the
RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous mode."
this terminal is at high level, if sync characters are received and synchronized. If a status word is
read, the terminal will be reset. In "external synchronous mode, "this is an input terminal. A
"High" on this input forces the 8251 to start receiving data characters.

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In "asynchronous mode," this is an output terminal which generates "high level"output upon the
detection of a "break" character if receiver data contains a "low-level" space between the stop
bits of two continuous characters. The terminal will be reset, if RXD is at high level. After Reset
is active, the terminal will be output at low level.

DSR (Input terminal)

This is an input port for MODEM interface. The input status of the terminal can be recognized
by the CPU reading status words.

DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status of DTR by a
command.

CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling a transmit circuit.
The terminal controls data transmission if the device is set in "TX Enable" status by a command.
Data is transmitable if the terminal is at low level.

RTS (Output terminal)

This is an output port for MODEM interface. It is possible to set the status RTS by a command.

RS232C Interface:-
RS-232 – Recommended Standard 232: The RS-232 is typically connected using a DB9 connector,
which has 9 pins, out of which 5 are input, 3 are output, and one is Ground. You can still find this
so-called “Serial” port in some old PCs. In our upcoming posts, we will discuss mainly about
RS232 and USART of Microporcessor/microcontrollers.

RS-232 interface basics:

The interface is intended to operate over distances of up to 15 meters. This is because any modem
is likely to be near the terminal. Data rates are also limited. The maximum for RS-232C is 19.2 k
baud or bits per second although slower rates are often used. In theory it is possible to use any
baud rate, but there area number of standard transmission speeds used.

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Common data transmission rates

50
75
110
150
300
600
1200
2400
4800
9600
19200
38400
76800
Note: speeds up to 19200 bits per second are normally used. Above this noise that is picked up,
especially over long cable runs can introduce data errors. Where high speeds and long data runs
are required then standards such as RS422 may be used.

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RS-232 connections
The RS-232C specification does not include a description of the connector to be used. However,
the most common type found is the 25 pin D-type connector.

RS232 did not define elements such as character encoding, framing of characters, error detection
protocols etc that are essential features when data transfer takes place between a computer and a
printer. Without which it could not be adopted to transfer data between a computer and a printer.
To overcome this problem a single integrated circuit called as UART known as universal
asynchronous receiver/transmitter is used in conjunction with RS232.

RS232 signal levels

The voltage levels are one of the main items in the specification. For RS232 data signals a voltage
of between -3V and -25V represents a logic 1. The logic 0 is represented by a voltage of between
+3V and +25V. Control signals are in the "ON" state if their voltage is between +3V and +25V
and "OFF" if they are negative, i.e. between -3V and -25V.

DTE-A DTE stands for data terminal equipment is an end instrument that convert user information
into signals or reconverts the receive signal. It is a functional unit of station that serves as data
source or data sink and provides for communication control function according to the link protocol.
A male connector is used in DTE and has pin out configuration.

DCE-A DCE stands for data communication equipments. It sits between the DTE and data
transmission circuit for example modem. A DCE device uses a female connector which has holes
on the surface to hold male connector.

A minimum of three signals are required for communication between a DTE and a DCE devices.
These signals are a transmission line, a reception line and ground. These two devices communicate
with each other by handshaking. It allows a DTE and a DCE device system to acknowledge each
other before sending the data.

Handshaking is a process in which a DTE device sends a signal to a DCE device to establish a
connection between the devices before the actual transfer of data. It sets the parameters of
communication channel established between two equipment’s before normal communication over
the channel begins. It follows physical establishment of the channel and precedes normal
information transfer. Handshaking makes it possible to connect relatively heterogeneous systems
or equipment over a communication channel without the need for human intervention to set

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parameters. This same concept is used in RS232 to allow two devices communicate with each
other before the actual exchange of information.

All these terms put together gives a complete picture of a RS232 system starting from DTE to
DCE with UART, line drivers and RS232 as conjunction between them.

The Electronic Industries Association (EIA)-232 standard supports two types of connectors -- a
25-pin D-type connector (DB-25) and a 9-pin D-type connector (DB-9). The type of serial
communications used by PCs requires only 9 pins so either type of connector will work equally
well.

UNIT 4: Intel 8086 Microprocessor: [10]

4.1 Introduction-Intel 8086 Hardware – Pin description – External memory Addressing

8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in

1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to
1MB storage. It consists of powerful instruction set, which provides operations like multiplication
and division easily.
Features of 8086 vs 8085
Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.
Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.

Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.

Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue.

Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined
architecture.

I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.

Architecture of 8086
The following diagram depicts the architecture of a 8086 Microprocessor

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8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit) and BIU (Bus
Interface Unit).

EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode
and execute those instructions. Its function is to control operations on data using the instruction
decoder & ALU. EU has no direct connection with system buses as shown in the above figure, it
performs operations over data through BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

Flag Register

It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result
stored in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags
and Control Flags.

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Conditional Flags

It represents the result of the last arithmetic or logical instruction executed. Following is the list
of conditional flags −

 Carry flag − This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow
from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e.
carry given by D3 bit to D4 is AF flag. The processor uses this flag to perform binary to
BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower
order 8-bits of the result contains even number of 1’s, then the Parity Flag is set. For odd
number of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero
else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is
negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is exceeded.

Control Flags

Control flags controls the operations of the execution unit. Following is the list of control flags −

 Trap flag − It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in a single
step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for
interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests when it is set then
string bytes are accessed from the higher memory address to the lower memory address
and vice-a-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store 16bit data.
The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred
to the AX, BX, CX, and DX respectively.

 AX register − It is also known as accumulator register. It is used to store operands for

arithmetic operations.
 BX register − It is used as a base register. It is used to store the starting base address of
the memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store the loop
counter.

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 DX register − This register is used to hold I/O port address for I/O instruction.

Stack pointer register

It is a 16-bit register, which holds the address from the start of the segment to the memory
location, where a word was most recently stored on the stack.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as
writing data to the ports and the memory. EU has no direction connection with System Buses so
this is possible with the BIU. EU and BIU are connected with the Internal Bus.

It has the following functional parts −

 Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of next
instructions and stores them in the instruction queue. When EU executes instructions and
is ready for its next instruction, then it simply reads the instruction from this instruction
queue resulting in increased execution speed.
 Fetching the next instruction while the current instruction executes is called pipelining.
 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the
addresses of instructions and data in memory, which are used by the processor to access
memory locations. It also contains 1 pointer register IP, which holds the address of the
next instruction to executed by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory location in
the code segment of the memory, where the executable program is stored.
o DS − It stands for Data Segment. It consists of data used by the program andis
accessed in the data segment by an offset address or the content of other register
that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and addresses
during execution.
o ES − It stands for Extra Segment. ES is additional data segment, which is used by
the string to hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the next
instruction to be executed.

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8086 was the first 16-bit microprocessor available in 40-pin DIP (Dual Inline Package) chip. Let us now
discuss in detail the pin configuration of a 8086 Microprocessor.

Figure: Pin Description of 8086

Let us now discuss the signals in detail −

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation.

Clock signal

Clock signal is provided through Pin-19. It provides timing to the processor for operations. Its
frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus

AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16-bit address
and after that it carries 16-bit data.

Address/status bus

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A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit
address and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data
using data bus D8-D15. This signal is low during the first clock cycle, thereafter it is active.

Read($\overline{RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 32. It is an acknowledgement signal from I/O devices that data is transferred.
It is an active high signal. When it is high, it indicates that the device is ready to transfer data.
When it is low, it indicates wait state.

RESET

It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock cycles to
RESET the microprocessor.

INTR

It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock
cycle of each instruction to determine if the processor considered this as an interrupt or not.

NMI

It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered input,
which causes an interrupt request to the microprocessor.

$\overline{TEST}$

This signal is like wait state and is available at pin 23. When this signal is high, then the
processor has to wait for IDLE state, else the execution continues.

MN/$\overline{MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the processor
is to operate in; when it is high, it works in the minimum mode and vice-aversa.

INTA

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It is an interrupt acknowledgement signal and id available at pin 24. When the microprocessor
receives this signal, it acknowledges the interrupt.

ALE

It stands for address enable latch and is available at pin 25. A positive pulse is generated each
time the processor begins any operation. This signal indicates the availability of a valid address
on the address/data lines.

DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The
transreceiver is a device used to separate data from the address/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It decides the direction of
data flow through the transreceiver. When it is high, data is transmitted out and vice-a-versa.

M/IO

This signal is used to distinguish between memory and I/O operations. When it is high, it
indicates I/O operation and when it is low indicates the memory operation. It is available at pin
28.

WR

It stands for write signal and is available at pin 29. It is used to write the data into the memory or
the output device depending on the status of M/IO signal.

HLDA

It stands for Hold Acknowledgement signal and is available at pin 30. This signal acknowledges
the HOLD signal.

HOLD

This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide the status
of instruction queue. Their conditions are shown in the following table −

QS0 QS1 Status

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0 0 No operation
0 1 First byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent byte from the queue

S0, S1, S2

These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26, 27, and
28. Following is the table showing their status −

S2 S1 S0 Status
0 0 0 Interrupt acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive

LOCK

When this signal is active, it indicates to the other processors not to ask the CPU to leave the
system bus. It is activated using the LOCK prefix on any instruction and is available at pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to release
the system bus. When the signal is received by CPU, then it sends acknowledgment. RQ/GT0 has
a higher priority than RQ/GT1.

4.2 Programming model of 8086, addressing, assembler directives

The programming model for a microprocessor shows the various internal registers that are
accessible to the programmer. The Following Figure is a model for the 8086. In general, each
register has a special function.

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c. Assembler directives:

 Assembler: is a program that accepts an assembly language program as input and

converts it into an object module and prepares for loading the program into memory for
execution.
 An assembler directive is a statement to give direction to the assembler to perform task of the
assembly process.
 An assembler supports directives to define data, to organise segments to control
procedure, to define macros. It consists of two types of statements: instructions and
directives. The instructions are translated to the machine code by the assembler whereas
directives are not translated to the machine codes.

Assembler Directives of the 8086 Microprocessor

(a) The DB directive
(b) The DW directive
(c) The DD directive
(d) The STRUCT (or STRUC) and ENDS directives (counted as one)
(e)The EQU Directive

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(f)The COMMENT directive

(g)ASSUME
(h) EXTERN
(i) GLOBAL
(j) SEGMENT
(k)OFFSET
(l) PROC
(m)GROUP
(n) INCLUDE

Data declaration directives:

1. DB - The DB directive is used to declare a BYTE -2-BYTE variable - A BYTE is made up of 8 bits.

Declaration examples:

Byte1 DB 10h
Byte2 DB 255 ; 0FFh, the max. possible for a BYTE
CRLF DB 0Dh, 0Ah, 24h ;Carriage Return, terminator BYTE

2. DW - The DW directive is used to declare a WORD type variable - A WORD occupies 16 bits or (2 BYTE).

Declaration examples:

Word DW 1234h
Word2 DW 65535; 0FFFFh, (the max. possible for a WORD)

3. DD - The DD directive is used to declare a DWORD - A DWORD double word is made up of 32 bits =2
Word's or 4 BYTE.

Declaration examples:

Dword1 DW 12345678h
Dword2 DW 4294967295 ;0FFFFFFFFh.

4. STRUCT and ENDS directives to define a structure template for grouping data items.

(1) The STRUCT directive tells the assembler that a user defined uninitialized data structure follows. The uninitialized
data structure consists of a combination of the three supported data types. DB, DW, and DD. The labels serve as
zero-based offsets into the structure. The first element's offset for any structure is 0. A structure element is referenced
with the base "+" operator before the element's name.
A Structure ends by using the ENDS directive meaning END of Structure.

Syntax:

STRUCT

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Structure_element_name element_data_type?
...
...
...
ENDS

(OR)

STRUC
Structure_element_name element_data_type?
...
...
...
ENDS
DECLARATION:
STRUCT
Byte1 DB?
Byte2 DB?
Word1 DW?
Word2 DW?
Dword1DW?
Dword2 DW?
ENDS

Use OF STRUCT:

The STRUCT directive enables us to change the order of items in the structure when, we reform a file header and
shuffle the data. Shuffle the data items in the file header and reformat the sequence of data declaration in the
STRUCT and off you go. No change in the code we write that processes the file header is necessary unless you
inserted an extra data element.

(5) The EQU Directive

The EQU directive is used to give name to some value or symbol. Each time the assembler finds the given names in
the program, it will replace the name with the value or a symbol. The value can be in the range 0 through 65535 and
it can be another Equate declared anywhere above or below.

The following operators can also be used to declare an Equate:

THIS BYTE
THIS WORD
THIS DWORD

A variable - declared with a DB, DW, or DD directive - has an address and has space reserved at that address for it in
the .COM file. But an Equate does not have an address or space reserved for it in the .COM file.

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Example:

A - Byte EQU THIS BYTE

DB 10
A_ word EQU THIS WORD
DW 1000
A_ dword EQU THIS DWORD
DD 4294967295
Buffer Size EQU 1024
Buffer DB 1024 DUP (0)
Buffed_ ptr EQU $ ; actually points to the next byte after the; 1024th byte in buffer.

(6) Extern:

It is used to tell the assembler that the name or label following the directive are I some other assembly module. For
example: if you call a procedure which is in program module assembled at a different time from that which contains
the CALL instructions ,you must tell the assembler that the procedure is external the assembler will put information in
the object code file so that the linker can connect the two module together.

Example:

PROCEDURE -HERE SEGMENT

EXTERN SMART-DIVIDE: FAR ; found in the segment; PROCEDURES-HERE
PROCEDURES-HERE ENDS

(7) GLOBAL:

The GLOBAL directive can be used in place of PUBLIC directive .for a name defined in the current assembly module;
the GLOBAL directive is used to make the symbol available to the other modules. Example:

GLOBAL DIVISOR:

WORD tells the assembler that DIVISOR is a variable of type of word which is in another assembly module or
EXTERN.

(8) SEGMENT:

It is used to indicate the start of a logical segment. It is the name given to the the segment. Example: the code
segment is used to indicate to the assembler the start of logical segment.

(9) PROC: (PROCEDURE)

It is used to identify the start of a procedure. It follows a name we give the procedure.

After the procedure the term NEAR and FAR is used to specify the procedure Example: SMART-DIVIDE PROC FAR
identifies the start of procedure named SMART-DIVIDE and tells the assembler that the procedure is far.

(10) NAME:

It is used to give a specific name to each assembly module when program consists of several modules.
Example: PC-BOARD used to name an assembly module which contains the instructions for controlling a printed
circuit board.

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(11) INCLUDE:

It is used to tell the assembler to insert a block of source code from the named file into the current source module.
This shortens the source module. An alternative is use of editor block command to cop the file into the current source
module.

(12) OFFSET:

It is an operator which tells the assembler to determine the offset or displacement of a named data item from the start
of the segment which contains it. It is used to load the offset of a variable into a register so that variable can be
accessed with one of the addressed modes. Example: when the assembler read MOV BX.OFFSET PRICES, it will
determine the offset of the prices.

(13) GROUP:

It can be used to tell the assembler to group the logical segments named after the directive into one logical group.
This allows the contents of all he segments to be accessed from the same group. Example: SMALL-SYSTEM
GROUP CODE, DATA, STACK-SEG.

4.3 Instruction set- data transfer group, Arithmetic group, logical group, control transfer
group, miscellaneous instruction groups

The 8086 microprocessor supports 8 types of instructions −

 Data Transfer Instructions

 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions

Let us now discuss these instruction sets in detail.

Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination
operand. Following are the list of instructions under this group −

Instruction to transfer a word

 MOV − Used to copy the byte or word from the provided source to the provided
destination.
 PPUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.

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 POPA − Used to get words from the stack to all registers.

 XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the memory.

Instructions for input and output port transfer

 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the provided port.

Instructions to transfer the address

 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
 LES − Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

 LAHF − Used to load AH with the low byte of the flag register.
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.

Arithmetic Instructions
These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, etc.

Following is the list of instructions under this group −

Instructions to perform addition

 ADD − Used to add the provided byte to byte/word to word.

 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.

Instructions to perform subtraction

 SUB − Used to subtract the byte from byte/word from word.

 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s complement.
 CMP − Used to compare 2 provided byte/word.
 AAS − Used to adjust ASCII codes after subtraction.

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 DAS − Used to adjust decimal after subtraction.

Instruction to perform multiplication

 MUL − Used to multiply unsigned byte by byte/word by word.

 IMUL − Used to multiply signed byte by byte/word by word.
 AAM − Used to adjust ASCII codes after multiplication.

Instructions to perform division

 DIV − Used to divide the unsigned word by byte or unsigned double word by word.
 IDIV − Used to divide the signed word by byte or signed double word by word.
 AAD − Used to adjust ASCII codes after division.
 CBW − Used to fill the upper byte of the word with the copies of sign bit of the lower
byte.
 CWD − Used to fill the upper word of the double word with the sign bit of the lower
word.

Bit Manipulation Instructions

These instructions are used to perform operations where data bits are involved, i.e. operations
like logical, shift, etc.

Following is the list of instructions under this group −

Instructions to perform logical operation

 NOT − Used to invert each bit of a byte or word.

 AND − Used for adding each bit in a byte/word with the corresponding bit in another
byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit in another
byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a byte/word with the
corresponding bit in another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.

Instructions to perform shift operations

 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in MSBs.
 SAR − Used to shift bits of a byte/word towards the right and copy the old MSB into the
new MSB.

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Instructions to perform rotate operations

 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to Carry
Flag [CF].
 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to Carry
Flag [CF].
 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to
MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to LSB.

String Instructions
String is a group of bytes/words and their memory is always allocated in a sequential order.

Following is the list of instructions under this group −

 REP − Used to repeat the given instruction till CX ≠ 0.

 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to the provided
memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided
memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in AL
or string word with a word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string word into AX.

Program Execution Transfer Instructions (Branch and Loop

Instructions)
These instructions are used to transfer/branch the instructions during an execution. It includes the
following instructions −

Instructions to transfer the instruction during an execution without any condition −

 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
 JMP − Used to jump to the provided address to proceed to the next instruction.

Instructions to transfer the instruction during an execution with some conditions −

 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.

 JAE/JNB − Used to jump if above/not below instruction satisfies.

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 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.

 JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
 JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1

Processor Control Instructions

These instructions are used to control the processor action by setting/resetting the flag values.

Following are the instructions under this group −

 STC − Used to set carry flag CF to 1

 CLC − Used to clear/reset carry flag CF to 0
 CMC − Used to put complement at the state of carry flag CF.
 STD − Used to set the direction flag DF to 1
 CLD − Used to clear/reset the direction flag DF to 0
 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

Iteration Control Instructions

These instructions are used to execute the given instructions for number of times. Following is
the list of instructions under this group −

 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX
=0
 JCXZ − Used to jump to the provided address if CX = 0

Interrupt Instructions
These instructions are used to call the interrupt during program execution.

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 INT − Used to interrupt the program during execution and calling service specified.
 INTO − Used to interrupt the program during execution if OF = 1
 IRET − Used to return from interrupt service to the main program

4.4 Some programming examples based on 8086 assembly language.

1. Write an ALP to find factorial of number for 8086.

MOV AX, 05H
MOV CX, AX
Back: DEC CX
MUL CX
LOOP back
; results stored in AX
; to store the result at D000H
MOV [D000], AX
HLT

2. Write a program to multiply 2 numbers (16-bit data) for 8086.

Title multiply two numbers
Dosseg
.model small
.stack 100h
.data
Multiplier dw 1234H
Multiplicant dw 3456H
Product dw ?
.code
MULT proc
MOV AX, @data
MOV DS, AX
MOV AX, Multiplicant
MUL Multiplier
MOV Product, AX
MOV Product+2, DX
MOV AH, 4CH
INT 21H
MULT endp
End MULT

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UNIT 5 Microcontrollers: Intel 8051 Microcontroller: [10 hour]

5.1 Introduction, Architecture, Memory Organization

What is a Microcontroller?

A single chip computer or A CPU with all the peripherals like RAM, ROM, I/O Ports,
Timers , ADCs etc... on the same chip. For ex: Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and
PIC 16X etc…
A microcontroller is a highly integrated single chip, which consists of on chip CPU (Central
Processing Unit), RAM (Random Access Memory), EPROM/PROM/ROM (Erasable
Programmable Read Only Memory), I/O (input/output) – serial and parallel, timers, interrupt
controller. For example, Intel 8051 is 8-bit microcontroller and Intel 8096 is 16-bit
microcontroller. The block diagram of Microcontroller is shown in Fig.2.

Fig.Block Diagram of a Microcontroller

Distinguish between Microprocessor and Microcontroller

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S.No Microprocessor Microcontroller

1 A microprocessor is a general A microcontroller is a dedicated chip which

purpose device which is called a is also called single chip computer.
CPU

2 A microprocessor do not contain A microcontroller includes RAM, ROM,

onchip I/OPorts, Timers, Memories serial and parallel interface, timers,
interrupt
etc..
circuitry (in addition to CPU) in a single
chip.
3 Microprocessors are
most Microcontrollers are used in small,
commonly used as the CPU in minimum component designs performing
control-oriented applications.
microcomputer systems

4 Microprocessor instructions are Microcontroller instructions are both bit

mainly nibble or byte addressable addressable as well as byte addressable.

5 Microprocessor instruction sets are Microcontrollers have instruction sets

mainly intended for catering to catering to the control of inputs and outputs.
large volumes of data.

6 Microprocessor based system design Microcontroller based system design is

is complex and expensive rather simple and cost effective

7 The Instruction set of The instruction set of a Microcontroller is

microprocessor is complex with very simple with less number of
large number of instructions. instructions. For, ex: PIC microcontrollers
have only 35 instructions.

8 A microprocessor has zero status A microcontroller has no zero flag.

flag

INTEL MCS 51 Family

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Microcontroller On chip RAM On chip Timers/Counters Interrupts Serial ports

(Bytes) program
memory

8031 128 None 2 5 1

8032 256 None 3 6 1

8051 128 4K ROM 2 5 1

8052 256 8K ROM 3 6 1

8751 128 4K EPROM 2 5 1

8752 256 8K EPROM 3 6 1

INTEL 8051 MICRCONTROLLER :

The 8051 microcontroller is a very popular 8-bit microcontroller introduced by Intel in the
year 1981 and it has become almost the academic standard now a days. The 8051 is based on an
8-bit CISC core with Harvard architecture. Its 8-bit architecture is optimized for control
applications with extensive Boolean processing. It is available as a 40-pin DIP chip and works at
+5 Volts DC. The salient features of 8051 controller are given below.

SALIENT FEATURES : The salient features of 8051 Microcontroller are

i. 4 KB on chip program memory (ROM or EPROM)).

ii. 128 bytes on chip data memory(RAM).

iii. 8-bit data bus

iv. 16-bit address bus

v. 32 general purpose registers each of 8 bits

vi. Two -16 bit timers T0 and T1

vii. Five Interrupts (3 internal and 2 external).

ix. Four Parallel ports each of 8-bits (PORT0, PORT1,PORT2,PORT3) with a total of 32 I/O

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lines.

x. One 16-bit program counter and One 16-bit DPTR ( data pointer)

xi. One 8-bit stack pointer

xii. One Microsecond instruction cycle with 12 MHz Crystal.

xiii. One full duplex serial communication port.

ARCHITECTURE & BLOCK DIAGRAM OF 8051 MICROCONTROLLER:

The architecture of the 8051 microcontroller can be understood from the block diagram. It
has Harward architecture with RISC (Reduced Instruction Set Computer) concept. The block
diagram of 8051 microcontroller is shown in Fig 3. below1.It consists of an 8-bit ALU, one 8-bit
PSW(Program Status Register), A and B registers , one 16-bit Program counter , one 16-bit Data
pointer register(DPTR),128 bytes of RAM and 4kB of ROM and four parallel I/O ports each of 8-
bit width.

Fig.3. Block Diagram of 8051 Microcontroller

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8051 has 8-bit ALU which can perform all the 8-bit arithmetic and logical operations in one
machine cycle. The ALU is associated with two registers A & B
A and B Registers : The A and B registers are special function registers which hold the results of
many arithmetic and logical operations of 8051.The A register is also called the Accumulator and
as it’s name suggests, is used as a general register to accumulate the results of a large number of
instructions. By default it is used for all mathematical operations and also data transfer operations
between CPU and any external memory.

The B register is mainly used for multiplication and division operations along with A register.

MUL AB : DIV AB.

It has no other function other than as a location where data may be stored.
The R registers: The "R" registers are a set of eight registers that are named R0, R1, etc. up to
and including R7. These registers are used as auxillary registers in many operations. The "R"
registers are also used to temporarily store values.
Program Counter(PC) : 8051 has a 16-bit program counter .The program counter always points
to the address of the next instruction to be executed. After execution of one instruction the program
counter is incremented to point to the address of the next instruction to be executed.It is the
contents of the PC that are placed on the address bus to find and fetch the desired instruction.Since
the PC is 16-bit width ,8051 can access program addresses from 0000H to FFFFH ,a total of 6kB
of code.

Stack Pointer Register (SP) : It is an 8-bit register which stores the address of the stack top. i.e
the Stack Pointer is used to indicate where the next value to be removed from the stack should be
taken from. When a value is pushed onto the stack, the 8051 first increments the value of SP and
then stores the value at the resulting memory location. Similarly when a value is popped off the
stack, the 8051 returns the value from the memory location indicated by SP, and then decrements
the value of SP. Since the SP is only 8-bit wide it is incremented or decremented by two . SP is
modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI.
It is also used intrinsically whenever an interrupt is triggered.

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STACK in 8051 Microcontroller : The stack is a part of RAM used by the CPU to store
information temporarily. This information may be either data or an address .The CPU needs this
storage area as there are only limited number of registers. The register used to access the stack is
called the Stack pointer which is an 8-bit register..So,it can take values of 00 to FF H.When the
8051 is powered up ,the SP register contains the value 07.i.e the RAM location value 08 is the first
location being used for the stack by the 8051 controller

There are two important instructions to handle this stack.One is the PUSH and the Other
is the POP. The loading of data from CPU registers to the stack is done by PUSH and the loading
of the contents of the stack back into aCPU register is done by POP.
EX : MOV R6 ,#35 H
MOV R1 ,#21 H
PUSH 6
PUSH 1
In the above instructions the contents of the Registers R6 and R1 are moved to stack and they
occupy the 08 and 09 locations of the stack.Now the contents of the SP are incremented by two
and it is 0A
Similarly POP 3 instruction pops the contents of stack into R3 register.Now the contents of the SP
is decremented by 1
In 8051 the RAM locations 08 to 1F (24 bytes) can be used for the Stack.In any program if we
need more than 24 bytes of stack ,we can change the SP point to RAM locations 30-7F H.this can
be done with the instruction MOV SP,# XX.
Data Pointer Register(DPTR) : It is a 16-bit register which is the only user-accessible. DPTR,
as the name suggests, is used to point to data. It is used by a number of commands which allow
the 8051 to access external memory. When the 8051 accesses external memory it will access
external memory at the address indicated by DPTR. This DPTR can also be used as two 8-registers
DPH and DPL.
Program Status Register (PSW) : The 8051 has a 8-bit PSW register which is alsoknown as Flag
register.In the 8-bit register only 6-bits are used by 8051.The two unused bits are user definable
bits.In the 6-bits four of them are conditional flags .They are Carry –CY,Auxiliary Carry-AC,

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Parity-P,and Overflow-OV .These flag bits indicate some conditions that resulted after an
instruction was executed.

The bits PSW3 and PSW4 are denoted as RS0 and RS1 and these bits are used th select the bank
registers of the RAM location. The meaning of various bits of PSW register is shown below.
CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag
FO PSW.5 Flag 0 available for general purpose .
RS1 PSW.4 Register Bank select bit 1
RS0 PSW.3 Register bank select bit 0
OV PSW.2 Overflow flag
--- PSW.1 User difinable flag
P PSW.0 Parity flag .set/cleared by hardware.

The selection of the register Banks and their addresses are given below.
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH

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Memory organization :
The 8051 microcontroller has 128 bytes of Internal RAM and 4kB of on chip ROM .The RAM is
also known as Data memory and the ROM is known as program memory. The program memory
is also known as Code memory .This Code memory holds the actual 8051 program that is to be
executed. In 8051 this memory is limited to 64K .Code memory may be found on-chip, as ROM
or EPROM. It may also be stored completely off-chip in an external ROM or, more commonly,
an external EPROM. The 8051 has only 128 bytes of Internal RAM but it supports 64kB of external
RAM. As the name suggests, external RAM is any random access memory which is off-chip.
Since the memory is off-chip it is not as flexible interms of accessing, and is also slower. For
example, to increment an Internal RAM location by 1,it requires only 1 instruction and 1
instruction cycle but to increment a 1-byte value stored in External RAM requires 4 instructions
and 7 instruction cycles. So, here the external memory is 7 times slower.

Internal RAM OF 8051 :

This Internal RAM is found on-chip on the 8051 .So it is the fastest RAM available, and it is also
the most flexible in terms of reading, writing, and modifying it’s contents. Internal RAM is
volatile, so when the 8051 is reset this memory is cleared. The 128 bytes of internal RAM is
organized as below.
(i) Four register banks (Bank0,Bank1, Bank2 and Bank3) each of 8-bits (total 32 bytes). The
default bank register is Bank0. The remaining Banks are selected with the help of RS0 and
RS1 bits of PSW Register.

(ii) 16 bytes of bit addressable area and

(iii) 80 bytes of general purpose area (Scratch pad memory) as shown in the diagram below. This
area is also utilized by the microcontroller as a storage area for the operating stack.

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The 32 bytes of RAM from address 00 H to 1FH are used as working registers organized as four
banks of eight registers each.The registers are named as R0-R7 .Each register can be addressed
by its name or by its RAM address.

For EX : MOV A, R7 or MOV R7,#05H

Internal ROM (On –chip ROM): The 8051 microcontroller has 4kB of on chip ROM but it can
be extended up to 64kB.This ROM is also called program memory or code memory. The CODE
segment is accessed using the program counter (PC) for opcode fetches and by DPTR for data.
The external ROM is accessed when the EA(active low) pin is connected to ground or the contents
of program counter exceeds 0FFFH.When the Internal ROM address is exceeded the 8051
automatically fetches the code bytes from the external program memory.

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SPECIAL FUNCTION REGISTERS (SFRs) : In 8051 microcontroller there certain registers

which uses the RAM addresses from 80h to FFh and they are meant for certain specific operations
.These registers are called Special function registers (SFRs).Some of these registers are bit
addressable also.

The list of SFRs and their functional names are given below. In these SFRs some of them are
related to I/O ports (P0,P1,P2 and P3) and some of them are meant for control operations
(TCON,SCON, PCON..) and remaining are the auxillary SFRs, in the sense that they don't directly
configure the 8051.

S.No Symbol Name of SFR Address (Hex)

1 ACC* Accumulator 0E0
2 B* B-Register 0F0

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3 PSW* Program Status word register 0DO

4 SP Stack Pointer Register 81
5 DPL Data pointer low byte 82
DPTR DPH Data pointer high byte 83
6 P0* Port 0 80
P1* Port 1 90
8 P2* Port 2 0A
9 P3* Port 3 0B
10 IP* Interrupt Priority control 0B8
11 IE* Interrupt Enable control 0A8
12 TMOD Tmier mode register 89
13 TCON* Timer control register 88
14 TH0 Timer 0 Higher byte 8C
15 TL0 Timer 0 Lower byte 8A
16 TH1 Timer 1Higher byte 8D
17 TL1 Timer 1 lower byte 8B
18 SCON* Serial control register 98
19 SBUF Serial buffer register 99
20 PCON Power control register 87

The * indicates the bit addressable SFRs

Table:SFRs of 8051 Microcontroller

5.2 Special Function Registers , Pins and Signals ,Timing and control , Port Operation –
Memory and I/O interfacing , Interrupts , Instruction Set and Programming.

PIN Diagram of 8051 Microcontroller : The 8051 microcontroller is available as a 40 pin DIP
chip and it works at +5 volts DC. Among the 40 pins , a total of 32 pins are allotted for the four
parallel ports P0,P1,P2 and P3 i.e each port occupies 8-pins .The remaining pins are VCC, GND,
XTAL1, XTAL2, RST, EA ,PSEN.

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XTAL1,XTAL2: These two pins are connected to Quartz crystal oscillator which runs the on-
chip oscillator. The quartz crystal oscillator is connected to the two pins along with a capacitor of
30pF as shown in the circuit. If we use a source other than the crystal oscillator, it will be
connected to XTAL1 and XTAL2 is left unconnected.

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Figure: Pin diagram of 8051 Microcontroller

RST: The RESET pin is an input pin and it is an active high pin. When a high pulse is applied to
this pin the microcontroller will reset and terminate all activities. Upon reset all the registers except
PC will reset to 0000 Value and PC register will reset to 0007 value.

(External Access): This pin is an active low pin. This pin is connected to ground when
microcontroller is accessing the program code stored in the external memory and connected to
Vcc when it is accessing the program code in the on chip memory. This pin should not be left
unconnected.

(Program Store Enable) : This is an output pin which is active low. When the
microcontroller is accessing the program code stored in the external ROM ,this pin is connected
to the OE (Output Enable) pin of the ROM.

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ALE (Address latch enable): This is an output pin, which is active high. When connected to
external memory , port 0 provides both address and data i.e address and data are multiplexed
through port 0 .This ALE pin will demultiplex the address and data bus .When the pin is High ,
the AD bus will act as address bus otherwise the AD bus will act as Data bus.

P0.0- P0.7(AD0-AD7) : The port 0 pins multiplexed with Address/data pins .If the microcontroller
is accessing external memory these pins will act as address/data pins otherwise they are used for
Port 0 pins.

P2.0- P2.7(A8-A15) : The port2 pins are multiplexed with the higher order address pins .When
the microcontroller is accessing external memory these pins provide the higher order address byte
otherwise they act as Port 2 pins.

P1.0- P1.7 :These 8-pins are dedicated for Port1 to perform input or output port operations.
P3.0- P3.7 :These 8-pins are meant for Port3 operations and also for some control operations like
Read,Write,Timer0,Timer1 ,INT0,INT1 ,RxD and TxD

8051 instruction sets

Depending on operation they perform, all instructions are divided in several
groups:

 Arithmetic Instructions
 Branch Instructions
 Data Transfer Instructions
 Logic Instructions
 Bit-oriented Instructions
The first part of each instruction, called MNEMONIC refers to the operation an
instruction performs (copy, addition, logic operation etc.). Mnemonics are
abbreviations of the name of operation being executed. For example:

 INC R1 – Means: Increment register R1 (increment register R1);

 LJMP LAB5 – Means: Long Jump LAB5 (long jump to the address marked as
LAB5);
 JNZ LOOP – Means: Jump if Not Zero LOOP (if the number in the accumulator is
not 0, jump to the address marked as LOOP);

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The other part of instruction, called OPERAND is separated from mnemonic by at

least one whitespace and defines data being processed by instructions. Some of
the instructions have no operand, while some of them have one, two or three. If
there is more than one operand in an instruction, they are separated by a comma.
For example:

 RET – return from a subroutine;

 JZ TEMP – if the number in the accumulator is not 0, jump to the address
marked as TEMP;
 ADD A,R3 – add R3 and accumulator;
 CJNE A,#20,LOOP – compare accumulator with 20. If they are not equal, jump to
the address marked as LOOP;

5.3 Interfacing with keyboards, LEDs, LCDs, ADC/DACs etc.

Interfacing of ADC 0804 to 8051 Microcontroller :

ADC 0804 is a single channel analog to digital converter i.e., it can take only one analog signal.
ADC 0804 has 8 bit resolution. The higher resolution ADC gives smaller step size. Step size is
smallest change that can be measured by an ADC. For an ADC with resolution of 8 bits, the step
size is 19.53mV (5V/255). The time taken by the ADC to convert analog data into digital form
depends on the frequency of clock source. The conversion time of ADC 0804 is around 110us. To
use the internal clock a capacitor and resistor are used as shown in the circuit. The input to the
ADC is given from a regulated power supply and a 10K potentiometer

The 8051 Microcontroller is used to provide the control signals to the ADC. CS(chip select) pin of ADC is
directly connected to ground. The pin P1.1, P1.0 and P1.2 are connected to the pin WR, RD and INTR of
the ADC respectively. When the input voltage from the preset is varied the output of ADC varies also
varies.

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From the circuit it is clear that the ADC interfaced directly to the microcontroller. The Port1 is
used as an input port which receives the digital data from the ADC.Port pins P2.5 and P2.6 are
used for SOC and EOC operation.When the conversion is over the ADC will send an interrupt
signal to the microcontroller through the pin P2.7 .Now the Microcontroller receives digital data
through the Port1.This data after conversion to decimal data is displayed on the LCD module .

The assembly language program for ADC is given below .

MOV P1 , 0FF H ; Make the port1 high and configure port1 as Input port

BACK: CLR P2.6 ; Generation of SOC pulse

SETB P2.5 ;

LOOP JB P2.7 , LOOP ; Wait for conversion, Is conversion over?

CLR P2.5 ; Enable Read the digital data

MOV A ,P1 ; Read digital data through Port1

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SETB P2.5 ; Disable read after read operation

CALL DISPLAY ; Display the data on LCD module

SJMP BACK ; Continue the conversion process

Stepper motor Interfacing

A stepper motor is a device that translates electrical pulses into mechanical movement. The
stepper motor rotates in steps in response to the applied signals. It is used in applications such as
disk drives, dot matrix printers, plotters and robotics.It is mainly used for position control. Stepper
motors have a permanent magnet called rotor (also called the shaft) surrounded by a stator . There
are also steppers called variable reluctance stepper motors that do not have a PM rotor. The most
common stepper motors have four stator windings that are paired with a center-tapped. This type
of stepper motor is commonly referred to as a. four-phase or unipolar stepper motor. The center
tap allows a change of current direction in each of two coils when a winding is grounded, thereby
resulting in a polarity change of the stator.

ASSEMBLY LANGUAGE PROGRAM

Main mov stepper, #0CH ; move the code to phase1 into the port

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acall delay
mov stepper, #06H ; phase II code
acall delay
mov stepper, #03H ;Phase III code
acall delay ;Call delay subroutine program
mov stepper, #09H ;Phase IV code
acall delay
sjmp Main
CALL DELAY PROGRAM :
mov r7,#4
wait2:
mov r6,#0FFH
wait1:
mov r5,#0FFH
wait:
djnz r5,wait
djnz r6,wait1
djnz r7,wait2
ret
end

INTERFACING DC MOTOR- 8051

A DC motor runs with the help of Direct Current. It produces torque by using both electricity and
magnetic fields. The DC motor has rotor, stator, field magnet, brushes, shaft, commutator. The DC
motor requires more current to produce initial torque than in running state.Interfacing the DC
motor directly to 8051 microcontroller is not possible. Because the DC motor uses large current
(200-300mA in small DC motors) to run. When this current flow into the 8051 microcontroller,
the IC will get damaged. Therefore we use a driving circuit with an opto isolator and a L298 Dual
H-Bridge driver. The opto-isolator provides additional protection to the microcontroller.

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Continuous, sustained operation of the motor will cause the L293 Dual H-Bridge driver to
overheat. So,a suitable heat sink must be used.

Assembly Language program

ORG 0000H Remarks

MAIN CLR P1.0
CLR P1.1
CLR P1.2
SETB P2.7

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MONITOR
SETB P1.0 Enable the H-bridge driver
JNB P2.7 CLOCKWISE
CLR P1.1 01 is for Counter clockwise
SETB P1.2
SJMP MONITOR
CLOCKWISE SETB P1.1 10 is for clockwise
CLR P1.2
SJMP MONITOR
INTERFACING DAC -8051 MICROCONTROLLER
The DAC 0800 is a simple monolithic 8-bit D/A converter. It has fast settling time of 100ns. It can be
directly interfaced to TTL, CMOS, PMOS and others. It operates at 4.5V to +18V supply. The number of
data bit inputs decides the resolution of the DAC since the number of analog output levels is equal to 2″,
where n is the number of data bit inputs. Therefore, an 8-input DAC such as the DAC0808 provides 256
discrete voltage (or current) levels of output.

The interfacing circuit is shown below. port 1(8 bits of the microcontroller is connected to the
input data lines of DAC-08.The reference current is determined by the resistor R1 and the reference
voltage V ref. The resistor R2 is generally equal to R1 to match the input impedance of reference
source. The output (taken from pin number 4 is observed either on a digital multimeter or on a
cathode ray oscilloscope.

The output current Io is calculated as follows:

Io = Vref/R1[Ao/2 + A1/4 + A2/8 + … +A7/256]

The output voltage Vo is obtained as follows: Vo =Io * R1

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Assembly Language Program

MOV A, #DATA* ; (A) = #Data

START : MOV 90H, A ; (port -1) = (A)

INC A

LJMP START ; Repeat

Interrupt Structure: An interrupt is an external or internal event that disturbs the

microcontroller to inform it that a device needs its service. The program which is associated with
the interrupt is called the interrupt service routine (ISR) or interrupt handler. Upon receiving
the interrupt signal the Microcontroller , finish current instruction and saves the PC on stack.
Jumps to a fixed location in memory depending on type of interrupt Starts to execute the interrupt
service routine until RETI (return from interrupt)Upon executing the RETI the microcontroller
returns to the place where it was interrupted. Get pop PC from stack

The 8051 microcontroller has FIVE interrupts in addition to Reset. They are
 Timer 0 overflow Interrupt

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 Timer 1 overflow Interrupt

 External Interrupt 0(INT0)

 External Interrupt 1(INT1)

 Serial Port events (buffer full, buffer empty, etc) Interrupt

Each interrupt has a specific place in code memory where program execution (interrupt service
routine) begins.
 External Interrupt 0: 0003 H

 Timer 0 overflow: 000B H

 External Interrupt 1: 0013 H

 Timer 1 overflow: 001B H

 Serial Interrupt : 0023 H

Upon reset all Interrupts are disabled & do not respond to the Microcontroller. These interrupts
must be enabled by software in order for the Microcontroller to respond to them. This is done by
an 8-bit register called Interrupt Enable Register (IE).

Interrupt Enable Register :

 EA : Global enable/disable. To enable the interrupts this bit must be set High.

 --- : Undefined-reserved for future use.

 ET2 : Enable /disable Timer 2 overflow interrupt.

 ES : Enable/disable Serial port interrupt.

 ET1 : Enable /disable Timer 1 overflow interrupt.

 EX1 : Enable/disable External interrupt1.

 ET0 : Enable /disable Timer 0 overflow interrupt.

 EX0 : Enable/disable External interrupt0

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Upon reset the interrupts have the following priority.(Top to down). The interrupt with the highest
PRIORITY gets serviced first.
1. External interrupt 0 (INT0)

2. Timer interrupt0 (TF0)

3. External interrupt 1 (INT1)

4. Timer interrupt1 (TF1)

5. Serial communication (RI+TI)

Priority can also be set to “high” or “low” by 8-bit IP register.- Interrupt priority register

IP.7: reserved
IP.6: reserved
IP.5: Timer 2 interrupt priority bit (8052 only)
IP.4: Serial port interrupt priority bit
IP.3: Timer 1 interrupt priority bit
IP.2: External interrupt 1 priority bit
IP.1: Timser 0 interrupt priority bit
IP.0: External interrupt 0 priority bit

TIMERS in 8051 Microcontrollers : The 8051 microcontroller has two 16-bit timers
Timer 0 (T0) and Timer 1(T1) which can be used either to generate accurate time delays or as
event counters. These timers are accessed as two 8-bit registers TLO, THO & TL1 ,TH1 because
the 8051 microcontroller has 8-bit architecture.

TIMER 0 : The Timer 0 is a 16-bit register and can be treated as two 8-bit registers (TL0 & TH0)
and these registers can be accessed similar to any other registers like A,B or R1,R2,R3 etc…

Ex : The instruction Mov TL0,#07 moves the value 07 into lower byte of Timer0.

Similarly Mov R5,TH0 saves the contents of TH0 in the R5 register.

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TIMER 1 : The Timer 1 is also a 16-bit register and can be treated as two 8-bit registers (TL1 &
TH1) and these registers can be accessed similar to any other registers like A,B or R1,R2,R3 etc…

Ex : The instruction MOV TL1,#05 moves the value 05 into lower byte of Timer1.
Similarly MOV R0,TH1 saves the contents of TH1 in the R0 register

TMOD Register : The various operating modes of both the timers T0 and T1 are set by an 8-bit
register called TMOD register. In this TMOD register the lower 4-bits are meant for Timer 0 and
the higher 4-bits are meant for Timer1.

GATE: This bit is used to start or stop the timers by hardware .When GATE= 1 ,the timers can be
started / stopped by the external sources. When GATE= 0, the timers can be started or stopped by
software instructions like SETB TR0 or SETB TR1

C/T (clock/Timer) : This bit decides whether the timer is used as delay generator or event
counter. When C/T = 0 ,the Timer is used as delay generator and if C/T=1 the timer is used as
an event counter. The clock source for the time delay is the crystal frequency of 8051.

M1,M0 (Mode) : These two bits are the timer mode bits. The timers of the 8051 can be configured
in three modes.Mode0, Mode1 and Mode2.The selection and operation of the modes is shown
below.

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S.No M0 M1 Mode Operation

1 0 0 0 13-bit Timer mode
8-bit Timer/counter. THx with TLx as 5-bit
prescalar
2 0 1 1 16-bit Timer mode.16-bit timer /counter
without pre-scalar
3 1 0 2 8-bit auto reload. THx contains a value that
is to be loaded into TLx each time it
overflows
4 1 1 3 Split timer mode

5.4 Introduction to high end processors and Introduction to AVR family architecture
There are major Microprocessor companies as Intel , AMD, ARM etc. These companies design
and manufacture different architecture of microprocessor as 32 bit and 64 bit. The ARM company
design 32 bit Microprocessor for Smartphone’s and Intel/AMD design and manufacture
Microprocessor for PC and High End Computers’s (Servers, Workstations, Data Centers). Intel
has x86 series of Microprocessor which now branded with multicore Itanium (I3, I5, I7 etc.) series
where AMD also have such 64 bit Microprocessors.

AVR was developed in the year 1996 by Atmel Corporation. The architecture of AVR was
developed by Alf-Egil Bogen and Vegard Wollan. AVR derives its name from its developers and
stands for Alf-Egil Bogen Vegard Wollan RISC microcontroller, also known
as Advanced Virtual RISC.

AVR microcontrollers are available in three categories:

1. TinyAVR – Less memory, small size, suitable only for simpler applications
2. MegaAVR – These are the most popular ones having good amount of memory (upto 256
KB), higher number of inbuilt peripherals and suitable for moderate to complex applications.
3. XmegaAVR – Used commercially for complex applications, which require large program
memory and high speed.
8051 PIC AVR
SPEED Slow Moderate Fast
MEMORY Small Large Large
ARCHITECTURE CISC RISC RISC
ADC Not Present Inbuilt Inbuilt
Timers Inbuilt Inbuilt Inbuilt
PWM Channels Not Present Inbuilt Inbuilt
Reduced Instruction Set Computer (RISC) Complex Instruction Set Computers (CISC)

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AVR Architecture
• RISC architecture with CISC instruction set • Powerful instruction set for C and Assembly
• Scalable • Same powerful AVR core in all devices
• Single cycle execution • One instruction per external clock
• Low power consumption • 32 Working Registers
• All Directly connected to ALU! • Very efficient core
• 20 MIPS @ 20MHz • High System Level Integration
• Lowest total system cost • User Friendly

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Practical Lab exercises: [30]

1. To familiarize with 8085 microprocessor and run a program to add two 8 bit data.
2. Write and execute a program to subtract two 8 bit data on 8085
3. Write and execute a program to add two 16 bit data on 8086 microprocessor
4. Write a logic program for the multiplication & division of numbers signed &
unsigned both.
5. Write a logic program to find the square of a number without using multiplication
instruction.
6. Write a logic program to find square of a number using look-up table.
7. Write a logic program to find the factorial of a given number.
8. Write a program to control LEDs connected at output port of 8051 microcontroller
9. Write a program to speed of dc shunt motor
10. Write and execute a program for traffic light control

Reference books:
1. Douglas V Hal, ‘Microprocessor and Interfacing, Programming and Hardware’ TMH
2006
2. Liu and Gibson,’ Micro computer System 8086/8088 family architecture,
programming and design’ PHI 2nd edition.
3. K Uma Rao, The 8051 Microcontroller, architecture, programming and applications’,
Pearson 2009.
3. Muhammed Ali Mazidi, Janice Gillies Pie Mazidi, “The 8051 Microcontroller and Embedded
Systems”— Pearson EducationAsia.

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