1. Design an odd counter with loadable din and synchronous reset?

2. Design an full adder using half subtractors?

3. Design an full adder using NAND gates?
4. Design an posedge and negedge detectors?
5. Design an comparator using MUX?
6. Design an comparator using 2:4 decoder?
7. Design an N:1 Mux?
8. Design an 5:1 Mux?
9. Design an SISO,PISO,PIPO,SIPO according to the mode input?
10.Design an 4-bit SIPO shift register which shifts 2-bits(shift for 2 times) to
left or right and should for 2 more times which should have previous value?
11.Design an RTL & TB by analysing the waveforms(CHANDRASEKHAR)?
12.Design an FSM using T_FF?
13.Design an 64-bit arithmetic shift register, with synchronous load. The shifter
can shift both left and right, and by 1 or 8 times. Write Test bench to verify it.
(Hint: use a 2 bit register to decide the shifting direction and the number of time
shifting has to be done i.e 1 or 8 times)?
14. Design an full adder using MUX?
15.Design an divider by 5 with 50% dutycycle?
16.Design an sequence detector 101101 overlapping?
17.Design an JK_FF using task?
18.Design an siso,sipo bidirectional shift register?
19.Write an RTL code for multiplication of two numbers without using multiplication
operator?
20. Design an 4*8 LIFO asynchronus or synchronous?
21. Design an SRAM?
22. Design an 50Mhz clock signal generator?
23. Design an Decimal to BCD encoder?
24. Design an mod 2bit counter usinh JK_Flipflop?
25. Design an sinewave generator?
26. Design a 8:3 priority encoder using 4:2 priority encoder assuming that they
have validout and enable pins?
27. Design an 2 digit bcd up counter which operates on synchronous active high/low
reset of ur choice?
28. Design an 2's complimenter adder/subtractor?
29. Design an RTL code for square root of given number and test it?
30. Write an RTL that swap two numbers with out using thrd variable?
31. Design an 2,6,5,3,1 sequence counter?
32. Design an RTL code for binray to gray converter and vice versa depends on it
mode input pin? Assume that if mode=1 binary to grey else grey to binary?
33. Design an 110110 sequence generator?
34. Design an Demultiplexer;
35. Design an RTL for replication knight movement in chessgame?
36. Design an clock divide by 4.5 circuit.
36. Design an circuit where There are 2 switches S1 & S2 which controls 3 bulbs
B1,B2,B3 . Only 1 bulb should be glowing at a time .There is a main switch S which
controls all 3 bulbs.When S is on ,S1 & S2 functions as usual.When S is off ,none
of the bulbs glow.
37. Write RTL for desigining the outputs q1,q2,q3 by analyzing the following
waveform :
Signals descriptions:
1)clk is clock and active at posedge
2)a is the input signal synchronous to clock at posedge .
3)q1,q2,q3 are the output flag signals .
q1 is high for 2 clock cycles as shown in the waveform and is detected in the 1st
cycle of valid a .
q2 is high for 1.5 clock cycles in the ninth clock cycle of valid a .
q3 is high for 1 clock cycles in the ninth clock cycle of valid a .
38. Design an D_ff using Multiplexer
39. Design an N-bit johnsoncounter,ringcounter?
40. Design an divide by counter with 50% duty cycle using ring counter?
41. Given Input clock design frequency = 200hz Write RTL code in Verilog to
generate one minute and one second pulses based on the input clock frequency .
Reset is asynchronous reset ,active
low.
42. Write a Behavioral verilog model for generating an infinite sequence of 5-7-5-
7.......................... using "for" loop ?
43. Write a verilog cod to get a chain of 500_Flipflops?
44. Write an verilog code for given specifications that if en=1 dout is equal to
dout when en=0 dout should hold previous value?
45. Write a verilog code for driving 30Mhz clock signal assuming input clock signal
is or 120 Mhz?
46. Write a verilog code for which will generate 0001 for giving 1011 as input?
47. Write a verilog code clcock divide by N?
48. Write a verilog code to generate 100mHZ clock signal with 80% duty cycle?
49. Write an 4-bit ripple counter?
50.Write an verilog cod to diplay days,hours,minutes from the given input as
second?
51:Write an rtl code to convert binary to decimal and vice veras base on mode
input?
52:Write an rtl code fro designing all logic gate using muxes?
53.Write a verilog code to find HCF and LCM of givin number?
54.Design an 3:8 decoder using 2:4 deocders?
55.Write a code for DVD plays for different test scenarios given like below poweron
button,volume increase button,volume decrease button,forwadchannel button,backward
channel button.
56.Write code for FSM TAP CONTROLLER.
57.Write verilog code for dividing 120 by 4 without using Division operator ?
58.Write Verilog code in-order to generate odd & even random numbers?
59.What is $urandom ?
60.Write RTL code for designing a DUAL port RAM with size of its memory as :
16x8 .Also verify the same by writing a Verilog based Test-bench .
The RAM supports simultaneous read & write operation .
61.Design a block with verilog which has 3 main inputs as followed.
1. system clock of pretty high freq
2. asynch clock input P
3. asynch clock input Q
P and Q clocks have 50% duty cycle each. Their frequencies are close enough
and they have phase difference. Design a block to generate these outputs.

1. eq : goes high if periods of P and Q are same

2. le : goes high if P's period is less than that of Q.
3. gr : goes high if P's period is greater than that of Q.
62.Write the verilog code for a counter of frequency 1GHZ.That has a flag for
every 10 seconds
63.Write the verilog code for T flop using D flop.
64.Write the program for finding factorial of a given number using recursive
function.
65.Write verilog code for parallel encoder and priority encoder.
66.Design 2 i/p full adder using LUT’s.
67.Write a verilog code for tri-state buffer using data flow model.
68.Write an RTL code for a 4-bit SIPO(serial-in-parallel-out) shift register which
shifts first 2-bits (shift for 2 times) to left/right and should shift for 2 more
times which should have the previous value.
69. Write a RTL CODE FOR FREQUENCY MULTIPLER BY 2.