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Curriculum-VLSI SoC Design Using Verilog HDL

The document outlines the curriculum for a course on VLSI SoC Design using Verilog HDL. The course contains 16 topics that cover VLSI introduction, SoC design, ASIC vs FPGA, VLSI design flow, Verilog HDL, data types, operators, advanced Verilog, assignments, structured procedures, synthesis coding style, finite state machines, and concludes with Verilog labs and solutions.

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Faisal Khan
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57 views

Curriculum-VLSI SoC Design Using Verilog HDL

The document outlines the curriculum for a course on VLSI SoC Design using Verilog HDL. The course contains 16 topics that cover VLSI introduction, SoC design, ASIC vs FPGA, VLSI design flow, Verilog HDL, data types, operators, advanced Verilog, assignments, structured procedures, synthesis coding style, finite state machines, and concludes with Verilog labs and solutions.

Uploaded by

Faisal Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI SoC Design using Verilog HDL Course Curriculum:

Topic 1: VLSI Introduction

 Lecture 1: Why VLSI?


 Lecture 2: Semiconductor Industry Overview

Topic 2: SoC Design

 Lecture 3: Smart Phone SoC


 Lecture 4: System On Chip Design Architecture and Methodology

Topic 3: ASIC Vs FPGA

 Lecture 5: ASIC Vs FPGA

Topic 4: VLSI Design Flow

 Lecture 6: VLSI Front-End Design Flow Part I


 Lecture 7: VLSI Front-End Design Flow Part II
 Lecture 8: VLSI Back-End Design Flow

Topic 5: Knowledge Check

 Quiz 1: Knowledge Check - VLSI SoC Design

Topic 6: Verilog HDL

 Lecture 9: Setting Expectations - Course Agenda


 Lecture 10: Introduction to Verilog HDL
 Quiz 2: Knowledge Check - Introduction to Verilog HDL

Topic 7: Data Types

 Lecture 11: Data Types


 Quiz 3: Knowledge Check - Data Types

Topic 8: Verilog Operators

 Lecture 12: Verilog Operators


 Quiz 4: Knowledge Check - Verilog Operators

Topic 9: Advanced Verilog for Verification

 Lecture 13: Advance Verilog for Verification


 Quiz 5: Knowledge Check - Advanced Verilog for Verification

Topic 10: Assignments

 Lecture 14: Assignments


 Quiz 6: Knowledge Check - Assignments

Topic 11: Structured Procedures

 Lecture 15: Structured Procedures


 Quiz 7: Knowledge Check - Structured Procedures

Topic 12: Synthesis Coding Style


 Lecture 16: Synthesis Coding Style
 Quiz 8: Knowledge Check - Synthesis Coding Style

Topic 13: Finite State Machine

 Lecture 17: Finite State Machine


 Quiz 9: Knowledge Check - Finite State Machine

Topic 14: Summary - Verilog HDL

 Lecture 18: Summary

Topic 15: Reference Material

 Lecture 19: Verilog HDL Reference Book

Topic 16: Verilog Labs

 Lecture 20: Instructions - Verilog Labs


 Lecture 21: Verilog Lab Manual
 Lecture 22: Download the Verilog Labs Folder
 Lecture 23: EDA Tools - Installation Guide
 Lecture 24: EDA Tools - User Guide
 Lecture 25: Solution to Lab 1
 Lecture 26: Solution to Lab 2
 Lecture 27: Solution to Lab 3
 Lecture 28: Solution to Lab 4
 Lecture 29: Solution to Lab 5
 Lecture 30: Solution to Lab 6
 Lecture 31: Solutions - Verilog Labs

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