A B C D E

1 1

LCFC Confidential
S145-IGM M/B FS440/FS541 Schematics Document
2 Intel Geminilake M-Processor with DDR4 + UMA 2

2018-07-09
REV:0.2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Cover Page

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 1 of 60
A B C D E
 A B C D E

LCFC confidential

HDMI (DDI 0)
HDMI Conn. Memory Bus DDR4 SO-DIMM
Page 32
1.2V DDR4 Page 17

1
eDP Conn eDP x2 Lane 1

USB2.0 x1
Int. Camera Conn. x1
USB2.0 Port6

USB3.0 x1
USB3.0 Conn
Int. MIC Conn. Page 29

Page 28

SATA Gen3 x1
SATA HDD
SATA Port0 Page 42

x1
NGFF PCI-Express USB3.0 Conn
SSD 4x Gen2 Geminilake-M USB2.0 x1
Page 31
Page 37

2 2

PCIe x1
BGA-1090
NGFF 24mm*25mm
USB2.0 x1 x1
WLAN&BT USB2.0 Conn
Page 31
(Support CNVi)
CNVi TDP 6W
PCIe Port5
USB2.0 Port7 Page 39

SPI SPI ROM (8MB)

W25Q64FWSSIQ
SPK Conn. Page 06
HD Audio x1

Codec & C/R USB2.0 x1 SPI TPM (Reserved)

HP&Mic
Combo Conn. Z32H330TC-SQN-725
Realtek Page 35

3
RTS5199 3
I2C Touch Pad
SD Conn.
USB2.0 Port5 Page 45
Page 4~16

LPC
IO Board

EC GPIO
IT8986E-BX_LQFP HALL Sensor Sub-board( for 14" 15")
Page 44 Page 45

Int.KBD
IO BOARD
Page 45 Thermal Sensor
(Reserved)
NCT7718W Page 38

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 2 of 60
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF ) PCIE PORT LIST
SIGNAL
STATE SLP_S0# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS/VTT Clock Port Device BIOS Device ID Map CLK REQ
+5VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON 0
+3VS
+3VALW_SOC +1.8VS S0IX(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON OFF 1 dGPU PCIe1(Func0):Root Port#3 CLKREQ0
V20B+ +3VALW +1.24VALW +1.2V +1.05VS 2
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 3
+1.8VALW +0.6VS
+3VL +5VALW 4 LAN PCIe0(Func0):Root Port#1 CLKREQ1
+CPU_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
State +5VL 5 WLAN PCIe0(Func1):Root Port#2 CLKREQ2
1 +VNN 1
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
BOM Structure Table
USB Port Table DDI PORT LIST BOM Structure BTO Item
S0 O O O O O XHCI Port Port device Port Device EMC@ For EMC part
EMC_NS@ For EMC un-stuff part
S3 DDI0 HDMI
O O O O X USB 3.0
0 USB3.0
DDI1 NC
EMC_15@ EMC 15" part
1 USB3.0 eDP eDP
S5 S4/AC Only 14@ For 14" part
O O O X X 0 15@ For 15" part

S5 S4 1 USB3.0 (2.0)
O X X X X RF@ For RF part
Battery only 2 BT
S5 S4 CD@ Cost Down part
3 USB3.0 (2.0)
AC & Battery X X X X X USB 2.0
4 USB2.0 DIS@ DIS SKU ID part
don't exist
UMA@ UMA SKU ID part
5 CARD READER
6 CAMERA
2
7 IGM@ IGM CPU SKU part 2

Touch Screen(RSVD)
SMBUS Control Table IGMR@ IGMR CPU SKU part

WLAN Thermal PCH TP

SOURCE VGA BATT IT8986HE SODIMM WiMAX Sensor Module Charger PMIC

LBG@ LBG project SKU part

EC_SMB_CK0 EC NEC@ NEC project SKU part
EC_SMB_DA0 +3VL X X V X X X X X X V CNVI@ CNVI SKU part

EC_SMB_CK1 EC
X V V X X X X X V X
EC_SMB_DA1 +3VL +3VL TMSEN@ Thermal Sensor part
TMSEN_UMA@ UMA Thermal Sensor part
EC_SMB_CK2 EC
X V X X V X X X X
EC_SMB_DA2 +3VS X +3VS
TPM@ TPM part
PCH_SMB_CLK PCH Debug@ USB debug feature part
PCH_SMB_DATA X X X V V X V X X X
+3VALW_SOC +3VS +3VS +3VALW_PCH USB@ Non USB debug feature part

TS@ Touch Screen part

3
EC SM Bus0 address EC SM Bus1 address EC SM Bus2 address PCH SM Bus address TS_LBG@ LBG project Touch Screen part
3

Device Address Device Address Device Address Device Address

TS_NEC@ NEC project Touch Screen part
PMIC 0x68 Smart Battery 0x16 Thermal Sensor 0x98(reserve) DDR SO-DIMM 0xA0
Charger 0x12 Wlan Rsvd UART@ UART debug part
RTCRST@ Clear RTCRST# function part

I2C4/I2C7 Bus address (Touch Pad) ME@ ME part

Device Address
@ un-stuff part
Slave 0x15 HDMI@ HDMI Logo part
Descriptor 0x0001
N4100@ GLK N4100 CPU part
N4000@ GLK N4000 CPU part
RCOMP RESISTOR REQUIREMENT N5000@ GLK N5000 CPU part
INTERFACE PIN NAME LOCATION VALUE(ohm)
N4100_QS@ GLK N4100 QS CPU part
MEM_CH0_RCOMP RC1 110 +/-1%
Memory
MEM_CH1_RCOMP RC2 110 +/-1%
HDA18@ HDA Bus 1.8V power part
USB2 USB2_RCOMP RC64 113 +/-1%
HDA33@ HDA Bus 3.3V power part
USB3/PCIe/SATA PCIE2_USB3_SATA3_RCOMP_P/N RC63 100 +/-1%
PCIe Refclk PCIE_REF_CLK_RCOMP RC62 56 +/-1%
4
DP/eDP*/HDMI* EDP_RCOMP_P/N RC79 100 +/-1% 4

MDSI MDSI_RCOMP RC78 150 +/-1%

NM_C111@ MB PCB part
CNVi CNV_WT_RCOMP RC48 150 +/-1%
NS_C121@ ODD PCB part
SMBUS/GPIO/EMMC for all 1.8V
only and 1.8V mode operation of EMMC_RCOMP RC20 200 +/-1%
1.8/3.3V CFIO interfaces Title
Security Classification LC Future Center Secret Data
Issued Date 2018/07/09 Deciphered Date 2019/07/08 Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 3 of 60
A B C D E
 5 4 3 2 1

DDRA_DQ[63:0] 17

DDRA_DQS[7:0] 17

DDRA_DQS#[7:0] 17

UC1A
DDR4_LP3_LP4 DDR4_LP3_LP4
DDRA_DQ40 BJ36 AT53 DDRA_DQS0
DDRA_DQ41 BK37 MEM_CH0_DQ40 MEM_CH0_DQS0_P AT55 DDRA_DQS#0
DDRA_DQ42 BJ35 MEM_CH0_DQ41 MEM_CH0_DQS0_N
DDRA_DQ43 BL36 MEM_CH0_DQ42 AW49 DDRA_DQS1
D DDRA_DQ44 BJ39 MEM_CH0_DQ43 MEM_CH0_DQS1_P AW48 DDRA_DQS#1 D
DDRA_DQ45 BL40 MEM_CH0_DQ44 MEM_CH0_DQS1_N
DDRA_DQ46 BJ40 MEM_CH0_DQ45 BC54 DDRA_DQS2
DDRA_DQ47 BK41 MEM_CH0_DQ46 MEM_CH0_DQS2_P BB53 DDRA_DQS#2
DDRA_DQ32 BA35 MEM_CH0_DQ47 MEM_CH0_DQS2_N
DDRA_DQ33 AY33 MEM_CH0_DQ32 AR41 DDRA_DQS3
DDRA_DQ34 BA33 MEM_CH0_DQ33 MEM_CH0_DQS3_P AR43 DDRA_DQS#3
DDRA_DQ35 AY35 MEM_CH0_DQ34 MEM_CH0_DQS3_N
DDRA_DQ36 BA37 MEM_CH0_DQ35 AV37 DDRA_DQS4
DDRA_DQ37 AY37 MEM_CH0_DQ36 MEM_CH0_DQS4_P AV35 DDRA_DQS#4
DDRA_DQ38 AY39 MEM_CH0_DQ37 MEM_CH0_DQS4_N
DDRA_DQ39 BA39 MEM_CH0_DQ38 BL38 DDRA_DQS5
DDRA_DQ56 BL34 MEM_CH0_DQ39 MEM_CH0_DQS5_P BJ38 DDRA_DQS#5
DDRA_DQ57 BL30 MEM_CH0_DQ56 MEM_CH0_DQS5_N
DDRA_DQ58 BJ29 MEM_CH0_DQ57 BF31 DDRA_DQS6
DDRA_DQ59 BK29 MEM_CH0_DQ58 MEM_CH0_DQS6_P BD31 DDRA_DQS#6
DDRA_DQ60 BJ33 MEM_CH0_DQ59 MEM_CH0_DQS6_N
DDRA_DQ61 BK33 MEM_CH0_DQ60 BJ32 DDRA_DQS7
DDRA_DQ62 BJ34 MEM_CH0_DQ61 MEM_CH0_DQS7_P BK31 DDRA_DQS#7
DDRA_DQ63 BJ30 MEM_CH0_DQ62 MEM_CH0_DQS7_N
DDRA_DQ48 BD29 MEM_CH0_DQ63 BG54
DDRA_DQ49 BF29 MEM_CH0_DQ48 DDR0 NCTF1 BH54
DDRA_DQ50 BH29 MEM_CH0_DQ49 NCTF2 BJ42
DDRA_DQ51 BF33 MEM_CH0_DQ50 NCTF3 BF39
DDRA_DQ52 MEM_CH0_DQ51 MEM_CH0_ODT1 DDRA_ODT1 17
BC29 BK43
DDRA_DQ53 MEM_CH0_DQ52 MEM_CH0_CS1_N DDRA_CS1# 17
BD33
DDRA_DQ54 BF35 MEM_CH0_DQ53 BL44
DDRA_DQ55 BH35 MEM_CH0_DQ54 NCTF4 BD39
MEM_CH0_DQ55 MEM_CH0_ODT0 BJ43 DDRA_ODT0 17
DDRA_DQ0 MEM_CH0_CS0_N DDRA_CS0# 17
AR53 BF54
DDRA_DQ1 MEM_CH0_DQ0 MEM_CH0_CKE1 DDRA_CKE1 17
AP55 BF55
DDRA_DQ2 AP53 MEM_CH0_DQ1 MEM_CH0_CKE0 DDRA_CKE0 17
DDRA_DQ3 AN54 MEM_CH0_DQ2 BE49
DDRA_DQ4 AU54 MEM_CH0_DQ3 MEM_CH0_CLK0_P BE51 DDRA_CLK0 17
DDRA_DQ5 MEM_CH0_DQ4 MEM_CH0_CLK0_N DDRA_CLK0# 17
AV53
DDRA_DQ6 AV55 MEM_CH0_DQ5 BC49
DDRA_DQ7 AW53 MEM_CH0_DQ6 MEM_CH0_CLK1_P BC48 DDRA_CLK1 17
DDRA_DQ8 MEM_CH0_DQ7 MEM_CH0_CLK1_N DDRA_CLK1# 17
C AU51 C
DDRA_DQ9 AU48 MEM_CH0_DQ8 BD45
DDRA_DQ10 MEM_CH0_DQ9 MEM_CH0_MA0 DDRA_MA0 17
AU49 BH50
DDRA_DQ11 MEM_CH0_DQ10 MEM_CH0_MA1 DDRA_MA1 17
BA46 BH47
DDRA_DQ12 BA48 MEM_CH0_DQ11 MEM_CH0_MA2 BF45 DDRA_MA2 17
DDRA_DQ13 MEM_CH0_DQ12 MEM_CH0_MA10 DDRA_MA10 17
BA49 BH43
DDRA_DQ14 BA51 MEM_CH0_DQ13 MEM_CH0_MA13 BD41 DDRA_MA13 17
DDRA_DQ15 MEM_CH0_DQ14 MEM_CH0_MA16 DDRA_MA16_RAS# 17
AR51 BH51
DDRA_DQ16 MEM_CH0_DQ15 MEM_CH0_BA1 DDRA_BS1# 17
AY55 BD43
DDRA_DQ17 BA54 MEM_CH0_DQ16 MEM_CH0_BA0 BF43 DDRA_BS0# 17
DDRA_DQ18 MEM_CH0_DQ17 MEM_CH0_BG1 DDRA_BG1 17
BA53 BF41
DDRA_DQ19 AY53 MEM_CH0_DQ18 MEM_CH0_ACT_N BG52 DDRA_ACT# 17
DDRA_DQ20 MEM_CH0_DQ19 MEM_CH0_MA3 DDRA_MA3 17
BC53
DDRA_DQ21 BD55 MEM_CH0_DQ20 BK45
DDRA_DQ22 BE54 MEM_CH0_DQ21 MEM_CH0_MA4 BJ46 DDRA_MA4 17
DDRA_DQ23 MEM_CH0_DQ22 MEM_CH0_MA5 DDRA_MA5 17
BD53 BJ44
DDRA_DQ24 AN43 MEM_CH0_DQ23 MEM_CH0_MA6 BJ47 DDRA_MA6 17
DDRA_DQ25 MEM_CH0_DQ24 MEM_CH0_MA7 DDRA_MA7 17
AN44 BJ45
DDRA_DQ26 MEM_CH0_DQ25 MEM_CH0_MA8 DDRA_MA8 17
AR48 BK47
DDRA_DQ27 AU41 MEM_CH0_DQ26 MEM_CH0_MA9 BJ51 DDRA_MA9 17
DDRA_DQ28 MEM_CH0_DQ27 MEM_CH0_MA11 DDRA_MA11 17
AU43 BJ52
DDRA_DQ29 AN41 MEM_CH0_DQ28 MEM_CH0_MA12 BJ48 DDRA_MA12 17
DDRA_DQ30 MEM_CH0_DQ29 MEM_CH0_MA14 DDRA_MA14_WE# 17
AN39 BJ50
DDRA_DQ31 MEM_CH0_DQ30 MEM_CH0_MA15 DDRA_MA15_CAS# 17
AU44 BL50
MEM_CH0_DQ31 MEM_CH0_BG0 DDRA_BG0 17
AY31 TP_DDRA_VREFDQ 1 TC208 @ VREF_DQ NOT APPLICABLE FOR DDR4
MEM_CH0_VREFDQ AV29
MEM_CH0_VREFCA DDRA_VREFCA 17
GEMINILAKE_FCBGA1090 1 OF 13
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (DDR4 CHA)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 4 of 60
5 4 3 2 1
 5 4 3 2 1

UC1B
DDR4_LP3_LP4 DDR4_LP3_LP4
AY3 BJ24
BD3 MEM_CH1_DQ40 MEM_CH1_DQS0_P BK25
BD1 MEM_CH1_DQ41 MEM_CH1_DQS0_N
BC3 MEM_CH1_DQ42 BD25
AY1 MEM_CH1_DQ43 MEM_CH1_DQS1_P BF25
BA3 MEM_CH1_DQ44 MEM_CH1_DQS1_N
BA2 MEM_CH1_DQ45 BL18
D
BE2 MEM_CH1_DQ46 MEM_CH1_DQS2_P BJ18 D
AR8 MEM_CH1_DQ47 MEM_CH1_DQS2_N
AN15 MEM_CH1_DQ32 AV19
AN17 MEM_CH1_DQ33 MEM_CH1_DQS3_P AV21
AU12 MEM_CH1_DQ34 MEM_CH1_DQS3_N
AN12 MEM_CH1_DQ35 AR13
AN13 MEM_CH1_DQ36 MEM_CH1_DQS4_P AR15
AU13 MEM_CH1_DQ37 MEM_CH1_DQS4_N
AU15 MEM_CH1_DQ38 BB3
AP3 MEM_CH1_DQ39 MEM_CH1_DQS5_P BC2
AU2 MEM_CH1_DQ56 MEM_CH1_DQS5_N
AV3 MEM_CH1_DQ57 AW7
AW3 MEM_CH1_DQ58 MEM_CH1_DQS6_P AW8
AN2 MEM_CH1_DQ59 MEM_CH1_DQS6_N
AP1 MEM_CH1_DQ60 AT1
AR3 MEM_CH1_DQ61 MEM_CH1_DQS7_P AT3
AV1 MEM_CH1_DQ62 MEM_CH1_DQS7_N
AR5 MEM_CH1_DQ63 BH9
BA8 MEM_CH1_DQ48 DDR1 MEM_CH1_MA0 BC13
AU7 MEM_CH1_DQ49 MEM_CH1_MA1 BD11
AU5 MEM_CH1_DQ50 MEM_CH1_MA2 BD13
BA5 MEM_CH1_DQ51 MEM_CH1_MA3 BF11
BA7 MEM_CH1_DQ52 MEM_CH1_MA10 BE5
AU8 MEM_CH1_DQ53 MEM_CH1_MA13 BH5
BA10 MEM_CH1_DQ54 MEM_CH1_MA16 BH6
MEM_CH1_DQ55 MEM_CH1_BA0 BF13
BJ26 MEM_CH1_BA1 BG4
BL26 MEM_CH1_DQ0 MEM_CH1_BG1 BE7
BJ27 MEM_CH1_DQ1 MEM_CH1_ACT_N
BK27 MEM_CH1_DQ2 BK11
BJ23 MEM_CH1_DQ3 MEM_CH1_MA11 BJ12
BK23 MEM_CH1_DQ4 MEM_CH1_MA12 BK9
BJ22 MEM_CH1_DQ5 MEM_CH1_MA14 BJ11
BL22 MEM_CH1_DQ6 MEM_CH1_MA15 BJ10
BD27 MEM_CH1_DQ7 MEM_CH1_BG0 BJ4
BF27 MEM_CH1_DQ8 MEM_CH1_MA4 BL6
BH27 MEM_CH1_DQ9 MEM_CH1_MA5 BJ5
BC27 MEM_CH1_DQ10 MEM_CH1_MA6 BJ9
C C
BH21 MEM_CH1_DQ11 MEM_CH1_MA7 BJ6
BF23 MEM_CH1_DQ12 MEM_CH1_MA8 BJ8
BD23 MEM_CH1_DQ13 MEM_CH1_MA9
BF21 MEM_CH1_DQ14 BF17
BK19 MEM_CH1_DQ15 MEM_CH1_CLK0_P BD17
BJ20 MEM_CH1_DQ16 MEM_CH1_CLK0_N
BL20 MEM_CH1_DQ17 BF15
BJ21 MEM_CH1_DQ18 MEM_CH1_CLK1_P BH15
BJ17 MEM_CH1_DQ19 MEM_CH1_CLK1_N
BJ16 MEM_CH1_DQ20 BJ13
BK15 MEM_CH1_DQ21 NCTF7 BL12
BL16 MEM_CH1_DQ22 NCTF8 BF1
BA21 MEM_CH1_DQ23 NCTF5 BF2
AY23 MEM_CH1_DQ24 MEM_CH1_CS1_N BC7
BA23 MEM_CH1_DQ25 MEM_CH1_ODT1
BA17 MEM_CH1_DQ26 BH2
AY21 MEM_CH1_DQ27 MEM_CH1_CS0_N BC8
AY17 MEM_CH1_DQ28 MEM_CH1_ODT0 BG2
AY19 MEM_CH1_DQ29 NCTF6 BK13
BA19 MEM_CH1_DQ30 MEM_CH1_CKE0 BJ14
MEM_CH1_DQ31 MEM_CH1_CKE1
AY29 DDRA_RCOMP RC1 1 2 110_0402_1%
MEM_CH0_RCOMP
BC15 DDRB_DRAMRST# 1 TP53 @
MEM_CH1_RESET_N AY27 DDRB_RCOMP RC2 1 2 110_0402_1%
MEM_CH1_RCOMP
AV27 con irm with G330 IGM， left SI unconnected,
MEM_CH1_VREFCA AY25 but Rcomp should connected__bron
MEM_CH1_VREFDQ
BC43 DDRA_DRAMRST#
MEM_CH0_RESET_N

GEMINILAKE_FCBGA1090 2 OF 13
@

B B
Follow CRB&PDG v1.2

+1.2V
1

RC3
1K_0402_1%
2

con irm with G330 IGM， follow CRB__bron

DDRA_DRAMRST# RC4 1 2 0_0402_5% DDRA_DRAMRST#_R

DDRA_DRAMRST#_R 17

Different with APL CRB(1K damping resistor)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (DDR4 CHB)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 5 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW_SOC

UC1G
LPC_CLKRUN#_R RC6 2 @ 1 10K_0402_5%
C26 L29
B25 AVS_I2S0_MCLK RSVD RSVD6 LPC_FRAME#_R RC27 2 @ 1 10K_0402_5%
C25 AVS_I2S0_BCLK M29
C24 AVS_I2S0_WS_SYNC RSVD5 P29 LPC_SERIRQ_R RC28 2 @ 1 10K_0402_5%
15 GPIO_159 B23 AVS_I2S0_SDI RSVD7 M27
AVS_I2S0_SDO AUDIO-AVS RSVD8 P27
M23 RSVD9 L27
SD Card I/F, Intel have changed to RSVD
L21 AVS_I2S1_MCLK RSVD3 L25
D
J21 AVS_I2S1_BCLK RSVD4 P25 D
15 GPIO_163 M21 AVS_I2S1_WS_SYNC RSVD2 L23
15 GPIO_164 AVS_I2S1_SDI RSVD10
P23
AVS_I2S1_SDO J25
LPC BUS I/O Voltage is controlled by Hardware Strap(GPIO_83)
34 HDA_BITCLK_AUDIO
HDA_BITCLK_AUDIO RC5 1 2 33_0402_5% HDA_BITCLK_AUDIO_R A22 RSVD1 Need BIOS soft strap to 3.3V
HDA_SYNC_AUDIO RC7 1 2 33_0402_5% HDA_SYNC_AUDIO_R C23 AVS_HDA_BCLK
34 HDA_SYNC_AUDIO AVS_HDA_WS_SYNC
15,34 HDA_SDIN0_GPIO_168 B21
HDA_SDOUT_AUDIO RC8 1 2 33_0402_5% HDA_SDOUT_AUDIO_R C22 AVS_HDA_SDI C37 CLK_PCI_EC_R RC11 2 1 33_0402_5%
34 HDA_SDOUT_AUDIO AVS_HDA_SDO LPC_CLKOUT0 CLK_PCI_EC 44
1HDA_RST_AUDIO# RC10 1 @ 2 33_0402_5% HDA_RST_AUDIO#_R C21 A38
TC203 AVS_HDA_RST_N LPC_CLKOUT1
@ B19 LPC/eSPI A34 LPC_AD0_R RC12 1 2 1/16W_20_5%_0402
AVS_DMIC_CLK_A1 LPC_AD0 LPC_AD1_R LPC_AD0 44
C20 C34 RC13 1 2 1/16W_20_5%_0402
15 GPIO_172 AVS_DMIC_CLK_B1 LPC_AD1 LPC_AD2_R LPC_AD1 44
C19 B35 RC14 1 2 1/16W_20_5%_0402 LPC_AD2 44
C18 AVS_DMIC_DATA_1 LPC_AD2 C35 LPC_AD3_R RC15 1 2 1/16W_20_5%_0402
15 GPIO_174 AVS_DMIC_CLK_AB2 LPC_AD3 LPC_AD3 44
For EMI A18
15 GPIO_175 AVS_DMIC_DATA_2 C33 LPC_CLKRUN#_R RC16 1 2 0_0402_5% LPC_CLKRUN#_EC 44
CC4220 1 2 22P_0201_258J HDA_BITCLK_AUDIO_R LPC_CLKRUN_N B33 LPC_FRAME#_R RC18 1 2 0_0402_5%
LPC_FRAME_N LPC_FRAME# 44
J13 B37 LPC_SERIRQ_R RC19 1 2 0_0402_5%
L15 EMMC_CLK LPC_SERIRQ LPC_SERIRQ 44
@
CC4221 1 2 2P_25V_NPO_0201 HDA_SYNC_AUDIO EMMC_RCLK
M19
@ H19 EMMC_D0 B29 SPI_CLK RC9461 1 2 0_0402_5% PCH_SPI_CLK_R
CC4222 1 2 2P_25V_NPO_0201 HDA_SDOUT_AUDIO J19 EMMC_D1 FST_SPI_CLK
P17 EMMC_D2 B31 SPI_D0 RC9462 1 2 0_0402_5% PCH_SPI_D0_R
P19 EMMC_D3 FST_SPI_MOSI_IO0 C30 SPI_D1 RC9463 1 2 0_0402_5% PCH_SPI_D1_R
Close to PCH EMMC_D4 FST_SPI_MISO_IO1
J15 eMMC FAST_SPI A30 SPI_D2 RC25 1 2 0_0402_5% PCH_SPI_D2
L17 EMMC_D5 FST_SPI_IO2 C29 SPI_D3 RC26 1 2 0_0402_5% PCH_SPI_D3
M17 EMMC_D6 FST_SPI_IO3
EMMC_D7 Place all damping resisor near SPI ROM for minimum SPI Stub
M13 C31 PCH_SPI_CS0#_R
EMMC_CMD FST_SPI_CS0_N C32 PCH_SPI_CS1#_R RC1647 2 @ 1 33_0402_5%
For unused EMMC interface, refer PDG. NC for all signals, except the FST_SPI_CS1_N TPM_SPI_CS# 7,35
U44
EMMC_RCOMP, which requires PD termination. -------intel schematic check list G51 EMMC_RST_N
RC20 2 1 200_0402_1% EMMC_RCOMP L13 EMMC_PWR_EN_N
EMMC_RCOMP for reserve,CRB use SIO_SPI_0_FS1
GEMINILAKE_FCBGA1090 7 OF 13
@
C C

SPI ROM PCH_SPI_CLK_R RC21 1 2 0_0402_5% PCH_SPI_CLK

RC41 1 2 0_0402_5% +VCC_SPI

EC_SPI_CLK 44
LPC_AD3 CC380 1 2 27P_0402_50V8J EMC_NS@
RC1642 1 2 10_0402_5% RC32 1 @ 2 100K_0402_5% PCH_SPI_CS0#
TPM@
TPM_SPI_CLK 35 LPC R/C close to PCH
LPC_AD2 CC381 1 2 27P_0402_50V8J EMC_NS@
RC33 1 2 3.3K_0402_5% PCH_SPI_D2
RC34 1 2 3.3K_0402_5% PCH_SPI_D3
LPC_AD1 CC382 1 2 27P_0402_50V8J EMC_NS@
PCH_SPI_CS0#_R RC22 2 1 0_0402_5% PCH_SPI_CS0#
Follow CRB: set WP# and HOLD# PU LPC_AD0 CC383 1 2 27P_0402_50V8J EMC_NS@
RC42 2 1 0_0402_5%
EC_SPI_CS0# 44
CLK_PCI_EC CC384 1 2 27P_0402_50V8J EMC_NS@

PCH_SPI_D0_R RC23 1 2 0_0402_5% PCH_SPI_D0

RC43 1 2 0_0402_5%
EC_SPI_D0 44
RC1644 1 2 10_0402_5%
TPM_SPI_MOSI 35
TPM@

PCH_SPI_D1_R RC24 1 2 0_0402_5% PCH_SPI_D1

RC44 1 2 0_0402_5%
EC_SPI_D1 44 Ball Name Signal Name I/O Voltage Default Term Buffer Type
RC1645 1 2 10_0402_5%
TPM@
TPM_SPI_MISO 35 FST_SPI_CS0_N PCH_SPI_CS0# 1.8V Native HSMV
B FST_SPI_MOSI_IO0 PCH_SPI_D0 1.8V Native HSMV B

FST_SPI_MISO_IO1 PCH_SPI_D1 1.8V Native HSMV

Near place RC21&RC41; RC22&42; RC23&RC43; RC24&RC44
FST_SPI_IO2 PCH_SPI_D2 1.8V Native HSMV
FST_SPI_IO3 PCH_SPI_D3 1.8V Native HSMV
FST_SPI_CLK PCH_SPI_CLK 1.8V Native HSMV

+1.8VALW
1

RC31
0_0402_5%
2

UC2 50mA
PCH_SPI_CS0# 1 8 +VCC_SPI
PCH_SPI_D1 2 /CS VCC 7 PCH_SPI_D3
5P_50V_B_NPO_0402

PCH_SPI_D2 3 DO(IO1) /HOLDor/RESET(IO3) 6 PCH_SPI_CLK

/WP(IO2) CLK 2 1
4 5 PCH_SPI_D0
GND DI(IO0) @ CC258
W25Q64FWSSIQ_SO8 C2092 0.1U_0201_6.3V6-K
1 2
1.8V SPI ROM

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Audio,eMMC,LPC,SPI)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 6 of 60
5 4 3 2 1
 5 4 3 2 1

UC1F

U49 M39 GPIO_79 15

U51 SIO_I2C0_SCL SIO_SPI_0_CLK
LPSS_SPI
SIO_I2C0_SDA J37
LPSS_I2C SIO_SPI_0_TXD GPIO_83 15
U46 L39
U48 SIO_I2C1_SCL SIO_SPI_0_RXD L37
GPIO_80 15
need BIOS remove GPIO 20K PD_bron
+1.8VALW SIO_I2C1_SDA SIO_SPI_0_FS0 J39
SIO_SPI_0_FS1 GPIO_81 15
AA39 RC1643 2 TPM@ 1 33_0402_5% TPM_SPI_CS# 6,35
AA41 SIO_I2C2_SCL M37
RPC21 SIO_I2C2_SDA SIO_SPI_2_CLK GPIO_84 15
1 4 DBG_I2C3_SDA DBG_I2C3_SCL R44 M33
DBG_I2C3_SCL DBG_I2C3_SDA SIO_I2C3_SCL SIO_SPI_2_TXD GPIO_89 15
2 3 R43 P35
for use debug SIO_I2C3_SDA SIO_SPI_2_RXD P33
GPIO_85 15
2.2K_0404_4P2R_5% TP_I2C4_SCL R49 SIO_SPI_2_FS0 P37
Reserve For TouchPad TP_I2C4_SDA SIO_I2C4_SCL SIO_SPI_2_FS1 GPIO_86 15
@ R51 L35 GPIO_87 15
SIO_I2C4_SDA SIO_SPI_2_FS2
29 USBDEBUG C50
D
RC9466 1 @ 2 0_0402_5% A50 SIO_I2C5_SCL D
39 PM_SLP_WLAN# SIO_I2C5_SDA
C48
C47 SIO_I2C6_SCL N54
+3VALW_SOC SIO_I2C6_SDA SIO_UART0_TXD GPIO_61 15
P53
TP_I2C7_SCL B47 SIO_UART0_RXD N53
TP_I2C7_SDA SIO_I2C7_SCL SIO_UART0_RTS_N GPIO_62 15
C46 M55
RC45 1 @ 2 1K_0402_5% PCH_SMB_ALERT# SIO_I2C7_SDA SIO_UART0_CTS_N
PCH_SMB_ALERT# A26 L54
Need Confirm PU is Stuff or Not, CRB v1.2 Reserve PCH_SMB_CLK_GPIO_177 SMB_ALERT_N SIO_UART2_TXD SOC_UART_TXD_GPIO_65 15,39
15 PCH_SMB_CLK_GPIO_177 B27 M53 SOC_UART_RXD 39
PCH_SMB_DATA C27 SMB_CLK LPSS SMBus SIO_UART2_RXD K53
SMB_DATA SIO_UART2_RTS_N GPIO_66 15 TPM_SPI_IRQ#
SMBus Alert is open drain, and it has 20 KΩ internal pull-up. L53 RC9460 1 TPM@ 2 0_0402_5%
SIO_UART2_CTS_N TPM_SPI_IRQ# 35

CLKIN_XTAL_LCP CNV_WR_CLKP H29 Only UART2 supports debug functionality follow CRB
39 CNV_WR_CLKP CNV_WR_CLKN CNV_WGR_CLK_P
H31
39 CNV_WR_CLKN CNV_WGR_CLK_N
CNV_WR_D0P M31
39 CNV_WR_D0P
1

CNVI@ CNV_WR_D0N P31 CNV_WGR_D0_P LPSS_UART

39 CNV_WR_D0N CNV_WGR_D0_N
RC267
10K_0402_1% CNV_WR_D1P D29
CNVI_RF_RST#_GPIO_195 39 CNV_WR_D1P CNV_WR_D1N F29 CNV_WGR_D1_P
39 CNV_WR_D1N CNV_WGR_D1_N CNVI
2

CNV_WT_CLKP F35
39 CNV_WT_CLKP CNV_WT_CLK_P
1

CNV_WT_CLKN D35
75K_0402_5%

39 CNV_WT_CLKN CNV_WT_CLK_N
CNVI@

RC3063

CNV_WT_D0P J35
39 CNV_WT_D0P CNV_WT_D0N CNV_WT_D0_P
H35
39 CNV_WT_D0N CNV_WT_D0_N
2

CNV_WT_D1P L31
39 CNV_WT_D1P CNV_WT_D1N CNV_WT_D1_P
J31
39 CNV_WT_D1N CNV_WT_D1_N
CLKIN_XTAL_LCP suggest reserve a pull down.
CLKIN_XTAL_LCP J29
39 CLKIN_XTAL_LCP CLKIN_XTAL_LCP
F19
15,39 XTAL_CLKREQ_GPIO_196 XTAL_CLKREQ
RC9450 1 CNVI@ 2 33_0402_5% CNVI_BRI_DT_R H17
15,39 CNVI_BRI_DT_GPIO_191 J17 CNV_BRI_DT
15,39 CNVI_BRI_RSP_GPIO_192 CNV_BRI_RSP
C RC9451 1 CNVI@ 2 33_0402_5% CNVI_RGI_DT_R D19 C
15,39 CNVI_RGI_DT_GPIO_193 D17 CNV_RGI_DT
15,39 CNVI_RGI_RSP_GPIO_194 CNV_RGI_RSP
15,39 CNVI_RF_RST#_GPIO_195 F17
CNV_RF_RESET_N
RC48 1 2 150_0402_1% CNVI_WT_RCOMP F33
Intel recommends Max routing length shorter than 1000mils, CNV_WT_RCOMP
spacing with other signals larger than 15mils.

GEMINILAKE_FCBGA1090 6 OF 13
@

+1.8VALW +3VALW +3VS +3VS

+1.8VALW

1
2
1
2

3
4
RPC2
@ 2.2K_0404_4P2R_5%
RPC1
RP16

5
1K_0404_4P2R_5% 2.2K_0404_4P2R_5%

4
3
2

@ QC2B
4
3

2
1
G1

TP_I2C4_SDA 1 6 TP_I2C4_SDA_M 3 4 TP_I2C4_SDA_R

S
S1 D1 TP_I2C4_SDA_R 45

D
L2N7002KDW1T1G_SOT363-6
QC1A 0_0402_5% 2 @ 1 RC55
PJT7838_SOT363-6

2
G
5

@ QC2A
B B
G2

TP_I2C4_SCL 4 3 TP_I2C4_SCL_M 6 1 TP_I2C4_SCL_R

S
S2 D2 TP_I2C4_SCL_R 45

D
DMN5L06DWK-7[Vgs(th)max=1.0V] L2N7002KDW1T1G_SOT363-6 The I2C signals are open drain, and it has internal pull-up.
SCH GLK request MOSFET output capacitance less than 10pF A 1 kΩ±5% for external pull-up resistor is recommended.
QC1B 0_0402_5% 2 @ 1 RC57
PJT7838_SOT363-6 Reserve Touch Pad I2C LS(MOS and IC) Lewis 2016/10/21

TP_I2C7_SDA RC58 1 2 0_0402_5% TP_I2C4_SDA_M

I2C7 I/O Voltage is 3.3V TP_I2C7_SCL RC59 1 2 0_0402_5% TP_I2C4_SCL_M

Need Confirm I2C7 PU Power Rail with Intel

Maybe Can Connect to TP_I2C4_SDA_R

SMBus +3VALW_SOC +3VS +3VS

1
2

1
2

RPC3 RPC4
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%
4
3

4
3
2
G

@ @

PCH_SMB_CLK_GPIO_177 6 1 SMB_CLK_S3
S

SMB_CLK_S3 17,39
D

@
QC3A
5

A A
G

L2N7002KDW1T1G_SOT363-6

PCH_SMB_DATA 3 4 @ SMB_DATA_S3
S

SMB_DATA_S3 17,39
D

L2N7002KDW1T1G_SOT363-6
QC3B

PCH_SMB_CLK_GPIO_177 RC60 1 2 0_0402_5% SMB_CLK_S3

PCH_SMB_DATA RC61 1 2 0_0402_5% SMB_DATA_S3 Title
Security Classification LC Future Center Secret Data
SMB_CLK&SMB_DATA is OD(PDG v1.2 P309), Reserve MOS LS, Keep +3VS PU, CRB w/o PU, need BIOS check if have internal PU Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (I2C,SMBus,CNVi,UART)
I/O Voltage is controlled by Hardware Strap(GPIO_163: PD) & Soft Strap 3.3(default)(SMIP v0.82 P84) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
SMBUS I/O Voltage is controlled by Hardware Strap(GPIO_163) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 7 of 60
5 4 3 2 1
 5 4 3 2 1

UC1D

RC62 1 2 56_0402_1% PCIE_REF_CLK_RCOMP L10 H1

PCIE_REF_CLK_RCOMP SATA_P1_USB3_P5_TXP H2
CLK_PCIE_SSD R12 SATA_P1_USB3_P5_TXN
37 CLK_PCIE_SSD PCIE_CLKOUT0P
CLK_PCIE_SSD# R10 SATA/USB3 H4
37 CLK_PCIE_SSD# PCIE_CLKOUT0N SATA_P1_USB3_P5_RXP G5
N7 SATA_P1_USB3_P5_RXN
N5 PCIE_CLKOUT1P
PCIE_CLKOUT1N PCIe B15 USB30_TX_P0
CLK_PCIE_WLAN USB3_P0_TXP USB30_TX_N0 USB30_TX_P0 29
39 CLK_PCIE_WLAN R7 C15
CLK_PCIE_WLAN# PCIE_CLKOUT2P USB3_P0_TXN USB30_TX_N0 29
R5
39 CLK_PCIE_WLAN# PCIE_CLKOUT2N F15 USB30_RX_P0
USB30_RX_P0 29
USB3.0
N8 USB3_P0_RXP D15 USB30_RX_N0
PCIE_CLKOUT3P USB3_P0_RXN USB30_RX_N0 29
N10
PCIE_CLKOUT3N USB3 C14 USB30_TX_P1
USB3_P1_TXP USB30_TX_N1 USB30_TX_P1 31
A14
USB3_P1_TXN USB30_TX_N1 31
E2
D 37 PCIE_PTX_DRX_P0 F2 PCIE_P0_TXP J11 USB30_RX_P1
USB30_RX_P1 31
USB3.0 D
37 PCIE_PTX_DRX_N0 PCIE_P0_TXN USB3_P1_RXP H11 USB30_RX_N1
USB3_P1_RXN USB30_RX_N1 31
G7
37 PCIE_PRX_DTX_P0 H6 PCIE_P0_RXP
37 PCIE_PRX_DTX_N0 PCIE_P0_RXN C10
PCIE_P3_USB3_P4_TXP PCIE_PTX_DRX_P3 37
A10 PCIE_PTX_DRX_N3 37
A7 PCIE_P3_USB3_P4_TXN
37 PCIE_PTX_DRX_P1 C7 PCIE_P1_TXP PCIe/USB3 H9
SSD
SSD 37 PCIE_PTX_DRX_N1 PCIE_P1_TXN PCIE_P3_USB3_P4_RXP F9
PCIE_PRX_DTX_P3 37
PCIE_P3_USB3_P4_RXN PCIE_PRX_DTX_N3 37
D4
37 PCIE_PRX_DTX_P1 E5 PCIE_P1_RXP C11
37 PCIE_PRX_DTX_N1 PCIE_P1_RXN PCIE_P4_USB3_P3_TXP B11
C9 PCIE_P4_USB3_P3_TXN
37 PCIE_PTX_DRX_P2 PCIE_P2_TXP
B9 D11
37 PCIE_PTX_DRX_N2 PCIE_P2_TXN PCIE_P4_USB3_P3_RXP F11
E7 PCIE_P4_USB3_P3_RXN
37 PCIE_PRX_DTX_P2 PCIE_P2_RXP PCIE_PTX_DRX_P5 PCIE_PTX_C_DRX_P5
37 PCIE_PRX_DTX_N2
F6 B13 CC273 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P5 39
PCIE_P2_RXN PCIE_P5_USB3_P2_TXP C13 PCIE_PTX_DRX_N5 CC274 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_N5
PCIE_P5_USB3_P2_TXN PCIE_PTX_C_DRX_N5 39
F13 PCIE_PRX_DTX_P5 WLAN
PCIE_P5_USB3_P2_RXP PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 39
D13 PCIE_PRX_DTX_N5 39
SSD_CLKREQ#_Q A46 PCIE_P5_USB3_P2_RXN
PCIE_CLKREQ_1# C45 PCIE_CLKREQ0_N C5 PCIE_USB3_SATA_RCOMP_DN
WLAN_CLKREQ#_Q B45 PCIE_CLKREQ1_N PCIE2_USB3_SATA3_RCOMP_N C6 PCIE_USB3_SATA_RCOMP_DP
PCIE_CLKREQ2_N PCIE2_USB3_SATA3_RCOMP_P

2
PCIE_CLKREQ_3# C44
PCIE_CLKREQ3_N RC63
PCIE_WAKE0# F47 AA10 100_0402_1%
PCIE_WAKE1# D47 PCIE_WAKE0_N NC1 AA8
PCIE_WAKE2# F45 PCIE_WAKE1_N NC2

1
PCIE_WAKE3# D50 PCIE_WAKE2_N W13
PCIE_WAKE3_N SSIC NC3 W12 Intel recommends to add a VSS shield at least 4Mmils
NC4 wide to shield between PCIE2_USB3_SATA3_RCOMP_P /
PCIE2_USB3_SATA3_RCOMP_N trace and adjacent I/O.
U15
SATA NC5

SATA_PTX_DRX_P0 J3 U7
42 SATA_PTX_DRX_P0 SATA_P0_TXP USB2_DP0
SATA_PTX_DRX_N0 J2 U5
42 SATA_PTX_DRX_N0 SATA_P0_TXN USB2_DN0
HDD SATA_PRX_DTX_P0 J7 N2 USB20_P1
42 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 SATA_P0_RXP USB2_DP1 USB20_N1 USB20_P1 29
J5 N3
42 SATA_PRX_DTX_N0 SATA_P0_RXN USB2_DN1 USB20_N1 29 USB 2.0( for standard USB 3.0 port)
C L2 USB20_P2 C
USB2_DP2 USB20_N2 USB20_P2 39
L3
USB2_DN2 USB20_N2 39 BT
R13 USB20_P3
USB2
USB2_DP3 R15 USB20_N3 USB20_P3
USB20_N3
31
31
USB 2.0( for standard USB 3.0 port)
USB2_DN3
M1 USB20_P4
USB2_DP4 M3 USB20_N4 USB20_P4
USB20_N4
31
31
USB 2.0( for standard USB 2.0 port)
USB2_DN4
R2 USB20_P5
USB2_DP5 R3 USB20_N5 USB20_P5
USB20_N5
34
34
CARD READER
USB2_DN5
P1 USB20_P6
USB2_DP6 P3 USB20_N6 USB20_P6 28 CAMERA
USB2_DN6
USB20_P7
USB20_N6 28
USB DUAL ROLE +1.8VALW
U8
USB2_DP7 U10 USB20_N7 USB20_P7
USB20_N7
28
28
Touch Screen
USB2_DN7 USB_OTG_ID RC65 2 @ 1 10K_0402_5%
U12 USB2_RCOMP RC64 1 2 113_0402_1% RC66 1 @ 2 0_0402_5%
USB2_RCOMP Intel recommends to add a VSS shield at least 4Mmils
V1 USB_OTG_ID wide to shield between USB2_RCOMP and adjacent I/O.
PCIE Configuration USB2_DUALROLE
USB2_VBUS_SNS
V3
U54
USB_VBUSSNS
USB_OC0#_GPIO_44 +1.8VALW
USB2_OC0_N USB_OC1#_GPIO_45 USB_OC0#_GPIO_44 15
U53
Port Config Device Name:Dev:Fun:DID:Root Port USB2_OC1_N USB_OC1#_GPIO_45 15,29,31
USB_VBUSSNS RC67 2 @ 1 10K_0402_5%
P0 GEMINILAKE_FCBGA1090 4 OF 13 RC68 1 2 0_0402_5%
@
P1
X4 SSD PCIe1(Func0):19:0:0x31D8:2 Follow PDG v1.2 P195 USB2.0 Disabling and Termination Guidelines
P2 When the platform does not use the USB2_OTG_ID, USB2_VBUS_SNS, and
USB2_OC0/1_N pins:
P3 USB2_OTG_ID and USB2_OC[x]_N pins can be left unconnected.
USB2_VBUS_SNS needs to be connected to GND.
P4 X1 PCIe0(Func0):20:0:0x31D6:0
P5 X1 WLAN PCIe0(Func1):20:1:0x31D7:1
USB OCP
Follow CRB un-stuff OC# PU+1.8VALW
resistor
CLOCK REQUEST Need Check LAN WAKE RPC5
B +1.8V_3.3V_PU CLKREQ can be set 1.8V/3.3V by soft strap USB_OC0#_GPIO_44 2 3 B

RPC6 CLKREQ0/2/4 default 3.3V USB_OC1#_GPIO_45 1 4

+1.8V_3.3V_PU
5 4 SSD_CLKREQ#_Q CLKREQ1 default 1.8V PCIE_WAKE[3:0]_N I/O Voltage is controlled by Soft Straps 10K_0404_4P2R_5%
6 3 WLAN_CLKREQ#_Q
7 2 PCIE_CLKREQ_3# PCIE_CLKREQ[3:0]_N I/O Voltage is controlled by Soft Straps @
8 1 PCIE_CLKREQ_1# RPC7
8 1 PCIE_WAKE0#
10K_0804_8P4R_5% 7 2 PCIE_WAKE2# WAKE0/2/3 default 3.3V
6 3 PCIE_WAKE3# WAKE1 default 1.8V
PCIE_WAKE1#
+3VS +3VS
5 4 WAKE1 need BIOS soft strap to 3.3V
10K_0804_8P4R_5%
PCIE_WAKE 1.8/3.3 Can be Set by Soft Straps
Need Confirm if Can Use PCIE_WAKE0 1.8/3.3(Default) for LAN_WAKE
10K_0402_5%

10K_0402_5%

or SW set PCIE_WAKE1# to 3.3V

2

@
RC71

RC75

+3VALW
SSD_CLKREQ#_Q
@
1

+1.8V_3.3V_PU
3

D QC5B
+3VS 5 RC73
G @ 10K_0402_5%
L2N7002KDW1T1G_SOT363-6
S @
4

1
2

D QC5A
RC72 2
SSD_CLKREQ# 37
@ 10K_0402_5% G QC6
L2N7002KDW1T1G_SOT363-6 PCIE_WAKE1# 3 1 PCIE_WAKE#
PCIE_WAKE# 39,44
S @
1

WLAN_CLKREQ#_Q @
LSI1012XT1G_SC-89-3
3

D QC4B LSI1012XT1G [Vgs(th)<1.0V]

5
G
L2N7002KDW1T1G_SOT363-6 PCIE_WAKE1# RC252 1 2 0_0402_5% PCIE_WAKE#
S
4

D QC4A
@ SSD_CLKREQ#_Q SSD_CLKREQ#
2 WLAN_CLKREQ# 39 RC3062 1 2 0_0402_5%
A G A
L2N7002KDW1T1G_SOT363-6
S
1

WLAN_CLKREQ#_Q RC253 1 2 0_0402_5% WLAN_CLKREQ#

Security Classification LC Future Center Secret Data Title
CLKREQ can be set 1.8V/3.3V by soft strap Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (PCIE&GPIO&SPI)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 8 of 60

5 4 3 2 1
 5 4 3 2 1

UC1C DDI PORT LIST

HDMI D2 32 HDMI_TX2+
HDMI_TX2+
HDMI_TX2-
AH1
AH3 DDI0_TXP_0 MDSI_A_CLKP
AL2
AM3
Port Device HPD Net HPD Pin
32 HDMI_TX2- DDI0_TXN_0 MDSI_A_CLKN

HDMI D1 32 HDMI_TX1+
HDMI_TX1+ AE2 AG13 DDI0 HDMI HDMI_HPD# C39
HDMI_TX1- AE3 DDI0_TXP_1 MDSI_C_CLKP AG12
32 HDMI_TX1- DDI0_TXN_1 DDI0/DDI_B MDSI_C_CLKN DDI1 N/A N/A C38
HDMI_TX0+ AJ2
HDMI D0 32
32
HDMI_TX0+
HDMI_TX0-
HDMI_TX0- AJ3 DDI0_TXP_2 AN5 EDP eDP EDP_HPD# B39
DDI0_TXN_2 MDSI_A_DP_0 AN7
HDMI_CLK+ AG2 MDSI_A_DN_0
HDMI CLK 32 HDMI_CLK+
HDMI_CLK- AG3 DDI0_TXP_3 AJ15
D 32 HDMI_CLK- DDI0_TXN_3 MDSI_A_DP_1 D
AJ17
AC12 MDSI MDSI_A_DN_1
AC10 DDI0_AUXP AJ7
+3VS +1.8V_3.3V_PU DDI0_AUXN MDSI_A_DP_2 AJ5
DDC Signals Can Be Set to 1.8/3.3(Default) by Soft Straps MDSI_A_DN_2
32 HDMI_HPD# C39
DDI0_HPD AJ10
DDPB_CLK B43 MDSI_A_DP_3 AJ12
32 DDPB_CLK DDI0_DDC_SCL MDSI_A_DN_3
2

DDPB_DATA C43
32 DDPB_DATA DDI0_DDC_SDA AG15
RC282 RC281
0_0402_5% MDSI_C_DP_0 AG17
0_0402_5% MDSI_C_DN_0
@ AA2
AA3 DDI1_TXP_0 AG8
1

DDI1_TXN_0 MDSI_C_DP_1 AG10

Y3 MDSI_C_DN_1
Y1 DDI1_TXP_1 DDI1/DDI_C AG7
RPC8 DDI1_TXN_1 MDSI_C_DP_2 AG5
3 2 DDPB_CLK AD1 MDSI_C_DN_2
4 1 DDPB_DATA AD3 DDI1_TXP_2 AE15
DDI1_TXN_2 MDSI_C_DP_3 AE17
AC2 MDSI_C_DN_3
10K_0404_4P2R_5% AC3 DDI1_TXP_3
DDI1_TXN_3
DDC Signals Can Be Set to 1.8/3.3(Default) by Soft Straps
AC7
AC5 DDI1_AUXP
DDI1_AUXN
C42 R53
A42 DDI1_DDC_SCL MIPI_I2C_SCL
C38 DDI1_DDC_SDA R54
DDI1_HPD MIPI_I2C_SDA

T53
CPU_EDP_TX0+ MDSI_C_TE GPIO_43 15
AE12 T55
28 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TXP_0 MDSI_A_TE GPIO_42 15
28 CPU_EDP_TX0- AE13
EDP_TXN_0
eDP CPU_EDP_TX1+ AC15
28 CPU_EDP_TX1+ CPU_EDP_TX1- EDP_TXP_1
AC17 eDP/DDI_A
28 CPU_EDP_TX1- EDP_TXN_1 MDSI_RCOMP
AL5 RC78 1 2 150_0402_1%
AE10 MDSI_RCOMP
C C
AE8 EDP_TXP_2
EDP_TXN_2 Reference to VSS, recommend to add a VSS shieldat
AE5
at least 12 mils wide placed between RCOMP and
AE7 EDP_TXP_3 adjacent I/O
EDP_TXN_3
CPU_EDP_AUX W17
28 CPU_EDP_AUX CPU_EDP_AUX# EDP_AUXP
W15
28 CPU_EDP_AUX# EDP_AUXN
EDP_HPD# B39
EDP_HPD
PCH_BKLT_CTRL_Q B41
PCH_ENBKL C40 PNL0_BKLCTL
PCH_LCD_VDDEN_Q C41 PNL0_BKLTEN
PNL0_VDDEN
1

EDP_RCOMP_P AA5
RC79 EDP_RCOMP_P
100_0402_1% EDP_RCOMP_N AA7
EDP_RCOMP_N
GEMINILAKE_FCBGA1090 3 OF 13
2

eDP RCOMP is used for DDI0/DDI1 ports of HDMI/DP

as well as the eDP interface. DDI0_RCOMP removed for GLK

EDP_HPD
PNL0_BKLCTL/PNL0_BKLTEN/PNL0_VDDEN Can be Set 1.8V/3.3V by Soft Strap
+3VALW +3VS +3VALW +3VS

4
3

4
3
B B
Follow CRB v1.2, PDG v1.2 Use 10K PU
RPC10
EDP_HPD# can set 1.8(default)/3.3 by soft strap RPC9
10K_0404_4P2R_5%
@ 10K_0404_4P2R_5%
+1.8V_3.3V_PU @

1
2

1
2
PCH_EDP_PWM PCH_ENVDD

RPC17

3
EDP_HPD# EDP_HPD# 1 4
CPU_EDP_HPD 2 3

D2

D2
5 5
G2 G2
1

D QC8 1/16W_100K_5%_4P2R_0404
2 @

S2

S2
G CPU_EDP_HPD 28

6
QC9B QC10B

4
S L2N7002KWT1G_SOT323-3 PJT138K_SOT363-6 @ PJT138K_SOT363-6
D1

D1
3

PCH_BKLT_CTRL_Q 2 PCH_LCD_VDDEN_Q 2
G1 G1
@
S1

S1
QC9A QC10A
1

1
PJT138K_SOT363-6 @ PJT138K_SOT363-6 GPIO Name I/O Voltage Default Term Buffer Type
PNL0_VDDEN 3.3V/1.8V 20K PD CMOS
PNL0_BKLTEN 3.3V/1.8V 20K PD CMOS
PNL0_BKLTCTL 3.3V/1.8V 20K PD CMOS
EDP_HPD# CPU_EDP_HPD
PJT138K[Vgs(th)<1.5V] PJT138K[Vgs(th)<1.5V]
RC82 1 @ 2 0_0402_5%

EDP_HPD# need BIOS soft strap to 3.3V PCH_LCD_VDDEN_Q PCH_ENVDD

RC83 1 2 0_0402_5%
PNL0_BKLCTL default 1.8V PCH_ENVDD 28
PNL0_BKLTEN default 1.8V PCH_LCD_VDDEN_Q VOH min is ???, need check 1.8V DC Specification
PNL0_VDDEN default 1.8V SY6288C20 VIH min is 1.35V, do NOT use level shift
(Follow BMWC1) 1.8V DC Specification :VOH=1.35V;VOL=0.45V
PCH_ENBKL
PCH_ENBKL 28
A A
PCH_ENBKL can direct connect to EC for costdown
PCH_BKLT_CTRL_Q RC84 1 2 0_0402_5% PCH_EDP_PWM
PCH_EDP_PWM 28
Reserve 0ohm directly connect to PCH_EDP_PWM for setting 3.3V by soft straps
PCH_BKLT_CTRL_Q need BIOS soft strap to 3.3V

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (DDI,EDP,HDMI,MDSI)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 9 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW_SOC Intel suggest PM_PLTRST# pu up to +3VALW,CRB PM_PLTRST# reserve pu up

RC85 2 @ 1 10K_0402_5% PM_PLTRST#

RC88 2 @ 1 100K_0402_5% SUSPWRDNACK_R

PM_RSTBTN# follow CRB use 10k pull up resistor;shcematic check list show
use a 1k pull up resistor to 3P3A
RC86 2 1 10K_0402_5% PM_RSTBTN# UC1H
RC90 2 1 100K_0402_5% PM_BATLOW#
PMC_I2C_SCL R46 B17 OSC_CLK_OUT0 1 TP61 @
PMC_I2C_SDA R48 PMC_I2C_SCL OSC_CLK_OUT_0 C17 OSC_CLK_OUT1 1 TP62 @
PM_PLTRST# & PM_RSTBTN# & SUSPWRDNACK is 3.3V level
set by GPIO_168 or Soft Stap? intel reply 3.3V level set by GPIO168 PMC_I2C_SDA OSC_CLK_OUT_1 U2 XTAL19_IN
L48 iCLK OSCIN T1 XTAL19_OUT
SUSPWRDNACK Follow CRB v1.2, Reserve 100K PU to +3VALW
N48 PMC_SPI_CLK OSCOUT
CRB PM_BATLOW# Reserve 100K PU to +3VALW
N44 PMC_SPI_FS0 D23 RTC_X1
L49 PMC_SPI_FS1 RTC_X1 F23 RTC_X2 +1.8VALW
RC91 2 1 100K_0402_5% PM_PLTRST# L51 PMC_SPI_FS2 RTC RTC_X2 J23 BVCCRTC_EXTPAD CC275 1 2 0.1u_0201_10V6K
N49 PMC_SPI_RXD VCC_RTC_EXTPAD H25 RTC_INTRUDER
RC92 1 @ 2 10K_0402_5% PM_SUSCLK PMC_SPI_TXD PMC INTRUDER D25 SYS_PWROK_R
Check if need reserve SUS_CLK PD(CRB/PDG/CKL/EDS w/o) SOC_PWROK F27 EC_RSMRST#_R H_THERMTRIP#_R RC93 1 2 10K_0402_5%
D RSM_RST_N D
PM_PLTRST# D54 F25 RTC_TEST# Add 10K PU for THERMTRIP#(20K Internal PU, 10K may cost down)
PMU_PLTRST_N RTC_TEST_N RTC_TEST# 44
PBTN_OUT#_R E54 D27 RTC_RST# H_PROCHOT# RC94 1 2 1K_0402_5%
PM_SLP_S0#_R PMU_PWRBTN_N RTC_RST_N RTC_RST# 44
Need confirm with PMIC if need connect S0IX C52
PM_SLP_S3#_R D51 PMU_SLP_S0_N J53 H_THERMTRIP#_R RC95 1 2 0_0402_5%
PMU_SLP_S3_N THERMTRIP_N H_THERMTRIP# 44,57 THERMTRIP_N signals is 1.8V tolerant.
+1.2VALW PM_SLP_S4#_R J49 J54 H_PROCHOT#
SUSPWRDNACK_R PMU_SLP_S4_N PROCHOT_N H_PROCHOT# 44
F54 AG43
PM_BATLOW# J48 SUSPWRDNACK Thermal NC8 H53 H_THERMTRIP#_R CC4223 1 2 0.01U_0402_25V7K
RC96 1 @ 2 0_0402_5% PM_RSTBTN# C51 PMU_BATLOW_N NC9 AG44
DEBUG_PORT_A0 PM_SUSCLK G49 PMU_RSTBTN_N PMU NC10 H55 @
RC97 1 @ 2 49.9_0402_1% EC feedback no need this function @ TP64 1 SUS_STAT# E52 PMU_SUSCLK NC11
SUS_STAT_N A4
Follow I+A, need check with EC
CPU_SVID_CLK F55 NC12 BH1
CPU_SVID_DAT G53 SVID0_CLK SVID NC13 A53 CPU_SKTPCC# 1 TP65 @Follow CRB v1.2 left as TP
+1.2VALW CPU_SVID_ALRT# G54 SVID0_DATA Spare SKTOCC_N F37
SVID0_ALERT_N NC14 BL2
DEBUG_PORT_A0 D1 NC15 BL3
RC98 1 @ 2 0_0402_5% DEBUG_PORT_A1 DEBUG_PORT_A1 D2 DEBUG_PORT_A0 Misc NC16 BL53
A54 DEBUG_PORT_A1 NC17 C2
RC99 1 @ 2 49.9_0402_1% C54 NC6 NC18 C3
NC7 NC19 R41
intel reply OK for NC but reserve pull up to be safe NC20
Follow CRB v1.2, need check with Intel
GEMINILAKE_FCBGA1090 8 OF 13
@

Connect SUSCLK to NGFF Conn.

+3VALW +3VS
Connect SUSCLK to EC in CRB +1.8V_3.3V_PU
3
4

+1.8VALW +3VALW
RPC11 PM_SLP_S4#_R RC371 1 @ 2 0_0402_5%
SYSON 44,46,55,57

4
3
10K_0404_4P2R_5% +1.8V_3.3V_PU
RPC12 PM_SLP_S3#_R RC372 1 @ 2 0_0402_5%
SUSP# 39,44,46,54,57
10K_0404_4P2R_5%
2
1

2
PLT_RST#
220P_0201_25V7-K

@ PLT_RST# 35,37,39,44

2
RC100 RC101 @

1
2
2.2K_0402_5% 10K_0402_5% RC102

2
@ @ 10K_0402_5%
0.1u_0201_10V6K
3

@ PM_SLP_S3#_R RC104 1 2 0_0402_5%

CC376

2 2 PM_SLP_S3# 44

1
QC12
CC375
D2

1
5 PM_SUSCLK 3 1 PM_SLP_S4#_R RC107 1 2 0_0402_5%
G2 SUSCLK 39 PM_SLP_S4# 44
EMC@
1 1 @ PM_SLP_S3#,PM_SLP_S4# is 3.3V level set by GPIO_168
S2

C
@ LSI1012XT1G_SC-89-3 C
6

QC11B
4

@ PJT138K_SOT363-6 RC105 1 2 0_0402_5% PBTN_OUT#_R RC106 1 2 0_0402_5% PBTN_OUT# 44

D1

PM_PLTRST# 2 +1.8V_3.3V_PU
G1
PBTN_OUT# is 3.3V level set by GPIO_168
PM_SUSCLK is 3.3V level set by GPIO_168 or Soft Strap
S1

PMU_BATLOW_N,PMU_PLTRST_N,PMU_PWRBTN_N,

2
QC11A Change LBSS138[Vgs(th)<1.5V] to PJQ1900[Vgs(th)<0.9V] PMU_RSTBTN_N,PMU_SLP_S0_N,PMU_SLP_S3_N,
1

@ PJT138K_SOT363-6 RC261
PMU_SLP_S4_N, PMU_SUSCLK,SUSCLK[1/2],SUS_STAT_N,SUSPWRDNACK, 10K_0402_5%
@
SOC_PWROKset by GPIO168
PJT138[Vgs(th)<1.5V]

1
SUSPWRDNACK_R RC254 1 2 0_0402_5% SUSPWRDNACK 44 PM_SLP_S0#_R RC262 1 2 0_0402_5%
PM_PLTRST# PLT_RST# PM_SLP_S0# 44
RC108 1 2 0_0402_5%
Reserve for PMIC
SUSPWRDNACK by GPIO_168 hard strap
PM_PLTRST# by GPIO_168 hard strap
PM_SLP_S0#_R by GPIO_168 hard strap

SVID Disable SYS_PWROK is 3.3V

+1.05VS Follow RVP2.0+PDG2.0 PMIC I2C +1.8VALW +1.8VALW
SYS_PWROK_R RC110 1 2 1K_0402_1%
SYS_PWROK_EC 44
+3VALW
CPU_SVID disable can NC---INTEL
CC278 2 1 0.01U_0201_25V6-K

100K_0402_5%
2
RC35 1 @ 2 160_0402_1% CPU_SVID_CLK EMC@
RC38 1 @ 2 240_0402_5% CPU_SVID_DAT
SYS_PWROK_R connector EC, EC
1
2

1
2
RC37 1 @ 2 68_0402_5% CPU_SVID_ALRT#_R RC36 1 @ 2 CPU_SVID_ALRT#

RC114
220_0402_5% RPC23 RPC22 RC269 1 @ 2 0_0402_5%
SYS_PWROK 44,57
2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% DC2

1
RSMRST# sequence control circuit @ 2 1
4
3

4
3
@
2

RC374 1 2 0_0402_5% SYS_PWROK_R @

LRB751V-40T1G_SOD323-2
G1
2EC_RSMRST#_R

Follow Intel request to add 100Kohm PD to avoid leakage.

L2N7002KWT1G_SOT323-3

RC280 1 2 0_0402_5% PMC_I2C_SCL 1 6 PMIC_I2C_SCL

+3VL S1 D1 PMIC_I2C_SCL 57
RC279 1 @ 2 0_0402_5% +3VALW
QC26A EC_RSMRST#_R RC109 1 2 1K_0402_1%
B EC_RSMRST# 44 B
PJT7838_SOT363-6
100K_0402_5%

100K_0402_5%

0.01U_0201_25V6-K
1

QC37 @
0_0402_5%

D
2

100K_0402_5%
RC276

RC273

RC274

G2

1
G
PMC_I2C_SDA 4 3 PMIC_I2C_SDA
2
RSM_RST_N is 3.3V

EMC@
CC276

RC112
S S2 D2 PMIC_I2C_SDA 57
1

@
1 RC375 1 @ 2 0_0402_5%
QC26B

2
3

D ALW_PGOOD 44,57
PJT7838_SOT363-6 DC1
5+5VALW_PG_GATE RC271 1 @ 2 0_0402_5%
6

G D QC27A +3VALW_PG 54 2 1
2 RC272 1 2 0_0402_5% PMC_I2C_SCL RC256 1 2 0_0402_5% PMIC_I2C_SCL
S G +5VALW_PG 54 PMC_I2C_SDA RC255 1 2 0_0402_5% PMIC_I2C_SDA
LRB751V-40T1G_SOD323-2
4

QC27B
S
CRB connect I2C to PMIC directly Follow SCH CKL add PD resistor, delete PU for EC is Push&Pull
1

L2N7002KDW1T1G_SOT363-6 L2N7002KDW1T1G_SOT363-6

32.768kHz CRYSTAL--EPSON SJ10000IX00 RTCRST#/SRTCRST# 19.2MHz CRYSTAL--TXC SJ10000LN00

VCCRTC XTAL19_IN_R RC117 1 2 0_0402_5% XTAL19_IN
RTC_X1_R RC116 1 2 0_0402_5% RTC_X1

RTC_TEST# RC118 1 2 20K_0402_1% EXC24CH500U_4P

4 3
RC119 1 2 10M_0402_5% RTC_X2_R RC120 1 2 0_0402_5% RTC_X2 4 3
RTC_RST# RC123 1 2 20K_0402_1%
1 2
1 2
YC1 LC2 EMC_NS@
1U_0402_6.3V6K

1U_0402_6.3V6K

1 2 1 1
1
CC279

JCMOS1
CC280

1 32.768KHZ_9PF_X1A0001410002 1 SHORT PADS

@ RC121 1 2 200K_0402_5% XTAL19_OUT_R RC122 1 2 0_0402_5% XTAL19_OUT
2

CC281 CC282 2 2
10P_0402_50V8J 9P_0402_50V8-B
2 2
YC2

JCMOS1 RTCRST# 1
OSC1 NC2
4 change PN to SJ10000TP00__1102 bron
1. Space 15MIL Place under Bottom Big Door Space 15Mil 2 3
2. No trace under crystal VCCRTC NC1 OSC2
A 3. Place on oppsosit side of MCP for temp influence 1 1
A

4. EDS request X'TAL ESR=50Kohm; +/-20ppm; X1,X2 pin capacitance=15pF 19.2MHZ_12PF_7V19200001

RTC_INTRUDER RC124 1 2 330K_0402_5% CC283 CC284
Need Check ESR and CL with Intel Follow CRB v2.0 & PDG v2.0 use 330K PU Resistor 4.7P_50V_J_NPO_0402 3.3P_50V_B_NPO_0402
2 2
Intel reply ESR max 50k
1. Space 15MIL
2. No trace under crystal
3. Place on oppsosit side of MCP for temp influence
4. PDG&EDS request X'TAL Max ESR=80ohm; +/-30ppm; Typical CL=12pF; Max PD=100uW

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (RTC&RCOMP&JTAG)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 10 of 60
5 4 3 2 1
 5 4 3 2 1

UC1E

AG53 DBG_PTI_CLK0 1 @
GPIO_8 TP72
PDG v1.2 P385:JTAGX is Unused Pin in GLK leave as No connect JTAG AG54 DBG_PTI_DATA0 1 @
GPIO_9 TP66
SCH checklist RC127,RC129 170 ohm, RC131 10K ohm AE54 DBG_PTI_DATA1 1 @
GPIO_10 TP67
+1.8VALW @ TP3704 1 AH53 AE53 DBG_PTI_DATA2 1 @
JTAGX GPIO_11 TP73
RC125 1 @ 2 51_0402_5% PCH_JTAG_TCK AM53 AD55 DBG_PTI_DATA3 1 @
JTAG_TCK GPIO_12 TP68
RC126 1 @ 2 51_0402_5% PCH_JTAG_TDI AJ54 AD53 DBG_PTI_DATA4 1 @
JTAG_TDI GPIO_13 TP69
RC127 1 @ 2 150_0402_5% PCH_JTAG_TDO AL53 AC54 DBG_PTI_DATA5 1 @
JTAG_TDO GPIO_14 TP74
RC128 1 @ 2 51_0402_5% PCH_JTAG_TMS AL54 AC53 DBG_PTI_DATA6 1 @
JTAG_TMS GPIO_15 TP70
RC131 1 @ 2 51_0402_5% PCH_JTAG_TRST# AK53 AB53 DBG_PTI_DATA7 1 @
JTAG_TRST_N GPIO_16 TP71
AA49 SOC_CS_WAKE 1 TC205 @ Need Check follow CRB
Need confirm with Intel if need stuff GPIO_17 TP_INT#_GPIO_18
ITP AC48
+1.8VALW GPIO_18 AC46 PMIC_IRQ#_R
intel reply can NC GPIO_19 SOC_CODEC_IRQ
AE51 1 TC204 @ Need Check follow CRB
RC129 1 @ 2 150_0402_5% PCH_JTAG_PRDY# AH55 GPIO_20 AE49 CNVI_MFUART2_RXD 1 TC206 @ Connect to CNVi WiFi though 33ohm
RC130 1 @ 2 51_0402_5% PCH_JTAG_PREQ# AJ53 JTAG_PRDY_N GPIO_21 AC51 CNVI_MFUART2_TXD 1 TC207 @ Connect to CNVi WiFi though 33ohm
JTAG_PREQ_N GPIO_22 AC49 CNVI_GNSS_PA_BLANKING 1 TC209 @ Connect to CNVi WiFi though 33ohm
GPIO_23 AA51
GPIO_24 AA46
GPIO_25
AE41
D GPIO_26 AE39 D
GPIO_27 GPIO_28 GPIO_27 15
AE46 GPIO_28 15
GPIO_28 AE44 SOC_KBRST#
GPIO_29 AC41
GPIO_30 AC39
GPIO_31 AC44
GPIO_32 AC43
GPIO_33 AA44
GPIO_34
AA54 PCH_BEEP 34
GPIO_35 AA53
GPIO_36 Y55 SOC_RUNTIME_SCI#
GPIO_37 Y53 SOC_WAKE_SCI# +1.8VALW
GPIO_38 W54
GPIO_39 W53 GLK_IERR# RC132 1 @ 2 1K_0402_5% intel feedback it can be no connector.
GPIO_40 V53 SOC_EXTSMI# Follow CRB v1.2, Need Confirm with Intel PU stuff or not
GPIO_41
L46 SOC_ACIN GPIO_105 can set 1.8V/3.3V(default) by soft strap
GPIO_105 H45 Follow CRB v1.2
GPIO_134 H47 +1.8VALW
GPIO_135 L43 RC9467 1 @ 2 0_0402_5%
GPIO_136 CNVI_EN# 39
M43 Follow CRB v1.2
GPIO_137 H37 SATA_GP0 RC133 1 2 100K_0402_5% Follow CRB v1.2, 1.8(Default)/3.3 Set by Soft Straps,
GPIO_138 H43 SATA_GP1 R9430 1 2 41.2K_0402_1% Need Confirm with Intel PU stuff or not
GPIO_139 SATA_DEVSLP0 +3VALW_SOC
J43 RC270 1 @ 2 10K_0402_5% Intel suggest follow CRB
GPIO_140 D43 SATA_DEVSLP1 RC268 1 @ 2 10K_0402_5% GPIO_140/GPIO_141 are OD Pin
GPIO_141 F43 SATA_LED# RC134 1 @ 2 8.2K_0402_5%
GPIO_142 +3VALW_SOC
H41 GPIO_142 default 3.3V
GPIO_143 F39
GPIO_144 L41 TP_INT#_GPIO_145
GPIO_145 F41
GPIO_146 BOARD_ID0
GPIO_146 need BIOS soft strp to 3.3V
GPIO H27
GPIO_210 U43 BOARD_ID1
GPIO_212 U41 BOARD_ID2
GPIO_213 U39 BOARD_ID3
GPIO_214

GEMINILAKE_FCBGA1090 5 OF 13
@

C C
intel feedback AC_PRESENT can pick any general GPIO
+1.8VALW
+3VS +1.8VALW +3VALW
+1.8VALW
+3VL_EC +3VL_EC
4
3

2
+1.8VALW

3
4

3
4
RPC13 RC242
RPC14 RPC15
3
4

10K_0404_4P2R_5% 2.2K_0402_5%
RPC16 10K_0404_4P2R_5% 10K_0404_4P2R_5%
@
10K_0404_4P2R_5%

2
@ SOC_RUNTIME_SCI# SOC_EXTSMI#
1
2

1
2

@ @
RC9464 BT_OFF# 39,44

2
1

2
1
QC24
10K_0402_5%
2
1

L2N7002KDW1T1G_SOT363-6
TP_INT# SOC_ACIN 3 1 AC_PRESENT
L2N7002KDW1T1G_SOT363-6

L2N7002KDW1T1G_SOT363-6
@
3

3
@ D QC15B D QC16B @
1
3

2
D QC13B QC14B 5 5 LSI1012XT1G_SC-89-3
D2
L2N7002KDW1T1G_SOT363-6

5 5 PJT7838_SOT363-6 G G RC243
G G2 10K_0402_5% Change LBSS138[Vgs(th)<1.5V] to PJQ1900[Vgs(th)<0.9V]

L2N7002KDW1T1G_SOT363-6

L2N7002KDW1T1G_SOT363-6
S S @
S2

4
6

S D QC13A
@ @
4

1
6

1
2 @ D QC15A D QC16A D QC23
PCH_TP_INT# 45
4

G QC14A 2 2 EC_SMI# 2
D1

PCH_BT_OFF# EC_SCI# 44 ACIN# 44

2 PJT7838_SOT363-6 G G G
S G1
1

S S S L2N7002KW T1G_SOT323-3
S1

3
@ @ @
1

+1.8VALW
TP_INT# RC135 1 @ 2 0_0402_5% PCH_TP_INT# SOC_ACIN RC241 1 2 0_0402_5% AC_PRESENT
GPIO_28 PCH_BT_OFF# AC_PRESENT 44
RC136 1 @ 2 0_0402_5%
2

TP_INT# IS Output, PU at Touch Pad Conn Side Reserve BT_OFF# from PCH, EC connect to WLAN
RC137
Follow CRB Connect to GPIO_18 1K_0402_5% GPIO_105 by GPIO_168 hard strap
+1.8VALW
1

SOC_RUNTIME_SCI# RC138 1 2 0_0402_5% EC_SCI# +1.8VALW +3VALW

2
If EC_SCI#_Q default term is PU, EC is OD for EC_SCI#, can use 0ohm short RC139
10K_0402_5%
TP_INT#_GPIO_18 RC278 1 2 0_0402_5%

2
Reserve for MS-Windows RS1

1
TP_INT#_GPIO_145 RC277 1 @ 2 0_0402_5% TP_INT# RC258 RC259
+1.8VALW 100K_0402_5% 10K_0402_5%

2
SOC_EXTSMI# RC140 1 2 0_0402_5% EC_SMI# @
B
EC_SMI# 44 B
GPIO_145

1
If SOC_EXTSMI# default term is PU QC25
0 = PAD VCCIO is 3.3V
2

PMIC_IRQ#_R 3 1
1 = PAD VCCIO is 1.8V (default) RC141
EC is OD for EC_SMI#, can use 0ohm short PMIC_IRQ# 57
GPIO_18=1.8V 1K_0402_5% @
LSI1012XT1G_SC-89-3
GPIO_145 need BIOS soft strp to 3.3V @
1

RC257 1 2 0_0402_5%
SOC_WAKE_SCI# RC142 1 @ 2 0_0402_5% EC_WAKE_SCI# 44
RC258 follow RVP2 LPDDR4 CRB design

+3VL_EC BOARD ID
intel feedback BOARD ID can pick any general GPIO
3
4

RPC20
10K_0404_4P2R_5% +1.8VALW
SOC_KBRST#
@
2
1

2 2.2K_0402_5%

2 2.2K_0402_5%

2 2.2K_0402_5%

2 2.2K_0402_5%
L2N7002KDW1T1G_SOT363-6

D QC22B
5
G
L2N7002KDW1T1G_SOT363-6

S
4

@ ID0 ID1 ID2 ID3 Description

6

@
1 IGM@

1 15@
QC22A

1 DIS@
D
2 0 UMA SKU
KBRST# 44
G

1
1 DIS SKU
S RSVD

RC244

RC245

RC246

RC247
1

BOARD_ID0
@ 0 IGM-R
BOARD_ID1
BOARD_ID2
BOARD_ID3
1 Normal IGM
1 UMA@ 2 2.2K_0402_5% 0 14" Panel

1 IGMR@ 2 2.2K_0402_5%

2 2.2K_0402_5%

2 2.2K_0402_5%
1 15" Panel

intel feedback pick any general 1.8V GPIO

A +1.8VALW in table EDS 2-28 A
@
1 14@

1
2

RC239
RC249

RC248

RC250

RC251

1K_0402_5%
1

SOC_KBRST# RC240 1 2 0_0402_5% KBRST#

If KBRST#_Q default term is PU

EC is OD for KBRST#, can use 0ohm short
Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (GPIO,JTAG,ITP)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 11 of 60
5 4 3 2 1
 5 4 3 2 1

+1.2V
2 x 0402_1uF; 4 x 0201_0.1uF
IccMAX=3.0A [6 x 0805_22uF on Power Side] +1.2V +VCCRAM_1P05 +1.05VS total IccMAX=4.5A
UC1J
+1.05VS +VCCRAM_1P05
1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
1 1 1 1 1 1 AP18 AC33 Need Short
AP21 VDDQ1 VCCRAM_1P05_3 AC35 J23
AP36 VDDQ2 VCCRAM_1P05_4 AE33 2 1 IccMAX=2.72A 3 x 0603_22uF; 7 x 0402_1uF Follow Intel CRB
CC286

CC287

CC288

CC289

CC290

CC291
VDDQ3 VCCRAM_1P05_7 2 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
AP38 AE35
2 2 2 2 2 2 VDDQ4 VCCRAM_1P05_8

EMC@

EMC@

EMC@

EMC@
AT18 AE36

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

JUMP_43X39
VDDQ5 VCCRAM_1P05_9

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AT20 AE38 @
AT21 VDDQ6 VCCRAM_1P05_10 AF27
VDDQ7 VCCRAM_1P05_11 1 1 1 1 1 1 1 1 1 1
AT35 AF28

CC292

CC293

CC368

CC294

CC295

CC299
D @ @ @ @ D
VDDQ8 VCCRAM_1P05_12

CC296

CC297

CC298

CC300
AT36 AF36
Note:Place CAPs Back of CPU Note:Place CAPs Near MLCC
AT38 VDDQ9 VCCRAM_1P05_13 AF38
+VCCRAM_1P05_FHV0_FHV1_FUSE
BA13 VDDQ10 VCCRAM_1P05_14 @ 2 2 2 2 2 2 2 2 2 2
BA15 VDDQ11 VCCRAM(1.05V) AG51 @ @
Place near UC1.AP36,AT36,AP38,
BA25 VDDQ12 VCC_1P05_INT2 AG49
AT38,AT35,AT18,AP18,AP21,AT20,
BA31 VDDQ13 VCC_1P05_INT1
AT21,BA43,BA41,BA31,BA13,BA15,BA25
BA41 VDDQ14 AJ51
BA43 VDDQ15 VCC_1P05_INT3
+1.05VS +VCCIOA VDDQ16
AP25 VCCRAM_1P05_1
AA36
AA38
+VCCRAM_1P05
+VCCIOA AP31 VCCIOA1 VCCRAM_1P05_2 AC36
IccMAX=1.19A 2 x 0603_22uF; 3 x 0402_1uF; 1 x 0402_2.2uF VCCIOA2 VCCRAM_1P05_5
RC153 1 2 0_0805_5% AT25 AC38
VCCIOA3 VCCRAM_1P05_6
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
AT27 Y36
AT28 VCCIOA4 VCCRAM_1P05_15 Y38
+1.05VS +VCCRAM_1P05_FHV0_FHV1_FUSE
VCCIOA5 VCCRAM_1P05_16

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

2.2U_0402_6.3V6M
AT29
VCCIOA6 RC154
AT31
1 1 1 1 1 1 VCCIOA7 VCCRTC 1 2 IccMAX=0.51A
CC301

CC302

CC303

CC304

CC305

CC306
T21
+VCC1P8 T23 VCC_1P8V_A3 P15 1/10W_0_+-5%_0603
2 2 2 2 2 2 T25 VCC_1P8V_A4 RTC VCCRTC_3P3V
@ V21 VCC_1P8V_A5
V23 VCC_1P8V_A6 AJ21
@ @ VCC_1P8V_A7 VCC_3P3V_A2
V25 VDD1(1.8V)
VCC_1P8V_A8 U17
AJ23 VCC_3P3V_A5
AG23 VCC_1P8V_A2
VCC_1P8V_A1 +VDD3_3P3
+VDD2_1P2_MPHY
+1.8VALW +VCC1P8 AC21
AE20 VDD2_1P2_MPHY1 VCC_3P3V_A1
AG21
T18
AE21 VDD2_1P2_MPHY2 VCC_3P3V_A3 T20
RC158 VDD2_1P2_MPHY3 VCC_3P3V_A4
C
1 x 0603_22uF; 5 x 0402_1uF AF20 V18 C
1 2 IccMAX=0.4A +VDD2_1P2_AUD_ISH AF21 VDD2_1P2_MPHY4 VCC_3P3V_A6 V20
VDD2_1P2_MPHY5 VCC_3P3V_A7
22UC_6.3VC_MC_X5RC_0603

VDD3(3.3V) Y18
VCC_3P3V_A8 Y20
0_0805_5% VCC_3P3V_A9 VCCRTC +3VALW_SOC +VDD3_3P3
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AC18
+VDD2_1P2_DSI AC20 VDD2_1P2_AUD_ISH1
1 1 1 1 1 1 VDD2_1P2_AUD_ISH2 RC159
CC307

IccMAX=0.15A Follow Intel CRB

CC308

CC309

CC310

CC311

CC312

AW 12 1 2
VDD2_1P2_DSI_CSI

22UC_6.3VC_MC_X5RC_0603
2 2 2 2 2 2 +VDD2_1P2_GLM

1U_0402_6.3V6K

1U_0402_6.3V6K
AL36 VDD2(1.2V) 1/10W_0_+-5%_0603
VDD2_1P2_GLM1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
AL38 1 1
AP20 VDD2_1P2_GLM2
@ @ @ VDD2_1P2_GLM4 1 1 1 1 1
+VDD2_1P2_PLL

CC313

CC314

CC315
@ @ @
AM20

CC316

CC317

CC318

CC319
VDD2_1P2_GLM3 2 @ 2
AL18 2 2 2 2 2
+VDD2_1P2_VNNAON AM18 VDD2_1P2_PLL1
VDD2_1P2_PLL2
+1.2VALW +VDD2_1P2_MPHY AA18
+VDD2_1P2_USB2 AA20 VDD2_1P2_VNNAON1
IccMAX=2.0A CRB: 2 x 0805_47uF; 1 x 0603_22uF; 3 x 0402_1uF VDD2_1P2_VNNAON2
1 RC160 2 IccMAX=0.55A DFC: 5 x 0603_22uF; 3 x 0402_1uF AG18
VDD2_1P2_USB2
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

AJ20
1/10W_0_+-5%_0603 VDD2_1P2_USB3
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 GEMINILAKE_FCBGA1090 10 OF 13
CC364

CC365

CC366

CC367

CC322

@
CC323

CC324

CC325

2 2 2 2 2 2 2 2
@ @
@
B B

+1.2VALW +VDD2_1P2_VNNAON
+VDD2_1P2_AUD_ISH +1.2VALW +VDD2_1P2_GLM
RC162 RC163
IccMAX=0.44A RC161

2 x 0603_22uF; 1 x 0402_1uF 1 2
1 2 IccMAX=0.22A 1 2 IccMAX=0.22A
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1/10W_0_+-5%_0603
1/10W_0_+-5%_0603
0_0805_5%
1U_0402_6.3V6K

1 1 1
CC326

CC327

CC328

2 2 2 Reserve for VDD2_1P2 and VDDQ Merged

@

Need Open
J22
+VDD2_1P2_DSI +VDD2_1P2_PLL +VDD2_1P2_USB2 +1.2V
2
2 1
1
+1.2VALW
RC164 RC165
IccMAX=0.22A RC166 JUMP_43X39
1 x 0603_22uF; 2 x 0402_1uF 1 x 0402_1uF @
1 2 1 2 1 2
IccMAX=0.11A
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1/10W_0_+-5%_0603 1/10W_0_+-5%_0603 IccMAX=0.22A

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
A 1/10W_0_+-5%_0603 A

1 1 1 1 1
CC329

CC330

CC331

CC332

CC333
2 2 2 @ 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 12 of 60
5 4 3 2 1
 5 4 3 2 1

+CPU_CORE +CPU_CORE +VNN +VNN

UC1I
IccMAX=25.0A 16 x 0402_1uF IccMAX=4.0A
AA28 AF35
AA29 VCC_VCG1 VNN1 AG27

CC100

CC101

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

AA31 VCC_VCG2 VNN2 AG28
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
4.3U_0402_4V6-M

4.3U_0402_4V6-M
@1 @ 1 AA33 VCC_VCG3 VNN3 AG36
1 1 1 1 1 1 1

1U_0402_6.3V6K

1U_0402_6.3V6K

3
@ @ 1 @1 AC28 VCC_VCG4 VNN4 AG46

CC343

CC344

CC345
AC31 VCC_VCG5 VNN5 AG48
CC341

CC338

CC339

CC342

CC346

CC347
AE28 VCC_VCG6 VNN6 AJ27
CC335

CC336

4
2 2 2 AE29 VCC_VCG7 VNN7 AJ28 2 2 2 2 @ 2 @ 2
D 2 2 AE31 VCC_VCG8 VNN8 AJ46 D
AF31 VCC_VCG9 VNN9 AJ48
AF33 VCC_VCG10 VNN10 AL27
AG31 VCC_VCG11 VNN11 AL28
add 3T_MLCC__bron AG33 VCC_VCG12 VNN12 AL48
AJ31 VCC_VCG13 VNN13 AL49
Follow Intel CRB AJ33 VCC_VCG14 VNN14 AM27
AJ35 VCC_VCG15 VNN15 AM28

CC102
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

AL31 VCC_VCG16 VNN16
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

4.3U_0402_4V6-M
@1 @ 1 @1 AL33 VCC_VCG17
1 1 1 1

3
@ @ AL35 VCC_VCG18
CC351

CC352

AM33 VCC_VCG19
CC348

CC349

CC350

CC354

CC355
AM35 VCC_VCG20

4
2 2 2 2 2 2 2 AM36 VCC_VCG21
D31 VCC_VCG22
D33 VCC_VCG23 AJ49
D37 VCC_VCG24 NC21
D39 VCC_VCG25
P39 VCC_VCG26
P41 VCC_VCG27
T28 VCC_VCG28
T29 VCC_VCG29
+CPU_CORE T31 VCC_VCG30
T33 VCC_VCG31 AW44
T35 VCC_VCG32 NC22
T36 VCC_VCG33 BH55
V28 VCC_VCG34 NC23
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

V29 VCC_VCG35 AG41 CPU_VCC_SENSE

V31 VCC_VCG36 VCC_VCG_SENSE AG39 CPU_VSS_SENSE CPU_VCC_SENSE 57
1 1 VCC_VCG37 VSS_VCG_SENSE CPU_VSS_SENSE 57
V33
V35 VCC_VCG38 AJ41 VNN_VCC_SENSE
CC357

CC358

V36 VCC_VCG39 VNN_SENSE AJ43 VNN_VSS_SENSE VNN_VCC_SENSE 57

2 2 VCC_VCG40 VNN_VSS_SENSE VNN_VSS_SENSE 57
EMC@

EMC@

Y28
Y29 VCC_VCG41 BL54
Y33 VCC_VCG42 NC24
Y35 VCC_VCG43
Follow CRB, Need EMC Team Confirmation VCC_VCG44
C GEMINILAKE_FCBGA1090 9 OF 13 C
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 13 of 60
5 4 3 2 1
 5 4 3 2 1

UC1K UC1L UC1M

AL23
A3 AF44 AN48 BC11 BJ54 VSS_221 J51
A6 VSS_6 VSS_53 AF45 AN49 VSS_111 VSS_165 BC17 BK1 VSS_222 VSS_272 K1
A12 VSS_13 VSS_54 AF47 AN51 VSS_112 VSS_166 BC19 BK17 VSS_223 VSS_273 K3
A16 VSS_1 VSS_55 AF48 AN53 VSS_113 VSS_167 BC21 BK21 VSS_224 VSS_274 K28
A20 VSS_2 VSS_56 AF50 AP23 VSS_114 VSS_168 BC23 BK35 VSS_225 VSS_275 K55
A24 VSS_3 VSS_57 AF52 AP27 VSS_115 VSS_169 BC25 BK39 VSS_226 VSS_276 L5
A28 VSS_4 VSS_58 AF53 AP28 VSS_116 VSS_170 BC31 BK55 VSS_227 VSS_277 L7
D
A32 VSS_5 VSS_59 AF55 AP29 VSS_117 VSS_171 BC33 BL5 VSS_228 VSS_278 L8 D
A36 VSS_7 VSS_60 AG20 AP33 VSS_118 VSS_172 BC35 BL8 VSS_229 VSS_279 L19
A40 VSS_8 VSS_64 AL21 AP35 VSS_119 VSS_173 BC37 BL10 VSS_230 VSS_280 L33
A44 VSS_9 VSS_87 AG25 AR2 VSS_120 VSS_174 BC39 BL14 VSS_231 VSS_281 M15
A48 VSS_10 VSS_65 AG29 AR7 VSS_124 VSS_175 BC41 BL24 VSS_232 VSS_282 M25
A51 VSS_11 VSS_66 AG35 AR10 VSS_130 VSS_176 BC45 BL28 VSS_233 VSS_283 M28
AA12 VSS_12 VSS_67 AG38 AR12 VSS_121 VSS_177 BC51 BL32 VSS_234 VSS_284 M35
AA13 VSS_14 VSS_68 AJ8 AR17 VSS_122 VSS_179 BD9 BL42 VSS_235 VSS_285 M41
AA15 VSS_15 VSS_77 AJ13 AR39 VSS_123 VSS_187 BD15 BL46 VSS_236 VSS_286 N12
AA17 VSS_16 VSS_69 AJ18 AR44 VSS_125 VSS_180 BD19 BL48 VSS_237 VSS_287 N28
AA21 VSS_17 VSS_70 AJ25 AR46 VSS_126 VSS_181 BD21 BL51 VSS_238 VSS_288 N46
AA23 VSS_18 VSS_71 AJ29 AR49 VSS_127 VSS_182 BD28 C1 VSS_239 VSS_289 N51
AA25 VSS_19 VSS_72 AJ36 AR54 VSS_128 VSS_183 BD35 C12 VSS_240 VSS_290 P21
AA27 VSS_20 VSS_73 AJ38 AT23 VSS_129 VSS_184 BD37 C16 VSS_241 VSS_291 P55
AA35 VSS_21 VSS_74 AJ39 AT33 VSS_131 VSS_185 BD47 C28 VSS_242 VSS_292 R8
AA43 VSS_22 VSS_75 AJ44 AU3 VSS_132 VSS_186 BE3 C36 VSS_243 VSS_293 R28
AA48 VSS_23 VSS_76 AK1 AU10 VSS_135 VSS_189 BE28 D6 VSS_244 VSS_294 T27
AB1 VSS_24 VSS_78 AK3 AU28 VSS_133 VSS_188 BE53 D9 VSS_245 VSS_295 T38
AB3 VSS_25 VSS_79 AK55 AU46 VSS_134 VSS_190 BF9 D21 VSS_246 VSS_296 U13
AB55 VSS_26 VSS_80 AL3 AU53 VSS_136 VSS_194 BF19 D28 VSS_247 VSS_297 V27
AC8 VSS_27 VSS_90 AL7 AV15 VSS_137 VSS_191 BF37 D41 VSS_248 VSS_298 V38
AC13 VSS_33 VSS_97 AL8 AV17 VSS_138 VSS_192 BF47 D45 VSS_249 VSS_299 V55
AC23 VSS_28 VSS_98 AL10 AV23 VSS_139 VSS_193 BG1 D55 VSS_250 VSS_300 W2
AC25 VSS_29 VSS_81 AL12 AV25 VSS_140 VSS_195 BG6 E28 VSS_251 VSS_301 W3
AC27 VSS_30 VSS_82 AL13 AV31 VSS_141 VSS_199 BG28 E50 VSS_252 VSS_302 W5
AC29 VSS_31 VSS_83 AL15 AV33 VSS_142 VSS_196 BG50 E55 VSS_253 VSS_303 W7
AE18 VSS_32 VSS_84 AL17 AV39 VSS_143 VSS_197 BG55 F1 VSS_254 VSS_304 W8
AE23 VSS_34 VSS_85 AL20 AV41 VSS_144 VSS_198 BH11 F4 VSS_255 VSS_305 W10
AE25 VSS_35 VSS_86 AL25 AW2 VSS_145 VSS_200 BH13 F21 VSS_256 VSS_306 W39
AE27 VSS_36 VSS_88 AL29 AW5 VSS_147 VSS_201 BH17 F31 VSS_257 VSS_307 W41
AE43 VSS_37 VSS_89 AL39 AW10 VSS_150 VSS_202 BH19 G28 VSS_258 VSS_308 W43
AE48 VSS_38 VSS_91 AL41 AW28 VSS_146 VSS_203 BH23 H13 VSS_259 VSS_309 W44
AF1 VSS_39 VSS_92 AL43 AW46 VSS_148 VSS_204 BH25 H15 VSS_260 VSS_310 W46
AF3 VSS_40 VSS_93 AL44 AW51 VSS_149 VSS_205 BH28 H21 VSS_261 VSS_311 W48
AF4 VSS_49 VSS_94 AL46 AW54 VSS_151 VSS_206 BH31 H23 VSS_262 VSS_312 W49
AF6 VSS_50 VSS_95 AL51 AY13 VSS_152 VSS_207 BH33 H28 VSS_263 VSS_313 W51
AF8 VSS_61 VSS_96 AM1 AY15 VSS_153 VSS_208 BH37 H33 VSS_264 VSS_314 Y21
AF9 VSS_62 VSS_99 AM21 AY28 VSS_154 VSS_209 BH39 H39 VSS_265 VSS_315 Y23
C C
AF11 VSS_63 VSS_100 AM23 AY41 VSS_155 VSS_210 BH41 J8 VSS_266 VSS_316 Y25
AF12 VSS_41 VSS_101 AM25 AY43 VSS_156 VSS_211 BH45 J27 VSS_267 VSS_317 Y27
AF14 VSS_42 VSS_102 AM29 B2 VSS_157 VSS_212 BJ2 J33 VSS_268 VSS_318 Y31
AF16 VSS_43 VSS_103 AM31 B55 VSS_158 VSS_215 BJ15 J41 VSS_269 VSS_319 T3
AF18 VSS_44 VSS_104 AM38 BA27 VSS_159 VSS_213 BJ19 J45 VSS_270 VSS_320 U3
AF23 VSS_45 VSS_105 AM55 BA29 VSS_160 VSS_214 BJ25 VSS_271 VSS_321
AF25 VSS_46 VSS_106 AN3 BB1 VSS_161 VSS_216 BJ28
AF29 VSS_47 VSS_108 AN8 BB28 VSS_162 VSS_217 BJ31 GEMINILAKE_FCBGA1090 13 OF 13
AF40 VSS_48 VSS_110 AN10 BB55 VSS_163 VSS_218 BJ37 @
AF42 VSS_51 VSS_107 AN46 BC5 VSS_164 VSS_219 BJ41
VSS_52 VSS_109 VSS_178 VSS_220
GEMINILAKE_FCBGA1090 11 OF 13
@ GEMINILAKE_FCBGA1090 12 OF 13
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 14 of 60
5 4 3 2 1
 5 4 3 2 1

Hardware STRAPS(Follow up CRB) Internal Schematics

GPIO# Purpose Termination Setting Pin Usage Remark
+1.8VALW +1.8VALW
Allow eMMC as a 1 = Enable(Default); 0 = Disable[√]
GPIO_27 Boot Source 20K PU 4.7K PD If platform is using SPI as the boot device, then Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P469)
provide a pull-down for this strap to disable eMMC
Allow SPI as a 1 = Enable(Default)[√]; 0 = Disable
GPIO_28 Boot Source 20K PU Floating If platform is using eMMC as boot device, then Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P469)
1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%
1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%
provide a pull down for this strap to disable SPI
Flash Descriptor 1 = Override; 0 = No Override(Normal Operation)[√]
GPIO_42 Override 20K PD Floating This strap enables the platform to override security Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P380)
features in the SPI
Ensure that this strap is pulled HIGH when RSM_RST_N
GPIO_43 RSVD 20K PU Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P39)

Ensure that this strap is pulled LOW when RSM_RST_N

D
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ GPIO_44 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P39) D

Top swap 1 = Enable; 0 = Disable(Default)[√]

2

2
GPIO_45 override 20K PD Floating This strap enables platform to change where the core Follow CRB(v1.2 P57); EDS(v1.2 P39)
will look for BIOS code for a SPI boot only
Enable TXE ROM 1 = Enable Bypass; 0 = Disable Bypass(Default)[√]
RC171

RC172

RC173

RC174

RC175

RC176

RC177

RC178

RC179

RC180

RC181

RC182

RC183

RC184

RC185

RC186
GPIO_61 Bypass 20K PD Floating This strap tells TXE 3.0 to bypass Read-Only Memory Follow CRB(v1.2 P58); EDS(v1.2 P39); PDG(v1.2 P380)
Allow eMMC as a Boot Source GPIO_27 11 Force DNX FW Load SOC_UART_TXD_GPIO_65 7,39 (ROM) that it has on SoC
Allow SPI as a Boot Source GPIO_28 11 LPC boot BIOS Strap GPIO_66 7 Ensure that this strap is pulled LOW when RSM_RST_N
GPIO_42 Flash Descriptor Override RSVD GPIO_62 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P39)
GPIO_42 9 GPIO_79 7
RSVD GPIO_43 9 RSVD GPIO_80 7
RSVD USB_OC0#_GPIO_44 8 RSVD GPIO_81 7 Force DNX FW 1 = Force; 0 = Do Not Force(Default)[√]
Top Swap Override USB_OC1#_GPIO_45 8,29,31 LPC 1.8V/3.3V Mode Select GPIO_83 7 GPIO_65 Load 20K PD Floating This strap is a recovery strap for corrupted FW image, Follow CRB(v1.2 P58); EDS(v1.2 P40); PDG(v1.2 P471)
Enable TXE ROM Bypass GPIO_61 7 Allow SPI as a Boot Source GPIO_84 7 will force TXE3.0 to execute a DnX flow
RSVD GPIO_62 7 RSVD GPIO_85 7 LPC boot BIOS 1 = Boot From LPC; 0 = Do Not(Default)[√]
GPIO_66 strap 20K PD Floating The board should strap this low and do not use Follow CRB(v1.2 P57); EDS(v1.2 P40)
otherwise
1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%
1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%
Ensure that this strap is pulled LOW when RSM_RST_N

1 1K_0402_5%
GPIO_79 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P40)

Ensure that this strap is pulled LOW when RSM_RST_N

GPIO_80 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P58); EDS(v1.2 P40)

Ensure that this strap is pulled HIGH when RSM_RST_N

GPIO_81 RSVD 20K PU 4.7K PU de-asserts for normal platform operation Follow CRB(v1.2 P58); EDS(v1.2 P40)
@ @ @ @ @ @ @ @ @ @ @ @ @
LPC 1.8V/3.3V 1=buffers set to 1.8V mode
GPIO_83 mode select 20K PD 4.7K PD 0=buffers set to 3.3V mode (default)[√] Follow CRB(v1.2 P57); EDS(v1.2 P40)
2

2
Allow SPI as a 1=disable
GPIO_84 boot source 20K PU 4.7K PD 0=enable (default)[√] Follow CRB(v1.2 P58); EDS(v1.2 P40)
RC187

RC188

RC189

RC190

RC191

RC192

RC193

RC194

RC195

RC196

RC197

RC198

RC199

RC200

RC201

RC202
Ensure that this strap is pulled LOW when RSM_RST_N
GPIO_85 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P58); EDS(v1.2 P40)

Ensure that this strap is pulled LOW when RSM_RST_N

GPIO_86 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P58); EDS(v1.2 P40)
C Ensure that this strap is pulled LOW when RSM_RST_N C
+1.8VALW +1.8VALW GPIO_87 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P40)

Ensure that this strap is pulled LOW when RSM_RST_N

GPIO_89 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P40)

Ensure that this strap is pulled LOW when RSM_RST_N

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%
1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%

1 4.7K_0402_5%
GPIO_159 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P40)

SMBus 1.8V/3.3V 1=buffers set to 1.8V mode

GPIO_163 mode select 20K PD 4.7K PD 0=buffers set to 3.3V mode (default)[√] Follow CRB(v1.2 P57); EDS(v1.2 P40)

Ensure that this strap is pulled LOW when RSM_RST_N

GPIO_164 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P40)
@ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ PMU 1.8V/3.3V 1=buffers set to 1.8V mode
GPIO_168 mode select 20K PD 4.7K PD 0=buffers set to 3.3V mode (default)[√] Follow CRB(v1.2 P57); EDS(v1.2 P40)
2

SMBus No Re- 1 = Enable ; 0 = Disable (default)[√]

GPIO_172 Boot 20K PD Floating Note: Platforms should strap this LOW. Functionality is Follow CRB(v1.2 P57); EDS(v1.2 P40)
handled by the PMC.
RC203

RC204

RC205

RC206

RC207

RC208

RC209

RC210

RC211

RC212

RC213

RC214

RC215

RC216

RC217

RC218

RC219

VDD2 1.24V vs. 1=VDD2 is 1.24V;

RSVD GPIO_86 7 VDD2 1.24V vs. 1.20V select GPIO_174 6 GPIO_174 1.20V select 20K PD Floating 0=VDD2 is 1.20V (default) Need Check Follow CRB(v1.2 P57); EDS(v1.2 P40)
RSVD GPIO_87 7 eSPI vs. LPC Select GPIO_175 6
RSVD GPIO_89 7 RSVD PCH_SMB_CLK_GPIO_177 7 1=eSPI mode; 0=LPC mode (default)
RSVD GPIO_159 6 eSPI Flash Sharing Mode CNVI_BRI_DT_GPIO_191 7,39 GPIO_175 eSPI vs. LPC 20K PD Floating Note: The default for A0 will be eSPI due to a bug on Follow CRB(v1.2 P57); EDS(v1.2 P41)
SMBus 1.8V/3.3V Mode Select GPIO_163 6 RSVD CNVI_BRI_RSP_GPIO_192 7,39 LPC.
RSVD GPIO_164 6 RSVD CNVI_RGI_DT_GPIO_193 7,39 Ensure that this strap is pulled LOW when RSM_RST_N
PMU 1.8V/3.3V Mode Select HDA_SDIN0_GPIO_168 6,34 RSVD CNVI_RGI_RSP_GPIO_194 7,39 GPIO_177 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P41)
SMBus No Re-Boot GPIO_172 6 RSVD CNVI_RF_RST#_GPIO_195 7,39
RSVD XTAL_CLKREQ_GPIO_196 7,39 eSPI Flash eSPI Flash Sharing Mode:
GPIO_191 Sharing Mode 20K PD Floating 1=slave attached flash sharing (SAFS); Follow CRB(v1.2 P57); EDS(v1.2 P41)
1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%
1 4.7K_0402_5%

1 4.7K_0402_5%

0=master attached flash sharing (MAFS; default)[√]

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%

1 10K_0402_5%
1 4.7K_0402_5%

Ensure that this strap is pulled LOW when RSM_RST_N

GPIO_192 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P41)

Ensure that this strap is pulled HIGH when RSM_RST_N

B
GPIO_193 RSVD 20K PU Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P41) B

Ensure that this strap is pulled LOW when RSM_RST_N

@ @ @ @ @ @ GPIO_194 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P41)
@ @ @ @ @ @ @ @ @
Ensure that this strap is pulled LOW when RSM_RST_N
2

GPIO_195 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P41)
2

Ensure that this strap is pulled LOW when RSM_RST_N

RC220

RC221

RC222

RC223

RC224

RC225

RC266

RC227

GPIO_196 RSVD 20K PD Floating de-asserts for normal platform operation Follow CRB(v1.2 P57); EDS(v1.2 P41)
RC228

RC229

RC230

RC231

RC232

RC233

RC234

RC235

RC236

ME_PROTECT Circuit +1.8VALW

2

RC237
2.2K_0402_5%
1
3

S
QC21
2

ME3 G
2
SHORT PADS EC_ME_PROTECT 44
1

D
DMG1013UW-7_SOT-323-3
@
1

A RC238 A
100K_0402_5%
GPIO_42
2

EC_ME_PROTECT GPIO_42 TXE Flash Descriptor Override

Security Classification LC Future Center Secret Data Title
Low High Override Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
High Low No Override (Normal Operation) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 15 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 16 of 60
5 4 3 2 1
 5 4 3 2 1

DDR4 Swap Mapping table DDR4 SO-DIMM DDRA_DQ[0..63]

DDRA_DQ[0..63] 4
DDRA_DQS#[0..7] SHOULD CHECK SO-DIMM CONNECTOR WITH ME
+1.2V
SHOULD
+1.2V
CHECK SO-DIMM CONNECTOR WITH ME
+1.2V +1.2V
DDRA_DQS#[0..7] 4
+1.2V +1.2V +1.2V +1.2V
DDR4 NET DDR4 SO-DIMM DDR4 NET DDR4 SO-DIMM JDDR1A DDRA_DQS[0..7] JDDR1B
DDRA_DQS[0..7] 4
DDRA_DQ0---DQ DQ0
DDRA_DQ1---DQ DQ5
DDRA_DQ2---DQ DQ1 1 2 131 132
DDRA_DQ1 VSS_1 VSS_2 DDRA_DQ3 4 DDRA_MA3 A3 A2 DDRA_EVENT# DDRA_MA2 4
DDRA_DQ3---DQ DQ4 DDRA_DQS0 ---DQS DQS0_c 3 4 133 134
DQ5 DQ4 4 DDRA_MA1 A1 EVENT_n
DDRA_DQ4---DQ DQ6 DDRA_DQS0#---DQS# DQS0_t 5 6 135 136
DDRA_DQ2 7 VSS_3 VSS_4 8 DDRA_DQ0 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
DDRA_DQ5---DQ DQ2 9 DQ1 DQ0 10
4 DDRA_CLK0 DDRA_CLK0# 139 CK0_t CK1_t 140 DDRA_CLK1# DDRA_CLK1 4
DDRA_DQ6---DQ DQ3 DDRA_DQS#0 VSS_5 VSS_6 4 DDRA_CLK0# CK0_c CK1_c DDRA_CLK1# 4
11 12 141 142
DDRA_DQ7---DQ DQ7 DDRA_DQS0 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRA_PAR 143 VDD_11 VDD_12 144
DQS0_t VSS_7 DDRA_DQ4 Parity A0 DDRA_MA0 4
15 16
DDRA_DQ7 17 VSS_8 DQ6 18
DDRA_DQ8 ---DQ DQ12 DQ7 VSS_9
D DDRA_DQ9 ---DQ DQ9 19 20 DDRA_DQ5 145 146 D
DDRA_DQ6 VSS_10 DQ2 4 DDRA_BS1# BA1 A10/AP DDRA_MA10 4
DDRA_DQ10---DQ DQ8 DDRA_DQS1 ---DQS DQS1_c 21 22 147 148
23 DQ3 VSS_11 24 DDRA_DQ8 149 VDD_13 VDD_14 150
DDRA_DQ11---DQ DQ11 DDRA_DQS1#---DQS# DQS1_t VSS_12 DQ12 4 DDRA_CS0# CS0_n BA0 DDRA_BS0# 4
DDRA_DQ15 25 26 151 152
DDRA_DQ12---DQ DQ14 DQ13 VSS_13 DDRA_DQ10 4 DDRA_MA14_WE# WE_n/A14 RAS_n/A16 DDRA_MA16_RAS# 4
27 28 153 154
DDRA_DQ13---DQ DQ10 DDRA_DQ9 29 VSS_14 DQ8 30 155 VDD_15 VDD_16 156
DDRA_DQ14---DQ DQ15 DQ9 VSS_15 DDRA_DQS#1 4 DDRA_ODT0 ODT0 CAS_n/A15 DDRA_MA15_CAS# 4
31 32 157 158
DDRA_DQ15---DQ DQ13 VSS_16 DQS1_c DDRA_DQS1 4 DDRA_CS1# CS1_n A13 DDRA_MA13 4
33 34 159 160
35 DM1_n/DBl1_n/NC DQS1_t 36 161 VDD_17 VDD_18 162
DDRA_DQ14 VSS_17 VSS_18 DDRA_DQ12 4 DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMM
DDRA_DQ16---DQ DQ24 37 38 163 164
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRA_SA2
DDRA_DQ17---DQ DQ29 VSS_19 VSS_20 C1/CS3_n/NC SA2
DDRA_DQ18---DQ DQ25 DDRA_DQS2 ---DQS DQS3_c DDRA_DQ13 41 42 DDRA_DQ11 167 168 @

0.1u_0201_10V6K

2.2U_0402_6.3V6M
43 DQ10 DQ11 44 DDRA_DQ38 169 VSS_53 VSS_54 170 DDRA_DQ36
DDRA_DQ19---DQ DQ28 DDRA_DQS2#---DQS# DQS3_t VSS_21 VSS_22 DQ37 DQ36 1 1
DDRA_DQ24 45 46 DDRA_DQ25 171 172
DDRA_DQ20---DQ DQ31 DQ21 DQ20 DDRA_DQ39 VSS_55 VSS_56 DDRA_DQ37
47 48 173 174
DDRA_DQ21---DQ DQ30 DDRA_DQ29 49 VSS_23 VSS_24 50 DDRA_DQ26 175 DQ33 DQ32 176
DDRA_DQ22---DQ DQ27 51 DQ17 DQ16 52 DDRA_DQS#4 177 VSS_57 VSS_58 178 2 2
DDRA_DQ23---DQ DQ26 DDRA_DQS#3 53 VSS_25 VSS_26 54 DDRA_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180

CD1

CD2
DDRA_DQS3 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRA_DQ35
57 DQS2_t VSS_27 58 DDRA_DQ31 DDRA_DQ34 183 VSS_60 DQ39 184
DDRA_DQ24---DQ DQ21 VSS_28 DQ22 DQ38 VSS_61
DDRA_DQ25---DQ DQ20 DDRA_DQ30 59 60 185 186 DDRA_DQ33
61 DQ23 VSS_29 62 DDRA_DQ27 DDRA_DQ32 187 VSS_62 DQ35 188
DDRA_DQ26---DQ DQ16 DDRA_DQS3 ---DQS DQS2_c VSS_30 DQ18 DQ34 VSS_63
DDRA_DQS3#---DQS# DQS2_t DDRA_DQ28 63 64 189 190 DDRA_DQ47
DDRA_DQ27---DQ DQ18 DQ19 VSS_31 DDRA_DQ19 DDRA_DQ44 VSS_64 DQ45
DDRA_DQ28---DQ DQ19 65 66 191 192
DDRA_DQ17 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDRA_DQ46
DDRA_DQ29---DQ DQ17 69 DQ29 VSS_33 70 DDRA_DQ16 DDRA_DQ45 195 VSS_66 DQ41 196
DDRA_DQ30---DQ DQ23 DDRA_DQ18 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRA_DQS#5
DDRA_DQ31---DQ DQ22 73 DQ25 VSS_35 74 DDRA_DQS#2 199 VSS_68 DQS5_c 200 DDRA_DQS5
+1.2V 75 VSS_36 DQS3_c 76 DDRA_DQS2 201 DM5_n/DBl5_n/NC DQS5_t 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRA_DQ43 203 VSS_69 VSS_70 204 DDRA_DQ41
DDRA_DQ32---DQ DQ34 VSS_37 VSS_38 DQ46 DQ47
DDRA_DQ33---DQ DQ35 DDRA_DQ21 79 80 DDRA_DQ20 205 206
DQ30 DQ31 DDRA_DQ42 VSS_71 VSS_72 DDRA_DQ40
RD92 240_0402_1%

RD93
DDRA_DQ34---DQ DQ38 DDRA_DQS4 ---DQS DQS4_c 81 82 207 208
DDRA_DQ23 83 VSS_39 VSS_40 84 DDRA_DQ22 209 DQ42 DQ43 210
DDRA_DQ35---DQ DQ39 DDRA_DQS4#---DQS# DQS4_t DQ26 DQ27 VSS_73 VSS_74
1

1
DDRA_DQ62 DDRA_DQ56

240_0402_1%
DDRA_DQ36---DQ DQ36 85 86 211 212
87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
DDRA_DQ37---DQ DQ32 89 CB5/NC CB4/NC 90 DDRA_DQ61 215 VSS_75 VSS_76 216 DDRA_DQ60
DDRA_DQ38---DQ DQ37 91 VSS_43 VSS_44 92 217 DQ49 DQ48 218
DDRA_DQ39---DQ DQ33 93 CB1/NC CB0/NC 94 DDRA_DQS#7 219 VSS_77 VSS_78 220
2

DDRA_DQS#8 95 VSS_45 VSS_46 96 DDRA_DQS7 221 DQS6_c DM6_n/DBl6_n/NC 222

DDRA_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRA_DQ63
DDRA_DQ40---DQ DQ43 DQS8_t VSS_47 VSS_80 DQ54
DDRA_DQ41---DQ DQ47 99 100 DDRA_DQ59 225 226
101 VSS_48 CB6/NC 102 227 DQ55 VSS_81 228 DDRA_DQ57
DDRA_DQ42---DQ DQ42 DDRA_DQS5 ---DQS DQS5_c CB2/NC VSS_49 VSS_82 DQ50
DDRA_DQS5#---DQS# DQS5_t 103 104 DDRA_DQ58 229 230
DDRA_DQ43---DQ DQ46 VSS_50 CB7/NC DQ51 VSS_83 DDRA_DQ55
DDRA_DQ44---DQ DQ44 105 106 231 232
107 CB3/NC VSS_51 108 DDRA_DQ53 233 VSS_84 DQ60 234
C DDRA_DQ45---DQ DQ40 109 VSS_52 RESET_n 110
DDRA_DRAMRST#_R 5
235 DQ61 VSS_85 236 DDRA_DQ54 C
DDRA_DQ46---DQ DQ41 4 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 4 DDRA_DQ51 VSS_86 DQ57
111 112 1 237 238
DDRA_DQ47---DQ DQ45 113 VDD_1 VDD_2 114 CD3 239 DQ56 VSS_87 240 DDRA_DQS#6
4 DDRA_BG1 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 4 VSS_88 DQS7_c DDRA_DQS6
115 116 0.1u_0201_10V6K 241 242
4 DDRA_BG0 BG0 ALERT_n DM7_n/DBl7_n/NC DQS7_t
DDRA_DQ48---DQ DQ62 117 118 @ 243 244
119 VDD_3 VDD_4 120 2 DDRA_DQ48 245 VSS_89 VSS_90 246 DDRA_DQ49
DDRA_DQ49---DQ DQ63 4 DDRA_MA12 A12 A11 DDRA_MA11 4 DQ62 DQ63
DDRA_DQ50---DQ DQ59 DDRA_DQS6 ---DQS DQS7_c 121 122 247 248
4 DDRA_MA9 A9 A7 DDRA_MA7 4 DDRA_DQ52 VSS_91 VSS_92 DDRA_DQ50
DDRA_DQ51---DQ DQ56 DDRA_DQS6#---DQS# DQS7_t 123 124 249 250
125 VDD_5 VDD_6 126 251 DQ58 DQ59 252
DDRA_DQ52---DQ DQ58 4 DDRA_MA8 A8 A5 DDRA_MA5 4 SMB_CLK_S3 VSS_93 VSS_94 SMB_DATA_S3
127 128 253 254
DDRA_DQ53---DQ DQ61 4 DDRA_MA6
129 A6 A4 130
DDRA_MA4 4
RD1 1 2
7,39 SMB_CLK_S3 +VDD_SPD 255 SCL SDA 256 DDRA_SA0 SMB_DATA_S3 7,39
DDRA_DQ54---DQ DQ57 VDD_7 VDD_8 +3VS VDDSPD SA0
257 258 +VTT
DDRA_DQ55---DQ DQ60 1/10W_0_+-5%_0603 259 VPP_1 VTT 260 DDRA_SA1
1 1 VPP_2 SA1
CD@
DDRA_DQ56---DQ DQ53 ARGOS_D4AR0-26001-1P40 CD4 CD5 261 262 +1.2V
2.2U_0402_6.3V6M 0.1u_0201_10V6K GND_1 GND_2
DDRA_DQ57---DQ DQ50 ME@ 2 2
DDRA_DQ58---DQ DQ51 DDRA_DQS7 ---DQS DQS6_c ARGOS_D4AR0-26001-1P40 Follow CRB v2.0, mount RD91
DDRA_DQS7#---DQS# DQS6_t ME@ DDRA_EVENT# RD91 1 2 240_0402_1%
DDRA_DQ59---DQ DQ55 DDRA_ALERT#
DDRA_DQ60---DQ DQ48 RD94 1 2 240_0402_1%
DDRA_PAR RD95 1 2 240_0402_1%
DDRA_DQ61---DQ DQ49
DDRA_DQ62---DQ DQ52 RD2 1 2 +VPP DDRA_ALERT# , DDRA_PAR Follow CRB v2.0, mount RD94,RD95
DDRA_DQ63---DQ DQ54 +2.5V_DDR
1/10W_0_+-5%_0603

Follow CRB v1.2 +VTT +2.5V_DDR

Layout Note:
Place near DIMM 2 x 0603_10uF; 4 x 0402_1uF add 3T_MLCC__bron 2 x 0603_10uF; 2 x 0402_1uF
+1.2V

CD38
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1

4.3U_0402_4V6-M
Note: @1 @1 @1 @1 1 1 1 1 1 1

3
CD119

CD7

CD8

CD9

CD@
CD10
VREF trace width:20 mils at least
1

0.1u_0201_10V6K
2 RD96 Spacing:20mils to other signal/planes

CD@

CD@
2

4
2 2 2 2 @2 2 2 2 2 2
Place near DIMM scoket

CD118

CD121

CD122
3.65K_0402_1%

CD6

CD11

CD12
con irm with G330 IGM， follow CRB__bron
2

B RD97 1 @ 2 0_0402_5% DDRA_VREFCA_TP 1 TP78 @ B

+VREF_CA_DIMM RD98 1 2 DDRA_VREFCA_R
2_0402_5% RD99 1 2 0_0402_5% Follow CRB add 2*0402_1uF
DDRA_VREFCA 4
1 @

CD120 +1.2V
1

1 0.022U_0201_6.3V6-K
RD100 2 cost down 1x 330uF from CRB
8 x 0603_10uF; 8 x 0402_1uF
CD14 3.65K_0402_1%
1

0.1u_0201_10V6K
2 RD101
2

24.9_0402_1%

CD39
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

4.3U_0402_4V6-M
CD19

CD20

CD21

CD22

CD23

CD24

CD25

CD26
2

3
CD@ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @

CD@

CD@

4
CD27

CD28

CD29

CD30

CD31

CD32

CD33

CD34
CD@ CD@ CD@

+1.2V

2 x 0402_4.7uF; 2 x 0201_0.1uF; 2 x 0402_33pF

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

RF@

RF@
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

33P_0402_50V8J

33P_0402_50V8J
0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 1 1 1
+3VS +3VS +3VS

2 2 2 2 2 2
1

CD15

CD16

CD17

CD18

CD36

CD37
RD7 RD8 RD9
0_0402_5% 0_0402_5% 0_0402_5%

@ @ @
For EMC
2

Near JDDRL1
DDRA_SA0 DDRA_SA1 DDRA_SA2

A A
1

RD10 RD11 RD12

0_0402_5% 0_0402_5% 0_0402_5%
2

con irm with G330 IGM， follow APL__bron

CRB v1.2 P64 Use 10K PD

SPD Address = A0H Title

Security Classification LC Future Center Secret Data
Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 17 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 18 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 19 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 20 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 SOC (Power2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 21 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 ATI_EXO-PRO_TMDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 22 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 ATI_EXO-PRO_DP Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 23 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 ATI_EXO-PRO_Power
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 24 of 60

5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 ATI_EXO-PRO_MEM IF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 25 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 ATI_R17M-P1-50_VRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 26 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 BLANK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 27 of 60
5 4 3 2 1
 5 4 3 2 1

B+ to +LEDVDD POWER CMOS CAMERA

LCD POWER CIRCUIT +3VS
Need Short
+3VS_EDP_R

+LCDVDD_CON
+3VS +LEDVDD J2 1 2
U9
W=60mils
V20B+ Need Open @ 1 2
F10 NEC@
5 1 R4712 1 2 0_0805_5% 2A 80 mil 2A 80 mil JUMP_43X39
IN OUT J28 1 2 1 2
1 2
1U_0402_6.3V6K

4.7U_0402_6.3V6M

0.1U_0201_6.3V6-K
1 2 @ +3VS_EDP
GND

33P_0402_50V8J

4.7U_0805_25V6-K

0.1U_0201_25V6-K
C1

CD@
C5002 C25 0.5A_32V_ERBRD0R50X
JUMP_43X39

15P_0402_50V8J
PCH_ENVDD 4 3 1 1 1 1 1 1 C23 LP2301ALT1G_SOT23-3
EN OCB

EMC@
C122

C4953
W=40 mils R3
2

C2
Q7 3 1 @ 1 LBG@ 2 0_0603_5%

D
F2

0.1U_0201_6.3V6-K

0.01U_0201_6.3V7-K

0.1U_0201_6.3V6-K
SY6288C20AAC_SOT23-5 EMC@
2 2 2 2 2 2

10U_0603_6.3V6M
EMC_NS@
1 2

RF@
D D
W=40mils

G
1 1 1 1

C4964
C5 C6 C3
PCH_ENVDD 3A_32V_0497003PKRHF
9 PCH_ENVDD
1

C23 0.1u for G HSW panel blink issue @

@2 2 2 2

CD@
R35 GLK will have internal 20K PD, confirm if need stuff R35
@
100K_0402_5%
R5 1 @ 2 0_0402_5%
44 CMOS_ON#
1.8V DC Specification :VOH=1.35V;VOL=0.45V For RF request: keep 0402
2

0.1U_0201_6.3V6-K
1
1
C9 C10
GLK SoC output enable Voh min is ???(only found 3.3V nominal@EDS v1.2 P192) +3VS 0.01U_0201_6.3V7-K
2 @ @
2
For EMI
Close to R5

100K_0402_1%
R19 1 2 0_0402_5% INVT_PWM
9 PCH_EDP_PWM

R8
GLK will have internal 20K PD, confirm if need stuff R20
1

R20

1
100K_0402_5%
@
CRB no 100K pull down @
EDP_AUX#
2

EDP_AUX
JEDP1
+LEDVDD 1
+3VS 2 1
2

100K_0402_1%
3
4 3
4
2

R9
5
R10 CPU_EDP_TX0+ C19 2 1 0.1U_0201_6.3V6-K EDP_TX0+ 6 5
9 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 6
4.7K_0402_5% C16 2 1 0.1U_0201_6.3V6-K 7
9 CPU_EDP_TX0-

1
@ 8 7
C
@ CPU_EDP_TX1+ C17 2 1 0.1U_0201_6.3V6-K EDP_TX1+ 9 8 C
9 CPU_EDP_TX1+
1

CPU_EDP_TX1- C18 2 1 0.1U_0201_6.3V6-K EDP_TX1- 10 9

9 CPU_EDP_TX1- 10
R12 1 2 0_0402_5% DISPOFF# 11
44 BKOFF# CPU_EDP_AUX EDP_AUX 11
C20 2 1 0.1U_0201_6.3V6-K 12
9 CPU_EDP_AUX CPU_EDP_AUX# EDP_AUX# 12
C21 2 1 0.1U_0201_6.3V6-K 13
9 CPU_EDP_AUX# 13
R14 1 2 0_0402_5% ENBKL 14
9 PCH_ENBKL ENBKL 44 14
DISPOFF# 15
15
1

INVT_PWM 16
R16 L12 EMC_NS@
AUX do NOT reserve pull high and pull low for eDP panel 17 16
USB20_N6 USB20_N6_R 9 CPU_EDP_HPD 17
100K_0402_5% 1 2 +LCDVDD_CON 18
1 2 19 18
W=60mils 20 19
CRB use a LS and no 100k pull down
2

USB20_P6 4 3 USB20_P6_R 21 20
4 3 22 21
34 DMIC_CLK 22
EXC24CH900U_4P 34 DMIC_DATA 23
GLK will have internal 20K PD, confirm if need stuff R16 24 23
+3VS_EDP 24
EMC_NS@ 25
C1320 1 2.047U_0201_6.3V6K
W=40mils 26 25
DMIC_CLK DISPOFF# INVT_PWM 27 26
USB20_P6 R182 1 2 0_0402_5% USB20_P6_R 28 27
8 USB20_P6 28
100P_0201_25V8J

USB20_N6 R183 1 2 0_0402_5% USB20_N6_R 29

1 8 USB20_N6 29

15P_50V_J_NPO_0201
C11

1 1 30
30

15P_50V_J_NPO_0201
EMC@

EMC@
C12
31
G1

EMC@
C13
32
2 G2
2 2 DRAPH_FC5AF301-3181H
ME@

EMC

B B

Touch Screen L15

USB20_P7 1 2 USB20_P7_CONN
Touch Screen
1 2

USB20_N7 4 3 USB20_N7_CONN F3 TS_NEC@

4 3 +5VS 1 2
EXC24CH900U_4P +TS_PWR
EMC_NS@ 0.5A_32V_ERBRD0R50X Change Symbol follow 140s whl 0711 bron

R17 1 @ 2 1/10W_0_+-5%_0603 1 TS_LBG@2

R26 1/10W_0_+-5%_0603 JTS1
1
+3VS C4998 1
For EMI 0.1u_0201_10V6K R28 2 TS@ 1 0_0402_5% TS_RS 2 1
44 EC_TS_ON 2
R18 1 TS@ 2 1/10W_0_+-5%_0603 TS@ 3
2 R23 1 TS@ 2 0_0402_5% USB20_N7_CONN 4 3
8 USB20_N7 USB20_P7_CONN 4
R24 1 TS@ 2 0_0402_5% 5
8 USB20_P7 5
6
USB20_N7_CONN 6 7
GND1 8
USB20_P7_CONN GND2
HIGHS_WS83061-S0171-HF
3

+TS_PWR
ME@
A A
1

D46
1

D45
AZC199-02S.R7G_SOT23-3
2

EMC_NS@ Title
AZ5725-01F.R7GR_DFN1006P2X2
Security Classification LC Future Center Secret Data
2

EMC_NS@ eDP/CMOS
Issued Date 2018/07/09 Deciphered Date 2019/07/08
1

For ESD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 28 of 60

5 4 3 2 1
 5 4 3 2 1

RIGHT SIDE USB3.0 PORT

+USB_VCCB

+5VALW +USB_VCCB C2910 1 2 100U_1206_6.3V6M

U5
5 1
IN OUT C2907 1 2 47U_6.3V_M_X5R_0805_H1.25
1
C4301 2
1U_0402_6.3V6K GND
@
4 3 USB_OC1#_GPIO_45 C2908 2 1 47U_6.3V_M_X5R_0805_H1.25
2 31,44 USB_ON# ENB OCB USB_OC1#_GPIO_45 8,15,31
SY6288D20AAC_SOT23-5 1 @
C2926 C2900 1 2 1U_0402_10V6K
D 1000P_0201_50V7-K D
Low Active 2A EMC_NS@ @
2 C2902 1 2 1U_0402_10V6K

@
C2909 1 2 470P_0402_50V7K

EMC_NS@

L4306 EMC@ JUSB2

USB20_N1_U 1 2 USB20_N1_R
1 2 C5003 1 2 0.1u_0201_10V6K USB30_TX_C_P0 R9465 1 @ 2 0_0402_5% USB30_TX_R_P0 9
8 USB30_TX_P0 StdA_SSTX+
1
USB20_P1_U 4 3 USB20_P1_R C5004 1 2 0.1u_0201_10V6K USB30_TX_C_N0 R9466 1 @ 2 0_0402_5% USB30_TX_R_N0 8 VBUS
4 3 8 USB30_TX_N0 USB20_P1_U USB20_P1_R StdA_SSTX-
R9467 1 @ 2 0_0402_5% 3
EXC24CH900U_4P UARTA_P80_EN 7 D+
USB20_N1_U R9468 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
R9452 1 @ 2 0_0402_5% USB30_RX_R_P0 6 D- GND_2 11
8 USB30_RX_P0 StdA_SSRX+ GND_3
4 12
R9453 1 @ 2 0_0402_5% USB30_RX_R_N0 5 GND_1 GND_4 13
8 USB30_RX_N0 StdA_SSRX- GND_5
R537

2
R9464 ALLTO_C19043-10905-L

Debug@

USB@
ME@

100K_0402_5%

0_0402_5%
L4307 EMC@

1
USB30_TX_C_N0 1 2 USB30_TX_R_N0 Change Symbol follow 140s whl 1023 bron
1 2

USB30_TX_C_P0 4 3 USB30_TX_R_P0
4 3
EXC24CH900U_4P

EMC
USB30_TX_R_P0

USB20_P1_R
+USB_VCCB USB30_TX_R_N0
C USB20_N1_R C
L4308 EMC@
USB30_RX_N0 1 2 USB30_RX_R_N0
1 2

1
D4310 EMC@ D50 D51

PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2
USB30_RX_P0 4 3 USB30_RX_R_P0 USB30_RX_R_N0 9 10 1 1USB30_RX_R_N0

1
4 3 D2901

EMC_NS@

EMC_NS@
1
EXC24CH900U_4P USB30_RX_R_P0 8 9 2 2 USB30_RX_R_P0 AZC199-02S.R7G_SOT23-3 D4309

EMC_NS@

AZ5725-01F.R7GR_DFN1006P2X2
EMC@

1
USB30_TX_R_N0 7 7 4 4USB30_TX_R_N0

USB30_TX_R_P0 6 6 5 5 USB30_TX_R_P0

2
2
3 3

2
2
8

1
AZ1045-04F_DFN2510P10E-10-9

place between CMC/R and ESD_bron 0814

USBDEBUG Kernel debug

Set input Set input

Set output Low ENABLE

For USB Debug Function

UARTA_P80_EN POST 80
B Set input DISABLE B

Set output Low ENABLE

USB20_P1 R9462 1 USB@ 2 0_0402_5% USB20_P1_U

R531 1 @ 2 0_0402_5% USB_UART_SEL

7 USBDEBUG
USB20_N1 R9463 1 USB@ 2 0_0402_5% USB20_N1_U
OE# S FUNCTION
H X DISABLE

L L D(+/-) to 1D(+/-)

L H D(+/-) to 2D(+/-)

+3VALW
1

+3VALW
R547
U3
Debug@ 10K_0402_5%
2

R9460 1 Debug@ 2 0_0402_5% EC_TX_R 1 10 R542 1 Debug@ 2 0_0402_5%

39,44 EC_TX 1D+ VCC USB_UART_SEL
R9461 1 Debug@ 2 0_0402_5% EC_RX_R 2 9 USB_UART_SEL
39,44 EC_RX 1D- S
1

USB20_P1 3 8 USB20_P1_U D
8 USB20_P1 2D+ D+ UARTA_P80_EN
NCY3958Y 2
USB20_N1 4 7 USB20_N1_U G L2N7002KWT1G_SOT323-3
8 USB20_N1 2D- D- Q56
5 6 S Debug@
3

GND1 OE#
11
GND2

NCT3958Y_DFN10_3X3
Debug@
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 3D Camera

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 29 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 BLANK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 30 of 60
5 4 3 2 1
 5 4 3 2 1

LEFT SIDE USB3.0 PORT x1

+USB_VCCA

C3111 1 2 100U_1206_6.3V6M

+5VALW +USB_VCCA C3103 1 2 47U_6.3V_M_X5R_0805_H1.25

U2
D D
5 1 @
IN OUT C3104 2 1 47U_6.3V_M_X5R_0805_H1.25
1
C128 2
1U_0402_6.3V6K GND
@
4 3 USB_OC1#_GPIO_45 C125 1 2
2 29,31,44 USB_ON# ENB OCB USB_OC1#_GPIO_45 8,15,29 1U_0402_10V6K
SY6288D20AAC_SOT23-5 1 @
C140 C127 1 2
1000P_0201_50V7-K 1U_0402_10V6K
Low Active 2A EMC_NS@ @
2 C3128 1 2 470P_0402_50V7K

EMC_NS@
JUSB1

USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9

8 USB30_TX_P1 StdA_SSTX+
1
USB30_TX_N1 C124 1 2 0.1u_0201_10V6K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
8 USB30_TX_N1 USB20_P3 USB20_P3_R StdA_SSTX-
R97 1 @ 2 0_0402_5% 3
8 USB20_P3 D+
L13 EMC@ 7
USB30_RX_N1 1 2 USB30_RX_R_N1 USB20_N3 R93 1 @ 2 0_0402_5% USB20_N3_R 2 GND_DRAIN 10
1 2 8 USB20_N3 USB30_RX_P1 USB30_RX_R_P1 D- GND_2
R94 1 @ 2 0_0402_5% 6 11
8 USB30_RX_P1 4 StdA_SSRX+ GND_3 12
USB30_RX_P1 4 3 USB30_RX_R_P1 USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13
4 3 8 USB30_RX_N1 StdA_SSRX- GND_5
EXC24CH900U_4P
ALLTO_C19043-10905-L
L16 EMC@ ME@
USB30_TX_C_N1 1 2 USB30_TX_R_N1 Change Symbol follow 140s whl 1023 bron
1 2

USB30_TX_C_P1 4 3 USB30_TX_R_P1
4 3
EXC24CH900U_4P
USB30_TX_R_P1
C
EMC C
USB20_P3_R
L8 EMC@ +USB_VCCA USB30_TX_R_N1
USB20_N3 1 2 USB20_N3_R USB20_N3_R D12 EMC@
1 2 USB30_RX_R_N1 9 10 1USB30_RX_R_N1
1

AZ5725-01F.R7GR_DFN1006P2X2

2
USB20_P3 4 3 USB20_P3_R D11 USB30_RX_R_P1 8 9 2 2 USB30_RX_R_P1
4 3

1
D13 D52 D53

PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2
EXC24CH900U_4P AZC199-02S.R7G_SOT23-3 USB30_TX_R_N1 7 7 4 4USB30_TX_R_N1

1
EMC@

EMC_NS@

EMC_NS@
USB30_TX_R_P1 6 5 USB30_TX_R_P1
EMC 6 5

2
3 3
EMC_NS@

2
8

2
AZ1045-04F_DFN2510P10E-10-9

2
1
place between CMC/R and ESD_bron 0814

+5VALW +USB_VCCD
U7
5 1
B IN OUT B
1
C3109 2
1U_0402_6.3V6K GND

29,31,44 USB_ON#
4 3 USB_OC1#_GPIO_45 EMC
2 ENB OCB
SY6288D20AAC_SOT23-5 1
C3110 L1
1000P_0201_50V7-K USB20_N4 1 2 USB20_N4_R
EMC_NS@ 1 2
Low Active 2A 2 USB20_N4_R
USB20_P4 4 3 USB20_P4_R
4 3 USB20_P4_R
EXC24CH900U_4P
EMC@

2
+USB_VCCD
D48
AZC199-02S.R7G_SOT23-3
EMC@
C3112 1 2 100U_1206_6.3V6M
+USB_VCCB +USB_VCCD
Don't Need Short +USB_VCCD
J6 C3107 1 2 47U_6.3V_M_X5R_0805_H1.25
1 2 @
1 2
@
JUMP_43X79 C3108 2 1 47U_6.3V_M_X5R_0805_H1.25

AZ5725-01F.R7GR_DFN1006P2X2

1
1
@ D3101
C4995 1 2 470P_0402_50V7K

1
EMC_NS@ Close to Connector
C4996 1 2 1U_0603_25V6M

@ 2
EMC_NS@
2

JUSB3
A A
1
USB20_N4 R4690 1 @ 2 0_0402_5% USB20_N4_R 2 VBUS
8 USB20_N4 USB20_P4 USB20_P4_R D-
R4691 1 @ 2 0_0402_5% 3
8 USB20_P4 4 D+ 5
GND GND1 6
GND2 7
GND3 8
GND4

ALLTO_C107G1-10803-L
ME@ Security Classification LC Future Center Secret Data Title
Change Symbol follow 140s whl 1023 bron
Issued Date 2018/07/09 Deciphered Date 2019/07/08 USB3.0&USB2.0 CONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 31 of 60
5 4 3 2 1
 5 4 3 2 1

R9433 1 2 0_0402_5%
+5VS_HDMI

LBAT54AWT1G_SOT323-3
R9434 1 @ 2 0_0402_5% D8
+5VALW

1
2

2
0_0402_5%

0_0402_5%
L2 EMC@
HDMI_CLK-_C HDMI_CLK-_CON 1

R4661

R4660
1 2 2 EMC_NS@
1 2 C26 10P_0201_25V8G
@
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2 EMC_NS@

1
4 3 C27 10P_0201_25V8G
EXC24CH900U_4P R9431 1 2 0_0402_5%
+3VS
L3 EMC@
D HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2 EMC_NS@ R9432 1 @ 2 0_0402_5% D
1 2 +1.8V_3.3V_PU
C28 10P_0201_25V8G

3
4
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2 EMC_NS@
4 3 C29 10P_0201_25V8G
RP10
EXC24CH900U_4P

2
2.2K_0404_4P2R_5%

G
L4 EMC@

2
1
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2 EMC_NS@
1 2 C30 10P_0201_25V8G
DDPB_CLK 1 6 HDMICLK_R

S
HDMI_TX1+_C HDMI_TX1+_CON 1 9 DDPB_CLK

D
4 3 2 EMC_NS@
4 3 C31 10P_0201_25V8G DDC Signals Can Be Set to 1.8/3.3 by Soft Straps Q157A
EXC24CH900U_4P
L2N7002KDW1T1G_SOT363-6
L5 EMC@

5
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 EMC_NS@

G
1 2 C32 10P_0201_25V8G

HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2 EMC_NS@

4 3 C33 10P_0201_25V8G DDPB_DATA 4 3 HDMIDAT_R

S
9 DDPB_DATA

D
EXC24CH900U_4P

EMC request stuff caps 03/09 Q157B SCH CKL request MOSFET output capacitance less than 10pF
EMC L2N7002KDW1T1G_SOT363-6

+5VS +5VS_HDMI_F +5VS_HDMI

D5
Follow PDG & CRB use 470ohm,SVT change 470 to 560 for HDMI issue 2 @ F1
C 1 1 2
F1 use SP040007H00 footprint,only change description , C
HDMI_CLK-_C R9436 1 2 1/16W_560_1%_0402 3 vaule and partnumber.
HDMI_CLK+_C R9437 1 2 1/16W_560_1%_0402 RB491D_SOT23-3 1.1A_8V_1206L110THYR SP040007K00 and SP040007H00 is same footprint.

LP2301ALT1G_SOT23-3 1
HDMI_TX0-_C R9438 1 2 1/16W_560_1%_0402 C34
HDMI_TX0+_C R9439 1 2 1/16W_560_1%_0402 1 3 Q22 0.1u_0201_10V6K

S
2

G
2
HDMI_TX1-_C R9440 1 2 1/16W_560_1%_0402
HDMI_TX1+_C R9441 1 2 1/16W_560_1%_0402
46,55 SUSP

JHDMI1
HDMI_TX2-_C R9442 1 2 1/16W_560_1%_0402
HDMI_TX2+_C R9443 1 2 1/16W_560_1%_0402 18 15 HDMICLK_R
+5V_Power SCL 16 HDMIDAT_R
Change to 0404 RP 04/29 SDA
HDMI_TX0+ C38 2 1 0.1u_0201_10V6K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7
9 HDMI_TX0+ TMDS_Data0+
1

Q13 D HDMI_TX0- C37 2 1 0.1u_0201_10V6K HDMI_TX0-_C R45 2 @ 1 0_0402_5% HDMI_TX0-_CON 9 13

9 HDMI_TX0- HDMI_TX1+ HDMI_TX1+_C HDMI_TX1+_CON TMDS_Data0- CEC
2 C40 2 1 0.1u_0201_10V6K R48 2 @ 1 0_0402_5% 4 17
+3VS 9 HDMI_TX1+ HDMI_TX1- HDMI_TX1-_C HDMI_TX1-_CON TMDS_Data1+ DDC/CEC_Ground HDMI_DET
G C39 2 1 0.1u_0201_10V6K R47 2 @ 1 0_0402_5% 6 19
9 HDMI_TX1- HDMI_TX2+ HDMI_TX2+_C HDMI_TX2+_CON TMDS_Data1- Hot_Plug_Detect
C42 2 1 0.1u_0201_10V6K R50 2 @ 1 0_0402_5% 1
9 HDMI_TX2+ HDMI_TX2- HDMI_TX2-_C HDMI_TX2-_CON TMDS_Data2+
S L2N7002KWT1G_SOT323-3 C41 2 1 0.1u_0201_10V6K R49 2 @ 1 0_0402_5% 3
9 HDMI_TX2-
3

TMDS_Data2-
R42 1 @ 2 8 14
5 TMDS_Data0_Shield Utility
100K_0402_5% 2 TMDS_Data1_Shield
TMDS_Data2_Shield
20
B 11 GND1 21 B
HDMI_CLK+ C36 2 1 0.1u_0201_10V6K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 TMDS_Clock_Shield GND2 22
9 HDMI_CLK+ HDMI_CLK- HDMI_CLK-_C R43 2 HDMI_CLK-_CON TMDS_Clock+ GND3
C35 2 1 0.1u_0201_10V6K @ 1 0_0402_5% 12 23
9 HDMI_CLK- TMDS_Clock- GND4

D6 D7 ALLTO_C128AF-K1935-L
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 10 9 HDMI_TX1-_CON ME@
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON +5VS_HDMI
Intel PDG & CRB Suggestion Circuit Change Symbol follow 140s whl 0711 bron
HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

2
+1.8V_3.3V_PU
HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON D4

2
3 3 3 3
R3405 @ LBAT54SWT1G_SOT323-3
8 8 10K_0402_5%

1
SCH CKL request Diode Cap less than 10pF

1
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
HDMI_HPD#
EMC_NS@ EMC_NS@ 9 HDMI_HPD#
EMC

1
D Q12
2 HDMI_DET
Follow CG711 G
D3 L2N7002KWT1G_SOT323-3
HDMI_DET 1 1 10 9 HDMI_DET S

2
HDMICLK_R 2 2 9 8 HDMICLK_R R41
100K_0402_5%
A HDMIDAT_R 4 4 7 7 HDMIDAT_R Vgs<=2.0V A

Intel PDG suggest use N-MOSFET Vgs<=1.5V

1
+5VS_HDMI 5 5 6 6 +5VS_HDMI

3 3

8
Security Classification LC Future Center Secret Data Title
AZ1045-04F_DFN2510P10E-10-9
Issued Date 2018/07/09 Deciphered Date 2019/07/08 HDMI_CONN
EMC_NS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
EMC Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 32 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 33 of 60
5 4 3 2 1
 5 4 3 2 1

D D

RA3025 1 2 1K_0402_5% CA423 1 2 0.1U_6.3V_K_X7R_0402

DA3002

44 BEEP# 3

@ 1 RA3023 1 2 1K_0402_5% CA3017 1 2 0.1U_6.3V_K_X7R_0402 BEEP

2
11 PCH_BEEP

10K_0402_5%
2
BAT54CW_SOT323-3

RA3024
RA3026 1 2 0_0402_5%

1
@

C C

+5VS
J1
+3VS 1
2 1
BEEP 3 2
4 3
5 4
+3VL 5
45 NOVO_BTN# 6
7 6
44 EC_MUTE# 7
CPU HDA BUS power 8
DVDD_IO 9 8
+3VALW need to confirm HDA power 8 USB20_N5 10 9
8 USB20_P5 10
11
RA27 1 2 1/10W_0_+-5%_0603 12 11
28 DMIC_CLK 12
@ 28 DMIC_DATA 13
B
14 13 B
DVDD_IO 15 14
+1.8VALW 6 HDA_BITCLK_AUDIO 15
16
6 HDA_SDOUT_AUDIO 17 16
1mA 6,15 HDA_SDIN0_GPIO_168 17
RA726 1 2 2 18
6 HDA_SYNC_AUDIO 18
1/10W_0_+-5%_0603 RA3027 19
DVDD_IO 19
0_0402_5% 20
+1.8VS 20
21
22 GND1
1

GND2
@
HIGHS_FC5AF201-1151H
ME@
HDA_BITCLK_AUDIO
Change Symbol follow 140s whl 0711 bron
1
CA3018
EMC_NS@
2
33P_0402_50V8J 20Pin CONN

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Codec & CR_RTS5199

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 34 of 60
5 4 3 2 1
 5 4 3 2 1

+3VALW +1.8V_TPM

+1.8VS
+1.8V_TPM
1A
RTPM17 1 @ 2 1/10W_0_+-5%_0603

2
+1.8VALW RTPM14 RTPM28
TPM@ @ RTPM28 staff for NationZ
RTPM18 1 TPM@ 2 1/10W_0_+-5%_0603 0_0603_5% 0_0603_5%
+1.8V_TPM

1
D D

10U_0603_6.3V6M

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
C808
C8794

C8799

C8795
4.7U_0402_6.3V6M
2 1 1 1 1 2
C259 C260
TPM@ @

TPM@

TPM@

TPM@
+1.8V_TPM +1.8V_TPM 1U_0402_6.3V6K 10U_0603_6.3V6M
@ 1 2 2 2 2 1

2
RTPM1 RTPM2
TPM@ 10K_0201_5% TPM@ 10K_0201_5%

22
U2101

1
1

NiC2

NiC1
VPS
RTPM3 2 TPM@ 1 0_0402_5% TPM_IRQ# 18
7 TPM_SPI_IRQ# SPI_PIRQ TPM_GP2 RTPM26 2 TPM@
3 1 10K_0402_5% +1.8V_TPM
NiC6 4 TPM_PIN4 RTPM24 2 @ 1 0_0402_5%
NiC7 +1.8V_TPM
21 5
6 TPM_SPI_MOSI MOSI NiC8
24 10
6 TPM_SPI_MISO MISO NiC9 11
NiC10 12
NiC11 13
20 NiC12 14
6,7 TPM_SPI_CS# SPI_CS NiC13 +1.8V_TPM
15
19 NiC14 16
6 TPM_SPI_CLK SPI_CLK NiC15 25
TPM_PLT_RST# 17 NiC16 26
SPI_RST NiC17 27 TPM_PIN27 RTPM25 1 @ 2 10K_0402_5%
6 NiC18 28
GPIO NiC19 31
7 NiC20
PP

29 TPM_PIN29 PIN29 reserve for TPM MS low power mode

1
NiC21 30
NiC22

GND1

GND2
C RTPM30 C

NiC3

NiC4

NiC5
@
10K_0402_5%
TPM@ ST33HTPH2E32AHB4_VQFN32_5X5

23

32

33
2

9
1TPM_PIN2
RTPM8
TPM@

+1.8V_TPM

0_0402_5%
2

1
TPM@
RTPM23
+3VALW
TABLE 10K_0402_5%

2
Pin TCG Infineon ST Micro Nuvoton NATIONZ

1
No RTPM33
PTP Spec (v38) SLB9670VQ2.0 FW 7.61 ST33HTPH2E32AHB4 NPCT750LABYX Z32H330TC TPM_PLT_RST# 2 TPM@ 1 0_0402_5% TPM_PLT_RST#_R
RTPM35 @
10K_0402_5%
1 VDD NC/VDD NC VSB VDD

2
3
TPM_PIN29 RTPM34 2 @ 1 0_0402_5% D
2 GND GND GND NC GND 5
3 GPIO NC NC NC NC QTPM1B G
4 GPIO NC NC PP/GPIO6 NC @ S
5 NC NC NC NC NC

4
6 VNC/GPIO GPIO GPIO GPIO3 NC L2N7002KDW1T1G_SOT363-6 L2N7002KDW1T1G_SOT363-6
7 GPIO/VDD PP PP NC PP

6
D QTPM1A
8 VDD VDD NC VHIO VDD 2
@ G
B B
S

1
9 GND GND NC NC GND
10 VNC NC NC NC NC
11 NC NC NC NC NC
12 NC NC NC NC NC
13 VNC/GPIO NC NC GPIO4 NC
14 VDD NC/VDD NC NC VDD
15 NC NC NC NC NC
16 GND NC/GND NC GND GND RB751V-40_SOD323-2
SCS00008K00
TPM@
D264
2 1 PLT_RST# 10,37,39,44
17 SPI_RST# RST# SPI_RST# PLTRST# SPI_RST#
18 SPI_PIRQ# PIRQ# SPI_PIRQ# PIRQ#/GPIO2 SPI_PIRQ#
19 SPI_CLK SCLK SPI_CLK SCLK SPI_CLK
20 SPI_CS# CS# SPI_CS# SCS#/GPIO5 SPI_CS# RTPM29 2 @ 1 0_0402_5%
21 MOSI MOSI MOSI MOSI/GPIO7 MOSI
22 VDD VDD VPS VHIO VDD
23 GND GND NC GND GND
24 MISO MISO MISO MISO MISO

25 NC NC NC NC NC
26 NC NC NC NC NC
27 NC NC NC NC NC
28 NC NC NC NC NC
29 VNC/GPIO NC NC SDA/GPIO0 NC
30 VNC/GPIO NC NC SCL/GPIO1 NC
A 31 VNC NC NC NC NC A

32 GND GND NC NC GND

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 TPM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 35 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 LAN_RTL8106E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 36 of 60
5 4 3 2 1
 5 4 3 2 1

+3VS Need Short +3VS_SSD

J4 1 2 @ Min 3A
1 2
D D
JUMP_43X79

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.01U_0201_10V6K
4.7U_0603_6.3V6K
@ 1 @1 1 1 1

C3713

C3701

C3702

C3703

C3704
change 0_0603 to Jump_bron 2 2 2 2 2

+3VS_SSD

JSSD1
swap PCIE port 0717_ bron 1 2
3 GND_1 3.3V_1 4
5 GND_2 3.3V_2 6
8 PCIE_PRX_DTX_N3 7 PERN3 N/C_2 8
8 PCIE_PRX_DTX_P3 9 PERP3 N/C_3 10
0.22U_0402_10V6K 1 2 C3711 PCIE_PTX_C_DRX_N3 11 GND_3 DAS/DSS# 12
8 PCIE_PTX_DRX_N3 PCIE_PTX_C_DRX_P3 PETN3 3.3V_3
0.22U_0402_10V6K 1 2 C3712 13 14
8 PCIE_PTX_DRX_P3 PETP3 3.3V_4
15 16
17 GND_4 3.3V_5 18
8 PCIE_PRX_DTX_N2 19 PERN2 3.3V_6 20
8 PCIE_PRX_DTX_P2 PERP2 N/C_4
C 21 22 C
0.22U_0402_10V6K 1 2 C3709 PCIE_PTX_C_DRX_N2 23 GND_5 N/C_5 24
8 PCIE_PTX_DRX_N2 PCIE_PTX_C_DRX_P2 PETN2 N/C_6
8 PCIE_PTX_DRX_P2 0.22U_0402_10V6K 1 2 C3710 25 26
27 PETP2 N/C_7 28
29 GND_6 N/C_8 30
8 PCIE_PRX_DTX_N1 PERN1 N/C_9
31 32
8 PCIE_PRX_DTX_P1 33 PERP1 N/C_10 34
0.22U_0402_10V6K 1 2 C3707 PCIE_PTX_C_DRX_N1 35 GND_7 N/C_11 36
8 PCIE_PTX_DRX_N1 PCIE_PTX_C_DRX_P1 PETN1 N/C_12 PCH_SATA_DEVSLP
0.22U_0402_10V6K 1 2 C3708 37 38 1
8 PCIE_PTX_DRX_P1 PETP1 DEVSLP TP3703
39 40
41 GND_8 N/C_13 42
8 PCIE_PRX_DTX_N0 @
43 PERN0/SATA-B+ N/C_14 44
8 PCIE_PRX_DTX_P0 PERP0/SATA-B- N/C_15
45 46
0.22U_0402_10V6K 1 2 C3705 PCIE_PTX_C_DRX_N0 47 GND_9 N/C_16 48
8 PCIE_PTX_DRX_N0 1 2 C3706 PCIE_PTX_C_DRX_P0 49 PETN0/SATA-A- N/C_17 50 PLT_RST#
0.22U_0402_10V6K
8 PCIE_PTX_DRX_P0 PETP0/SATA-A+ PERST# SSD_CLKREQ_Q# PLT_RST# 10,35,39,44
51 52 R3704 1 2 0_0402_5% SSD_CLKREQ# 8
53 GND_10 CLKREQ# 54 1
8 CLK_PCIE_SSD# REFCLKN PEWAKE# TP3701
55 56
8 CLK_PCIE_SSD REFCLKP N/C_18
57 58 @
GND_11 N/C_19
59 NC NC 60
61 NC NC 62
63 NC NC 64 +3VS_SSD
65 NC NC 66
TP3702 67 68
1 SSD_DET 69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72
73 GND_12 3.3V_8 74
@
75 GND_13 3.3V_9
GND_14
77 76
PEG1 PEG2

ARGOS_NASM0-S6701-TS40
ME@

B Change Symbol follow 140s whl 0711 bron B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 LAN_Transformer

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 37 of 60
5 4 3 2 1
 5 4 3 2 1

THERMAL SENSOR
Near CPU Core
Close to U1 REMOTE2+
REMOTE+_R R176 1 2 0_0402_5% REMOTE2+
REMOTE+_R TMSEN_UMA@

1
1
C44 REMOTE-_R R177 1 2 0_0402_5% REMOTE2-

C
2200P_0402_25V7-K TMSEN_UMA@ 1 Q16
TMSEN@ C46 2 B LMBT3904WT1G_SOT323-3
2 REMOTE-_R 100P_0201_25V8J
@
2

E
TMSEN_UMA@
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:

3
Set Thermal Sensor as a BOM Structure Trace width/space:10/10 mil
Trace length:<8" REMOTE2-
D D

Near CPU
+3VALW

SMSC thermal sensor

placed near DIMM

1
R25
+3VS 13.7K_0402_1%
U1
1 8 EC_SMB_CK2
EC_SMB_CK2 44

2
VDD SCL NTC_V2
1 REMOTE+_R 2 7 EC_SMB_DA2
D+ SDA EC_SMB_DA2 44

1
C47
0.1U_0201_6.3V6-K REMOTE-_R 3 6 R288
TMSEN@ D- ALERT#
100K_0402_1%_TSM0B104F4251RZ
2 R51 2 @ 1 4 5
+3VS T_CRIT# GND
10K_0402_5%

2
NCT7718W_MSOP8 TMSEN@
Address 1001_101xb

2
R191 R192
0_0402_5% 0_0402_5%
+5VLP +5VLP
+5VLP @

1
HW thermal sensor

2
1 R252 R253 EC_AGND
C4 21.5K_0402_1% 21.5K_0402_1%
0.1U_0201_6.3V6-K @ @
@

1
2
U4 @
C 1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1 C
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
44,54 EC_ON OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

Over temperature threshold:

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

FAN Conn

B B

+5VS_FAN
JFAN1
F4 @ 1
44 EC_FAN_PWM 1
1 2 44 EC_FAN_SPEED 2
3 2
1A_32V_ERBRD1R00X +5VS_FAN 4 3
+5VS +5VS_FAN 4
5
R3915 1 @ 2 1/10W_0_+-5%_0603 6 GND1
GND2
1
C3907 1
@ C3908 @ HIGHS_WS33040-S0351-HF
10U_0805_10V6K .1U_0402_10V6-K
ME@
2
2

Change Symbol follow 140s whl 0711 bron

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Thermal sensor/FAN CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 38 of 60
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX) UART Transceiver

+3VALW +3VALW

+1.8VALW

+3V_WLAN

1 100K_0402_5%

1 100K_0402_5%
+3VS

@
1 1
R9469 1 2 0_0805_5%
+3VALW

10U_0603_10V6K

4.7U_0805_6.3V6K
+3VALW @1

UART@

UART@
1

C4002
@

C4003
U24
+3VALW
R9470 1 2 0_0805_5% 16 1

2
+3VALW 2 2 VCCA DIR1
15 2

R259

R258
VCCB DIR2

1
R4664 1 2 0_0402_5% UART_B1 14 3 UART_RX_DEBUG
U6 7 SOC_UART_RXD B1 A1
R2225 @
75K_0402_5% 5 1 R9471 1 2 0_0805_5% R4666 1 2 0_0402_5% UART_B2 13 4 UART_TX_DEBUG
IN OUT 7,15 SOC_UART_TXD_GPIO_65 B2 A2
@
2 12 5

2
GND B3 A3
1
WLAN_PWR_EN

C4009
0.01U_0402_25V7K
4 3 11 6
Q2202 EN OCB B4 A4

1
2N7002KW_SOT323-3 1 10 7 +3VALW +1.8VALW
@ D R2229 SY6288C20AAC_SOT23-5 2@ GND DIR3
2 200K_0402_5% @ 9 8
11 CNVI_EN# OE DIR4
G @
1

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
2
R2226 S SN74AVC4T774PWR_TSSOP16 1 1
3

75K_0402_5% @

C4967

C4968
@
2

2 2

UART@

UART@
R2223 1 @ 2 0_0402_5% Place near U24.15&U24.16 Pin
7 PM_SLP_WLAN#

R2233 1 @ 2 0_0402_5%
10,44,46,54,57 SUSP#

2 2
+3V_WLAN

10U_0603_6.3V6M
0.01U_0201_10V6K
1 1 1

.1U_0402_10V6-K
C4004

C4001

C4005
2 2 2

JWLAN1

1 2
USB20_P2 3 GND1 3.3VAUX1 4
8 USB20_P2 USB20_N2 USB_D+ 3.3VAUX2
5 6 1
8 USB20_N2 7 USB_D- LED1# 8 T4001
CNV_WR_D1N 9 GND2 PCM_CLK/I2S_SCK 10 CNVI_RF_RST#_R R4026 1 CNVI@ 2 0_0402_5%
7 CNV_WR_D1N CNV_WR_D1P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RST#_GPIO_195 7,15
11 12
7 CNV_WR_D1P 13 SDIO_CMD PCM_IN/I2S_SD_IN 14 XTAL_CLKREQ_R R4021 1 CNVI@ 2 0_0402_5%
CNV_WR_D0N SDIO_DATA0 PCM_OUT/I2S_SD_OUT XTAL_CLKREQ_GPIO_196 7,15
15 16 1
7 CNV_WR_D0N CNV_WR_D0P 17 SDIO_DATA1 LED#2 18 T4002 +1.8VALW
7 CNV_WR_D0P SDIO_DATA2 GND11
19 20
CNV_WR_CLKN 21 SDIO_DATA3 UART_WAKE# 22 CNVI_BRI_RSP_R R4022 1 CNVI@ 2 33_0402_5%
7 CNV_WR_CLKN CNV_WR_CLKP 23 SDIO_WAKE# UART_RXD CNVI_BRI_RSP_GPIO_192 7,15
7 CNV_WR_CLKP SDIO_RESET#

20K_0402_5%
2
RC848
KEY E
25 PIN24~PIN31 NC PIN 24
27 26

1
29 28
31 30 Close to M.2 CONN
3 3
33 32
GND3 UART_TXD CNVI_RGI_RSP_R CNVI_RGI_DT_GPIO_193 7,15
35 34 R4055 1 CNVI@ 2 33_0402_5%
8 PCIE_PTX_C_DRX_P5 37 PETP0 UART_CTS 36 CNVI_RGI_RSP_GPIO_194 7,15
+3VS +3V_WLAN 8 PCIE_PTX_C_DRX_N5 PETN0 UART_RTS EC_TX_RSVD CNVI_BRI_DT_GPIO_191 7,15
39 38 R4006 1 @ 2 0_0402_5%
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R4007 1 @ 2 0_0402_5%
WLAN 8 PCIE_PRX_DTX_P5
2

43 PERP0 VENDOR_DEFINED2 42
8 PCIE_PRX_DTX_N5 PERN0 VENDOR_DEFINED3
2

R4066 45 44
G

47 GND5 COEX3 46 EC_RX 29,44

10K_0402_5%
Q4008 8 CLK_PCIE_WLAN REFCLKP0 COEX2
@ @ 49 48 +3V_WLAN
8 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R4010 1 2 0_0402_5%
SUSCLK 10
1

3 1 WLAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST#

8 WLAN_CLKREQ# CLKREQ0# PERST0# PLT_RST# 10,35,37,44
S

R4012 1 @ 2 0_0402_5% PCIE_WAKE#_WLAN 55 54 BT_OFF#_R R4013 1 2 1K_0402_5%

8,44 PCIE_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# BT_OFF# 11,44
L2N7002KWT1G_SOT323-3 44 LAN_WAKE# R4034 1 2 0_0402_5% 57 56 R4014 1 2 0_0402_5%
GND7 W_DISABLE1# PCH_WLAN_OFF# 44
@
R4697 1 2 0_0402_5% @ @
R4011 1 2 0_0402_5% CNV_WT_D1N 59 58 SMB_DATA_S3_R 1 2
R4008 @ 0_0402_5%

100K_0402_5%
7 CNV_WT_D1N RSRVD/PETP1 I2C_DATA SMB_DATA_S3 7,17

1
CNV_WT_D1P 61 60 SMB_CLK_S3_R R4696 1 @ 2 0_0402_5%

100K_0402_5%
7 CNV_WT_D1P 63 RSRVD/PETN1 I2C_CLK 62 1 2 SMB_CLK_S3 7,17
R4017 0_0402_5%

R9472

R9473
CNV_WT_D0N GND8 ALERT# CLKIN_XTAL_LCP_R EC_TX 29,44
65 64 R4024 1 2 0_0402_5%
7 CNV_WT_D0N CNV_WT_D0P RSRVD/PERP1 RSRVD CLKIN_XTAL_LCP 7
67 66 CNVI@
7 CNV_WT_D0P RERVD/PERN1 UIM_SWP/PERST1#

1
If support AOAC, NC R4011; 69 68

2
CNV_WT_CLKN 71 GND9 UIM_POWER_SNK/CLKREQ1# 70 R4018
if not support AOAC, stuff R4011. 7 CNV_WT_CLKN CNV_WT_CLKP 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 100K_0402_5%
7 CNV_WT_CLKP RSRVD/REFCLKN1 3.3VAUX3 BT_OFF#
75 74
GND10 3.3VAUX4

2
77 76 PCH_WLAN_OFF#
GND15 GND14

+3V_WLAN
ARGOS_NASE0-S6701-TS40
ME@

8/16 Update Conn. P/N SP070013200 wei

0.01U_0201_10V6K

10U_0603_6.3V6M

1 1 1
.1U_0402_10V6-K
C4007

C4006

C4008

4 4

@2 @ 2 @2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 39 of 60
A B C D E
 A B C D E

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 40 of 60
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 41 of 60
5 4 3 2 1
 A B C D E F G H

SATA HDD Conn.

1 1

SATA HDD P/N Pin Define Same as CG411 JHDD1

10 11
SATA_PTX_DRX_P0 C4932 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_P0 9 10 GND1
8 SATA_PTX_DRX_P0 9
SATA_PTX_DRX_N0 C4933 1 2 0.01U_0201_6.3V7-K SATA_PTX_C_DRX_N0 8 12
8 SATA_PTX_DRX_N0 8 GND2
7
SATA_PRX_DTX_N0 C4934 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_N0 6 7
8 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C4935 1 2 0.01U_0201_6.3V7-K SATA_PRX_C_DTX_P0 5 6
8 SATA_PRX_DTX_P0 4 5
3 4
2 3
1 2
+5VS_HDD 1
HIGHS_FC5AF101-2931H
ME@

Change Symbol follow 140s whl 0711 bron

2 2

Need Short
J3
1 2 @
1 2
JUMP_43X79

F5
1 2

2A_32V_ERBRD2R00X
NEC@
U28 +5VS_HDD
5 1 +5VS_HDD
+5VS IN OUT
2 1 1 1 1 1 1 1
GND

47U_6.3V_M_X5R_0805_H1.25
C74 C76 C77 C78 C4956
HDD_EN 4 3 C75 1000P_0201_50V7-K C4930 1U_0402_10V6K 10U_0805_10V6K 10U_0805_10V6K 33P_0402_50V8J
44,54 HDD_EN EN OCB
@ @ EMC_NS@ 0.1U_0201_6.3V6-K @ @ RF@
2 2 2 2 2 2 2
SY6288C20AAC_SOT23-5
For RF request: keep 0402
High Active 2A EMC

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 HDD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 42 of 60
A B C D E F G H
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 43 of 60
5 4 3 2 1
 5 4 3 2 1

KSI[0..7]
45 KSI[0..7]
KSO[0..17] RE1 1 2
45 KSO[0..17] +3VL
1/10W_0_+-5%_0603

Same as SOC LPC power RE3 1 2 0_0603_5% +3VALW

@ +3VL_EC_R
+3VL_EC +3VL_EC +3VS +3VL
RE4 1 2 0_0402_5%
VFSPI Pin for IT8986HE Flash SPI Bus Power +3VALW All capacitors close to EC RE92 1 2 0_0402_5%

1000P_0201_25V7K
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
RE16 1 @ 2 0_0402_5% RE6 1 @ 2 0_0402_5%

EMC@
+3VL_EC +1.8VALW
2 2 2 2 2 2 2 1 2 2 2
+3VL_EC_R

CE25

CE26

CE27

CE28

CE29

CE30

CE31

CE38

CE33

CE32

CE34
RE17 1 2 0_0402_5% VFSPI
BEAD change to 0ohm
+1.8VALW
Close EC 1 1 1 1 1 @1 1 2 @1 @1 @1

CD@
CE24 1 2 0.1U_0201_6.3V6-K VCOREVCC
RE93 1 2 0_0402_5%
VFSPI

D
EC_AGND D
minimum trace width 12 mil

114
121
127

106
12

11

26
50
92

74
UE1

VSTBY(PLL)

VSTBY_FSPI
VCC

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5

AVCC
VCORE
+3VL_EC

SUSP# RE18 1 @ 2 100K_0402_5%

PLEASE DO NOT PLACE ANY PULL-UP RESISTOR ON GPG[7:2]
3 RE95 1 2 0_0402_5% SUSP# RE19 1 @ 2 100K_0402_5%
GPH7 PMIC_THERMTRIP# 57
4 24
+3VL_EC 11 KBRST# KBRST#/GPB6 1.8V IN 5VT 8/16mA PWM0/GPA0 PWR_LED# 45
5 25 SYSON RE96 1 @ 2 100K_0402_5%
6 LPC_SERIRQ SERIRQ/GPM6 5VT 8/16mA PWM1/GPA1 BATT_CHG_LED# 45
6 28
6 LPC_FRAME# LFRAME#/GPM5 5VT 8/16mA PWM2/GPA2 BATT_LOW_LED# 45
DE1 7 29 CE42 1 2 0.1U_0201_6.3V6-K
6 LPC_AD3 LAD3/GPM3 PWM3/GPA3
1 2 @ 8 PWM 30
6 LPC_AD2 LAD2/GPM2 PWM4/GPA4 EC_FAN_PWM
9 31 EMC_NS@
6 LPC_AD1 LAD1/GPM1 PWM5/GPA5 EC_FAN_PWM 38
LRB751V-40T1G_SOD323-2 10 32
6 LPC_AD0 CLK_PCI LAD0/GPM0 PWM6/SSCK/GPA6 BEEP# 34
RE71 1 2 0_0402_5% 13 LPC 34
6 CLK_PCI_EC LPCCLK/GPM4 PWM7/RIG1#/GPA7 LAN_WAKE#
RE8 1 2 100K_0402_5% WRST# 14 120 LAN_WAKE# 39 +3VL_EC
15 WRST# TMRI0/GPC4 124 RE102 1 2 0_0402_5% SUSP#
1U_0402_6.3V6K

11 EC_SMI# ECSMI#/GPD4 1.8V IN TMRI1/GPC6 SUSP# 10,39,46,54,57 LAN_WAKE#

1 16 RE5 1 @ 2 100K_0402_5%
29,39 EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 1.8V IN HDD_EN_R
17 66 RE105 1 2 100K_0402_5%
CE12

29,39 EC_TX PLT_RST# TXD/SOUT0/LPCPD#/GPE6 1.8V IN ADC0/GPI0 NTC_V1 38

EMC_NS@ 22 67 @
PLT_RST# 10,35,37,39 PLT_RST# LPCRST#/GPD2 1.8V IN ADC1/GPI1 BATT_TEMP NTC_V2 38
CE1 1 2 220P_0201_25V7-K 23 68 +3VS
2 11 EC_SCI# ECSCI#/GPD3 1.8V IN ADC2/GPI2 BATT_TEMP 52,53
126 ADC 69
57 PM_SLP_S0#_EC GA20/GPB5 1.8V IN ADC3/GPI3 PCH_PWR_EN 46 EC_LID_OUT#
EMC@ 70 RE88 1 @ 2 10K_0402_5%
CE37 1 2 10P_0201_25V8G CLK_PCI IT8986E/BX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72 Psys
OTP_RESET 51
ADP_I 53 change 1.8VALW_PG to PCH_1.24V_EN 03/10
EC_FAN_SPEED RE10 1 2 10K_0402_5%
ADC6/DSR1#/GPI6 Psys 53
KSI0 58
KSI0/STB#
LQFP-128L ADC7/CTS1#/GPI7
73 HDD_EN_R RE99 1 2 0_0402_5% HDD_EN
HDD_EN 42,54 EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
KSI1 59 78
KSI1/AFD# DAC2/TACH0B/GPJ2 PMIC_EN PCH_WLAN_OFF# 39
For factory EC flash KSI2 60 79 +1.8VALW
KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC PMIC_EN 57 PMIC_EN connect to PMIC 03/10
KSI3 61 DAC 80
EC_SMB_CK1 PAD 1 @ KSI4 62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 EC_BT_OFF# RE67 1 2 0_0402_5% ENBKL RE9 1 @ 2 100K_0402_5%
EC_SMB_DA1 IT2 KSI4 DAC5/RIG0#/GPJ5 BT_OFF# 11,39
PAD 1 @ KSI5 63
IT3 KSI5 EC_RTCRST#_ON +3VL_EC
PAD 1 @ KSI6 64 85
IT4 KSI6 PS2CLK0/TMB0/CEC/GPF0 RPE7
PAD 1 @ KSI7 65 86
IT5 KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK0 PBTN_OUT# 10 EC_SMB_DA0
PAD 1 @ KSO0 36 87 1 4
IT6 KSO0/PD0 1.8V IN SMCLK0/GPF2 EC_SMB_DA0 EC_SMB_CK0
KSO1 37 Int. K/B PS2 1.8V IN 88 2 3
KSO2 38 KSO1/PD1 SMDAT0/GPF3 89 RE101 1 2 0_0402_5% SYSON @
KSO3 39 KSO2/PD2 Matrix 1.8V IN PS2CLK2/GPF4 90
SYSON 10,46,55,57
2.2K_0404_4P2R_5%
KSI7 PAD 1 @ KSO4 40 KSO3/PD3 1.8V IN PS2DAT2/GPF5 SUSPWRDNACK 10 need move to 1.8V GPIO 06/26 +3VL
IT7 KSO4/PD4
KSI6 PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96
IT8 KSO5/PD5 GPH3/ID3 EC_LID_OUT# CMOS_ON# 28
WRST# PAD 1 @ KSO6 42 97 BKOFF# RE36 1 @ 2 100K_0402_5%
IT9 KSO6/PD6 GPH4/ID4 EC_LID_OUT# 45
KSO7 43 98 RE104 1 2 0_0402_5%
KSO7/PD7 GPH5/ID5 ALW_PGOOD 10,57 LID_SW#
KSO8 44 99 RE38 1 @ 2 100K_0402_5%
KSO8/ACK# GPH6/ID6 SYS_PWROK_EC 10
C KSO9 45 C
KSO10 46 KSO9/BUSY 101 BKOFF# RE40 1 @ 2 10K_0402_5%
KSO11 51 KSO10/PE FSCE#/GPG3 102 EC_SPI_CS0# 6
+3VL KSO12 52 KSO11/ERR# FMOSI/GPG4 103 EC_SPI_D0 6 LID_SW# CE35 1 2 0.1U_0201_6.3V6-K
KSO12/SLCT SPI Flash ROM FMISO/GPG5 EC_SPI_D1 6 For Mirror Code
KSO13 53 105
KSO14 54 KSO13 FSCK/GPG7 EC_SPI_CLK 6
RE35 1 @ 2 100K_0402_5% ON/OFF KSO15 55 KSO14
KSO16 56 KSO15 108 ACIN# +3VL_EC
+3VL_EC KSO17 57 KSO16/SMOSI/GPC3 AC_IN#/GPB0 109 LID_SW#
KSO17/SMISO/GPC5 UART LID_SW#/GPB1 LID_SW# 45
GPG2 RE44 2 1 100K_0402_5%
RPE8
1 4 EC_SMB_CK1 ON/OFF 110 82 RE103 1 2 0_0402_5% SYS_PWROK GPG2 RE46 1 @ 2 10K_0402_5%
EC_SMB_DA1 45 ON/OFF EC_ON PWRSW/GPB3 EGAD/GPE1 SYS_PWROK 10,57
2 3 RE91 1 @ 2 0_0402_5% 111 SM Bus 83 when mirror, GPG2 pull high
EC_SMB_CK1 XLP_OUT/GPB4 EGCS#/GPE2 EC_MUTE# 34
115 84 when no mirror, GPG2 pull low
52,53 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 1.8V IN 5VT 8/16mA EGCLK/GPE3 NUM_LED# 45
2.2K_0404_4P2R_5% BATT&Charger 116
+3VS 52,53 EC_SMB_DA1 EC_SMB_CK2 SMDAT1/GPC2 1.8V IN
117 GPIO 77
38 EC_SMB_CK2 EC_SMB_DA2 118 SMCLK2/PECI/GPF6 1.8V IN GPJ1 100 GPG2
EC_TS_ON 28 For Mirror Code +3VALW
RPE9 VGA&Thermal Sensor 38 EC_SMB_DA2 SMDAT2/PECIRQT#/GPF7 1.8V IN SSCE0#/GPG2
10,57 H_THERMTRIP# 94 122 PM_SLP_S0# 10
1 4 EC_SMB_CK2 95 CRX1/SIN1/SMCLK3/GPH1/ID1 1.8V IN 1.8V IN DTR1#/SBUSY/GPG1/ID7 113 BKOFF# PMIC_EN RE97 2 1 10K_0402_5%
EC_SMB_DA2 11 EC_WAKE_SCI# CTX1/SOUT1/SMDAT3/GPH2/ID2 1.8V IN CRX0/GPC0 BKOFF# 28
2 3 107 NOVO# 45
+3VL GPE4/BTN# 119
2.2K_0404_4P2R_5% 1.8V IN DSR0#/GPG6 123
GPG6 can not pull up (HW strapping) +3VL_EC
CTX0/TMA0/GPB2 EC_ME_PROTECT 15
TMSEN@ RE27 1 2 0_0402_5% 112 18
VSTBY0 1.8V IN RI1#/GPD0 PM_SLP_S3# 10
125 WAKE UP 21 PM_SLP_S4# 10
+5VALW SSCE1#/GPG0 1.8V IN RI2#/GPD1 76 EC_ON_GPIO RE65 2 1 100K_0402_5%
GPG0 can not pull up (HW strapping) TACH2/GPJ0 48 EC_ON_GPIO EC_RSMRST# 10
RE69 1 2 1K_0402_5% EC_ON
TACH1A/TMA1/GPD7 EC_FAN_SPEED EC_ON 38,54
47 EC_FAN_SPEED 38
RE15 1 2 100K_0402_5% USB_ON# USB_ON# 33 TACH0A/GPD6 19 EMC_NS@
29,31 USB_ON# GINT/CTS0#/GPD5 5VT 8/16mA 1.8V IN L80HLAT/BAO/GPE0 CAPS_LED# 45 BATT_TEMP
35 GPIO 20 CE16 1 2 100P_0201_25V8J
RTS1#/GPE5 1.8V IN L80LLAT/GPE7 ENBKL 28
93
6 LPC_CLKRUN#_EC CLKRUN#/GPH0/ID0 1.8V IN EMC_NS@
ACIN# CE17 1 2 100P_0201_25V8J
H_THERMTRIP# CE2 1 2 0.01U_0402_25V7K RE70 1 2 0_0402_5% 2 NEC@
8,39 PCIE_WAKE# CK32KE/GPJ7 EC_ON
128 Clock RE98 1 2 0_0402_5% MAINPWON @
11 AC_PRESENT CK32K/GPJ6 MAINPWON 51
@ ON/OFF CE18 1 2 1U_0402_6.3V6K

@
+3VALW NOVO# EC4 1 2 0.01U_0201_6.3V7-K

SYS_PWROK
AVSS
VSS1
VSS2
VSS3
VSS4
VSS5

RE94 2 1 10K_0402_5% EMC_NS@

PM_SLP_S3# CE40 1 2 1000P_0201_25V7K
Output Type Register (GPOTn[7:0])
The adjustable output types are only available on port GPA0-3, GPB0-B7, IT8986E-BX_LQFP128_14X14 EMC_NS@
1
27
49
91
104

75

PM_SLP_S4# CE39 1 2 1000P_0201_25V7K

GPD0-D7, GPE0-E7 , GPF0-F7 , GPH0-H6 and GPJ0-J5.
B For each bit: B
0: Push-pull output
1: Open-drain output
EC_AGND

Change RE72 to 0ohm jump +3VL RE86 1 @ 2 0_0402_5%

RTC_RST# 10
RE72 1 2 0_0402_5% H_PROCHOT# 10 RE87 1 2 0_0402_5%
53 VR_HOT# RTC_TEST# 10
RTCRST@
1
47P_0201_25V8-J
1

1
QE1 D 1 QE3 D
H_PROCHOT#_EC RE42 EC_RTCRST#_ON
2 2
CE14

G 100K_0402_5% G

10K_0402_5%
EMC_NS@

1
L2N7002KWT1G_SOT323-3 S 2 ACIN# RE74 1 2 0_0402_5% S L2N7002KWT1G_SOT323-3

RTCRST@
11 ACIN#
3

3
@

RE50
RTCRST@
1

D QE2
RE90 1 2 0_0402_5% 2
ACIN 53

2
Confirm with EC to change PROCHOT# setting(OD) G

S L2N7002KWT1G_SOT323-3
3

@
ACIN change to high active to cost QE2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 EC ITE8986E-BX

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 44 of 60
5 4 3 2 1
 5 4 3 2 1

ON/OFF switch K/B Connector

KSI[0..7]
KSI[0..7] 44 Follow KBL-R Modify LED damping resistor for 320 LED issue--07/26
KSO[0..17]
KSO[0..17] 44
+3VL +3VALW
JKB1
1
1

2
R923 1 2 0_0402_5% ON/OFFBTN# 2
R82 R83 EMC_NS@ PWR_LED# R285 1 2 200_0402_1% 3 2
100K_0402_5% 100K_0402_5% PWR_CAPS_LED C133 1 2 100P_0201_25V8J R279 1 15@ 2 200_0402_1% NUM_LED#_R 4 3
44 NUM_LED# 1 15@ 2 0_0402_5% KSO17_R 5 4
@ KSO17 R281
KSO16 R280 1 15@ 2 0_0402_5% KSO16_R 6 5

1
D15 KSI1 7 6
NOVO# 2 KSI7 8 7
44 NOVO# NOVO_BTN# 8
1 KSI6 9
NOVO_BTN# 34 9
ON/OFF R85 1 2 0_0402_5% 3 KSO9 10
KSI4 11 10
LBAT54CWT1G_SOT323-3 KSI5 12 11
EMC@ KSO0 13 12
D @ 13 D
CAPS_LED# C117 1 2 100P_0201_25V8J KSI2 14
KSI3 15 14
NUM_LED#_R C118 1 2 100P_0201_25V8J KSO5 16 15
KSO1 17 16
+3VALW +3VL EMC_15@ KSI0 18 17
KSO2 19 18
ON/OFFBTN# KSO4 20 19
20

2
KSO7 21
R111 R114 KSO8 22 21

AZ5123-01F.R7GR_DFN1006P2X2
100K_0402_5% 100K_0402_5% KSO6 23 22
23

1
@ D25 KSO3 24
KSO12 25 24

1
1

1
KSO13 26 25
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF 8/23 PWR LED function under check KSO14 27 26
ON/OFF 44 28 27
KSO11
CAPS_LED# NUM_LED#_R PWR_LED# KSO10 29 28
29

2
J5 1 2 @ KSO15 30
EMC@ CAPS_LED# R9427 1 2 200_0402_1% CAPS_LED#_R 31 30 34
44 CAPS_LED#

2
SHORT PADS PWR_CAPS_LED 32 31 GND2 33
32 GND1

1
HIGHS_FC8AR321-3160-1H
place bottom side D22 D23 D47 ME@

1
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2
EMC@ EMC_15@ EMC@ Need Short
@
+3VALW J27 1 2 Change Symbol follow 140s whl 0711 bron
1 2

2
2

2
JUMP_43X39
NEC@
For EMC 1 2

F7 0.5A_32V_ERBRD0R50X

TP/B Connector TP_PWR

C +3VS C

R141 1 2 0_0402_5% 1 LBG@ 2 0_0402_5% JTP1

+3VALW R9444 R4675 1 2 0_0402_5% EC_LID_OUT#_R 1
44 EC_LID_OUT# PCH_TP_INT# PCH_TP_INT#_R 1
R9425 1 @ 2 0_0402_5% R4676 1 2 0_0402_5% 2
11 PCH_TP_INT#
0.1u_0201_10V6K

F9 3 2
1 3
1 2 TP_I2C4_SDA_R 4
7 TP_I2C4_SDA_R TP_I2C4_SCL_R 5 4
7 TP_I2C4_SCL_R 6 5
0.5A_32V_ERBRD0R50X 1 TP_PWR
2 6
C114

EMC_NS@

EMC_NS@
NEC@ 2
C115 7
C116 8 GND1
100P_0201_25V8J GND2
2
100P_0201_25V8J
1 HIGHS_FC5AF061-2931H
ME@
TP_I2C4_SDA_R
TP_I2C4_SCL_R
TP_PWR
3

DT1
2

Change Symbol follow 140s whl 0711 bron

EMC_NS@ R9418
10K_0402_5%
1

PCH_TP_INT#
AZC199-02S.R7G_SOT23-3
1

For EMC

LED

B
LID Switch +3VL
B

U21
R1 1 2 0_0402_5% +VCC_LID 2
LED3 PWR_LED# VCC
2
PWR_LED# 1 2 R4672 1 2 1.5K_0402_5% C4945
44 PWR_LED# +5VALW LID_SW#
0.01U_0201_6.3V7-K 3
OUTPUT LID_SW# 44
1

L-C192WDT-LCFC_WHITE
D16 1 1 1
1

AZ5725-01F.R7GR_DFN1006P2X2 GND
C195
EMC_NS@ AH9247-W-7_SC59-3 100P_0201_25V8J
EMC@
2
2

Copy from G330 IGM bron

2

BATT_LOW_LED# LED1 1 2 R925 1 2 470_0402_5% BATT_LOW_LED# BATT_CHG_LED#

44 BATT_LOW_LED# +3VALW
AZ5123-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

L-C192JFCT-LCFC_SUPER_AMBER
1

D18 D19
1

BATT_CHG_LED# LED2 1 2 R924 1 2 1.5K_0402_5%

A 44 BATT_CHG_LED# +5VALW A
EMC_NS@
L-C192WDT-LCFC_WHITE
2

2
2

EMC_NS@
Check LED location and BOM structure when placement and Load BOM, PWR LED and BATT LED
have the same location on 14"/15" 02/26

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 KBD/PWR/IO/LED/TP Conn.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 45 of 60

5 4 3 2 1
 A B C D E

+5VLP +5VALW

1
R156 R157
100K_0402_5% 100K_0402_5%
@
1 1

2
SUSP
32,55 SUSP

1
Q6 D
2
10,39,44,54,57 SUSP# G

L2N7002KWT1G_SOT323-3 S

+5VALW +1.8V_3.3V_PU Power Rail for 1.8/3.3 Select by Soft Strap

+3VALW to +3VALW_SOC

1
2 2

R155
100K_0402_5%
@ +1.8VALW

2
PCH_PWR_EN#_R R9435 1 @ 2 100K_0402_5% PCH_PWR_EN# R4658 1 @ 2 0_0603_5%

+1.8VS

1
Q30 D
PCH_PWR_EN 2 R4659 1 @ 2 0_0603_5% +1.8V_3.3V_PU
44 PCH_PWR_EN
G
+3VALW
@ S 2N7002KW_SOT323-3

3
1
R9428 1 2

R162 +3VS 1/10W_0_+-5%_0603

100K_0402_5%
@ R9429 1 @ 2 0_0603_5%
2 Need Check which Power Rail use for +1.8V_3.3V_PU
(+3VALW is the better choice)

3 3

+3VALW +3VALW_SOC +3VALW_SOC

For DisCharge +1.2V
Need Short +3VLP +3VALW
J7 @ +VTT

1
1 2
1 2 +2.5V_DDR

100K_0402_5%

100K_0402_5%
R935

1
47_0603_5% @ @
JUMP_43X79
R159 @

R178

R179
Id=3.2A 47_0603_5%

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

2
@

2
LP2301ALT1G_SOT23-3 1 1

2
6
C4965

C4966
@ D Q156A R9449
3 1 2
S

Q29 SYSON# 100K_0402_5%

1
D Q8 @ G
0.01U_0201_10V6K

3
2 2
EMC_NS@

1 1 EMC_NS@ 2 SUSP D Q156B

1
C129 C130 G S 5
G

SYSON 10,44,55,57 @
2

1
0.1U_0201_6.3V6-K L2N7002KDW1T1G_SOT363-6 @ G
@ @ S L2N7002KWT1G_SOT323-3

3
2 2 S L2N7002KDW1T1G_SOT363-6

4
@
PCH_PWR_EN#_R R158 1 @ 2 0_0402_5%
Place near CLK_PCI_EC under +3VALW_SOC moat
1

4 1 4
C131
R164 0.1U_0201_6.3V6-K
100K_0402_5% @
@ 2
Security Classification LC Future Center Secret Data Title
2

Issued Date 2018/07/09 Deciphered Date 2019/07/08 DC V TO VS INTERFACE

reserve to cut off SOC 3VALW when clear CMOS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 46 of 60
A B C D E
 5 4 3 2 1

CPU Thermal Holex4

PCB Fedical Mark PAD
H4 H6 H7 H8
H1 HOLEA HOLEA HOLEA HOLEA
HOLEA FD1 FD2 FD3 FD4 FD5 FD6

1
1

1
D D

PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2 PAD_CT7P0B6P0D3P2

PAD_C10P0D8P0

H9 H10 H11 H12 H13 H14 H15 H16

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_C7P0D4P0 PAD_C7P0D4P0 PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P8 PAD_C7P0D2P4 PAD_CT7P0B10P0D4P0 PAD_CT7P0B10P0D4P0
C C

H17 H18 H19

HOLEA HOLEA HOLEA
1

PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X3P0D2P5X3P0N PAD_C2P5D2P5N

Shielding
SH1 ME@ SH2 ME@

1 1
1 1

B B
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

SH5 ME@ SH6 ME@ SH7 ME@ SH8 ME@

1 1 1 1
1 1 1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 47 of 60
5 4 3 2 1
 5 4 3 2 1

14&15 PCB MB PCB ODD/B

ZZZ2 NM_C111@ ZZZ3 NS_C121@

D D

PCB 1C9 NM-C111 REV0 M/B PCB 1A4 NS-C121 REV0 IO/B
DA600014W00 DA600014Q00

UC1 UC1 UC1

GLK CPU N5000@ N4100@ N4000@

N5000 N4100 N4000

MP Sample
S IC FH8068003067406 SR3RZ B0 1.1G 12 ! S IC FH8068003067408 SR3S0 B0 1.1G 12 ! S IC FH8068003067417 SR3S1 B0 1.1G 12 !
SA00008UP20 SA00008XK10 SA00008XM10

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 48 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/07/09 Deciphered Date 2019/07/08 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 49 of 60
5 4 3 2 1
 5 4 3 2 1

+5VLP/ 100mA
V20B+ SYSON SLP_S4# +1.05VS / 4.5A
CONVERTOR AOS
+5VALW/8A +1.24VA / 3A AO3402_SOT-23-3 +1.8VS / 1A
SUSP# SLP_S3#
Adaptor Load Switch
D
+1.8VA /3A D
EC_ON EN PGOOD ALW_PWRGD
ALW_PGOOD OUTPUT FOR SYSTEM
PAGE 55
Richtek VNN/4.5A
LV5083 +3VLP/ 100mA RICHTEK
PMIC
FOR SYSTEM LV5077
+2.5V / 1A +1.8VS / 1A
PAGE 54 +3VALW/6A PMIC
LDO +3VALW
PGOOD ALW_PWRGD FOR SYSTEM +VTT / 1A GMT
POWER G918T12U_SOT23-5 +2.5V / 1A
LDO
+1.2V / 8A
Controller FOR SYSTEM
PAGE 55
CPU Core/25A

TI
PGOOD SYS_PWROK
BQ24780SRUYR PAGE 57

Battery Charger
Switch Mode
PAGE 53

C C

SMBus

Battery
Li-ion
2S1P/30WH/35WH

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2013/08/05 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 50 of 60
5 4 3 2 1
 5 4 3 2 1

VIN
EMC@
HCB2012KF-121T50_0805
JDCIN1 PF101 PL101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 3 7A_24VDC_F1206HI7000V024TM
GND2 EMC_NS@

1000P_0201_50V7-K
4 HCB2012KF-121T50_0805
GND3 @

1000P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K
5 PL102
GND4

PC101

EMC@ PC102
6 PJ101 1 2
GND5

2
EMC@ PC103

EMC_NS@ PC104
D 7 2 1 D
GND6 2 1
JUMP_43X79

1
EMC_NS@
HIGHS_PJSS0026-8B01H
ME@ @

OTP

PD2
PD1
1SS355VMTE-17
+3VL 1SS355VMTE-17 PR1 PR2 1 2
44 MAINPWON PR53
100K_0402_1% 10K_0402_1% VIN
VCCRTC 1 2 2 1 1 2 1 2 @
1 2
@ @ @ V20B+
0_0402_5% PD3

2
C 1SS355VMTE-17 C
@ @

3
RTC_VCC E
PQ1
2 2
B PR3
PMBT3906 750K_0402_5%

1
C
1

1
@
JRTC1 +CPU_CORE +GPU_CORE
3 2 @
PR101 1 1
2 1 540_0402NEW_30% 540_0402NEW_30%
2

1
PD101 1K_0603_5% 3 C PRT2 PRT3
GND1
2

@ BAT54CW_SOT323-3 4 PQ2 2 2 1 2 1
GND2

2N7002KW_SOT323-3
PC105 PMBT3904 B
1U_0402_6.3V6K E 2 @ @
1

1
HIGHS_WS33020-S0351-HF D PQ3
@ 2
PC1
ME@ G OTP_RESET 44
1U_0603_25V7-K
1
@ S

3
2 1 2 1
RTC_VCC 35MIL
+3VL 20MIL @ PRT6 PRT5
540_0402NEW_30% 540_0402NEW_30%
VCCRTC 35MIL
@ @
CHARGER 1.2V

B B

+3VL +3VL

2
PR5 PR6
47K_0402_1% 47K_0402_1%

1
@ @

3
D

6
D 5 PQ4B
2 PQ4A G 2N7002KDWH_SOT363-6
G 2N7002KDWH_SOT363-6
S

4
S

1
@
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 PWR-DCIN / RTC charger

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 51 of 61
5 4 3 2 1
 5 4 3 2 1

SUYIN_125022HB008M202ZL VBAT EMC@

D JBATT1 D
HCB2012KF-121T50_0805
1 PL201
1
9 2
2
3 EC_SMCA
1 2 BATT+ 2S1P BAT +6V
PR202 1 2 100_0402_1%
EC_SMB_CK1 44,53
10 GND1 3 4 EC_SMDA 1 2 1 2
GND2 4 5 PR201 100_0402_1%
EC_SMB_DA1 44,53 ~ 8.4 V
5 6 PL202
6 7 HCB2012KF-121T50_0805
7

2
8
8 EMC@

1
ME@ PC201 PC202
1000P_0201_50V7-K 0.01U_0201_25V6-K

2
Reverse PD201 PD202 EMC@ EMC@
For EMI request
PD201

EMC_NS@
AZC199-02S.R7G_SOT23-3

1 PR209
1 2
+3VALW
100K_0402_1%

PR213
C BATT_TEMP_IN 1 2 C
10K_0402_5%
BATT_TEMP 44,53 A/D
1
1

PD202
AZ5215-01F_DFN1006P2E2
EMC_NS@
2
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-BATTERY CONN/OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 52 of 60
5 4 3 2 1
 5 4 3 2 1

PL301 EMC_NS@
HCB2012KF-121T50_0805
1 2

PL303 EMC_NS@
HCB2012KF-121T50_0805
1 2
VIN PQ311
N1
PQ312
N2
AON6414AL_DFN8-5 AON7408L_DFN8-5
PR301
1 1 PJ301 0.01_1206_1%
2 2 JUMP_43X118
5 3 3 5 1 2 1 4
1 2 V20B+
@ 2 3
D D

10U_0805_25V6K
470P_0201_50V7-K

0.022U_0402_25V7K
4

2
PC301

PC304
10U_0805_25V6K
1

2
PC303

1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K
0.1U_0201_25V6-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K
1

EMC_NS@

EMC_NS@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@
PC302

2
PR302

PC312

PC331

PC337

PC338

PC339

PC340

PC341

PC342

PC343

PC344

PC345

PC346
2

EMC@
4.7_0603_5%

EMC@

5
2

PQ314
PC305 AON6324_DFN8-5
1 2

0.1U_0201_25V6-K
0.1U_0201_25V6-K BQ24780_BATDRV 4

2
PC307

PC306
0.1U_0201_25V6-K

0.01U_0201_25V6-K
2

1
499K_0402_1%

3
2
1
2

PC308
PR303

1
VIN BATT+

2
BAT54CW_SOT323-3
PD302
2

3
V20B+

VIN

2200P_0201_25V7-K
1
1

1
4.02K_0603_1%

4.02K_0603_1%

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
2

2
ACN
ACP
PR310

PR311

EMC@
PC310

PC336

PC314

PC335

PC313
10_1206_5%
2
43K_0402_1%

1
1

5
PR314
BQ24780_VDD
2

1
PR313

C C
1U_0603_25V6K 2.2U_10V_K_X5R_0603

ACN
ACP
PR315 1 2 7.15K_0402_1% PC315 PC316
@ @

1
2 1 780_VCC 28 24 1 2 PQ316
2

VCC REGN 4
1 2 ACDET 6 AON7408L_DFN8-5
PC309 0.01U_0402_25V7K ACDET PR316 PC318
25 BST_CHG1 2 2 1
BTST PR317

3
2
1
BQ24780SRUYR_QFN24_4X4 2.2_0603_5% 0.047U_0603_16V7K 0.01_1206_1%
3 26 DH_CHG PL302
0.5C charge
CMSRC HIDRV PR344 1 2 1 4 BATT+
PR339 2 @ 1 20K_0402_1% 4 1 2 4.7UH_PCMB063T-4R7MS_5.5A_20%
ACDRV 2 3

1
PR324 2 @ 1 100K_0402_1% 27 LX_CHG 2.2_0603_5%
BQ24780_VDD PHASE PR321

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
2

2
PR325 1 2 0_0402_5% ACIN_R 5 2.2_0805_5%

PC332

PC333
44 ACIN ACOK
EMC_NS@

PC320

PC319
PR320 1 2 0_0402_5% EC_SMB_DA1_R 11 PR343 PQ317

1
44,52 EC_SMB_DA1 SDA PU301 23 DL_CHG 1 2 4
LODRV AON7408L_DFN8-5

1
PR322 1 2 0_0402_5% EC_SMB_CK1_R 12 22 2.2_0603_5%
44,52 EC_SMB_CK1 SCL GND PC321
@ @
1000P_0402_50V7K

3
2
1

2
PR323 1 2 0_0402_5% ADP_I_R 7 29 EMC_NS@

0.1U_0201_25V6-K

0.1U_0201_25V6-K
44 ADP_I IADP PAD

2
IDCHG 8 18 BQ24780_BATDRV

PC322

PC323
IDCHG BATDRV
@ @
1 2 0_0402_5% 9

1
44 Psys PMON 17 PR338 2 1 10_0603_5%
PR341 BATSRC
VR_HOT# 44
100P_0201_25V8J

100P_0201_25V8J
2

20 SRP_R PR328 2 1 10_0603_5% SRP

0.1U_0201_25V6-K
PR340 1 2 10 SRP
2

PROCHOT#

2
PC324

PC325

0_0402_5%

PC327
20K_0402_1%

100P_0201_25V8J
1

13
PR342

CMPIN
@

1
BATPRES#
TB_STAT#

14
PC334
1

CMPOUT 19 SRN_R PR329 2 1 10_0603_5% SRN

1

B
ILIM 21 SRN B
ILIM
2

@
16

15

PR330
0_0402_5%
1

PR331 PR332
1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
14.7K_0402_1%
316K_0402_1%
0.1U_0201_25V6-K
1

100K_0402_1%
2

PC328

PR333

need config special

appliction
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CHARGER

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 53 of 60
5 4 3 2 1
 5 4 3 2 1

V20B+
+5VLP
@
PJ3501
2A 2 1 +3VALW_VIN
2 1 PU3501 Vout=3.3V±5%

25
10U_0805_25V6K

10U_0805_25V6K

0.1U_0201_25V6-K
1

1
JUMP_43X79 LV5083AGQUF_UQFN36_5X4
Vset=3.37V±1.5%

10U_0805_25V6K

10U_0805_25V6K
1

1
EMC@
PR3511 PC3541

PC3569

PC3570

PC3535
+3VALW

VDDSW
3 +3VALW_BS 1 2 1 2

PC3534

PC3536
OCP=12A

2
11 BOOT1 10_0603_5%

2
VIN1 0.1U_0603_25V7-M PL3501 PJ3502
D
1 +3VALW_LX 1 2 +3VALW_P 2 1
8A OVP=(1.15~1.25)*Vout D
LX1_1 2 1.5UH_PCMB063T-1R5MS_10A_20% 2 1
PR3515 1
@
2 0_0402_5% +3VALW_EN 10 LX1_2 35 JUMP_43X79
UVP=(0.55~0.65)*Vout
@ EN1 LX1_3 1 1 1 1
38,44 EC_ON

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
@

PC3539

PC3542

PC3543

PC3544
Fsw=500Khz

1
@ 6 +3VALW_P
PC3537 +3VALW_PG 9 VOUT1
0.1U_0201_25V6-K PGOOD1 +3VALW 2 2 2 2

2
PC3538
4
V20B+ 1 2 7 VBYP3
VCC1 +3VLP
@ 1U_0402_25V6-K PC3545
PJ3503 5
100mA 1 2
3.5A 2 1 +5VALW_VIN LDO3
2 1 4.7U_0603_6.3V6K +3VL

0.1U_0201_25V6-K
JUMP_43X79 +3VLP PJ3505
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PR3512
1

1
EMC@
PC3554 2 1
PC3571

PC3572

PC3546

PC3547

PC3548
14 22 +5VALW_BS 1 2 1 2 2 1
@
VIN2 BOOT2 +5VALW
+3VALW
2

2
23 10_0603_5% 0.1U_0603_25V7-M PL3502 JUMP_43X39 PJ3504
LX2_1 24 +5VALW_LX 1 2 +5VALW_P 2 1
8A Vout=5V±3%
LX2_2 36 1.5UH_PCMB063T-1R5MS_10A_20% 2 1
PR3516 1 2 0_0402_5% +3/5VALW_EN 15 LX2_3 JUMP_43X79
Vset=5.1V±1.5%
@ @ EN2 1 1 1 1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
19 +5VALW_P @

PC3555

PC3551

PC3552

PC3553
VOUT2 OCP=12A
1

+5VALW OVP=(1.15~1.25)*Vout
2

PC3549 16 2 2 2 2
100K_0402_5%

100K_0402_5%

PGOOD2
2

0.1U_0201_25V6-K
PR3513

UVP=(0.55~0.65)*Vout
2

@
PR3514

21
PC3550 VBYP5 Fsw=500Khz
1

@
1 2 18 +5VLP
1

VCC2

+3VALW_LX

+5VALW_LX
+5VALW_PG 10
1U_0402_6.3V6-K 20
100mA 1 2
+3VALW_PG

LDO5
+3VALW 4.7U_0603_6.3V6K
PC3559

22UC_6.3VC_MC_X5RC_0603
C 33 C
2

VINSW1

1
1 @ +3VS
PC3567 22UC_6.3VC_MC_X5RC_0603 PJ3506 PR3508 PR3509
@ 1U_0402_25V6-K PC3566 29 +3VS_SW 1 2 2.2_0805_5% 2.2_0805_5%
1

VOUTSW1 1 2
@ 1 EMC_NS@ EMC_NS@

1
2 JUMP_43X79

PC3564

+3VALW_SN 2

1+5VALW_SN 2
+3VALW_PG 10 31 3VS_SS @
SS1 PC5978

2
2
PR3517 1 2 0_0402_5% +3VS_EN 30 2 0.1U_0201_25V6-K
ENSW1 @ Need Short
10,39,44,46,57 SUSP# PC3562
+5VALW 2200p_0402_25V7-K @ +5VS

1
2

PJ3507
PC3530 34 28 +5VS_SW 1 2
VINSW2 VOUTSW2 1 2

1
@ 1U_0402_25V6-K 1 PC3533
1U_0402_25V6-K
1

PC3565 JUMP_43X79 PC3532 1000P_0402_50V7K

PC3568

2
1
22UC_6.3VC_MC_X5RC_0603
22UC_6.3VC_MC_X5RC_0603 26 5VS_SS @ 1000P_0402_50V7K EMC_NS@

PC3563

2
SS2 PC5979
@ EMC_NS@
1

2
PGND_2

PGND_1

AGND_2

AGND_3

AGND_1
2 @ 27 0.1U_0201_25V6-K

2
ENSW2 PC3561 2
2200p_0402_25V7-K

1
1 2 0_0402_5% +5VS_EN
13

12

17

32

8
2

PR3518
@ PC3531 @
1U_0402_25V6-K
1

PR6661
2 1 0_0402_5%
42,44 HDD_EN

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 54 of 60
5 4 3 2 1
 5 4 3 2 1

MOS. AO3402 VGS MAX is 12V +1.8VS

+1.8VALW TO +1.8VGS
+1.8VALW PQ3101 Can change to low cost and small
AO3402_SOT-23-3
size MOS. AO3402
+1.8VGS /0.5A Rdson<65mohm
1 3
D S

PC3105

PC3106

PC3102

PC3104

PC3103
0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1
G
1 1 1 1 1
PR3103

2
+5VALW @ @ 470_0603_5%
D
@ D
1 2 PR3104 2 2 2 2 2
@

2
V20B+ 20K_0402_5%

1
1 2 PR3102 SUSP#_N_R D PQ3102
120K_0402_5% 2 SUSP
G

2N7002KW_SOT323-3

1
@ @

1
PQ3103 D PR3101 1 S 2N7002KW_SOT323-3

3
SUSP 2 150K_0402_5% PC3101
32,46 SUSP G @ 0.1U_0201_25V6-K

2
S 2

3
C C

RT5077A Test high temperature must add this solution

SDV Must Add in bom

+3VALW
+2.5V_DDR
PJ3102 PU3101 PJ3101
2 1 3 4 2 1
200mA
2 1 VIN VOUT 2 1
2
JUMP_43X39 GND 5 1
PR3105 2 JUMP_43X39
1 SET 42.2K_0402_1%
1 SHDN
@ @ @
PC3107 PR31081 2 20K_0402_1%
1U_0402_6.3V6K G918T12U_SOT23-5
2 @
@ @

PR3109
10,44,46,57 SYSON 2 1

0_0402_5%

B B
@

1
PC6733
1U_0402_6.3V6K
2
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_1.8VS/2.5V_DDR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 55 of 60
5 4 3 2 1
 A B C D

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 RT5077A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
A2 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 56 of 60
A B C D
 5 4 3 2 1

+3VALW PR6657
10K_0402_1% V20B+
1 2 RT5077A_RSMRST#
@
PR6660 2 1 RT5077A_THERMTRIP#
0_0402_5%
+5VALW
44 PMIC_THERMTRIP#
PJ6619/PJ6620 opition for RT5077A temperature high risk

1
PR6658

2
1 2 RT5077A_POWER0K
@
PR6634
100K_0402_5%
PR6612
2.2_0603_5%
+1.8VALW

2
100K_0402_5%
PR6659 PR6623 2 1 0_0402_5% PR6611
44 PMIC_EN

2
10K_0402_1% PJ6619 @
10_0603_5% 200mA

1
1 2 PR6627 2 1 0_0402_5% RT5077A_VSYS RT5077A_VNN_CT 2 1
10 PMIC_I2C_SDA 2 1

0.1U_0402_25V6
1

1
PR6625 2 1 0_0402_5% RT5077A_VCC

PC6607
100K_0402_5%
0.1U_0402_25V6
PR6640 10 PMIC_I2C_SCL JUMP_43X39

PC6602

PR6632
1
SUSP# 2 1 RT5077A_SLP_S0# PR6626 2 1 0_0402_5%
10,44,46,55 SYSON +1.8VS

2
PC6618

2
@ 100K_0402_5% 44 PM_SLP_S0#_EC @ PR6622 2 1 0_0402_5% +3VALW

2
4.7U_0402_6.3V6M 2 PJ6620
PU6601 @
PR6621 2 1 0_0402_5% 2 1

11

52
10,39,44,46,54 SUSP# 2 1

7
RT5077AGQW_WQFN52_6X6 PJ6621 @
1
PR6624 2 1 0_0402_5% 2 1

VIN_CT
VCC

VSYS
10,44 ALW_PGOOD RT5077A_EN
30 2 1 JUMP_43X39
PC6621
PR6619 2 1 0_0402_5% PMIC_EN
D RT5077A_EN 10,44 H_THERMTRIP#
20 2
10U_0603_6.3V6M JUMP_43X39 200mA +2.5V_DDR D
RT5077A_SLP_S4# PR6616 2 1 0_0402_5% RT5077A_SDA 13 GATE_VIN PJ6605
10,44 SYS_PWROK I2C_SDA @ 200mA
RT5077A_SLP_S0# RT5077A_SCL 12 19 LDO1_VOUT 2 1
RT5077A_SLP_S3#
11 PMIC_IRQ#
PR6617 2 1 0_0402_5%
RT5077A_SLP_S4# 16
I2C_SCL GATE_VOUT
1
2 1
Location confirm change to063 for costdown
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

@ @ @ @ RT5077A_SLP_S0# 14 SLP_S4# PC6708 JUMP_43X39

RT5077A_SLP_S3# 15 SLP_S0#
SLP_S3# 10U_0603_6.3V6M
1

RT5077A_RSMRST# 36 47 RT5077A_VIN1 2
PC6724

PC6723

PC6722

PC6721

Roc=(IOC *Ron)*12/Ioc_set RSMRST# VIN1_1

IOC2(VCCGI)=38A(23.7K) RT5077A_THERMTRIP# 17 48
PL6604
+VNN
2

RT5077A_POWER0K 27 THERMTRIP# VIN1_2

IOC6(VDDQ)=12A(57.6K) PCH_PWROK 45 RT5077A_LX1 RT5077A_LX1 1 2
5A
RT5077A_IRQ# 39 LX1_1 46

2.2_0805_5%
IRQ# LX1_2

EMC_NS@
PR6636 23.7K_0402_1%
RT5077A_OCSET2 VNN_VCC_SENSE 0.47UH_PCMB063T-R47MS_18A_20%
RT5077A_VCC 1 2 1

PR6601
PR6635 57.6K_0402_1% 9 VOUT1
1 2 RT5077A_OCSET6 10 OCSET2 Vout=1.0~1.1V
DDRSEL PR6633 100K_0402_5% OCSET6
OCP=10A

2
High,VDDQ=1.2V LDO Out 1.8v 1 2 23
DDR_SEL RT5077A_VIN3 +1.05VS OVP=(1.3~1.4)*Vout

22UC_6.3VC_MC_X5RC_0603
40

1VNN_SN
Low, VDDQ=1.1V LDO Out 1.8v VIN3_1
UVP=(0.55~0.65)*Vout

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
@ 41
VIN3_2 PL6603
2

Floating,VDDQ=1.2V LDO Out 2.5v PJ6608

4.5A Fsw=1.2MHz

1000P_0402_50V7K
RT5077A_LX31 1v05S_OUT

EMC_NS@
PR6637 37 2 1 1 2 1
RT5077A_LX2 43 LX3_1 38 0.47UH_PCMB063T-R47MS_18A_20% 2 1

PC6644

PC6704

PC6696
100K_0402_5% PHASE2 LX3_2 1 1 1 1 1 1
@ JUMP_43X79

PC6653

PC6652

PC6637

PC6645

PC6688

PC6705
VCORE_FB RT5077A_EN2 44 24 RT5077A_VOUT3 1 2 @ +VNN
+CPU_CORE
1

2
DRV_EN2 VOUT3 PR6647 100_0402_5% 2 2
RT5077A_PWM2 42 2 2 2 2 2 2
PWM2 PR6648 2 1 +1.05VS
10K_0402_1% VCORE_VSEN 35 0_0402_5%
+1.8VALW VID1=1.3V
PC6691 VOUT2
1

1 2 1 2 1 PR6645 2
PC6690
1 2 34 25 +5VALW Vout=1.782~1.818V Vboot=1.05V
PR6644
FB2 VIN4 @ OCP=6A
1 1 1 1 1 1 1
DCR=7.4mohm

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
100_0402_5% @ PJ6607

PC6654

PC6686

PC6666

PC6662

PC6685

PC6635

PC6631
RT5077A_LX4 1V8SALW_OUT 3A
3300P_0402_50V7K PR6646
1.05K_0402_1% PC6726
560P_50V_K_X7R_0402 33
COMP2 LX4_1
28
29
1 2
1UH_PH041H-1R0MS_3.8A_20%
2
2 1
1
OVP=(1.15~1.25)*Vout TDC/Iccmax=4/5A
1 1 1
OCP=8A
2

LX4_2 2 2 2 2 2 2 2
UVP=(0.55~0.65)*Vout

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR6618 1 2 0_0402_5% 1 2 1 2 PR6649 100_0402_5%
PL6605 JUMP_43X79

PC6639

PC6650

PC6706
13 CPU_VCC_SENSE 1
8 26 RT5077A_VOUT4 1 2
PR6628 @ OVP=Vout+350mV

PC6737
10P_0402_50V8-F VSSSENSE2 VOUT4 Fsw=1.2MHz
4.7K_0402_1% VCORE_ISENP 32 2 2 2 @ UVP=Vout-300mV
0.1U_0402_25V6

ISENSEP2
1

PR6650 2 1 +1.8VALW 2
Loadline=6mΩ
1000P_0402_50V7K

VCORE_ISENN 31 0_0402_5%
PC6601

ISENSEN2
2

Fsw=600KHz
PC6695

+1.2VALW
2

+1.2V 2 PR6655 1
@ 22 +5VALW
1

0_0402_5% VIN5
VCORE_VSEN
EMC_NS@
VDDQ_OUT
1 2 RT5077A_VO6 5 21 RT5077A_LX5 1 2 1V2ALW_OUT 2
PJ6604
2.5A
1
+5VALW
PR6656 VOUT6 LX5 1UH_PH041H-1R0MS_3.8A_20% 2 1
RT5077A_LX6 50 18 RT5077A_VOUT5
1 1 1 1 1 1.5A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
0_0402_5% PL6606 PJ6602

PC6663

PC6707

PC6661

PC6731

PC6730
PHASE6 VOUT5 JUMP_43X39 1 1 1 1 1 1
VCORE_RGNG RT5077A_VIN1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR6620 1 2 0_0402_5% 2 1

PC6667

PC6682

PC6668

PC6649

PC6628

PC6672
13 CPU_VSS_SENSE 2 1
1

C RT5077A_EN6 51 PR6652 100_0402_5% @ C

DRV_EN6 2 2 2 2 2 1

22UC_6.3VC_MC_X5RC_0603
PR6643 1 2 JUMP_43X79

PC6622
0.1U_0402_25V6

0.1U_0402_25V7-K
1
RT5077A_PWM6 2 2 2 2 2 2

EMC_NS@
49 @

PC6610
100_0402_5% PWM6
1

PC6732 2 1 +1.2VALW 2
PC6608

2
10U_0603_6.3V6M
2

1 2 VDDQ_OUT 4 PR6651
VTT_IN
1A @ @
3 0_0402_5% @ @ @ @ @ @
+VTT VTT

AGND

EPAD
EMC_NS@ +5VALW
10U_0603_6.3V6M

1 2
VTT_SNS
PC6619

PJ6610
1.5A

0.1U_0402_25V7-K
6

53
RT5077A_VIN3 2 1
2 2 1
1 1 @

22UC_6.3VC_MC_X5RC_0603
JUMP_43X39

PC6669
@

PC6613
2 2

PC6604

+5VALW PR6610 VCC_VIN 2

PJ6606
1
3A +5VALW
2 1 1 2 2 1 V20B+ 1.5A

22UC_6.3VC_MC_X5RC_0603
JUMP_43X79

0.1U_0402_25V7-K

0.1U_0402_25V7-K
EMC_NS@
0.1U_0402_25V6 @ @ 1
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
2.2_0603_5%
5

1
@
PC6612
PR6615 1 1

33U_D2_25VM_R40M
+

PC6736

PC6632
2 1
PC6734

PC6735

PC6625

PC6626

PC6614
2

2
0_0603_5% 2 2 2
1U_0402_10V6-K

2.2_0603_5%
1

1 2 VCORE_HG 4
PC6617

PU6602 4 PR6607 @
8 BOOT AON6380_DFN8-5 @ +CPU_CORE +5VALW
2

VCC 3 PQ6602 PL6601

RT5077A_PWM2 5 UGATE 0.22UH_PCMB063T-R22MS_23A_20%
21A 1.5A
3
2
1

PWM 2 RT5077A_LX2 1 2

place beside the RT5077

0.1U_0402_25V7-K
RT5077A_EN2 1 PHASE
EN
5

7 1 1 @
6 LGATE PR6602

PC6665
GND1 9

22UC_6.3VC_MC_X5RC_0603
1/8W_1_5%_0805

PC6611
GND2 1
PJ6617 @
0_0603_5% 1 2 VCORE_ISENN + PC6697 2 2
1CORE_SN 2

RT9610CGQW_WDFN8_2X2 1 2 VCORE_LG 4 330U_D2_2V_Y

PR6605 JUMPER
AON6324_DFN8-5 PJ6615 2
@
PQ6601 1 2 VCORE_SW_R
B B
3
2
1

JUMPER
PC6694 +VNN
3300P_0402_50V7K +CPU_CORE
2

1.47K_0603_0.5% 1.47K_0603_0.5%
PR6653 PR6654
2 1 2 1 VCORE_SW_R

1
PR6641
PC6615 100_0402_5%

22UC_6.3VC_MC_X5RC_0603
1 2 1
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
0.1U_0402_25V6

PC6660
1 1 1 1 1 1 1 1 1 1 1 1

2
PC6638

PC6633

PC6630

PC6647

PC6648

PC6655

PC6643

PC6651

PC6646

PC6641

PC6659

PC6656

PR6639 1 2 750_0402_1%
2
2 2 2 2 2 2 2 2 2 2 2 2 VNN_VCC_SENSE 13
PR6629 PH6601
VCORE_ISENP 2 1VCORE_ISENP_R 2 1
VID1=1.3V

0.022U_0402_25V7K
536_0402_1% 4.7K_0402_1%_TSM0A472F34D1RZ

1
Vboot=0V

PC6711
DCR=2.5mohm

2
@ @ @ @ @ @ @ @
@
TDC/Iccmax=18/21A
OCP=33.6A
VCORE_ISENN OVP=Vout+350mV
VNN_VSS_SENSE 13
Loadline=6mΩ
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

UVP=Vout-300mV
0.1U_0402_25V6

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

1
Fsw=600KHz
PC6701

PC6703

PC6702

PC6700

PC6699

PC6634

PC6636

PC6642

PC6687

PC6640

PC6727

PC6729

PC6629

PC6728

PC6657

0.022U_0402_25V7K

0.022U_0402_25V7K
PR6642
PC6605

1
100_0402_5%
2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

PC6710

PC6709
2

2
PC6606
Vout=1.28~1.42V
OCP=15A
@
PR6613
PJ6601 @ OVP=(1.15~1.25)*Vout
2 1 1 2
@ @ @ VDDQ_IN
@
@ 2A @
2 1
@ @
UVP=(0.55~0.65)*Vout
2 1 V20B+ Fsw=1MHz
PC6609 EMC@

0.1U_0402_25V6
2.2_0603_5%
5

JUMP_43X39
10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V7-K

@
1

1
PC6624

PC6623
AON7408L_DFN8-5
PQ6603

UG_VDDQ 4 @
A 0_0603_5% PJ6612 A
1 2 2 1 +1.2V
PU6603 4 PR6608 2 1
8 BOOT
+5VALW JUMP_43X79
3
2
1

VCC 3
UGATE PL6602 @ 8A
RT5077A_PWM6 5 PJ6611
PWM 2 RT5077A_LX6 1 2 VDDQ_OUT 2 1
RT5077A_EN6 1 PHASE 0.47UH_PCMB063T-R47MS_18A_20% 2 1
EN 7
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

JUMP_43X79
0.1U_0402_25V6

PR6614 LGATE
2

EMC_NS@

6 1 1 1 1 1 1 1 1
GND1
1

2 1 9
PC6675

PC6681

PC6683

PC6679

PC6684

PC6670

PC6678

PC6689

PC6603

GND2
5

PR6603
4.7_0805_5%
1U_0402_10V6-K

2.2_0603_5% RT9610CGQW_WDFN8_2X2
1

2 2 2 2 2 2 2 2
AON7380_DFN8-5

0_0603_5% EMC_NS@
PC6616

1
PQ6604

1 2
PR6604
2

LG_VDDQ 4 PC6692
Security Classification LC Future Center Secret Data Title
680P_0402_50V7K
EMC_NS@ Issued Date 2015/08/20 Deciphered Date 2016/08/20 RT5077A
2

@
@
3
2
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 57 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 RT5077A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 58 of 60
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2016/08/16 Deciphered Date 2017/08/15 PWR-+1.05VGS/+1.35V_VRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 59 of 60
5 4 3 2 1
 5 4 3 2 1

20161216:SDV to SIT
1.p56-p57 add R=100ohm,C=680pF in FB pin;
2.pr3324 change to 55.4kohm,pr3323 change to 24.3k;
D 3.VNN pr3430 from 0ohm change to 20ohm, pr3428 from 210 change to 249ohm,pr3410 from 34k to 35.7k; D
4.Vcore pr3330 from 0ohm change to 20ohm, pr3328 change from 287ohm to 402ohm,pr3327 change from 28.7k to 23.2k, pr3304 change from 24k to 30k;
5. GPU change 14 items to support AMD request.

20161219:SDV to SIT
1.DEL 8pcs MLCC for VNN test result.(PC3422,PC3426,PC3434,PC3436,PC3437,PC3432,PC3435,PC3433)

20161226:SDV to SIT
1. PMIC change 1.24V Vin from 3VALW to1.8VALW;
2.chenge PR2431 from PX@ to @, PR2433 from @ to PX@,
3.change PR734 to @.

20170104:SDV to SIT
1. PMIC change LV5075B TO LV5075A

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/08 Deciphered Date 2014/01/21 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FS440/FS541
Date: Monday, November 05, 2018 Sheet 60 of 60
5 4 3 2 1