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Verilog Implementation of Turbo Encoder and Decoder Using Log Map Based
Iterative Decoding

Article · November 2015

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VERILOG IMPLEMENTATION OF TURBO ENCODER AND DECODER USING LOG MAP BASED
ITERATIVE DECODING
A. Hinduja1, Sudheer Kumar Terlapu2

1PGScholar (M. Tech Student, 2nd Year), Department of Electronics and Communication Engineering-VLSID.
2AssociateProfessor, Department of Electronics & Communication Engineering, Sri Vishnu Engineering College for Women,
Bhimavaram, India.

ABSTRACT : Field Programmable Gate Arrays (FPGAs) provide the flexibility in operation and function by a simple change in the
configuration bit stream. With increasing demand for different data rates and services for communication systems, reconfigurability
is of most importance. Another cause for the limitation in BER performance is a poor interleaver design. Due to highly correlated
sequences, the BER decreases to a certain level from where there is no further improvement in the decoding process. Low complexity
turbo-like codes based on simple two-state trellis or simple graph structure results in decoder with low complexity. Out of this
Convolution encoder and turbo codes are widely used due to the excellent error control performance. The most popular
communications decoding algorithm, the iterative decoding requires an exponential increase in hardware complexity to achieve
greater decode accuracy. This work focuses on the realization of turbo encoder and decoder using Log-Map based Iterative decoding
technique. In this work an 8 bit turbo system was performance of turbo decoder found in terms of decoder iterations.

KEYWORDS: Convolution Codes, Turbo Codes, VLSI Code Design.

HOW TO CITE THIS ARTICLE: A. Hinduja, Sudheer Kumar Terlapu.“ Verilog Implementation of Turbo Encoder and Decoder Using
Log Map Based Iterative Decoding”. Journal of Technological Advances and Scientific Research; Volume 1, Issue 04,
October-December 2015; Page: 322-327, DOI: 10.14260/jtasr/2015/44.

INTRODUCTION: Digital communications has better error The main advantage of FEC is to avoid the retransmission
correction capability when compared to analog at the cost of higher bandwidth requirements on average and
communications.[1] Data transmission in discrete messages therefore is employed in the situations where retransmission
provides for greater signal processing capability.[2] The ability is relatively costly or impossible.[10] The original information
to process a communications signal means that the errors may or may not appear in the encoded output. Turbo system is
caused due to noise or other impairments in the course of an example of Forward error correction.[9]
transmission can be detected and corrected.[4] In addition, [9]The original information may or may not appear in the

digital systems offer faster data processing.[3]They are not only encoded output. Turbo system is an example of Forward error
more cost-effective but are less subject to distortion and correction.[10]
interference which makes them more reliable than the analog [11] Shows design and implementation aspects of parallel

systems. Turbo codes are finding use in 3G/4G mobile turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate
applications where designers seek to achieve reliable using multiple soft-input soft-output decoders that operate in
information transfer over bandwidth or latency-constrained parallel. [12]shows the design of new turbo codes that can
communication links in the presence of data-corrupting achieve near-Shannon-limit performance. The design criterion
noise.[5] for random interleavers is based on maximizing thefree
Turbo encoders and decoders are key elements in distance of the turbo code, i.e., the minimum output weight of
today’s communication systems to achieve possible data codewords due to weight-2 input sequences. An upper bound
reception with the fewest possible errors the best.[7] The above on the free distance of a turbo code has been derived. [13]
Figure shows the Turbo System where Encoder generates a shows development of an application specific design
multiplexed code of two coders fed with direct and interleaved methodology for low power solutions.[14]
data.[8] Forward error correction (FEC) is a technique for error The methodology starts from high level models which
control during data transmission, whereby redundant can be used for software solution and proceeds towards high
information is added to the original data, which allows the performance hardware solutions.[15] The effect on
receiver to detect and correct errors without the need to performance due to variation in parameters like frame length,
resend the data.[6] number of iterations, type of encoding scheme and type of the
interleaver in the presence of additive white Gaussian noise
has been studied with the floating point C model.[16] In order
Financial or Other, Competing Interest: None. to obtain the effect of quantization and word length variation,
Submission 19-11-2015, Peer Review 20-11-2015
a fixed point model of the application has also been
Acceptance 24-11-2015, Published 28-11-2015.
Corresponding Author: developed.[17] The MAP turbo decoder is too complex to be
A. Hinduja, implemented due to the large number of multiplications and
Bhimavaram, Balusumudi, the need of non-linear functions.
Pataramalayam Street, For that reason, two simplified versions of it were
3rd Floor-204.
E-mail: [email protected]
proposed in the past, namely Log-MAP and Max-Log-MAP.[18]
DOI:10.14260/jtasr/2015/44. The latter algorithm is sub-optimum in terms of bit error
rate (BER) performance but easier to be implemented, as it
requires only additions and the max operator. Another sub-

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optimum algorithm that is suitable for turbo decoding is the Turbo encoders and decoders are key elements in
soft output Veterbi algorithm (SOVA). It is a modified Veterbi today’s communication systems to achieve possible data
algorithm (VA) that produces, in addition to the most likely reception with the fewest possible errors the best Turbo
path sequence, a reliability value of each estimated bit.[19] System where Encoder generates a multiplexed code of two
So we introduce turbo encoder and decoder with SISO coders fed with direct and interleaved data.
coding technique. It proposed reconfigurable turbo decoder.
In turbo decoder, there is less delay and it occupies less area
when compared to conventional veterbi Decoder. In most of
real time applications like bit error rate and recently in digital
wireless communications, the turbo codes are used for error
correction. We also implemented turbo system in MATLAB to
verify the bit error rate performance and found that bit error
rate decreases with increase in number of iterations. It is very
efficient to communication systems. The main advantage of
Turbo code Decoder is it has low bit error rate.

ENCODING OF TURBO CODE: As conventional code, the

encoder for a Turbo code accepts k-bit blocks of the
information sequence u and produces an encoded sequence
(code word) p of n-symbol blocks. Moreover, each encoded
block depends not only on the corresponding k-bit message Fig. 3: Encoder State Diagram Implementation
block at the same time unit, but also on m previous message
blocks. Forward Error Correction (FEC) is a technique for error
control during data transmission, whereby redundant
information is added to the original data, which allows the
receiver to detect and correct errors without the need to
resend the data.Figure 3 depicts the implementation of RSC
state table shown in figure 2. The Turbo encoder comprises
two RSC encoders and an interleaver as shown in figure 5.
Here the purpose of interleaver is to scramble input
information so that there is no correlation between the data
applied to the encoders.

Fig.1: Encoder Block Diagram for an RSC Code.[1]

The encoder is a memory-two encoder. The two memory
elements can take on four possible states. A hardware
realization for encoder is shown in Figure 1. The value of the
two memory elements in the encoder, R0 and R1; define the
“state” of the encoder. A state diagram is created from the
possible state changes of R0 and R1 (as all possible input
sequences are generated) and is used to create a trellis
diagram utilized in the decoder operation. The state diagram
for the encoder is shown in Figure 2.

Fig. 4: Encoder of Turbo Code.[2]

Figure 3 depicts the implementation of RSC state table

shown in figure 2. The Turbo encoder comprises two RSC
encoders and an interleaver as shown in figure 4. Here the
purpose of interleaver is to scramble input information so that
there is no correlation between the data applied to the
encoders.

DECODING OF TURBO CODE: A turbo decoder is associate

repetitious decoder, within which multiple decoders share
chance info with each other in a repetitious fashion. The turbo
decoder receives as its input a soft call worth from the rectifier.
Fig. 2: State diagram for the encoder.[1]

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This soft call worth can represent the chance that the
transmitted bit was a one or zero.
A Parallel concatenated code decoder consists of two
identical decoders, two identical interleavers, one
deinterleaver, and a hard-decision output logic block, as
shown in Fig. 6. Most A Posteriori (MAP) Soft-in, Soft-out
(SISO) decoder is employed for the 2 decoders. The interleaver
used is same because the interleaver employed in the encoder,
and therefore the deinterleaver performs the alternative
operation of the interleaver. The 3 outputs from the encoder:
u, p, and q, are received into the decoder as u’, p’, and q’. The
received bits: u’, p’, and q’ correspond to u, p, and alphabetic
character once having been littered with the transmission. Fig. 7: Implemented Decoder Black Box

Fig. 8: SISO Decoder Architecture

A portion of the force of turbo codes originates from the

Fig. 5: PCCC Iterative Decoder Block Diagram
way that the two encoded information groupings are decoded
independently, yet the likelihood data from every decoder
(Outward data) is shared. Since both decoders work on the
same arrangement of data bits, every decoder has the capacity
of helping the other. Subsequently, every cycle through the
decoder gives an increment (to a point) in the likelihood of
creating the right codeword at the decoder yield.

INTERLEAVERS: Interleavers are used in noncorrelation of

two data outputs. Input bits are scrambles. Interleavers are
classified into different types. They are Matrix interleavers,
Random interleavers, Circular shift interleavers, odd and even
interleavers. The purpose of the interleaver is to reorder a
group of K input bits before they are encoded by the second
RSC encoder. Typically, a turbo encoder interleaver is
implemented by some type of pseudo-random algorithm. The
Fig. 6: SISO Decoder Block Diagram interleaving algorithm that is used in the encoder can have
significant impact on the performance of the decoder.[6] For
The decoder works on a 3K-bit square of got groupings the purposes of this study, only one interleaver type was used,
u', p', and q'. Each 3K-bit piece of got information goes through a random K-bit interleaver.
various emphasess in the two decoder framework. The The interleaver utilized as a part of the decoder must
quantity of emphasess relies on the execution prerequisites match the interleaver utilized as a part of the encoder. The
and framework level contemplations. Once an adequate interleaver will be distinctive regarding equipment usage,
number of decoder cycles have been performed, the outward taking into account the way that delicate qualities (or multi-bit
data from both decoders and the log-probability proportion of qualities) are going between the decoders. Consequently, the
the got methodical images are utilized to process the decoded size and many-sided quality of the interleaver execution is
message. identified with the quantity of bits (or quantization) chosen as
the yield of every decoder. The deinterleaver performs the

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inverse capacity of the interleaver; where the interleaver
permutes the information, the de-interleaver de-permutes the
information back to the first request.

IMPLIMENTATION: The schematic of the 8 bit turbo

transmitter is shown below figure 10. It adds two coded bits
for each transmitting bit, so the number of output bits from the
transmitter is twenty four. In these eight bits are original bits,
eight from first RSC and eight from second RSC whose input is
interleaved version of input. The transmitter follows the state
diagram of RSC to get work done.

Fig .11: Implemented Receiver

The figure 12 below shows the wave forms of

implemented encoder. The figure 13 below shows the wave
Fig. 9: Trellis for Decoder Implementation forms of implemented decoder, the decoder having two RSC
decoders with interleaver and De-interleaver blocks. Initially
one decoder decodes the information and then the second
decoder decodes information depending on the interleaved
output of the first decoder and input, finally the output of the
second decoder applied to De-interleaver to produce hard
decision output.

Fig. 10: Implemented Transmitter

These bits are transmitted over space to reach the

receiver. The received signal is added up with noise so the
receiver has to receive signals intelligently to avoid errors. The
Fig. 12: Implemented encoder output wave forms
receiver implementation is shown in figure11. It follows the
Trellis (figure 9) to receive the information depending on
present information being received and past information
received. The receiver runs four state machines at a time with
all possibilities to receive signals with less number of errors.

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REFERENCES:
1. Rajesh Akula Performance. Design of turbo encoder and
decoder using iterative method. International Journal of
Electronics and Communications (IJEC), Volume-1,
Issue-1 in August 2012 ISSN-0098.
2. C. Benkeser, A. Burg, T. Cupaiuolo and Q. Huang. Design
andoptimization of an HSDPA turbo decoder ASIC. IEEE
JSSC, Vol. 44, No. 1, pp. 98–106, Jan. 2008.
3. R. Dobkin, M. Peleg, and R. Ginosar. Parallel VLSI
architecture for MAP turbo decoder in Proc. IEEE Int.
Symp. PIMRC, Vol. 1, Sept. 2002, pp. 384–388.
4. J. H. Han1, Erdogan T. Arslan1, High Speed Max-Log-MAP
Turbo SISO Decoder Implementation Using Branch
Metric. A unified Turbo/Viterbi channel decoder for
3GPP mobile wireless in 0.18 μm CMOS. Vol. 37, No. 11,
pp. 1555-1564, 2002.
5. Sae-Young Chung, G. David Forney, Thomas J. Richardson
Fig. 13: Implemented Receiver output wave forms and Rüdiger Urbanke. On the Design of Low-Density
Parity-Check Codes within 0.0045 dB of the Shannon
Limit. Vol. 5, No. 2, page(s):58-60, February 2001.
6. R. W. Hamming. Error detecting and correcting codes.
Bell Sys. Tech. J. Vol. 29, pp. 147–160, 1950 18, pp. 794-
807, May 2010.
7. Sadjadpour, H. R. Sloane, N. J. A. Salehi, M. Nebe, G.
Interleaver design for turbo codes, IEEE Journal on
Selected Areas in Communications, Volume: 19, Issue: 5,
page(s): 831-837, May 2001.
8. J. Vogt and A. Finger. Improving the max-log-MAP turbo
decoder. Elec. Letters, Vol. 36, no. 23, pp. 1937–1939,
Nov. 2000.
Fig.14: The bit error rate comparison in MATLAB 9. T. P. Fowdur, K. M. S. Soyjaudah. Joint source channel
decoding and iterative symbol combining with turbo
If the two decoders iterate for one more cycle, the information trellis-coded modulation. Signal Processing, Volume 89,
received can be a bit accurate. The accuracy further improved Issue 4, page(s):570-582, April 2009.
by increasing number of iterations. The figure 13 above shows 10. Erl-Huei Lu, Yi-Nan Lin, Wei-Wen Hung. Improvement of
the bit error rate considering white Gaussian noisy channel turbo decoding using cross-entropy Computer
with binary phase shifting modulation technique. Communications, Volume 32, Issue 6, page(s):1034-
1038,27 April 2009.
Parameter Veterbi Decoder Turbo Decoder
11. Fan Zhang and Henry D. Pfister. On the Iterative
Area (LUT’s) 120 [14] 77
Decoding of High-Rate LDPC Codes with Applications in
Delay (ns) 23.829 [14] 10.482
Table1: Comparison Table Compressed Sensing. arXiv: 0903.2232v2 [cs.IT], 17
June, 2009.
The implementation was compared with conventional 12. David Haley, Vincent Gaudet, Chris Winstead, Alex Grant,
Veterbi Decoder and observed that the proposed one occupies Christian Schlegel. A dual-function mixed-signal circuit
less area and produces less amount of delay. for LDPC encoding/decoding Integration, the VLSI
Journal, Volume 42, Issue 3, page(s): 332-339, June 2009.
CONCLUSION: The turbo encoder and Decoder were 13. Mohammad Salim, R.P. Yadav, S. Ravikanth, Dept. of
implemented in Verilog to deploy on to the FPGA. The Electronics & Communication Engineering, MNIT, Jaipur,
synthesis done for the 8 bit transmitter and receiver for Rajasthan (India), Performance Analysis of Log-map,
Spartan 3E Field programmable Gate Array. The decoder is SOVA and Modified SOVA Algorithm for Turbo Decoder‖,
able to receive information same as the information International Journal of Computer Applications (0975 –
transmitted from the Transmitter. These parameters can have 8887) Volume 9– No.11, November 2010 .
negative effects when very low BERs are simulated. Another 14. Anapartha Sunanda, Susmitha Remmanapudi. VLSI
cause for the limitation in BER performance is a poor Implementation of Efficient Convolutional Encoder and
interleaver design. Due to highly correlated sequences, the Modified Viterbi Decoder in Special Issue-3, November
BER decreases to a certain level from the decoding process. 2014 SJ Impact Factor-3.995 ISSN: 2321-9653.
This is the effect of the turbo code BER curve. The simulation 15. O. M. Collins and M. Hizlan. Determinate State
result curve also presents a change in slope but at very low Convolutional Codes IEEE Transactions on
BER’s. Communications. Vol. 41, pp. 1785, 1794, Dec. 1993.

Journal of Technological Advances & Scientific Research/ eISSN- 2454-1788, pISSN- 2395-5600/ Vol. 1/ Issue 04/ Oct-Dec. 2015 Page 326
Jtasr.com Project Article
16. L. Bahl, J. Cocke, F. Jelinek, and J. Raviv. Optimal decoding 18. A. J. Viterbi. Error bounds for convolutional codes and an
of linear codes for minimizing symbol error rate. IEEE asymptotically optimum decoding algorithm. IEEE
Trans. Inform. Theory, Vol. IT-20, pp. 248, 287, Mar. Trans. Inf. Th., vol. 13, no. 2,pp. 260–269, Apr. 1967.
1974. 19. M. Bickerstaff, L. Davis, C. Thomas, D. Garrett, and C.
17. A. P. Hekstra. An alternative to metric rescaling in Viterbi Nicol. logMAP turbo decoder for 3GPP-HSDPA mobile
decoders. IEEE Trans. Comm., Vol. 37, No. 11, pp. 1220– wireless in IEEE ISSCC Dig. Tech. papers, Vol. 1, San
1222, Nov. 1989. Francisco, CA, USA, Feb. 2003, pp. 150–484.

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