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MP 2

The x86 architecture evolved over several decades from the 8086 to include increasingly powerful processors like the 80386, 80486, Pentium, and beyond. Key developments included expanding from 16-bit to 32-bit addressing and data widths, onboard floating point units, caches, and increased clock speeds and instructions per cycle. The x86 uses a CISC instruction set decoded into micro-operations. It features segmentation for memory addressing and general purpose registers for data with specialized registers like EIP, EFLAGS, and segment registers.

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26 views

MP 2

The x86 architecture evolved over several decades from the 8086 to include increasingly powerful processors like the 80386, 80486, Pentium, and beyond. Key developments included expanding from 16-bit to 32-bit addressing and data widths, onboard floating point units, caches, and increased clock speeds and instructions per cycle. The x86 uses a CISC instruction set decoded into micro-operations. It features segmentation for memory addressing and general purpose registers for data with specialized registers like EIP, EFLAGS, and segment registers.

Uploaded by

ayan hazarika
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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X86 - ISA

The 80x86 Family


Name Date Trans Clock Data
istors speed width
8080 1974 6K 2MHz 8
8086 1978 29K 5MHz 16
80286 1982 134K 12 MHz 16
80386 1985 275K 16-33 MHz 32
80486 1989 1.2 M 20 -100 32
MHz
Pentium 1993 3.1M 60-200 32 /64
MHz
Pentium 1997 7.5 M 233-450 32/ 64
II MHz
Pentium 1999 9.5M 450 -933 32 /64
III MHz
Pentium 4 2000 42 M 1.5 GHz 32/ 64

The Evolution of Microprocessors


The 16-bit Processors
8086 80286
• 20 Address lines • 24 Address lines
• 220 – 1 MB • 224 – 16 MB
• 2.5 MIPS • 4 MIPS
The 32-bit Processors
80386 80486
• 32 Address lines • 32 Address lines
• 232 – 4GB • 232 – 4GB
• Floating Pt Unit
• Internal Cache
• 50 MIPS
Characteristics of the X86 Family
• CISC
• Instructions – broken up into µops
• Complex Instruction Decoder
Memory Interface


1
2
3
ES Instruction 4
CS Queue 5

SS 6
BIU
DS
IP
Control & Timing

EU
AH AL
BH BL
CH CL
ALU
DH DL
BP
SP Operands
SI Flags
DI

Block Diagram of 8086


8086 - Buses

A0 Add
Bus
A19

D0
Data
D15 Bus
8086

Control
signals
Memory Address Space
A19……………A0
0……………….0 00000H

1……………….1 FFFFFH

00000H

Memory
Address
Space

FFFFFH
Microprocessor

Fetches Instruction BIU

Executes Instruction EU
Address bus

BIU Discs
I/o
ROM RAM
Ports Video

Data Bus

ALU

CLK
Control
& Timing

EU
Variation of 8086 - 8088
• External Data Bus – 8-bits
• Inst Queue – 4 bytes
X86 - ISA
8086-80486 Programmers Model
BIU
Memory Addressing
• Real
– Access only 1 MB of Memory
– Only 20 Address Lines Required
• Protected
Programmer’s Model - BIU

EIP IP

CS
DS
ES
SS
FS
GS
Code Segment

Data Segment

Extra Segment

Stack Segment
CS = 2000H Base address
IP = 3000H Offset address

CS

2000H : 3000H
DS

ES
Physical address
= 20000H + SS
3000H

23000H
2000 0000

3000
Code
Segment

FFFF
Advantage of Segmentation
• Relocation
• Program – Specify only offset
• Program – F0000H  10000H
• Program contents need not be change – only
Segment needs to change from F000H 
0000H
58FFFH
Extra
49000H 4900 ES
43FFFH
Stack
34000H 3400 SS
2FFFFH
Code
20000H 2000 CS
1FFFFH
Data
10000H 1000 DS

00000H
High Memory
• HIMEM.SYS
• A20
• Segment Address – FFFFH
• Offset Address – 4000H
• 103FF0H
• 03FF0H
X86 - ISA

8086-80486 Programmers Model


EU
Programmers Model
AX Accumulator
BX Base Index
CX Count
DX Data
SP Stack Pointer
BP Base Pointer
SI Source Index
DI Destination Index
Registers
MULTIPURPOSE REGISTERS

AX, BX, CX, DX, BP, DI, SI

SPECIAL PURPOSE REGISTERS

IP, SP, FLAGS

CS, DS, SS, ES


( Segment Registers )
Registers - MPR

AX AH AL
(8 bit) (8 bit)
(Accumulator)

BX BH BL
(Base Register)

CX CH CL
(Used as a counter)

DX DH DL

(Used to point to data in I/O operations)


Programmer’s Model-MPR

EAX AH AL
EBX BH BL
ECX CH CL
EDX DH DL
EBP BP
ESI SI
EDI DI
ESP SP
Default 16 bit segment and offset address
combinations

Segment offset special purpose

CS IP Instruction
Address

SS SP (or) BP Stack address

BX,DI,SI
DS an 8-bit number Data address
16 – bit number

ES DI for string String destination


Instructions address
Programmer’s Model -SFR

EFLAGS FLAGS
Flags
• Status
• Control
Flag Register

A V R N IOPL O D I T S Z A P C
C M F T
80x86-Summary
BIU (Bus Interface Unit)
provides hardware funcns for generation of the memory
and I/O addresses for the transfer of data between
itself and the outside world

EU (Execution Unit)
receives program instruction codes and data from the
BIU executes these instructions and stores the results
in the general- purpose registers

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