Laboratory Exercise Dig7

Finite State Machines

This is an exercise in using finite state machines.

Part I

We wish to implement a finite state machine (FSM) that recognizes two specific sequences of applied input sym-
bols, namely four consecutive 1s or four consecutive 0s. There is an input w and an output z. Whenever w = 1 or
w = 0 for four consecutive clock pulses the value of z has to be 1; otherwise, z = 0. Overlapping sequences are
allowed, so that if w = 1 for five consecutive clock pulses the output z will be equal to 1 after the fourth and fifth
pulses. Figure 1 illustrates the required relationship between w and z.

Clock

Figure 1. Required timing for the output z.

A state diagram for this FSM is shown in Figure 2. For this part you are to manually derive an FSM circuit that
implements this state diagram, including the logic expressions that feed each of the state flip-flops. To implement
the FSM use nine state flip-flops called y 8 , . . . , y0 and the one-hot state assignment given in Table 1.

State Code
Name y 8 y7 y6 y5 y4 y3 y2 y1 y0
A 000000001
B 000000010
C 000000100
D 000001000
E 000010000
F 000100000
G 001000000
H 010000000
I 100000000

Table 1. One-hot codes for the FSM.

1
 Reset

A/0
w=0 w=1
1
B/0 0 F/0

w=0 1
1 0
C/0 G/0

w=0 1 0 1

D/0 1 0 H/0

w=0 1

0 E/1 I/1 1

Figure 2. A state diagram for the FSM.

Design and implement your circuit on the DE2 board as follows.

1. Create a new Quartus II project for the FSM circuit. Select as the target chip the Cyclone II EP2C35F672C6,
which is the FPGA chip on the Altera DE2 board.
2. Write a Verilog file that instantiates the nine flip-flops in the circuit and which specifies the logic expressions
that drive the flip-flop input ports. Use only simple assign statements in your Verilog code to specify the
logic feeding the flip-flops. Note that the one-hot code enables you to derive these expressions by inspection.
Use the toggle switch SW0 on the Altera DE2 board as an active-low synchronous reset input for the FSM,
use SW1 as the w input, and the pushbutton KEY 0 as the clock input which is applied manually. Use the
green LED LEDG0 as the output z, and assign the state flip-flop outputs to the red LEDs LEDR 8 to LEDR0 .

3. Include the Verilog file in your project, and assign the pins on the FPGA to connect to the switches and the
LEDs, as indicated in the User Manual for the DE2 board. Compile the circuit.
4. Simulate the behavior of your circuit.
5. Once you are confident that the circuit works properly as a result of your simulation, download the circuit
into the FPGA chip. Test the functionality of your design by applying the input sequences and observing
the output LEDs. Make sure that the FSM properly transitions between states as displayed on the red LEDs,
and that it produces the correct output values on LEDG 0 .
Off campus students: Use the supplied testbench on Moodle called Dig7part1_tb.v and include your
module in the file. You may need to rename your module to FSM. Run the ModelSim simulation to
completion and plot waveforms that include the error_count (should be 0) Clock, Reset, Wseq[0], z_alt
and z_student as binary representations (the default). Note that the implementation of the altFSM should
be different to your implementation – the alt version uses a different set of states to the lab notes but is
correct. The Alt version is merely for checking the correct answer. Save the testbench and show
ModelSim and $display messages to your demonstrator.
6. Finally, consider a modification of the one-hot code given in Table 1. When an FSM is going to be im-
plemented in an FPGA, the circuit can often be simplified if all flip-flop outputs are 0 when the FSM is in
the reset state. This approach is preferable because the FPGA’s flip-flops usually include a clear input port,
which can be conveniently used to realise the reset state, but the flip-flops often do not include a set input
port.
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 Table 2 shows a modified one-hot state assignment in which the reset state, A, uses all 0s. This is accom-
plished by inverting the state variable y 0 . Create a modified version of your Verilog code that implements
this state assignment. (Hint: you should need to make very few changes to the logic expressions in your
circuit to implement the modified codes.) Compile your new circuit and test it both through simulation and
by downloading it onto the DE2 board.

State Code
Name y 8 y7 y6 y5 y4 y3 y2 y1 y0
A 000000000
B 000000011
C 000000101
D 000001001
E 000010001
F 000100001
G 001000001
H 010000001
I 100000001

Table 2. Modified one-hot codes for the FSM.

Part II

For this part you are to write another style of Verilog code for the FSM in Figure 2. In this version of the code you
should not manually derive the logic expressions needed for each state flip-flop. Instead, describe the state table
for the FSM by using a Verilog case statement in an always block, and use another always block to instantiate
the state flip-flops. You can use a third always block or simple assignment statements to specify the output z. To
implement the FSM, use four state flip-flops y 3 , . . . , y0 and binary codes, as shown in Table 3.

State Code
Name y 3 y2 y1 y0
A 0000
B 0001
C 0010
D 0011
E 0100
F 0101
G 0110
H 0111
I 1000

Table 3. Binary codes for the FSM.

A suggested skeleton of the Verilog code is given in Figure 3.

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 module part2 ( . . . );
. . . define input and output ports

. . . define signals
reg [3:0] y_Q, y_D; // y_Q represents current state, y_D represents next state
parameter A = 4'b0000, B = 4'b0001, C = 4'b0010, D = 4'b0011, E = 4'b0100,
F = 4'b0101, G = 4'b0110, H = 4'b0111, I = 4'b1000;

always @(w, y_Q)

always @(posedge Clock)

. . . assignments for output z and the LEDs

Figure 3. Skeleton Verilog code for the FSM. This Code can be downloaded
from Moodle as LabDig7Fig3skeletonCode.v

Implement your circuit as follows.

1. Create a new project for the FSM. Select as the target chip the Cyclone II EP2C35F672C6.

2. Include in the project your Verilog file that uses the style of code in Figure 3. Use the toggle switch SW 0 on
the Altera DE2 board as an active-low synchronous reset input for the FSM, use SW 1 as the w input, and the
pushbutton KEY 0 as the clock input which is applied manually. Use the green LED LEDG 0 as the output z,
and assign the state flip-flop outputs to the red LEDs LEDR 3 to LEDR0 . Assign the pins on the FPGA to
connect to the switches and the LEDs, as indicated in the User Manual for the DE2 board.
3. Before compiling your code it is necessary to explicitly tell the Synthesis tool in Quartus II that you wish to
have the finite state machine implemented using the state assignment specified in your Verilog code. If you
do not explicitly give this setting to Quartus II, the Synthesis tool will automatically use a state assignment
of its own choosing, and it will ignore the state codes specified in your Verilog code. To make this setting,
choose Assignments > Settings in Quartus II, and then click on the Analysis and Synthesis item on the
left side of the window. As indicated in Figure 4, change the parameter State Machine Processing to the
setting User-Encoded.

4. To examine the circuit produced by Quartus II open the RTL Viewer tool. Double-click on the box shown
in the circuit that represents the finite state machine, and determine whether the state diagram that it shows
properly corresponds to the one in Figure 2. To see the state codes used for your FSM, open the Compilation
Report, select the Analysis and Synthesis section of the report, and click on State Machines.

5. Simulate the behavior of your circuit.

6. Once you are confident that the circuit works properly as a result of your simulation, download the circuit
into the FPGA chip. Test the functionality of your design by applying the input sequences and observing

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 the output LEDs. Make sure that the FSM properly transitions between states as displayed on the red LEDs,
and that it produces the correct output values on LEDG 0 . Off campus students: use the testbench code in
the file Dig7part2_tb.v and follow a similar approach to part 1.

7. In step 3 you instructed the Quartus II Synthesis tool to use the state assignment given in your Verilog
code. To see the result of removing this setting, open again the Quartus II settings window by choosing
Assignments > Settings, and click on the Analysis and Synthesis item. Change the setting for State
Machine Processing from User-Encoded to One-Hot. Recompile the circuit and then open the report
file, select the Analysis and Synthesis section of the report, and click on State Machines. Compare the
state codes shown to those given in Table 2, and discuss any differences that you observe.

Figure 4. Specifying the state assignment method in Quartus II.

Part III

For this part you are to implement the sequence-detector FSM by using shift registers, instead of using the more
formal approach described above. Create Verilog code that instantiates two 4-bit shift registers; one is for recog-
nizing a sequence of four 0s, and the other for four 1s. Include the appropriate logic expressions in your design to
produce the output z. Make a Quartus II project for your design and implement the circuit on the DE2 board. Use
the switches and LEDs on the board in a similar way as you did for Parts I and II and observe the behavior of your
shift registers and the output z. Off campus students: Start by writing a separate module call Shifter4 as outlined
in the testbench file digpart3_tb.v . This module is instantiated twice in the FSM module. Repeat the process
in part 1 to complete this section.

Answer the following question: could you use just one 4-bit shift register, rather than two? Explain your answer.

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Part IV

We want to design a modulo-10 counter-like circuit that behaves as follows. It is reset to 0 by the Reset input. It
has two inputs, w1 and w0 , which control its counting operation. If w 1 w0 = 00, the count remains the same. If
w1 w0 = 01, the count is incremented by 1. If w 1 w0 = 10, the count is incremented by 2. If w 1 w0 = 11, the
count is decremented by 1. All changes take place on the active edge of a Clock input. Use toggle switches SW 2
and SW1 for inputs w1 and w0 . Use toggle switch SW0 as an active-low synchronous reset, and use the pushbutton
KEY0 as a manual clock. Display the decimal contents of the counter on the 7-segment display HEX0.

1. Create a new project which will be used to implement the circuit on the DE2 board.

2. Write a Verilog file that defines the circuit. Use high level behavioural style of code with arithmetic
operators such as + addition and - subtraction. You should be able to write Verilog with no more
than 4 cases in any case statements.
3. Include the Verilog file in your project and compile the circuit.
4. Simulate the behavior of your circuit.
5. Assign the pins on the FPGA to connect to the switches and the 7-segment display.
6. Recompile the circuit and download it into the FPGA chip. Test the functionality of your design by
applying some inputs and observing the output display.

Off campus students: The altMod10Counter is used by the testbench as a correct solution. Do not
base your solution on this since it has problems when used for synthesis. Your implementation should
have two always blocks, where one is a combinational logic function to generate the next count value
given the current count and inputs w. The second always block updates to register holding the output
count and is conditioned on the positive edge of the clock, so generates four flip-flops since your code
should update the four bit Q10 in the block from the output of the combinational block above.
Note that the testbench for the mod 10 counter is straightforward and has separate tests for increment
by 1 and 2 and decrement. The increment by 2 tests odd and even starting values to cover different
wrap around conditions.
Run the testbench to completion and show ModelSim with the number_errors, Wseq, Clock, Reset,
Q10alt and Q10student to your demonstrator.

Concluding Remarks
This lab commenced in Part I with an implementation of a FSM using flip-flop instantiations and assign
statements to implement the next state behaviour of the the FSM. This low level approach is NOT
RECOMMENDED in practice since it is tedious and error prone, but it does illustrate how a FSM is represented
in hardware. The latter parts of the lab use a HIGH LEVEL BEHAVIOURAL Verilog coding style that
involves defining the next state behaviour using always blocks with if and case statements, from which the
compiler will derive the next state functions in an optimal way for the target device, in our case an FPGA. The
state behaviour is directly apparent from this description which means the designer can quickly, simply
and reliably make updates in a solution. Please try to always use high level approaches unless there is a
good reason to revert to detailed logic equations. For example you will be asked to complete a design in an
assignment towards the end of semester where you will be assessed based on your high level behavioural
solutions in Verilog.