ESP32­S3 Series

Hardware Design Guidelines

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Introduction
Hardware design guidelines give advice on how to integrate ESP32-S3 into other products.
ESP32-S3 is a series of high-performance Wi-Fi and Bluetooth® 5 (LE) SoCs.

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These guidelines will help to ensure optimal performance of your product with respect to tech-
nical accuracy and conformity to Espressif’s standards.
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Version 1.0
Espressif Systems
Copyright © 2021

www.espressif.com
Contents

Contents

1 Overview 5

2 Schematic Checklist 6
2.1 Power Supply 7
2.1.1 Digital Power Supply 7
2.1.2 Analog Power Supply 8

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2.2 Power-on Sequence and System Reset 9
2.2.1 Power-on Sequence 9
2.2.2 System Reset 9

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2.2.3 Power-up and Reset Timing 9
2.3 Flash and SRAM 10
2.3.1 SiP Flash and SiP PSRAM 10
2.3.2 External Flash and External RAM 10

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2.4 Clock Source 11
2.4.1 External Clock Source (compulsory) 11
2.4.2 RTC (optional) 12
2.5 RF 13
2.6 UART 13
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2.7 ADC 13
2.8 Strapping Pins 13
2.9 USB 15
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2.10 Touch Sensor 16

3 PCB Layout Design 17

3.1 General Principles of PCB Layout 17
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3.2 Positioning a Module on a Base Board 18

3.3 Power Supply 20
3.4 Crystal Oscillator 21
3.5 RF 22
3.6 Flash and PSRAM 24
3.7 UART 24
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3.8 USB 24
3.9 Touch Sensor 24
3.9.1 Electrode Pattern 25
3.9.2 PCB Layout 25
3.9.3 Waterproof and Proximity Sensing Design 26
3.10 Typical Layout Problems and Solutions 27
3.10.1 Q: The current ripple is not large, but the TX performance of RF is rather poor. 27
3.10.2 Q: The power ripple is small, but RF TX performance is poor. 27
3.10.3 Q: When ESP32-S3 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 28
3.10.4 Q: TX performance is not bad, but the RX sensitivity is low. 28

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Contents

4 Hardware Development 29
4.1 ESP32-S3 Modules 29
4.2 ESP32-S3 Development Boards 29

5 Related Documentation and Resources 30

Glossary 31

Revision History 32

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List of Illustrations

List of Tables
1 Description of ESP32-S3 Power-up and Reset Timing Parameters 9
2 Pin-to-Pin Mapping Between Chip and SiP Flash/PSRAM 10
3 JTAG Signal Source Selection 14
4 Strapping Pins 14
5 Parameter Descriptions of Setup and Hold Times for the Strapping Pin 15

List of Figures

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1 ESP32-S3 Schematic 6

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2 Schematic for the Digital Power Supply Pins 7
3 Schematic for the Analog Power Supply Pins 8
4 ESP32-S3 Power-up and Reset Timing 9
5 Schematic for the External Flash and RAM (PSRAM) 11

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6 Schematic for the Crystal 11
7 Schematic for the Oscillator 12
8 Schematic for the External Crystal (RTC) 12
9 Schematic for RF Matching 13
10 Setup and Hold Times for the Strapping Pin 15
11 ESP32-S3 PCB Layout 17
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12 Placement of ESP32-S3 Modules on Base Board (antenna feed point on the right) 18
13 Placement of ESP32-S3 Modules on Base Board (antenna feed point on the left) 18
14 Keepout Zone for ESP32-S3 Module’s Antenna on the Base Board 19
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15 ESP32-S3 Power Traces in a Four-layer PCB Design 20
16 ESP32-S3 Analog Power Traces in a Four-layer PCB Design 21
17 ESP32-S3 Crystal Oscillator Layout 22
18 ESP32-S3 RF Layout in a Four-layer PCB Design 22
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19 ESP32-S3 PCB Stack up Design 23

20 ESP32-S3 Stub in a Four-layer PCB Design 23
21 ESP32-S3 Flash Layout 24
22 A Typical Touch Sensor Application 25
23 Electrode Pattern Requirements 25
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24 Sensor Track Routing Requirements 26

25 Shield Electrode and Protective Sensor 26

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1 Overview

1 Overview
Note:

Check the link or the QR code to make sure that you use the latest version of this document:
https://espressif.com/sites/default/files/documentation/esp32-s3_hardware_design_guidelines_en.
pdf

ESP32-S3 is a highly-integrated, low-power, 2.4 GHz Wi-Fi + Bluetooth® LE (5) System-on-Chip (SoC) solution.
It has the following features:

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• Xtensa® 32-bit LX7 CPU operating at clock speeds up to 240 MHz

• Complete Wi-Fi + Bluetooth subsystem integrating radio and baseband, RF switch, RF balun, power

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amplifier, low noise amplifier (LNA), etc

• State-of-the-art power management unit

• Industry-leading RF performance

• Powerful AI computing ability

• Rich set of peripherals

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ESP32-S3 also integrates advanced calibration circuitry that compensates for radio imperfections, and thus
reduces the cost and time to the market for your product, and eliminates the need for specialized testing
equipment.
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The SoC is an ideal choice for a wide variety of application scenarios related to AI and Artificial Intelligence of
Things (AIoT), such as:
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• Wake word detection

• Speech commands recognition

• Face detection and recognition

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• Smart home

• Smart appliances

• Smart control panel

• Smart speaker
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For more information about ESP32-S3 series, please refer to ESP32-S3 Series Datasheet.

Note:
Unless otherwise specified, ”ESP32-S3” used in this document refers to the series of chips, instead of a specific chip
variant.

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 2 Schematic Checklist

2 Schematic Checklist
The integrated circuitry of ESP32-S3 requires only 20 electrical components (resistors, capacitors, and
inductors), one crystal and one SPI flash memory chip. The high integration of ESP32-S3 allows for simple
peripheral circuit design. This chapter details ESP32-S3 schematics.

ESP32-S3 schematic is shown in Figure 1.

5 4 3 2 1

GND

GND GND

3
Y1

GND

GND XOUT

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D C1 C4

XIN
TBD TBD VDD33

The values of C1 and C4 vary with

2
the selection of the crystal.

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R1

The value of R4 varies with the actual GND 10K(NC)

VDD33 PCB board. 40MHz(±10ppm)
GPIO46
GPIO45
U0RXD
C3 C2 R3 499 U0TXD
GPIO42
0

1uF 10nF GPIO41

GPIO40
VDD33 GPIO39

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GND GND GND GPIO38
R4

L1 0
C
C6 C7 C8 C9 C10
VDD33
57

56
55
54
53
52
51
50
49
48
47
46
45
44
43

10uF 1uF 0.1uF TBD 0.1uF

GND

VDDA
VDDA
XTAL_P
XTAL_N
GPIO46
GPIO45
U0RXD
U0TXD
MTMS

GPIO38
MTDI
VDD3P3_CPU
MTDO
MTCK

GND GND GND GND GND

VDD_SPI
ANT1
1 RF_ANT L2 TBD LNA_IN 1 42 GPIO37
LNA_IN GPIO37

8
2 2 41 GPIO36
3 VDD3P3 GPIO36 40 GPIO35
L3 C11 C12

VDD
PCB_ANT CHIP_PU 4 VDD3P3 GPIO35 39 GPIO34 SPICS0 1 5 SPID
TBD TBD TBD GPIO0 5 CHIP_PU GPIO34 38 GPIO33 /CS DI
GPIO1 6 GPIO0 GPIO33 37 GPIO47 SPICLK 6 2 SPIQ
GPIO1 SPICLK_P CLK DO
E
GPIO2 7 36 GPIO48
GND GND GND GPIO3 8 GPIO2 SPICLK_N 35 R16 0 SPID SPIHD 7 3 SPIWP

GND
GPIO4 9 GPIO3 SPID 34 R15 0 SPIQ /HOLD /WP
C5 GPIO4 SPIQ
GPIO5 10 33 R10 0 SPICLK
GPIO6 11 GPIO5 SPICLK 32 SPICS0 U2 FLASH-3V3
TBD

4
GPIO7 12 GPIO6 SPICS0 31 R14 0 SPIWP
B
GPIO8 13 GPIO7 SPIWP 30 R13 0 SPIHD
GPIO9 14 GPIO8 SPIHD 29 GND
GND
VDD3P3_RTC

GPIO9 VDD_SPI
ID XTAL_32K_N
XTAL_32K_P

VDD_SPI
The values of C11, L2 and C12
C14 VDD_SPI
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

C13
SPICS1

vary with the actual PCB board.

8
NC: No component. 0.1uF 1uF

VDD
U1 ESP32-S3 SPICS1 1 5 SPID
15
16
17
18
19
20
21
22
23
24
25
26
27
GPIO26 28

VDD33 GND GND CS SI/SIO0

SPICLK 6 2 SPIQ
SCLK SO/SIO1
SPIHD 7 3 SPIWP
VSS

C15 SIO3 SIO2

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GPIO10
GPIO11
GPIO12
GPIO12
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1

0.1uF U3 PSRAM-3V3 (Optional)

4

GND GND
A

Figure 1: ESP32­S3 Schematic

5 4 3 2 1
Notice:
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Figure 1 shows the connection for quad SPI flash/PSRAM. In cases when external octal SPI flash/PSRAM is used, or
when octal SiP PSRAM is used in ESP32-S3R8 and ESP32-S3R8V, GPIO33 ~ GPIO37 are occupied and cannot be used
for other functions.

Any basic ESP32-S3 circuit design may be broken down into 10 major sections:

• Power supply • UART

• Power-on sequence and system reset • ADC

• Flash and SRAM • USB

• Crystal oscillator • Touch Sensor

• RF • Strapping pins
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 2 Schematic Checklist

The rest of this document details the specifics of circuit design for each of these sections.

2.1 Power Supply

Details of using power supply pins can be found in Section Power Scheme in ESP32-S3 Series Datasheet.

2.1.1 Digital Power Supply

ESP32-S3 has pin46 VDD3P3_CPU that supplies power to CPU IO, in a voltage range of 3.0 V ~ 3.6 V. It is
recommended to add an extra 0.1 µF decoupling capacitor close to each digital power supply pin.

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Pin29 VDD_SPI can serve as the power supply for the external device at either 1.8 V if GPIO45 is pulled high
during boot, or at 3.3 V if GPIO45 is pulled low during boot. It is recommended to add extra 0.1 µF and 1 µF
decoupling capacitors close to VDD_SPI.

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4 3 2
• When VDD_SPI operates at 1.8 V, it is powered by the internal Flash Voltage Regulator on the chip. The
GND
maximum current this Flash Voltage Regulator can offer is 40 mA.
GND GND
3

• When VDD_SPI
Y1 operates at 3.3 V, it is driven directly by VDD3P3_RTC through RSP I resistor, therefore,

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GND XOUT

GND

there will be some voltage drop from VDD3P3_RTC.

C1 C4
VDD33
XIN

VDD_SPI
TBD can also be driven
TBDby an external power supply.

and C4 vary with

2

he crystal. R1
Notice:
10K(NC)
varies with the actual
When using VDD_SPI as the power supply pin for the external 3.3 V flash/PSRAM, the supply voltage should be 3.0 V or
GND
40MHz(±10ppm) GPIO46
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above, so as to meet the requirements of flash/PSRAM’s working voltage. GPIO45
U0RXD
R3 499 U0TXD
C2 GPIO42
0

GPIO41
10nF
The schematic for the digital power supply pins is shown in Figure 2. GPIO40
ID
GPIO39
GND GPIO38
R4

GND
2.0nH
C10
C9 VDD33
57

56
55
54
53
52
51
50
49
48
47
46
45
44
43

0.1uF
0.1uF
GND

VDDA
VDDA
XTAL_N
XTAL_P
GPIO46
GPIO45
U0RXD
U0TXD
MTMS

MTDO
VDD3P3_CPU

MTCK
GPIO38
MTDI
NF

GND GND
VDD_SPI

TBD LNA_IN 1 42 GPIO37

LNA_IN GPIO37
8

2 41 GPIO36
3 VDD3P3 GPIO36 40 GPIO35
C12
VDD

CHIP_PU 4 VDD3P3 GPIO35 39 GPIO34 SPICS0 1 5 SPID

TBD GPIO0 5 CHIP_PU GPIO34 38 GPIO33 /CS DI
GPIO1 6 GPIO0 GPIO33 37 GPIO47 SPICLK 6 2 SPIQ
GPIO2 7 GPIO1 SPICLK_P 36 GPIO48 CLK DO
GND GPIO3 8 GPIO2 SPICLK_N 35 R16 0 SPID SPIHD 7 3 SPIWP
GND

9 GPIO3 SPID 34 /HOLD /WP

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GPIO4 R15 0 SPIQ

GPIO5 10 GPIO4 SPIQ 33 R10 0 SPICLK
nd C12 GPIO5 SPICLK
GPIO6 11 32 SPICS0 U2 FLASH-3V3
board.
4

GPIO7 12 GPIO6 SPICS0 31 R14 0 SPIWP

GPIO8 13 GPIO7 SPIWP 30 R13 0 SPIHD
GPIO9 14 GPIO8 SPIHD 29 GND
VDD3P3_RTC

GPIO9 VDD_SPI
XTAL_32K_N
XTAL_32K_P

VDD_SPI
C14 VDD_SPI
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

C13
SPICS1

0.1uF 1uF
VDD

U1 ESP32-S3 SPICS1 1 5 SPID

15
16
17
18
19
20
21
22
23
24
25
26
27
GPIO26 28

VDD33 GND GND CS SI/SIO0

SPICLK 6 2 SPIQ
SCLK SO/SIO1
SPIHD 7 3 SPIWP
VSS

C15 SIO3 SIO2

GPIO10
GPIO11
GPIO12
GPIO12
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1

0.1uF U3 PSRAM-3V3 (Optional)

4

GND GND

Figure 2: Schematic for the Digital Power Supply Pins

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2 Schematic Checklist

2.1.2 Analog Power Supply

Pin2 VDD3P3, pin3 VDD3P3, pin20 VDD3P3_RTC, pin55 VDDA, and pin56 VDDA are the analog power supply
pins, working at 3.0 V ~ 3.6 V.

It should be noted that the sudden increase in current draw, when ESP32-S3 is transmitting signals, may cause a
power rail collapse. Therefore,
5
it is highly recommended to add another 10
4
µF capacitor to the power trace, 3

which can work in conjunction with the 0.1 µF capacitor. In addition, a CLC filter circuit needs to be added near
VDD3P3 pins so as to suppress high-frequency harmonics. The recommended rated current of the inductor is
GND
500 mA or above. Refer to Figure 3 and place the appropriate decoupling capacitor near each analog power
pin. GND GND

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Y1

GND

GND XOUT
Notice: The values of C1 and C4 vary with
D C1 C4
the selection of the crystal.
• The recommended power supply voltage for ESP32-S3 is 3.3 V and the output current is no less than 500 mA. TBD

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TBD V
The value of R4 varies with the actual
• It is suggested to add an ESD protection diode at the power entrance.
PCB board.

2
GND

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VDD33 40MHz(±10ppm)

C3 C2

0
1uF 10nF

VDD33
GND GND GND

R4
L1 0
E
C
C6 C7 C8 C9
57

56
55
54
53
52
51
50
49
48
47
46
45
44
43
10uF 1uF 0.1uF TBD
GND

MTDO
VDDA
VDDA
XTAL_P
XTAL_N
GPIO46
GPIO45
U0RXD
U0TXD
MTMS

VDD3P3_CPU

MTCK
GPIO38
MTDI
ID
GND GND GND GND

ANT1
1 RF_ANT L2 TBD LNA_IN 1 42
2 2 LNA_IN GPIO37 41
3 VDD3P3 GPIO36 40
L3 C11 C12
PCB_ANT CHIP_PU 4 VDD3P3 GPIO35 39
CHIP_PU GPIO34
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TBD TBD TBD GPIO0 5 38

GPIO1 6 GPIO0 GPIO33 37
GPIO2 7 GPIO1 SPICLK_P 36
GND GND GND GPIO3 8 GPIO2 SPICLK_N 35
GPIO4 9 GPIO3 SPID 34
C5 GPIO4 SPIQ
GPIO5 10 33
GPIO6 11 GPIO5 SPICLK 32
TBD GPIO6 SPICS0
B GPIO7 12 31
GPIO8 13 GPIO7 SPIWP 30
GPIO9 14 GPIO8 SPIHD 29
GND
VDD3P3_RTC

GPIO9 VDD_SPI
XTAL_32K_N
XTAL_32K_P
CO

The values of C11, L2 and C12

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1

vary with the actual PCB board.

NC: No component.
U1 ESP32-S3
15
16
17
18
19
20
21
22
23
24
25
26
27
GPIO26 28

VDD33

C15
GPIO10
GPIO11
GPIO12
GPIO12
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1

0.1uF

GND
A

Figure 3: Schematic for the Analog Power Supply Pins

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2 Schematic Checklist

2.2 Power­on Sequence and System Reset

2.2.1 Power­on Sequence
ESP32-S3 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized.
This is achieved by delaying the activation of CHIP_PU after the 3.3 V rails have been brought up. More details
can be found in Section 2.2.3.

Notice:
To ensure that power is supplied to the chip during power-up, it is advised to add an RC delay circuit at the CHIP_PU
pin. The recommended setting for the RC delay circuit is usually R = 10 kΩ and C = 1 µF. However, specific parameters

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should be adjusted based on the power-up timing of the power supply and the power-up and reset sequence timing of
the chip.

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2.2.2 System Reset
CHIP_PU serves as the reset pin of ESP32-S3. The reset voltage (VIL_nRST ) should be in the range of (–0.3 ~

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0.25 × VDD) V. VDD is the I/O voltage for a particular power domain of pins. To avoid reboots caused by external
interferences, make the CHIP_PU trace as short as possible. Also, add a pull-up resistor as well as a capacitor to
the ground whenever possible.

Notice:
CHIP_PU pin must not be left floating.
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2.2.3 Power­up and Reset Timing
Figure 4 shows the power-up and reset timing of ESP32-S3 series of SoCs. Details about the parameters are
listed in Table 1.
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t0 t1

2.8 V

VDDA,
VDD3P3,
VDD3P3_RTC,
VDD3P3_CPU
CO

VIL_nRST
CHIP_PU

Figure 4: ESP32­S3 Power­up and Reset Timing

Table 1: Description of ESP32­S3 Power­up and Reset Timing Parameters

Parameter Description Min (µs)

Time between bringing up the power rails of VDDA, VDD3P3,
t0 50
VDD3P3_RTC, VDD3P3_CPU and activating CHIP_PU
t1 Duration of CHIP_PU signal level < VIL_nRST to reset the chip 50

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2 Schematic Checklist

2.3 Flash and SRAM

ESP32-S3 requires SiP flash or external flash to store application firmware and data. SiP PSRAM or external
RAM is optional.

2.3.1 SiP Flash and SiP PSRAM

SiP flash and SiP PSRAM refer to the flash and PSRAM that can be integrated into the package, depending on a
chip variant. For the pin-to-pin mapping between the chip and SiP flash/PSRAM, please refer to Table 2. The
chip pins listed here are not recommended for other usage.

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Table 2: Pin­to­Pin Mapping Between Chip and SiP Flash/PSRAM

ESP32­S3FN8 SiP flash (8 MB, Quad SPI)

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SPICLK CLK
SPICS0 CS#
SPID DI
SPIQ DO

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SPIWP WP#
SPIHD HOLD#
ESP32­S3R2 SiP PSRAM (2 MB, Quad SPI)
SPICLK CLK
SPICS1 CE#
E
SPID SI/SIO0
SPIQ SO/SIO1
SPIWP SIO2
ID
SPIHD SIO3
ESP32­S3R8 / ESP32­S3R8V SiP PSRAM (8 MB, Octal SPI)
SPICLK CLK
SPICS1 CE#
NF

SPID DQ0
SPIQ DQ1
SPIWP DQ2
SPIHD DQ3
GPIO33 DQ4
CO

GPIO34 DQ5
GPIO35 DQ6
GPIO36 DQ7
GPIO37 DQS/DM

2.3.2 External Flash and External RAM

ESP32-S3 supports up to 1 GB external flash and 1 GB external RAM. Make sure to select appropriate external
flash and RAM according to the power voltage on VDD_SPI. It is recommended to add a zero-ohm series resistor
on the SPI communication lines, as Figure 5 shows, to lower the driving current, reduce interference to RF, adjust
timing, and better shield from interference.

The schematic for the external flash and RAM is shown in Figure 5.

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 R4
C10
2 Schematic Checklist VDD33
57

56
55
54
53
52
51
50
49
48
47
46
45
44
43
0.1uF C
GND

VDDA
VDDA
XTAL_N
XTAL_P
GPIO46
GPIO45
U0RXD
U0TXD
MTMS

MTDO
VDD3P3_CPU

MTCK
GPIO38
MTDI
GND
VDD_SPI

42 GPIO37
LNA_IN GPIO37

8
41 GPIO36
VDD3P3 GPIO36 40 GPIO35

VDD
VDD3P3 GPIO35 39 GPIO34 SPICS0 1 5 SPID
CHIP_PU GPIO34 38 GPIO33 /CS DI
GPIO0 GPIO33 37 GPIO47 SPICLK 6 2 SPIQ
GPIO1 SPICLK_P 36 GPIO48 CLK DO
GPIO2 SPICLK_N 35 R16 0 SPID SPIHD 7 3 SPIWP

GND
GPIO3 SPID 34 R15 0 SPIQ /HOLD /WP
GPIO4 SPIQ 33 R10 0 SPICLK
GPIO5 SPICLK 32 SPICS0 U2 FLASH-3V3

4
GPIO6 SPICS0 31 R14 0 SPIWP
GPIO7 SPIWP 30 R13 0 SPIHD
GPIO8 SPIHD 29 GND
VDD3P3_RTC

GPIO9 VDD_SPI
XTAL_32K_N
XTAL_32K_P

B
VDD_SPI
C14 VDD_SPI
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

C13
SPICS1

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8
0.1uF 1uF

VDD
U1 ESP32-S3 SPICS1 1 5 SPID
15
16
17
18
19
20
21
22
23
24
25
26
27
GPIO26 28

GND GND CS SI/SIO0

SPICLK 6 2 SPIQ

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SCLK SO/SIO1
SPIHD 7 3 SPIWP

VSS
C15 SIO3 SIO2
GPIO10
GPIO11
GPIO12
GPIO12
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1

0.1uF U3 PSRAM-3V3 (Optional)

4
B

D
GND GND

Figure 5: Schematic for the External Flash and RAM (PSRAM)

NT A
VDD33
VDD33
NC: No component.
vary with the actual PCB board.
The values of C11, L2 and C12

PCB_ANT

ANT1

GND

2.4 Clock Source

10uF

C6
2
1

5
ESP32-S3 has two clock sources:
GND

GND

E
RF_ANT

1uF

C7

3 2 1
• External crystal oscillator clock source
TBD

C11

1uF

C3
GND

GND

GND

PCB board.
The value of R4 varies with the actual

the selection of the crystal.

The values of C1 and C4 vary with
0.1uF

C8

• RTC clock source

ID
L2

L1

2.4.1 External Clock Source (compulsory)

10nF
TBD

TBD

TBD

0
C12

C9

C2
GND

GND

GND

Currently, the ESP32-S3 firmware only supports 40 MHz crystal or oscillator.

NF
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CHIP_PU

LNA_IN

Crystal

The circuit for the crystal is shown in Figure 6. The specific capacitive values of C1 and C4 depend on further
14
13
12
11
10

testing of, and adjustment to, the overall performance of the whole circuit. In order to reduce the drive strength of
9
8
7
6
5
4
3
2
1

4
U1

the crystal and minimize the impact of crystal harmonics on RF performance, a zero-ohm series resistor on the
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CHIP_PU
VDD3P3
VDD3P3
LNA_IN
CO
GND

57
XTAL_P clock trace is required.
GNDNote that the accuracy of the selected crystal should be within ±10 ppm.
15 56
GPIO10 VDDA
TBD

16 55
C1

GPIO11 VDDA
GND

17 54 R4 0
18 GPIO12 XTAL_P 53
19 GPIO13 XTAL_N 52
GPIO14 GPIO46
40MHz(±10ppm)

GND

20 51 1 4
21 VDD3P3_RTC GPIO45 50 XIN GND
22 XTAL_32K_P U0RXD 49
Y1

23 XTAL_32K_N U0TXD 48
GPIO17 MTMS
GND

24 47 2 3
25 GPIO18 MTDI 46 GND XOUT
26 GPIO19 VDD3P3_CPU 45
27 GPIO20 MTDO 44
GPIO21 MTCK
GND

28 43
SPICS1 GPIO38
TBD

C4
SPICLK_N
SPICLK_P
VDD_SPI
ESP32-S3

GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
SPICS0
SPICLK
SPIWP
SPIHD

SPIQ
SPID

Figure 6: Schematic for the Crystal

29
30
31
32
33
34
35
36
37
38
39
40
41
42

VDD33
R13
R14

R10
R15
R16

GND

R3

Espressif Systems 11
0.1uF

C13

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0.1uF

C10

10K(NC)

R1

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0
0

0
0
0

499
1uF

C14
 2 Schematic Checklist

B
Oscillator

If an oscillator is used, its output should be connected to XTAL_P on the chip through a series inductor (a 20 nH
inductor can be used initially). XTAL_N can be floating. Make sure that the oscillator output is stable and its

NC: No component.
vary with the actual PCB board.
The values of C11, L2 and C12

PCB_ANT

ANT1

GND
3 accuracy is within ±10 ppm. It is recommended
2 that the circuit design for the oscillator
1 is compatible with the
crystal. In case of defects in the circuit design, you can still use the crystal. The circuit for the oscillator is shown

2
1
in Figure 7.
5

GND

GND
RF_ANT
VDD33 Y1

TBD

C11
XTAL_P

GND

GND
R4 0 4 3 L3 TBD
VDD33 VDD OUT

L L2
C1 1 2 D
Tri-State GND
10nF
R1 40MHz(±10ppm)

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10K(NC) GND GND

TBD

TBD
C12
GPIO46

GND

GND
GPIO45 Figure 7: Schematic for the Oscillator
U0RXD
R3 499 U0TXD

VDD33

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GPIO42

GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CHIP_PU

LNA_IN
GPIO41
Notice: GPIO40
GPIO39
Defects in the GPIO38
manufacturing of crystal and oscillators (for example, large frequency deviation of more than ±10 ppm,
unstable performance within operating temperature range, etc) may lead to the malfunction of ESP32-S3, resulting in a
decrease
C10 of the RF performance.

14
13
12
11
10
VDD33

9
8
7
6
5
4
3
2
1
0.1uF
4

C
U1
0.1uF

E
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CHIP_PU
VDD3P3
VDD3P3
LNA_IN
C15

GND
GND

2.4.2 RTC (optional) GN

42 GPIO37
ID
GPIO37 41 ESP32-S3 supports
GPIO36an external 32.768 kHz crystal or an external15
signal (e.g., an oscillator) to act as the RTC
GPIO36
GPIO35
40 GPIO35
sleep clock. Figure the external 32.76816kHzGPIO10
8 shows the schematic forVDD_SPI crystal. VDD
GPIO34
39
38
GPIO34
GPIO33
17 GPIO11 VDD
GPIO33 37 GPIO47 18 GPIO12 XTAL_
SPICLK_P 19 GPIO13 XTAL_
GND

36 GPIO48 C17 TBD

PICLK_N
20 GPIO14 GPIO4
R12

35 R16 0 SPID
VDD

SPID
NF

21 VDD3P3_RTC GPIO4
1

34 R15 0 SPIQ SPICS0 1 5

GPIO15 SPID
SPIQ /CS
X1 DI
22 XTAL_32K_P U0RX
33 R10 0 SPICLK
SPICLK 32 SPICS0 SPICLK 6 GPIO16
2 SPIQ XTAL_32K_N
32.768kHz U0TX
TBD

SPICS0 31 R14 0 SPIWP CLK DO 23

2

SPIWP 24 GPIO17 MTM

GND

30 R13 0 SPIHD SPIHD 7 3 SPIWP

GND

SPIHD
VDD_SPI
29 /HOLD
C18 TBD
/WP
25 GPIO18 MTD
26 GPIO19 B VDD3P3_CP
U2 FLASH-3V3
27 GPIO20 MTDO
4

C13 C14 VDD_SPI GPIO21(RTC) MTC

Figure 8: Schematic for the External
28 Crystal
SPICS1 GPIO3
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0.1uF 1uF GND

ESP32-S3R8
ESP32-S3R2
ESP32-S3

SPICLK_N
SPICLK_P
VDD_SPI

SP32-S3
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
SPICS0
SPICLK
SPIWP
SPIHD

SP32-S3R2 GND
Notice:GND
SPIQ
SPID
3

SP32-S3R8
• Please note the requirements for the 32.768 kHz crystal.
– Equivalent series resistance (ESR) ⩽ 70 kΩ.
29
30
31
32
33
34
35
36
37
38
39
40
41
42

– Load capacitance at both ends should be configured according to the crystal’s specification.
GND

R13
R14

R10
R15
R16

GND

• The parallel resistor R is used for biasing the crystal circuit (5 MΩ < R ⩽ 10 MΩ). In general, you do not need to
0.1uF

C13

populate the resistor.

• If the RTC source is not required, then the pins for the external 32.768 kHz crystal can be used as other GPIOs.
GND

0
0

0
0
0

A
1uF

C14 VDD_SPI

SPIHD
SPIWP
SPICS0
SPICLK
SPIQ
SPID
GPIO48
GPIO47
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37

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SPIHD

SPICLK

SPICS0

3 2 1
 C3 C2
2 Schematic Checklist

0
1uF 10nF

VDD33
2.5 RF GND GND GND

R4
L1 0
C
A π-type matching network is essential for antenna matching in the circuit design. CLC structure is
C6 C7 C8 C9
recommended for the matching network. It is also recommended to add an LC filter circuit at the π-type

57

56
55
54
53
52
51
50
49
48
47
46
45
10uF 1uF 0.1uF TBD
matching network side to suppress secondary harmonics. The parameters of the components in the matching

GND

VDDA
VDDA
XTAL_P
XTAL_N
GPIO46
GPIO45
U0RXD
U0TXD
MTMS

MTDO
VDD3P3_CPU
MTDI
network are subject to the actual antenna and PCB layout. Figure 9 shows the RF matching schematic.
GND GND GND GND

ANT1
1 RF_ANT L2 TBD LNA_IN 1
2 2 LNA_IN
3 VDD3P3
L3 C11 C12
PCB_ANT CHIP_PU 4 VDD3P3

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TBD TBD TBD GPIO0 5 CHIP_PU
GPIO1 6 GPIO0
GPIO2 7 GPIO1
GND GND GND GPIO3 8 GPIO2

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GPIO4 9 GPIO3
C5 GPIO4
GPIO5 10
GPIO6 11 GPIO5
TBD GPIO6
B GPIO7 12
GPIO8 13 GPIO7
GPIO9 14 GPIO8
GND

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VDD3P3_RTC
GPIO9

XTAL_32K_N
XTAL_32K_P
The values of C11, L2 and C12

GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO17
GPIO18
GPIO19
GPIO20
vary with the actual PCB board.
NC: No component.
Figure 9: Schematic for RF Matching
U1

15
16
17
18
19
20
21
22
23
24
25
26
VDD33
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2.6 UART
C15
You need to connect a 499 Ω series resistor to the U0TXD line in order to suppress the 80 MHz harmonics.

GPIO10
GPIO11
GPIO12
GPIO12
GPIO14

GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
ID
0.1uF

GND
2.7A ADC
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It is recommended to add a 0.1 µF filter capacitor to a pad when using the ADC function. ADC1 is
recommended for use.

2.8 Strapping Pins

Note:
5 4
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The content below is excerpted from Section Strapping Pins in ESP32-S3 Series Datasheet.

ESP32-S3 has four strapping pins:

• GPIO0

• GPIO45

• GPIO46

• GPIO3

Software can read the values of corresponding bits from register “GPIO_STRAPPING”.

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2 Schematic Checklist

During the chip’s system reset (power-on-reset, RTC watchdog reset, brownout reset, analog super watchdog
reset, and crystal clock glitch detection reset), the latches of the strapping pins sample the voltage level as
strapping bits of “0” or “1”, and hold these bits until the chip is powered down or shut down.

GPIO0, GPIO45 and GPIO46 are connected to the chip’s internal weak pull-up/pull-down during the chip reset.
Consequently, if they are unconnected or the connected external circuit is high-impedance, the internal weak
pull-up/pull-down will determine the default input level of these strapping pins.

GPIO3 is floating by default. Its strapping value can be configured to determine the source of the JTAG signal
inside the CPU, as shown in Table 4. In this case, the strapping value is controlled by the external circuit that
cannot be in a high impedance state. Table 3 shows more configuration combinations of

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EFUSE_DIS_USB_JTAG, EFUSE_DIS_PAD_JTAG, and EFUSE_STRAP_JTAG_SEL that determine the JTAG
signal source.

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Table 3: JTAG Signal Source Selection

EFUSE_STRAP_JTAG_SEL EFUSE_DIS_USB_JTAG EFUSE_DIS_PAD_JTAG JTAG Signal Source

1 0 0 Refer to Table 4

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0 0 0 USB Serial/JTAG controller
don’t care 0 1 USB Serial/JTAG controller
don’t care 1 0 On-chip JTAG pins
don’t care 1 1 N/A
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To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-S3.

After reset, the strapping pins work as normal-function pins.

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Refer to Table 4 for a detailed configuration of the strapping pins.

Table 4: Strapping Pins

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VDD_SPI Voltage 1
Pin Default 3.3 V 1.8 V
GPIO45 Pull-down 0 1
2
Booting Mode
Pin Default SPI Boot Download Boot
GPIO0 Pull-up 1 0
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GPIO46 Pull-down Don’t care 0

Enabling/Disabling ROM Messages Print During Booting 3 4

Pin Default Enabled Disabled

GPIO46 Pull-down See the fourth note See the fourth note
JTAG Signal Selection
EFUSE_DIS_USB_JTAG = 0, EFUSE_DIS_PAD_JTAG = 0,
Pin Default
EFUSE_STRAP_JTAG_SEL=1
0: JTAG signal from on-chip JTAG pins
GPIO3 N/A
1: JTAG signal from USB Serial/JTAG controller

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Note:

1. VDD_SPI voltage is determined either by the strapping value of GPIO45 or by VDD_SPI_TIEH. When
EFUSE_VDD_SPI_FORCE is 0, VDD_SPI voltage is determined by the strapping value of GPIO45; when
EFUSE_VDD_SPI_FORCE is 1, VDD_SPI voltage is determined by VDD_SPI_TIEH.

2. The strapping combination of GPIO46 = 1 and GPIO0 = 0 is invalid and will trigger unexpected behavior.

3. ROM boot messages can be printed over U0TXD (by default) or GPIO17 (U1TXD), depending on the eFuse bit
EFUSE_UART_PRINT_CHANNEL.

4. When both EFUSE_DIS_USB_SERIAL_JTAG and EFUSE_DIS_USB_OTG are 0, ROM boot messages will be printed
to the USB Serial/JTAG controller. Otherwise, the messages will be printed to UART, controlled by GPIO46 and

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EFUSE_UART_PRINT_CONTROL. Specifically, when EFUSE_UART_PRINT_CONTROL value is:
0, print is normal during boot and not controlled by GPIO46.
1 and GPIO46 is 0, print is normal during boot; but if GPIO46 is 1, print is disabled.

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2 and GPIO46 is 0, print is disabled; but if GPIO46 is 1, print is normal.
3, print is disabled and not controlled by GPIO46.

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Figure 10 shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high.
Details about the parameters are listed in Table 5.

tSU tHD
E
VIL_nRST
CHIP_PU
ID

VIH
NF

Strapping pin

Figure 10: Setup and Hold Times for the Strapping Pin
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Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pin

Parameter Description Min (µs)

tSU Setup time before CHIP_PU goes from low to high 0
tHD Hold time after CHIP_PU goes high 3

2.9 USB
ESP32-S3 has a full-speed USB On-The-Go (OTG) peripheral with integrated transceivers. The USB peripheral is
compliant with the USB 1.1 specification. GPIO19 and GPIO20 can be used as D- and D + of USB respectively.
It is recommended to populate zero-ohm series resistors between the mentioned pins and the USB connector.
Also reserve a footrpint for a capacitor to ground on each trace.

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2 Schematic Checklist

ESP32-S3 also integrates a USB Serial/JTAG controller that supports USB 2.0 full-speed device.

2.10 Touch Sensor

When using the touch function, it is recommended to populate a zero-ohm series resistor at the chip side to
reduce the coupling noise and interference on the line, and to strengthen the ESD protection. The recommended
resistance is from 470 Ω to 2 kΩ, preferably 510 Ω. The specific value also depends on the actual test results of
the product.

The ESP32-S3 touch sensor has a waterproof design and digital filtering function. Note that only GPIO14
(TOUCH14) can drive the shield electrode.

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ID
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3 PCB Layout Design

3 PCB Layout Design

This chapter introduces the key points of how to design an ESP32-S3 PCB layout using the
ESP32-S3-WROOM-1 module as an example.

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Figure 11: ESP32­S3 PCB Layout

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3.1 General Principles of PCB Layout

It is recommended to use a four-layer PCB design:

• Layer 1 (TOP): Signal traces and components

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• Layer 2 (GND): No signal traces here to ensure a complete GND plane

• Layer 3 (POWER): GND plane should be applied to better isolate the RF and crystal oscillator parts. It is
acceptable to route signal traces on this layer, provided that there is a complete GND plane under the RF
and crystal oscillator.

• Layer 4 (BOTTOM): Route power traces here. It is not recommended to place any components on this layer.

A two-layer PCB design can also be used:

• Layer 1 (TOP): Signal traces and components

• Layer 2 (BOTTOM): Do not place any components on this layer and keep traces to a minimum. Ideally, it
should be a complete GND plane.

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3 PCB Layout Design

3.2 Positioning a Module on a Base Board

If module-on-board design is adopted, attention should be paid while positioning the module on the base board.
The interference of the base board on the module’s antenna performance should be minimized.

The module should be placed as close to the edge of the base board as possible. The side of the module
carrying the on-board PCB antenna should be placed outside the base board whenever possible. In addition, the
feed point of the antenna should be closest to the board. In the following example figures, positions with mark
✓are strongly recommended, while positions without a mark are not recommended.

1 2 3

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Feed Point

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Base board

5 4
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Figure 12: Placement of ESP32­S3 Modules on Base Board (antenna feed point on the right)
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1 2 3
Feed Point
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Base board

5 4
Figure 13: Placement of ESP32­S3 Modules on Base Board (antenna feed point on the left)

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3 PCB Layout Design

If the positions recommended are not feasible, please make sure that the module is not covered by any metal
shell. Besides, the clearance area outside the antenna should be kept clean (namely no copper, routing,
components on it) and as large as possible, as shown in Figure 14. If there is base board under the antenna area,
it is recommended to cut it off to minimize its impact on the antenna.

Unit: mm
: Clearance Area

Min15 Max 2

Max 1
6

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Base board
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ID
Figure 14: Keepout Zone for ESP32­S3 Module’s Antenna on the Base Board

If the product is designed with a layout that does not meet the above rules, it is necessary to test the throughput
and communication distance of the whole product to ensure product performance. When designing an end
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product, attention should be paid to the interference caused by the housing of the antenna and it is
recommended to carry out RF verification.
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3.3 Power Supply

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Figure 15: ESP32­S3 Power Traces in a Four­layer PCB Design

• Four-layer PCB design is recommended over a two-layer design. The power traces should be routed on
Layer 4 (BOTTOM) whenever possible. Vias are required for the power traces to go through the layers and
ID
get connected to the pins on the top layer. There should be at least two vias if the main power traces need
to cross layers. The drill diameter on other power traces should be no smaller than the width of the power
traces.

• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure 15. The width of the main
NF

power traces should be no less than 25 mil. The width of the power traces for VDD3P3 pins should be no
less than 20 mil. Recommended width of other power traces is 10 mil.

• The ESD protection diode is placed next to the power port (circled in red in the top left quarter of Figure 15).
The power trace should have a 10 µF capacitor on its way to the chip, to be used in conjunction with a 0.1
µF capacitor. Then the power traces are divided into two ways from here and form a star-shape topology,
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thus reducing the coupling between different power pins. Note that all decoupling capacitors should be
placed close to the power pin, and ground vias should be added close to the capacitor’s ground pin to
ensure a short return path.

• As shown in Figure 16, it is recommended to connect the capacitor to ground in the LC filter circuit near
VDD3P3 pins to the fourth layer through a via, and maintain a keep-out area on other layers.

• The power trace begins at the power entrance and reaches VDD3P3. It is required to add GND isolation
between this power trace and the GPIO traces on the left, and place vias whenever possible.

• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.

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3 PCB Layout Design

Note:
If you need to add a thermal pad EPAD under the chip on the bottom of the module, it is recommended to employ a
nine-grid on the EPAD, cover the gaps with ink, and place ground vias in the gaps, as shown in Figure 16. This can avoid
tin leakage when soldering the module EPAD to the substrate.

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Figure 16: ESP32­S3 Analog Power Traces in a Four­layer PCB Design

3.4 Crystal Oscillator

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Figure 17 shows the reference design of the crystal oscillator. In addition, the following should be noted:

• The crystal oscillator should be placed far from the clock pin to avoid the interference on the chip. The gap
should be at least 2.0 mm. It is good practice to add high-density ground via stitching around the clock
trace for better isolation.

• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.
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• The external regulating capacitor should be placed on the near left or right side of the crystal oscillator, and
at the end of the clock trace whenever possible, to make sure the ground pad of the capacitor is close to
that of the crystal oscillator.

• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The vias on the power traces on both sides of the crystal clock trace
should be placed as far away from the clock trace as possible, and the two sides of the clock trace should
be surrounded by grounding copper.

• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example large inductance component, and ensure that there is a clean large-area
ground plane around the crystal oscillator.

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3.5 RF
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Figure 17: ESP32­S3 Crystal Oscillator Layout

The RF trace is routed as shown highlighted in pink in Figure 18.

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Figure 18: ESP32­S3 RF Layout in a Four­layer PCB Design

• The RF trace should have 50 Ω single-ended characteristic impedance. The reference plane is the second
layer. A π-type matching circuit and an LC filter circuit should be added on the RF trace and placed close
to the chip, in a zigzag.

• For designing the RF trace at 50 Ω single-ended impedance, please refer to the PCB stack-up design
shown in Figure 19.

• The RF trace should have consistent width and not branch out. It should be as short as possible with
dense ground vias around for inteference shielding.

• The RF trace should be routed on the outer layer without vias, i.e., should not cross layers. The RF trace
should be routed at a 135° angle, or with circular arcs if trace bends are required.

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• Please add a stub between the ground and the capacitors near the chip to suppress second harmonics. It
is preferable to keep the stub length 15 mil, and determine the stub width according to the number of PCB
layers, so that the characteristic impedance of the stub is 100 Ω ± 10%. In addition, please connect the
stub via to the third layer, and maintain a keep-out area on the first and second layers. The trace
highlighted in Figure 20 is the stub. Note that a stub is not required for package types above 0201.

• The ground plane on the adjacent layer needs to be complete. Do not route any traces under the RF trace
whenever possible.

• There should be no high-frequency signal traces routed close to the RF trace. The RF antenna should be
placed away from high-frequency components, such as crystals, DDR, high-frequency clocks, etc. In

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addition, the USB port, USB-to-serial chip, UART signal lines (including traces, vias, test points, header
pins, etc.) must be as far away from the antenna as possible. The UART signal line should be surrounded
by ground copper and ground vias.

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Thickness (mm) Impedance (Ohm) Gap (mil) Width (mil) Gap (mil)

- 50 12.2 12.6 12.2

NT
Base copper Thickness DK
Stack up Material
(oz) (mil)

SM 0.4 4

L1_Top Finished copper 1 oz 0.33 0.8

PP 7628 TG150 RC50% 8 4.39

L2_Gnd 1 1.2
E
Core Core Adjustable 4.43
L3_Power 1 1.2

PP 7628 TG150 RC50% 8 4.39

ID
L4_Bottom Finished copper 1 oz 0.33 0.8

SM 0.4 4

Figure 19: ESP32­S3 PCB Stack up Design

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Figure 20: ESP32­S3 Stub in a Four­layer PCB Design

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3.6 Flash and PSRAM

Place the zero-ohm series resistors on the SPI lines closer to the chip. Route the SPI traces on the inner layer
(e.g., the third layer) whenever possible. Add ground copper and ground vias around the clock and data traces of
SPI separately. Octal SPI traces should have matching lengths.

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Figure 21: ESP32­S3 Flash Layout

3.7 UART
The series resistor on the U0TXD trace needs to be placed close to the chip and away from the crystal. The
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U0TXD and U0RXD traces on the top layer should be as short as possible, surrounded by ground copper and
ground vias.
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3.8 USB
Place the RC circuit on the USB traces closer to the chip. Please use differential pairs and route them in parallel
at equal lengths. Make sure there is a complete reference ground plane and surround the USB traces with
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ground copper.

3.9 Touch Sensor

ESP32-S3 offers up to 14 capacitive IOs that detect changes in capacitance on touch sensors due to finger
contact or proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It
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allows to use touch pads with smaller area to implement the touch detection function. You can also use the
touch panel array to detect a larger area or more test points.

Figure 22 depicts a typical touch sensor application.

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3 PCB Layout Design

Protective cover
Substrate

ESP CHIP

C
Electrode

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Figure 22: A Typical Touch Sensor Application

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In order to prevent capacitive coupling and other electrical interference to the sensitivity of the touch sensor
system, the following factors should be taken into account.

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3.9.1 Electrode Pattern
The proper size and shape of an electrode improves system sensitivity. Round, oval, or shapes similar to a
human fingertip are commonly applied. Large size or irregular shape might lead to incorrect responses from
nearby electrodes.
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Figure 23: Electrode Pattern Requirements

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Note:
The examples illustrated in Figure 23 are not of actual scale. It is suggested to use a human fingertip as reference.

3.9.2 PCB Layout

Figure 24 illustrates the general guidelines to routing traces.

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Figure 24: Sensor Track Routing Requirements

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Specifically,

• The trace should be as short as possible and no longer than 300 mm.

• The trace width (W) can not be larger than 0.18 mm (7 mil).

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• The alignment angle (R) should not be less than 90°.

• The trace-to-ground gap (S) should be in the range of 0.5 mm to 1 mm.

• The electrode diameter (D) should be in the range of 8 mm to 15 mm.

• Hatched ground should be added around the electrodes and traces.

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• The traces should be isolated well and routed away from that of the antenna.
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3.9.3 Waterproof and Proximity Sensing Design
ESP32-S3 touch sensor has a waterproof design and features proximity sensor function. Figure 25 shows an
example layout of a waterproof and proximity sensing design.
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Touch sensor (TOUCH1 ~ TOUCH14)

Protective sensor (TOUCH1 ~ TOUCH14)

Shied electrode

Figure 25: Shield Electrode and Protective Sensor

Note the following guidelines to better implement the waterproof and proximity sensing design:

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• The recommended width of the shield electrode width is 2 cm.

• Employ a grid on the top layer with a trace width of 7 mil and a grid width of 45 mil (25% fill). The filled grid
is connected to the driver shield signal.

• Employ a grid on the bottom layer with a trace width of 7 mil and a grid width of 70 mil (17% fill). The filled
grid is connected to the driver shield signal.

• The protective sensor should be in a rectangle shape with curved edges and surround all other sensors.

• The recommended width of the protective sensor is 2 mm.

• The recommended gap between the protective sensor and shield sensor is 1 mm.

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• The sensing distance of the proximity sensor is directly proportional to the area of the proximity sensor.
However, increasing the sensing area will introduce more noise. Actual testing is needed for optimized

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performance.

• It is recommended that the shape of the proximity sensor is a closed loop. The recommended width is 1.5
mm.

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Note:
For more details on the hardware design of ESP32-S3 touch sensor, please refer to ESP32-S3 Touch Sensor Application Note.

3.10 Typical Layout Problems and Solutions

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3.10.1 Q: The current ripple is not large, but the TX performance of RF is rather poor.
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Analysis:

The current ripple has a strong impact on the RF TX performance. It should be noted that the ripple must be
tested when ESP32-S3 is in the normal working mode. The ripple increases when the power gets high in a
different mode.
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Generally, the peak-to-peak value of the ripple should be <80 mV when ESP32-S3 sends MCS7@11n packets,
and <120 mV when ESP32-S3 sends 11m@11b packets.

Solution:
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Add a 10 µF filter capacitor to the branch of the power trace (the branch powering the chip’s analog power pin).
The 10 µF capacitor should be as close to the analog power pin as possible for small and stable current
ripples.

3.10.2 Q: The power ripple is small, but RF TX performance is poor.

Analysis:

The RF TX performance can be affected not only by power ripples, but also by the crystal oscillator itself. Poor
quality and big frequency offsets of the crystal oscillator decrease the RF TX performance. The crystal oscillator
clock may be corrupted by other interfering signals, such as high-speed output or input signals. In addition,
high-frequency signal traces, such as the SDIO traces and UART traces under the crystal oscillator, could also

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3 PCB Layout Design

result in the malfunction of the crystal oscillator. Besides, sensitive components or radiation components, such
as inductors and antennas, may also decrease the RF performance.

Solution:

This problem is caused by improper layout and can be solved by re-layout. Please see Section 3.4 for
details.

3.10.3 Q: When ESP32­S3 sends data packages, the power value is much higher or
lower than the target power value, and the EVM is relatively poor.

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Analysis:

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The disparity between the tested value and the target value may be due to signal reflection caused by the
impedance mismatch on the transmission line connecting the RF pin and the antenna. Besides, the impedance
mismatch will affect the working state of the internal PA, making the PA prematurely access the saturated region
in an abnormal way. The EVM becomes poor as the signal distortion happens.

Solution:

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Match the antenna’s impedance with the π-type circuit on the RF trace, so that impedance of the antenna as
seen from the RF pin matches closely with that of the chip. This reduces reflections to the minimum.
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3.10.4 Q: TX performance is not bad, but the RX sensitivity is low.
Analysis:
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Good TX performance indicates proper RF impedance matching. Poor RX sensitivity may result from external
coupling to the antenna. For instance, the crystal oscillator signal harmonics could couple to the antenna. If the
TX and RX traces of UART cross over with RF trace, then, they will affect the RX performance, as well. If there are
many high-frequency interference sources on the board, signal integrity should be considered.
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Solution:

Keep the antenna away from crystal oscillators. Do not route high-frequency signal traces close to the RF trace.
Please see Section 3.5 for details.
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4 Hardware Development

4 Hardware Development

4.1 ESP32­S3 Modules

For a list of ESP32-S3 modules please check Modules section of Espressif website.

To review module reference designs please check Documentation section of Espressif website.

Notes on Using Modules

• The module uses one single pin as the power supply pin. You can connect the module to a 3.3 V power

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supply that can drive at least 500 mA output current. The 3.3 V power supply works both for the analog
circuit and the digital circuit.

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• The EN pin is used for enabling the module. Set the EN pin high for normal working mode. There is no RC
delay circuit on the module. It is recommended to add an external RC delay circuit to the module. For
details please refer to Section 2.2.

• Lead the GND, RXD, TXD pins out and connect them to a USB-to-UART converter for firmware download,

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log-printing and communication.

By default, the initial firmware has already been downloaded in the flash. If you need to download different
firmware, please follow the steps below:

1. Set the module to UART Download mode by pulling IO0 (pulled up by default) and IO46 (pulled down by
default) low.
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2. Power on the module and check whether the module has entered UART Download mode via serial port.

3. Download your firmware into flash using Flash Download Tool.

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4. After firmware has been downloaded, pull IO0 high to enter SPI Boot mode.

5. Power on the module again. The chip will read and execute the new firmware during initialization.
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Notice:
• During the whole process, you can check the status of the chip with the log printed through UART. If the firmware
cannot be downloaded or executed, you can check if the working mode is normal during the chip initialization by
looking at the log.

• The serial tool cannot be used for both the log-print and flash-download tools simultaneously.
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4.2 ESP32­S3 Development Boards

For a list of the latest designs of ESP32-S3 boards please check Development Boards section of Espressif
website.

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5 Related Documentation and Resources

5 Related Documentation and Resources

Related Documentation
• ESP32-S3 Series Datasheet – Specifications of the ESP32-S3 hardware.
• ESP32-S3 Technical Reference Manual – Detailed information on how to use the ESP32-S3 memory and peripherals.
• Certificates
http://espressif.com/en/support/documents/certificates
• Documentation Updates and Update Notification Subscription
http://espressif.com/en/support/download/documents

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Developer Zone

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• ESP-IDF and other development frameworks on GitHub.
http://github.com/espressif
• ESP32 BBS Forum – Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions,
share knowledge, explore ideas, and help solve problems with fellow engineers.

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http://esp32.com/
• The ESP Journal – Best Practices, Articles, and Notes from Espressif folks.
http://blog.espressif.com/
• See the tabs SDKs and Demos, Apps, Tools, AT Firmware.
http://espressif.com/en/support/download/sdks-demos
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Products
• ESP32-S3 Series SoCs – Browse through all ESP32-S3 SoCs.
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http://espressif.com/en/products/socs?id=ESP32-S3
• ESP32-S3 Series Modules – Browse through all ESP32-S3-based modules.
http://espressif.com/en/products/modules?id=ESP32-S3
• ESP32-S3 Series DevKits – Browse through all ESP32-S3-based devkits.
http://espressif.com/en/products/devkits?id=ESP32-S3
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• ESP Product Selector – Find an Espressif hardware product suitable for your needs by comparing or applying filters.
http://products.espressif.com/#/product-selector?language=en

Contact Us
• See the tabs Sales Questions, Technical Enquiries, Circuit Schematic & PCB Design Review, Get Samples
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(Online stores), Become Our Supplier, Comments & Suggestions.

http://espressif.com/en/contact-us/sales-questions

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Glossary

Glossary

CLC Capacitor-Inductor-Capacitor
DDR Double-Data Rate
ESD Electrostatic Discharge
GND Ground
LC Inductor-Capacitor
PA Power Amplifier
RC Resistor-Capacitor

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RTC Real-Time Clock
RX Receive

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SiP System-in-Package
TX Transmit
Zero-ohm resistor A zero-ohm resistor is a placeholder on the circuit so that another higher ohm
resistor can replace it, depending on design cases.

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Revision History

Revision History

Date Version Release Notes

2021-09-30 v1.0 First release

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Espressif Systems 32 ESP32-S3 Series Hardware Design Guidelines v1.0

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WARRANTIES TO ITS AUTHENTICITY AND ACCURACY.
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INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
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