‫جمهورية العراق‬

‫وزارة التعليم العالي والبحث العلمي‬

‫جامعة بغداد‪/‬كلية العلوم‬
‫قسم الحاسبات‬

‫‪Interrupt‬‬

‫تقرير مقدم‬
‫الى قسم الحاسبات من متطلبات للحصول على درجة النهائي في مادة‬
‫معمارية الحاسوب‬
‫باشراف‬
‫‪Dr. Assmaa A. Fahad.‬‬
‫اعداد‬
‫اسيا عكاب يوسف زغير‬

‫‪2020\2019‬‬
 Introduction

Normal execution of a given software application is contained

within the bounds of one program, or
instruction stream. Such execution is provable, as well as
traceable. However, system designers and
implementer also have to understand how breaks in program
flow occur, and how they may affect the
running program. Flow breaks fall into two general classes:

• Exceptions and traps are predictable, synchronous breaks in

program flow. They are synchronous because they are caused
by the execution of certain instructions (divide by zero; illegal
memory access; software interrupt). Exceptions and traps
trigger execution of instructions that are not part of the
program, but perform work on behalf of it.
• Interrupts are asynchronous breaks in program flow that
occur as a result of events outside the running program. They
are usually hardware related, stemming from events such as a
button press, timer expiration, or completion of a data transfer.
We can see from these examples that interrupt conditions are
independent of particular instructions; they can happen at any
time. Interrupts trigger execution of instructions that perform
work on behalf of the system, but not
necessarily the current program.
Interrupts

Interrupt is a signal emitted by hardware or software when a

process or an event needs immediate attention. It alerts the
processor to a high priority process requiring interruption of
the current working process. In I/O devices one of the bus
control lines is dedicated for this purpose and is called the
Interrupt Service Routine (ISR).

When a device raises an interrupt at lets say process i, the

processor first completes the execution of instruction i. Then it
loads the Program Counter (PC) with the address of the first
instruction of the ISR. Before loading the Program Counter
with the address, the address of the interrupted instruction is
moved to a temporary location. Therefore, after handling the
interrupt the processor can continue with process i+1.

While the processor is handling the interrupts, it must inform

the device that its request has been recognized so that it stops
sending the interrupt request signal. Also, saving the registers
so that the interrupted process can be restored in the future,
increases the delay between the time an interrupt is received
and the start of the execution of the ISR. This is called Interrupt
Latency
Types of Interrupts

• External – Generated by an I/O device

• Internal – Exception within a program
• Program Generated – Used to transfer control to the operating system

1-External Interrupts
• I/O devices tell the CPU that an I/O request has completed by sending
an interrupt signal to the processor.
• I/O errors may also generate an interrupt.
• Most computers have a timer which interrupts the CPU every so many
Milliseconds.
2-Internal Interrupts
• When the hardware detects that the program is doing something
wrong, it will usually generate an interrupt.
– Arithmetic error
- Invalid Instruction
– Addressing error - Hardware malfunction
– Page fault
- Debugging
• A Page Fault interrupt is not the result of a program error, but it does
require the operating system to get control.
• Internal interrupts are sometimes called exceptions
• Internal interrupts are signaled during an instruction.
• Execution of an instruction can raise an arithmetic error interrupt.
• Page faults can be created during the instruction fetch, operand fetch
or operand store or all of the above.
.
Interrupt Service Routines

• When an interrupt occurs, execution starts in an interrupt

service routine (ISR) or interrupt handler.
• The ISR is almost always in the OS.
• The interrupt service routine processes the event or queues a
program to process the event.
• After an external interrupt, the service routine will return to
the program.
ISR Entry Point
• It is possible for all interrupt service routines to start at the
same location. The software can determine what kind of
interrupt.
• The hardware can assist by using the interrupt type as an
index into a table of ISR addresses.
• Each interrupt may have a different ISR entry point or classes
of interrupts may have a common entry point.
Hardware

When a device asserts its interrupt request signal, it must be

processed in an orderly fashion. All CPU,
and many devices, have some mechanism for
enabling/disabling interrupt recognition and processing:
• At the device level, there is usually an interrupt control
register with bits to enable or disable the interrupts that device
can generate.
• At the CPU level, a global mechanism functions to
inhibit/enable (often called the global interrupt enable)
recognition of interrupts.
• Systems with multiple interrupt inputs provide the ability to
mask (inhibit) interrupt requests individually and/or on a
priority basis. This capability may be built into the CPU or
provided by an external interrupt controller. Typically, there
are one or more interrupt mask registers, with individual bits
allowing or inhibiting individual interrupt sources.
• There is often also one non-maskable interrupt input to the
CPU that is used to signal important conditions such as
pending power fail, reset button pressed, or watchdog timer
expiration.
 Figure 1 shows an interrupt controller, two devices capable of
producing interrupts, a processor, and the interrupt-related paths
among them. The interrupt controller multiplexes multiple input
requests into one output. It shows which inputs are active and
allows individual inputs to be masked. Alternatively, it prioritizes
the inputs, shows the highest active input, and provides a mask for
inputs below a given level. The processor status register has a global
interrupt enable flag bit. In addition, a watchdog timer is connected
to the non-maskable interrupt input.

The interrupt software associated with a specific device is known as

its interrupt service routine (ISR), or handler.
Sequence of events involved in handling an IRQ:

Devices raise an IRQ.

Processor interrupts the program currently being executed.

Device is informed that its request has been recognized and

the device deactivates the request signal.

The requested action is performed.

Interrupt is enabled and the interrupted program is resumed.

Handling Multiple Devices:

When more than one device raises an interrupt request signal,

then additional information is needed to decide which which
device to be considered first. The following methods are used
to decide which device to select: Polling, Vectored Interrupts,
and Interrupt Nesting. These are explained as following below
1-Polling:
In polling, the first device encountered with with IRQ bit set is
the device that is to be serviced first. Appropriate ISR is called
to service the same. It is easy to implement but a lot of time is
wasted by interrogating the IRQ bit of all devices.
2-Vectored Interrupts:
In vectored interrupts, a device requesting an interrupt
identifies itself directly by sending a special code to the
processor over the bus. This enables the processor to identify
the device that generated the interrupt. The special code can
be the starting address of the ISR or where the ISR is located in
memory, and is called the interrupt vector.
3-Interrupt Nesting:
In this method, I/O device is organized in a priority structure.
Therefore, interrupt request from a higher priority device is
recognized where as request from a lower priority device is
not. To implement this each process/device (even the
processor). Processor accepts interrupts only from
devices/processes having priority more than it.
Software

Some older CPU routed all interrupts to a single ISR. Upon

recognizing an interrupt, the CPU saved

some state information and started execution at a fixed location.

The ISR at that location had to poll the

devices in priority order to determine which one required

service. However, the basic process of

interrupt handling is the same as in the more complex case.

Most modern CPU use the same general mechanism for

processing exceptions, traps, and interrupts:

an interrupt vector table. Some CPU vector tables contain only

the address of the code to be executed. In most cases, a specific
ISR is responsible for servicing each interrupting device and
acknowledging,

clearing, and rearming its interrupt; in some cases, servicing

the device (for example, reading data from

a serial port) automatically clears and rearms the interrupt.

Interrupts may occur at any time, but the CPU does not instantly
recognize and process them immediately. First, the CPU will not
recognize a new interrupt while interrupts are disabled. Second,
the CPU must, upon recognition, stop fetching new instructions
and complete those still in progress. Because the interrupt is
totally unrelated to the running program it interrupts, the CPU
and ISR work together to save and restore the full state of the
interrupted program (stack, flags, registers, and so on). The
running program is not affected by the interruption, although it
takes longer to execute. The hardware and software flow for a
timer interrupt is shown in Figure 2.
Many interrupt controllers provide a means of prioritizing
interrupt sources, so that, in the event of multiple interrupts
occurring at (approximately) the same time, the more time-
critical ones are processed first. These same systems usually also
provide for prioritized interrupt handling, a means by which a
higher-priority interrupt can interrupt the processing of a
lower-priority interrupt. This is called interrupt nesting. In
general, the ISR should only take care of the time-critical
portion of the processing, then, depending on the complexity of
the system, it may set a flag for the main loop, or use an
operating system call to awaken a task to perform the non-
time-critical portion.

end
 source

www.embedded.com

www.geeksforgeeks.org

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