ISSN 2321 3361 © 2019 IJESC

Research Article Volume 9 Issue No. 6

An Approach to Physical Design of 28nm Technology Based

Processor Chip using IC Compiler
Tanmoy Saha1, Revathi. K2
M. Tech Student1, Assistant Professor2
Department of Electronic & Communication
S. E. A. College of Engineering, Bangalore, India
Abstract:
With the advancement of modern technology the world has come into System-On-Chip (SOC) based automation systems. Modern
technology has abandoned analog bulky system occupying large areas. Based on CMOS logic, technology is growing but at the
same time area, cost, power and efficiency trade-off of the system has become more concerned matter. In 2008, when transistor
based processor become commercially available, it has become more commonplace for semiconductor fabrication through
generation of 65nm processes. Each and every system has limitations. Now-a-days works are progressing on 5 nm technology.
The sheer purpose of this project is to develop a design of chip using 28nm library of MOSFET semiconductors using physical
design flow technique. Here 28nm refers to channel-length of gate of MOSFET. All the physical design has been simulated on IC
Compiler tool, founded by Synopsys. The project has been demonstrated as a single voltage and single row with double spacing
of macros. But it can also be demonstrated as Multi Voltage with double row single spacing, which can deem as cost beneficiary.
Large fabrication companies use Si02 dies for fabrication. Physical design uses technology library such as 60nm, 45nm, 28nm etc
which are actually provided by most fabrication houses according to their requirement.
Keywords: 28 nm Library, ASIC DESIGN, RTL net list, Power Planning, Cell Density, Pin Density, Routing, DRC Violation
GDSII.

I. INTRODUCTION conducted by some photo-lithographic process and sometimes

in hand with very care in wafer fabrication houses.
Semiconductor is usually a chemical compound element
conducts electricity for few rules, thus making it for III. PHYSICAL DESIGN
controlling of current. There is a difference in substances
between conductors and insulators. Semiconductors has An ASIC (Application Specific Integrated Circuit) contains the
intermediate sized band gap that actually acts as insulators in functional properties of hundred thousand gates. There are
absolute temperature (-273 K). Obviously, Insulators are other than conventional IC’s and are designed to play for
materials which have large band gap. Conductors are having certain amount of application. It is a digital or mixed-signal
the overlapped, the valence and conduction bands, so they circuit. The foremost step of the ASIC Design Flow is the
may not have a band gap. Semiconductors have band gap of 1. specification for what provides information about design after
Elements of group IV, as – Silicon (Si), Germanium (Ge), and which implementation of circuit begins. Customer provides all
Gallium Arsenide (GaAs) are used as semiconductors. Some the data. Engineers after getting all the data, the design phase
compounds of these are also used as semiconductors. starts. After this RTL Level Design stage begins. This stage is
Semiconductors are made up of covalent bonds. Making technology independent also known as Architectural Design.
crystalline structure, semiconductors need 4 valence electrons For the verification of this design, we need to verify its
for each valence electron. This bond called covalent bond. functionality through Simulation, which is done by Functional
Design & Logic Design. Next will be the verification of
II. LITERATURE REVIEW functionality by synthesis. A Technology Dependent design is
resulted in output of this phase. The important notes are that
In the designing of integrated circuits, Physical Design Flow is
the tool metamorphoses the plan effectuation usually in
mostly used tools. It is a step which comes after circuit design
Verilog, which is later converted into gates and .vg file.
in the cycle of standard circuit design. Divine goal of physical
design flow is to create a correct geometric representation of
circuit component such as devices, logic gates, inverter,
multiplexer, interconnects in a shape according to specified
requirements and become ready for manufacturing in
corresponding layers of materials. After manufacturing it
should make sure the working of the component. It is often
termed as layout. Physical design has steps and sub-steps.
Some steps include designing, some steps work for
verification of designing and rest are used for affirmation of
layout design. It has three (03) major categories namely:
Front-End designing using Hardware Description Language,
Physical Verification and Back-End Design. After proper plan
of circuit layout next step is or manufacturing which is Figure. 1. Flow of Asic

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 IV. EXPERIMENTAL PROCEDURES drivers or having multiple drivers, cells or designs that does
not have any inputs or outputs, pin counts that are not matched
In Physical Design, we need to do things carefully and step by between its reference and an instances, hierarchical wire loops
step are as follows: and so forth.
1. First we have to import the input files.
ii. Check_timing
2. Then we have to invoke ICC.
Syntax - check_timing
3. After that we will source input files.
It shows result of the constrained paths if it is there or not in a
4. Then we will do some sanity checks.
design and the consistent prevails or not.
5. Then we will create floor plan by specifying aspect
ratio 1 and utilization 0.7 iii. Check_netlist
6. After that we will set colors for different macros. Syntax - check_netlist It shows results for certain problems
7. Then we have to place and fix macros. such as input ports unloaded or un-driven output ports, nets
8. Now we will fix pins for the macros. free of loads or drivers or having multiple drivers, cells or
9. Then we will apply keep-out margin for macros. designs that does not have any inputs or outputs, pin counts
10. After that we will place placement blockages here. that are not matched between its reference and an instances,
11. Then we have to source cut row file and tick site row hierarchical wire loops and so forth.
to see site rows.
12. Now we will bring PG connections in this design. iv. Check_library
13. Now some sanity checks are mandatory. Syntax - check_library
14. Now we will do standard cell placement. It provides information of consistency between physical and
15. If you got any validation in the previous stage, then logical libraries.
we have to fix that. Other important sanity checks are
16. Now we have to check GRC. • I/O Placement,
17. Now we will have to check and fix cell density and • report_qor
pin density.
18. Now we have to fix and legalize placement. This command reports:
19. Now we have to define NDR rules.  Timing path group
20. Then again we have to unfix placement.  Count details of cell
21. Then again we will legalize and fix placement.  Combinational and non-combinational statistics of
22. Now we will do some sanity checks. current design
23. Now we have to source CTS file provided.  Total area
24. Then in main window we can check the clock.  Static power report
25. Now we have to run provided cts_opt file.  DRV- Design Rule Violation
26. Then we have to check hold and setup timings.  Timing details of compilation
27. If there any validation, we have to fix them –
• For Setup: VT Swapping means HVT to LVT, V. RESULTS AND DISCUSSIONS
Upsizing and Adding buffer. After so many iterations of VT Swapping, Cell Sizing and so
•For Hold: VT Swapping means LVT to HVT, many buffers adding, I haven’t got any Setup and Hold
Downsizing and Adding buffer. Violation in my design as well as I’m successful to meet and
28. Now we have to save our design for future works. fix all the DRC Violations.
29. Now we will do some sanity checks.
30. Then we will run the provided Routing file.
31. Again if there any setup or hold violation then we
have to fix them using upper methods.
32. Now we will look for DRC Violations.
33. If any we have to fix them by VT Swapping, Cell
Sizing and Adding Buffer.
34. But we can’t touch the “Don’t touch” violators.

 Sanity Checks
Sanity checks is very important in terms of timing which Figure.2. Started Dragging Macros For Macros Placement
provides checking of quality of the netlist. It also consists of After Setting Colors
checking the issues related to library file, timing constraints,
I/Os and optimization directives. It is done before each and
every steps of physical design and it is started from floor
planning. If sanity checks are not done, errors will occur in
the inputs. After setting up all the required data, the very first
thing we will do, we will perform a sanity check.

There are 4 four important sanity checks.

i. Check_design
Syntax - check_design
• Gives floating pin warning (if any).
• High fan-out nets (some threshold).
It shows results for certain problems such as input ports
unloaded or un-driven output ports, nets free of loads or Figure. 3. Macros Placement

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Figure.4. Pg Routing By Initiating Pg Grids
Figure.9. Inserting Buffer

Figure.5. detailed routing. Figure.10. Upsizing & Downsizing In Eco Net

Figure.11. Drc Violation & Legalizing Placements

Figure.6. Checking Cell Density

Figure.7. checking pin density.

Figure.12. Fixing Drc

Figure. 8. Checking Clock Figure.13. Final Result using 28nm Library

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VI. CONCLUSION

As VLSI, especially PD (Physical Design) domain is a great

Research and Development field and as my design hasn’t any
DRC Violations as well as hasn’t any Setup and Hold
Violations so this design can be great in future.

FUTURE SCOPE
It can be used in making a chip or processor. This project has
been demonstrated in Single voltage and single row with
double spacing of macros. It can also be demonstrated in
Double row single spacing with 12nm Technology, 5nm
Technology and as on. Also FINFET has taken in place of
MOSFET technology due to some of its limitation.

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Implementation Perspective –Khosrow Golshan

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