Dayananda Sagar College of Engineering

Department of Electronics and Communication Engineering

ShavigeMalleshwara Hills, Kumaraswamy Layout, Bangalore – 560 078.
(An Autonomous Institute affiliated to VTU, Approved by AICTE & ISO 9001:2008 Certified )
Accredited by National Assessment and Accreditation Council (NAAC) with ‘A’ grade

ASSIGNMENT

Program: B.E. Branch: ECE

Course: Fundamentals of VLSI Design Semester : 6th Sem
Course Code: 18EC6DCFOV Sec: A

A Report on

Design and simulate 32 bit Carry select adder using Verilog

Submitted by

Pankaj j kampli 1DS17EC080

Darshan G Ekabote 1DS18EC024
Chhanukya KV 1DS19EC405
Shivamurthy S 1DS17EC115

Faculty In-charge

Dr. Santhosh kumar R

Prof. ,ECE,DSCE
Introduction
A carry select adder is an arithmetic combinational logic circuit which adds two N-bit binary numbers and outputs
their N-bit binary sum and a 1-bit carry. This is no different from a ripple carry adder in function, but in design
the carry select adder does not propagate the carry through as many full adders as the ripple carry adder does.
This means that the time to add two numbers should be shorter. It seems this optimisation was used by Charles
Babbage in his design for the Analytical Engine.
A carry select adder is a particular way to implement an adder, which is a logic element that computes the (n+1)-
bit sum of two n-bit numbers. The carry select adder is simple but rather fast.

The idea behind a N-bit carry select adder is to avoid propagating the carry from bit to bit in sequence. If we have
two adders in parallel: one with a carry input of 0, the other with a carry input of 1, then we could use the actual
carry input generated to select between the outputs of the two parallel adders. This means all adders could be
performing their calculations in parallel. Having two adders for each result bit is quite wasteful so we could
configure the N-bit adder to use 2*N/M-1 M-bit ripple carry adders in parallel. Note that the adder for the least
significant bits will always have a carry input of 0 so no parallel addition is needed in this case.

Block diagram of 32 bit Carry select adder.

-1-
Working

Figure 1 Block diag of 32 bit carry select adder

Two 4-bit ripple carry adders are multiplexed together, where the resulting carry and sum bits are selected by the
carry-in. Since one ripple carry adder with carry-in of 0, and the other with a carry-in of 1, the actual carry-in
yields the desired result.
Structural code is mentioned below. Input a,b (32 bit) with carry cin(1 bit) for output sum(32 bit) and carry cout(1
bit).
Here, 32 bit input is not given directly, instead is sliced into 4 bits (8 times) and given to ripple carry adder.
Ripple carry adder comprises of full adder and mux. Input for full adders with carry as 0 and 1 is carried out.
Output carry of previous adder becomes the input carry of next full adder. The output from these full adders with
carry as 0 and 1 is now given to mux as inputs. Now from the input cin, output is obtained.

Verilog Code for Carry select adder:

`timescale 1ns / 1ns
module carry_select_adder_32bit(a, b, cin, sum, cout);
input [31:0] a,b;
input cin;
output [31:0] sum;
output cout;
wire [6:0] c;
ripple_carry_4_bit rca1(

-2-
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c[0]));

carry_select_adder_4bit_slice csa_slice1( // first 4-bit by ripple_carry_adder

.a(a[7:4]),
.b(b[7:4]),
.cin(c[0]),
.sum(sum[7:4]),
.cout(c[1]));

carry_select_adder_4bit_slice csa_slice2(
.a(a[11:8]),
.b(b[11:8]),
.cin(c[1]),
.sum(sum[11:8]),
.cout(c[2]));

carry_select_adder_4bit_slice csa_slice3(
.a(a[15:12]),
.b(b[15:12]),
.cin(c[2]),
.sum(sum[15:12]),
.cout(c[3]));

carry_select_adder_4bit_slice csa_slice4(
.a(a[19:16]),
.b(b[19:16]),
.cin(c[3]),
.sum(sum[19:16]),

-3-
.cout(c[4]));

carry_select_adder_4bit_slice csa_slice5(
.a(a[23:20]),
.b(b[23:20]),
.cin(c[4]),
.sum(sum[23:20]),
.cout(c[5]));

carry_select_adder_4bit_slice csa_slice6(
.a(a[27:24]),
.b(b[27:24]),
.cin(c[5]),
.sum(sum[27:24]),
.cout(c[6]));

carry_select_adder_4bit_slice csa_slice7(
.a(a[31:28]),
.b(b[31:28]),
.cin(c[6]),
.sum(sum[31:28]),
.cout(cout));
endmodule

module carry_select_adder_4bit_slice(a, b, cin, sum, cout); //4-bit Carry Select Adder Slice//
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] s0,s1;
wire c0,c1;

-4-
ripple_carry_4_bit rca1(
.a(a[3:0]),
.b(b[3:0]),
.cin(1'b0),
.sum(s0[3:0]),
.cout(c0));

ripple_carry_4_bit rca2(
.a(a[3:0]),
.b(b[3:0]),
.cin(1'b1),
.sum(s1[3:0]),
.cout(c1));
mux2X1 #(4) ms0(
.in0(s0[3:0]),
.in1(s1[3:0]),
.sel(cin),
.out(sum[3:0]));
mux2X1 #(1) mc0(
.in0(c0),
.in1(c1),
.sel(cin),
.out(cout));
endmodule

module mux2X1( in0,in1,sel,out); //2:1 Mux//

parameter width=16;
input [width-1:0] in0,in1;
input sel;
output [width-1:0] out;
assign out=(sel)?in1:in0;
endmodule

-5-
module ripple_carry_4_bit(a, b, cin, sum, cout); //4-bit Ripple Carry Adder//
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire c1,c2,c3;
full_adder fa0(
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1));
full_adder fa1(
.a(a[1]),
.b(b[1]),
.cin(c1),
.sum(sum[1]),
.cout(c2));
full_adder fa2(
.a(a[2]),
.b(b[2]),
.cin(c2),
.sum(sum[2]),
.cout(c3));
full_adder fa3(
.a(a[3]),
.b(b[3]),
.cin(c3),
.sum(sum[3]),
.cout(cout));
endmodule

-6-
module full_adder(a,b,cin,sum, cout); //Full Adder//
input a,b,cin;
output sum, cout;
wire x,y,z;

half_adder h1(.a(a), .b(b), .sum(x), .cout(y));

half_adder h2(.a(x), .b(cin), .sum(sum), .cout(z));
or or_1(cout,z,y);
endmodule

module half_adder( a,b, sum, cout ); // Half Adder//

input a,b;
output sum, cout;
xor xor_1 (sum,a,b);
and and_1 (cout,a,b);
endmodule

Simulation Output:

Example were cout is 0

-7-
Example were cout is 1

RTL Schematic:

-8-
Figure 2 Each Carry select adder slice consists of ripple carry adder and mux

Figure 3 Carry select adder 4 bit slice block

Figure 4 4- bit Ripple carry adder block

-9-
Figure 5 Full adder block

Figure 6 Half adder block

HDL Synthesis Report

Macro Statistics
# Multiplexers : 14
1-bit 2-to-1 multiplexer :7
4-bit 2-to-1 multiplexer :7
# Xors : 120
1-bit xor2 : 120

References:

1. http://www.barrywatson.se/dd/dd_carry_select_adder.html
2. http://vlsigyan.com/carry-select-adder-verilog-code/
3. https://en.wikipedia.org/wiki/Carry-select_adder
- 10 -