Digital IC Design LAB MANUAL Subject Code : Laboratory I Regulations : R18-JNTUH Class : Year I Sem. M.Tech (VLSI System Design) Department of Electronics and Communication Engineering BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY Ibrahimpatnam - 501 510, HyderabadBharat Institute Of Engineering & Technology Digital IC Design Lab Manual [2] brarar INSTITUTE OF ENGINEERING AND TECHNOLOGY Ibrahimpatnam - 501 510, Hyderabad ELECTRONICS AND COMMUNICATION ENGINEERING VISION AND MISSION OF THE INSTITUTION ion To achieve autonomous and university status and spread universal education by inculcating discipline, character and knowledge into the young minds and mounds them into enlightened citizens. Mission Our mission is to impart education in a conductive ambience as comprehensive as possible with the support of all the modern technologies and make the students acquire the ability and passion to work wisely, creatively and effectively for the betterment of our society. VISION AND MISSION OF ECE DEPARTMEN Vision The vision of the Department of Electronics and Communication Engineering is to effectively serve the educational needs of local and rural students within the core area of electronics and communication engineering and develop high quality engineers and responsible citizens. Mission The mission of the Department of Electronics and Communication Engineering is to work closely with industry, research organizations to provide high quality education in both theoretical and practical applications of electronics and communication engineering.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual | @)| BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY Ibrahimpatnam - 501 510, Hyderabad ELECTRONICS AND COMMUNICATION ENGINEERING ational Objectives (PEOs: A graduate of the Electronics & Communication Engineering Program should: Program Educational Objective 1: (PEO1) Graduates will be able to synthesize mathematics, science, engineering fundamentals, laboratory and work-based experiences to formulate and solve engineering problems in Electronics and Communication engineering domains and shall have proficiency in Computer-based engineering and the use of computational tools design of electronics systems. Program Educational Objective 2: (PEO2) Graduates will succeed in entry-level engineering positions within the core Electronics and Communication Engineering, computational or manufacturing firms in regional, national, or international industries and with government agencies. Program Educational Objective 3: (PEO3) Graduates will succeed in the pursuit of advanced degrees in Engineering or other fields where a solid foundation in mathematics, basic science, and engineering fundamentals is required... Program Educational Objective 4: (PEO4) Graduates will be prepared to communicate and work effectively on team based engineering projects and will practice the ethics of their profession consistent with a sense of social responsibility. Program Educational Objective 4: (PEOS) Graduates will be prepared to undertake Research and Development works in the areas of Electronics and Communication fields. Sey POI | Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the solution of complex engineering problems related to Electronics and Communication Engineering. PO2 | Problem analysis: Identify, formulate, review research literature, and analyze complex engineering problems related to Electronics and Communication Engineering and reaching substantiated conclusions using first principles of mathematics, natural sciences, and engineering sciences.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual PO3 Design/development of solutions: Design solutions for complex engineering problems related to Electronics and Communication Engineering and design system components or processes that meet the specified needs with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations. PO4 Conduct investigations of complex problems: Use research-based knowledge and research methods including design of experiments, analysis and interpretation of data, and synthesis of the information to provide valid conclusions. POS; Modern tool usage: Create, select, and apply appropriate techniques, resources, and modem engineering and Electronics and Communication Engineering tools including prediction and modeling to complex engineering activities with an understanding of the limitations. PO6 ‘The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the Electronics and Communication Engineering professional engineering practice. PO7 Environment and sustainability Understand the impact of the Electronics and Communication Engineering professional engineering solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development. POS Ethies: Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice. PO9 Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary settings. POIO ‘Communication: Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to comprehend and write effective reports and design documentation, make effective presentations, and give and receive clear instructions. POI Project management and finance: Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a member and leader in a team, to manage projects and in multidisciplinary environments. POI2 Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and life-long leaming in the broadest context of technological change.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual PSOL PSO1:Professional Skills: An ability to understand the basic concepts in Electronics & Communication Engineering and to apply them to various areas, like Electronics, Communications, Signal processing, VLSI, Embedded systems etc., in the design and implementation of complex systems. PSO2 PSO2:Problem-Solving Skills: An ability to solve complex Electronics and communication Engineering problems, using latest hardware and software tools, along with analytical skills to arrive cost effective and appropriate solutions PSO3 PSO3: Successful Career and Entrepreneurship: An understanding of social- awareness & environmental-wisdom along with ethical responsibility to have a successful career and to sustain passion and zeal for real-world applications using optimal resources as an Entrepreneur.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Digital IC Design Lab LIST OF EXPERIMENTS 1 | HDL code to realize all the logic gates 12 2 | Design and Simulation of adder, Serial Binary Adder, 14 Multi Precession Adder, Carry Look Ahead Adder 3_| Design of 2-to-4 decoder 16 4 _| Design of 3-to-8 encoder (without and with parity) 18 5_| Design of 8-to-1 multiplexer 19 6 | Design of 4 bit binary to gray converter 21 7__| Design of Full adder using 3 modeling styles 23 8 | Design of flip flops: SR, D, JK, T 25 9° | Design of 4-bit binary, BCD counters ( synchronous/ 28 asynchronous reset) or any sequence counter 10 | Design of ALU to Perform — ADD, SUB, AND-OR, I’s 29 and 2’s Compliment, 11_| Static and Dynamic Characteristics of CMOS Inverter 33 12 | Implementation of EX-OR gate using complementary 36 CMOS, Psedo-NMOS, Dynamic and domino logic style 13 | Implementation of Full Adder using Transmission Gates 38 14 _| * Design of Traffic Light Controller using VHDL Code 41 * Topic beyond syllabus_Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual OBJECTIVES: To understand the logic gates using Verilog HDL Programming and verify their simulation and synthesis reports. To understand the various design style of simple and complex digital Integrated Circuits (IC). To understand about models and mode! parameters of MOSFET amplifier CMOS Inverter ete. which are suited for Digital IC Design Lab. Furthermore, to develop the necessary framework and tools to analyze and design such systems HARDWARE/SOFTWARE REQUIREMENTS: Intel based PC with minimum of 3.60 MHZ or faster processor with at least 4GB RAM and 1 TB free disk space Electronic design automation (EDA) equivalent software. COURSE OUTCOMES: 1. 2 To understand the SPICE software for circuit design. To understand basic DC characteristics of the CMOS integrated circuits, as well as their dynamic properties during switching processes. Understand the concepts of digital system design methods through practical domain. Leam techniques and engineering tools (such as Xilinx/Altera/Cypress/equivalent based FPGAJCPLD kits) to design, and implement.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Mapping course outcomes leading to the achievement of the program outcomes: Program specific Course Program outcomes outcomes ‘outcomes Pot | P02 | Pos | pos | pos | pos | p07 | pos | pos | poio | poit | por2 | pso1 | pso2 | Pso3s col 3 3 3 2 3 - - - 2 1 - 2 3 3 3 co2 2 3 2 3 3 - - - 2 1 - 2 3 3 3 C03 3 2 3 2 - - - - 1 1 - 3 3 3 3 cO4 3 2 2 2 - - - - 1 1 - 3 3 3 3 Low 2-supportive Shighly ratedBharat Institute Of Engineering & Technology Digital IC Design Lab Manual ATTAINMENT OF PROGRAM OUTCOMES & PROGRAM SPECIFIC OUTCOMES Sr.No. | Name of the Experiment Program Outcomes (POs) Program Specific Attained ‘outcomes (PSOs) attained 1 HDL code to realize all the | POI,PO2,PO3,PO4,PO5,PO9 | PSOI,PSO2,PSO3 logic gates 2 Design and Simulation of | POI,PO2,PO3,PO4,PO5,PO9__ | PSOI,PSO2,PSO3 adder, Serial Binary Adder, Multi Precession Adder, Carry Look Ahead Adder 3 Design of 2-t0-4 decoder POI,PO2,PO3, PO4,POS,PO9_| PSO1,PSO2,PSO3 4 Design of 3-to-8 encoder | POI,PO2,PO3, PO4,POS,PO9 | PSO1,PSO2,PSO3 (without and with parity) 5 Design of 8-to-1 multiplexer | POI,PO2,PO3, PO4,POS,PO9 _ | PSO1,PSO2,PSO3 6 Design of 4 bit binary to gray | PO1,PO2,PO3, PO4,PO5,PO9 | PSO1,PSO2,PSO3 ‘converter 7 8 Design of Full adder using 3 | PO1,PO2,PO3, PO4,PO5,PO9 | PSOI,PSO2,PSO3 modeling styles 9 Design of flip flops: SR, D, JK, | POI,PO2,PO3, PO4,PO5,PO9 | PSO1,PSO2,PSO3 it 10 Design of 4-bit binary, BCD | POI,PO2,PO3, PO4,POS,PO9 | PSO1,PSO2,PSO3 counters (/__synchronous/ asynchronous reset) or any sequence ‘counter i Design of ALU to Perform — | POI,PO2,PO3, PO4,PO5,PO9 | PSOI,PSO2,PSO3 ADD, SUB, AND-OR, 1’s and 2s Compliment, 2D Static and Dynamic | POI,PO2,PO3, PO4,PO5,PO9 | PSOI,PSO2,PSO3 Characteristics of CMOS Inverter 3 Implementation of EX-OR gate | POI,PO2,PO3, PO4,PO5,PO9 | PSOI,PSO2,PSO3 using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style 4 Implementation of Full Adder | POI,PO2,PO3, PO4,POS,PO9 | PSO1,PSO2,PSO3 using Transmission Gates 15 * Design of Traffic Light | POI,PO2,PO3, PO4,PO5,PO9, | PSOI,PSO2,PSO3 Controller using VHDL Code_| POLL *Topic beyond syllabusBharat Institute Of Engineering & Technology Digital IC Design Lab Manual An Introduction to VHDL VHDL is an acronym for Very high speed integrated circuit (VHSIC) Hardware Description Language which is a programming language that describes a logic circuit by function, data flow behavior, and/or structure. This hardware description is used to configure a programmable logic device (PLD), such as a field programmable gate array (FPGA), with a custom logic design. it is used for many purposes. For describing hardware. ‘Asa modeling language. For simulation of hardware. For early performance estimation of system architecture. For synthesis of hardware, A VHDL design begins with an ENTITY block that describes the interface for the design. The interface defines the input and output Hogic signals of the circuit being designed. The ARCHITECTURE block describes the internal operation of the design. Within these blocks are numerous other functional blocks used to build the design elements of the logic being created. VLSI Design Flow boven pte f ¥Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual VHDL Program Structure Proeace om — Lorre oa entity entity-name is [port(interface-signal-declaration):] end [entity] [entity-name); architecture architecture-name of entity-name is [declarations] begin architecture body end [architecture] [architecture-name}; STD_LOGIC_1164: The STD_LOGIC_1164 package has been developed and standardized by the IEEE. It introduces a special type called std_ulogic, which has nine different logic values. The reason for this enhancement is that the type bit is not suitable for the precise modeling of digital circuits due to the missing values, such as uninitialized or high impedance. The type std_ulogic consists of the following elements: Declaration: type std_ulogic is uninitialized forcing unknown forcing 0 forcing 1 high impedance ‘weak unknown weak 0 weak 1"); = "don't care”Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 1 Objective: HDL code to realize all the logie gates TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14.1 VHDL Code The VHDL for a two input AND gate is shown below: library IEEE; use IEEE,STD_LOGIC_1164.ALL; entity and_or_top is Port (INAI: in STD_LOGIC; ~ AND gate input INA2: in STD_LOGIC; -- AND gate input OA :outSTD_LOGIC; -- AND gate output end and_or top; architect Behavioral of and_or_top is bes OA <= INA and INA2; ~ 2 input AND gate end Behavioral Equivalent gate described by the above code:Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual VHDL code for a two input OR gate: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and_or_top is Port (INOI: in STD_LOGIC; ~ OR ate input INO2: in STD_LOGIC; — OR gate input 00: out STD_LOGIC); -- OR gate output end and_or_top; architec! Behavioral of and_or_top is begin 00 <= INOI or INO2 2 input OR gate end Behavioral; Equivalent gate described by the above code: Experiment No. 2Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Objective: Design and Simulation of adder, Serial Binary Adder, Multi Precession Adder, Carry Look Ahead Adder. TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14.1 VHDL Code VHDL code for an N-bit Serial Adder Design use just one full adder circuit with a flip-flop at the carry output. The circuit is sequential with a reset and clock input, In each clock cycle, one bit from each operand is passed to the full adder, and the carry output is fed back as the carry input for the next SUM calculation. The above block diagram shows how a serial adder can be implemented. The D flipflop is used to pass the output carry, back to the full adder with a clock eycle delay. ‘carry-out| Clock Reset VHDL CODE: library ieee; use ieee.std_logic_1164.all; serial adder for N bits. Note that we dont have to mention N here. entity serial_adder is port(Clk,reset : in std_logie; --clock and reset signal a,b,cin : in std_logic; --note that cin is used for only first iteration, S.cout : out std_logic —note that s comes out at every clock cycle and cout is valid only for last clock cycle ); end serial_adder; architecture behav of serial_adder is intermediate signals. signal ¢,flag : std_logie = beginBharat Institute Of Engineering & Technology Digital IC Design Lab Manual process(clk,reset) —-we use variable, so that we need the carry value to be updated immediately variable c : std_logic ="0'; begin if(reset ='1') then ~active high reset cout <=; flag <= elsif(rising_edge(clk)) then if(flag = "01 then on first ite c= cin tion after reset, assign cin toc. flag <="I'; --then make flag 1, so that this if statement isnt executed any more. end ify cout <= '0'; sa xorb xor ¢; -SUM = (a and b) or (¢ and b) o (a and c); ~CARRY end if end process;Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Objective Design of 2-t0-4 decoder TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14.1 VHDL Code Binary decoder has n-bit input lines and 2 power n output lines. It can be 2-to-4, 3-10-8 and 4-10-16 line configurations. Binary decoder can be easily constructed using basic logic gates. VHDL Code for 2 to 4 decoder using if else statement library IEEE; use IEEE.STD_LOGIC_1164.ll; entity decoderl is port(a: in STD_LOGIC_VECTOR(I downto 0); b: out STD_LOGIC_VECTOR(3 downto 0); end decoder! architecture bhy of decoder! is begin process(a) begin if @="00") then b<= "0001"; elsif (a="01") then b<= "0010"; elsif (a="10") then b<= "0100"; else b<= "1000"; end if; end process; end bhy; Waveform for 2 to 4 decoderBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Figure Simulation result of 2-to-4 decoderBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 4 Objective Design of 3-t0-8 decoder ‘TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14.1 VHDL Code of 3-t0-8 decoder ENTITY Decoder3_8_ Enable IS port (a: in std_logie_vector(2 downto 0); e:in std_logi y-out std_logic_vector(7 downto 0)); END ENTITY Decoder3_8_ Enable; ARCHITECTURE RTL OF Decoder3_8 1S BEGIN process (¢, a) begin ife =" then iffa="000" then y="00000001" celsif'a="001" then y="00000010" clsif'a="010" then y="00000100" celsif'a="011" then y="00001 000" clsif'a="100" then y="00010000" elsif a="101" then y="00100000" clsif'a="110" then y="01000000" celsif'a="111" then y="10000000" else; end if, cend process END ARCHITECTURE RTL;Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 5 Objective Design of 8-to-1 multiplexer TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14.1 Theory: Multiplexer is a digital switch. It allows digital information from several sources to be rooted on toa single output line, The basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2AN input lines and N selection lines whose bit combinations determine which input is selected. Therefore multiplexer is many into one and it provides the digital equivalent of an analog selector switch. VHDL CODE LIBRARY IEEE; USE IEEE STD_LOGIC_1164.ALL; USE IEBESTD_LOGIC_ARITH.ALL; USE IEFESTD_LOGIC_UNSIGNED.ALL; ENTITY MUX8_1 IS PORT ( SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0); A,B, C, D, E,F, G, H: IN STD_LOGIC; MUX_OUT : OUT STD_LOGIC ); END MUX8_1; ARCHITECTURE BEHAVIORAL OF MUX8_1 IS BEGIN PROCESS (SEL,A.B.C,D.EF,G.H) BEGIN CASE SEL ISBharat Institute Of Engineering & Technology Digital IC Design Lab Manual WHEN "000" => MUX_OUT MUX_OUT <=B; WHEN "010" => MUX_OUT < WHEN "O11" => MUX_OUT <=D: WHEN "100" > MUX_OUT MUX_OUT <=F; WHEN "110" => MUX_OUT <=G. WHEN "111" => MUX_OUT <=, WHEN OTHERS => NULL; END CAS END PROCESS; END BEHAVIORAL; Simulation results of Mux FigureBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 6 Objective 4 bit binary to Gray code converter TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14.1 VHDL Code ~ om ~ ~~ aa une Figure Block diagram of 4 bit Binary to Gray code converter. LIBRARY ieee; USE ieee.std_logic_1164.ALL; n2gray is port( bin : in std_logic_vector(3 downto 0); —-binary input G : out std_logic_vector(3 downto 0) ~gray code output); end bin2gray; architecture gate_level of bin2gray is begin ~xor gates. G(3) <= bin@); G(2) <= bin(3) xor bin(2); G(1) <= bin(2) xor bin(1); G(0) <= bin(1) xor bin(0);Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Figure Simulation Waveform of 4 bit Binary to Gray code ConverterBharat Institute Of Engineering & Technology Digital IC Design Lab Manua Experiment No. 7 Objective Design of Full adder VHDL code TOOLS USED: 1. Operating System-Windows-64bit 2, Xilinx ISE 14.1 VHDL Code The VHDL Code for full-adder circuit adds three one-bit binary numbers (A B Cin) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout). Truth Table describes the functionality of full adder. sum(S) output is High when odd number of inputs are High. Cout is Hi when two or more inputs are High. VHDL Code for full adder can also be constructed with 2 half adder Port mapping in to full adder, Ua eos Figure Block Diagram of Full adder library IEEE; use IEEE.STD_LOGIC_1164.ALL entity full_adder_vhdl_code is Port (A: in S D_LOGIC;Bharat Institute Of Engineering & Technology Digital IC Design Lab Manua Bri STD_LOGIC: Cin : in STD_LOGIC; S : out STD_LOGIC: Cout : out STD_LOGIC); end full_adder_vhdl_code; architecture gate_level of full_adder_vhdl_code is begin S<= A XOR B XOR Cin; Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ; end gate_level: Figure Simulation Waveform of Full adderBharat Institute Of Engineering & Technology Digital IC Design Lab Manua Experiment No. 8 Objective Design of SR and D flip flop TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14. VHDL Code SR Flip Flop A flip-flop cireuit can be constructed from two NAND gates or two NOR gates. These flip-flops are shown in Figure, Each flip-flop has two outputs, Q and Q’, and two inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop. Figure Block Diagram of SR Flip Flop library ieee ic_1164.all; ic_arith.all use ieee. std_lo; use ieee. std_lo; use ieee. std_lo; entity SR_FF is PORT( S,R,CLOCK: in std_logic Q, QBAR: out std end SR_FE Architecture behavioral of SR_FF is begin PROCESS(CLOCK) variable tmp: std_logicBharat Institute Of Engineering & Technology Digital IC Design Lab Manua if(CLOCK="' and CLOCK'EVENT) then if(S=0' and R=0')then tmp:=tmp; sif(S1' and R='I'then np:="Z" sif(S—0' and R='I')then tn end if, end if Q< tmp: QBAR <= not tmp: end PROCESS; end behavioral: np:='1' D Flip-Flop The D flip-flop shown is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state, Figure Block Diagram of D Flip Flop library ieee; use ieve. std_logic_1164.all; use ieee. std_logic_arith.all; use ieee. std_logic_unsigned all;Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual entity D_FF is PORT( D,CLOCK: in std_logic; Q: out std_logic); end D_FF; architecture behavioral of D_FF is begin process(CLOCK) begin if(CLOCK="I' and CLOCK'EVENT) then Q<=D; end if, end process; end behavioral;Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 9 Objective Design of BCD Counter TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14. VHDL code library ieee; use ieee.std_logic_1164.all; use iece.numeric_std.all; entity bed_counter! is port ( ick in std_logie; itstb : in std_logic; i_syne reset rin std logic; i_count_ena in std_logie; o_bed : out std_logic_vector(3 downto 0)); end bed_counterl; architecture rtl of bed_counter| is signal r_ count : unsigned(3 downto 0); begin o_bed <=std_logic_vector(r_count); p_count : process(i_clk,i_rstb) begin if ti_rstb='0') then rcount <= (others=>'0’); elsif(rising_edge(i_clk)) then if(i_syne_reset='I') then count <=(others=>'0'); elsif{i_count_ena='1') then if(r_count = 9) then r_count <=(others=>'0’; else r_count <=r_count +1; end if;Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual end process p_count; end rtl; co BCD Sas Po 0000 ° 001 0010 oon 0100 0101 o110 out 1000 1001 ole soln a lel Figure BCD counting states Figure Simulation results of BCD counterBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 10 Objective Design of ALU TOOLS USED: 1. Operating System-Windows-64bit 2. Xilinx ISE 14. VHDL code entity ALUis generic (width: integer=32); port ( A: instd_logic_vector((width-1) downto 0); B: in std_logc_vector((width-1) downto 0); Sd: in std_logic_vector(3 downto 0); Y: out std_logic_vector((width-1) downto 0) ); end ALU; architecture behv of ALU is begn process(A,B,Sel) begin case Sel is when "0000" =>Y <=A +B; when "0001" => <=A +{not B) +1; when "0010" =>Y <=A +1; when "OOL1" =>Y <=A-1; when "0100" =>Y <=B +1; when "0101" =>Y <=B- 1;Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual when "0110" SY Y <8; when "1000" =>Y <=not A; when "1001" =>Y <=not 8; When "1010" >Y <=A and B; when "1011" =>Y Y Y Y <= "2000; end case; end process; end bey; LOGIC UNIT - Y Gr: u x SEL Ge re) SECC: Fig. Block diagram of 32-bit ALUBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Table Truth table of ALU ‘SEL OPERATION FUNCTION UNIT “000 Y==A*B Addition = ARITHMETIC 0001 Y¥<= A+B"+1 Subtraction ARITHMETIC 0010 Y<= Atl Increment A ARITHMETIC Ol Y=A-1 Decrement A. ARITHMETIC 0100 Y<= B+1 Increment B ARITHMETIC 0101 Y=B-1 Decrement B_ ARITHMETIC 0110 YA ‘TransferA = ARITHMETIC Onl Y=B ‘TransferB = ARITHMETIC 1000 Y<= not A NOT A LOGIC 1001 Y<= not B NOTB LOGIC 1010 Y<= AandB AANDB LOGIC 1011 Y= AorB AORB LOGIC 1100 Y<=AnandB = ANANDB — LOGIC 1101 Y<= AnorB ANORB LOGIC 1110 Y<=AxorB AEX-ORB LOGIC 1111 Y<=not(AxorB) AEX-NORB LOGICBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 11 Objective: Static and Dynamic Characteristics of CMOS Inverter TOOLS USE] - Operating System-Linux 2. Mentor Graphics Tool Theory: Inverter is the basic building block of all the digital circuits and its can be used to implement any combinational and sequential circuits for various applications. CMOS Inverters designed and simulated using HEP-2 tool of Mentor graphics. As per the technology, voltage is scaled down. So Voltage Scaling is used to obtain the Low Power CMOS Cell Library for the digital circuits. Based on the simulation results following observations are made: (a) Performance of the cell based on static characteristics. (b) Performance of the cell based on dynamic characteristics. From the above observations the power dissipation of Inverter cell has been carried out and to evaluate the performance of the CMOS Inverter using above-mentioned performance parameters.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Figure. Design of CMOS Inverter Figure . Symbol of CMOS Inverter Fig 2. represents the symbol of inverter basically designed by CMOS. After the implementation of CMOS NOT gate there is an option in the mentor graphies tool that >Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual the whole CMOS cell can be saved as a library element, which can used as a component in the designing of other logic gates. The aspect ratio of the CMOS cells is define as the ratio of (W/L)p to ( W/L)n. Regarding the aspect ratio of the implemented cells, we have shown the values in terms of ELDONET file ( tool used for simulation and provide all the information regarding the design) from the mentor graphics tool for CMOS INVERTER gate and consider the same aspect ratio for the designing of other cells. Figure Voltage Transfer Characteristic of an inverter at Multi VDDBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Figure . Simulation results of CMOS inverter Conclusion: Hence verified the simulation results of CMOS Inverter. Experiment No. 12 Objective: Implementation of EX-OR gate using complementary CMOS, Psedo-NMOS, Dynamic and domino logic style TOOLS USED: 1. Operating System-Linux 2. Mentor Graphics Tools Theory: XOR gate is commonly called as Parity Generator. It is widely used in communication circuits. XOR gate is normally realized using NAND, NOR and NOT gates. NAND, NOR and NOT gates were used to design low power XOR gate. This way the complexity of realizing XOR using transistors could be avoided. The designed cells are saved as a library element and used in the implementation of other logic gates and various digital circuits.Bharat Institute Of Engineering & Technology Digital IC Design Lab ManualBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Figure . XOR Gate Simulation using HEP-2 Conclusion: Hence verified the simulation results of XOR gate. Experiment No. 13 Objective: Implementation of Full Adder using Transmission Gates TOOLS USED: . Operating System-Linux 2. Mentor Graphics Tools Theory: Although a CMOs transmission gate has better quality there is full swing signal in a CMOS transmission gate, i.e., needs complementary signal values to control the gates of PMOS and NMOS. Usually an inverter is needed to generate a complementary input. Conventional a logical circuit can be realized with a canonical CMOS transistor. According to transmission gate theory if a high impedance state is available fewer transistor can be used.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual B Figure The XOR Function Implemented by Transmission Gates. 200N 400 aon 800N 100N The input signal A and B. 00. Fig Simulation Results of four transistors XOR gateBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Figure The Full adder Function Implemented by Transmission Gates. Conclusion: Hence verified the simulation results of full adder gate.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual TSMC 180nm Technology Tene seascapeBharat Institute Of Engineering & Technology Digital IC Design Lab Manual Experiment No. 14 Objective: Design of Traffic Light Controllers using VHDL Code Tools Used 1. Operating System: Window 2. Xilinx 14.1 ISE Theory: A simple traffic light controller can be implemented by a state machine that has a state diagram such as the one shown in Figure. Its state progresses according the value of the timer used. When the value of timer reaches a specific value, the state of the system changes. A set of 4 traffic lights have been designed for a 4 — way junction as shown. The states are defined in terms of the output. Timer goes from 0 to 100 and then itis reset to 0. Each light is programmed to run as follows: 1. It is GREEN for 20 s. 2. Then it remains YELLOW for Ss. During this time all other lights remain RED. This process is continued for all the lights successively. State Table = 0 so SO 1234 20 So Si 1234 25 SL $2 1234 45 $2 S3 1234 50 S3 S434 70 S4 —S5_—1234 75 SS S6 124 95 S6 S7___ 1234 100 S7 SO 123.Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual Fig State DiagramBharat Institute Of Engineering & Technology Digital IC Design Lab Manual library IEEE; use IEEE.STD_LOGIC_1164.a1: use IEEE.STD_LOGIC_unsigned.all; entity traffic is ort ( elk : 4n STD_Losrc; er : in STD_LOGIC: redi : out STD_LOGIC: yellow1 : out S1D_LosIc; greeni : out STD_Lostc: ed2 : out STD_LOGIC: yellow2 : out STD_LOGIC: green? : out STD_LoGr red3 : out STD_LOGIC: yellows : out STD_LOGIC; greens : out STD_Locr xed4 : out STD_LOGIC: yellows : out STD_LOGIC; green4 : out s7D_fosic ” end entity traffic: architecture trafficA of traffic is type state type is (30, si, s2, 3, 34, 35,36,37); signal state : state type := 207 signal count : integer i= signal lights: std_logic_vector (11 downto 0): begin STATEpro : process (state) begin case state is when s0 => lights <= "001100100100" when 21 => lights < 1100100100" when s2 => lights <= "100001100100"; when 83 => lights <= "100010100100";Bharat Institute Of Engineering & Technology Digital IC Design Lab Manual When 34 => lights wen 85 => lights <= "100100010 when 36 => lights <= "10010010000: when 87 => lights <= "100100100010"; when others => lights <= lights: end case; end process: LT : process (clk) vega] cage count is when 0 => state <= 90; count <= count + 1; when 20 => state when 25 => stare when 45 => state when 50 => stare when 70 => state when 75 => stace yellow ends green ends) yellow ends when 95 => stare green ends) when 100 => count when others => count <= count +1: end case: green¢ <= lights(0) yellowd <= lights(1); Fedé <= lights (2) green3 <= lights(3); yellows <= lignts(4): red3 <= lights(5) green? <= lignts(é) yellow2 <= lights(7); red2 <= lights(): greent <= lights(3) yellow. <= lignts(19) redi <= lights(11); Simulation Results. STBharat Institute Of Engineering & Technology Conclusion: Simulation results are verified correctly