Scribd
Upload
73 views

Activity2 2623

The document is a summary of assignments for an IT course. It includes: 1. A problem to design a circuit for a binary slot machine jackpot using NAND gates. The truth table and K-map solution are provided. 2. A problem to design a circuit to detect if a binary input number is divisible by 2 or 3 using NOR gates. The truth table and POS solution are given. 3. Two problems to simplify Boolean functions with don't care conditions and implement the solutions using various logic gate networks.

Uploaded by

ryle34
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
73 views

Activity2 2623

The document is a summary of assignments for an IT course. It includes: 1. A problem to design a circuit for a binary slot machine jackpot using NAND gates. The truth table and K-map solution are provided. 2. A problem to design a circuit to detect if a binary input number is divisible by 2 or 3 using NOR gates. The truth table and POS solution are given. 3. Two problems to simplify Boolean functions with don't care conditions and implement the solutions using various logic gate networks.

Uploaded by

ryle34
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 14

Summative Assessment#2

IT2623

Ryle Ibañez 3/07/2022

2ITB Mrs. Maria Lourdes Edang

1. A certain Jose Velarde owns binary slot machine at CASINO FILIPINO. The slot machine is
composed of 4 slots. The jackpot is won whenever 3 adjacent slots consisting of alternating 0's
and l's come up. Determine the equation of this slot machine used to award the jackpot.
Simplify the function and implement it using NAND gates only.

Truth Table

A B C D S
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0
K-MAP

SOP

Circuit Diagram

S = B’CD’ + A’BC’ + BC’D + AB’C


2. Design a circuit that accepts the binary code of decimal numbers 0 to IS and it outputs a 1 when
the input decimal is divisible by 2 or 3 (except 0). Simplify the function and implement it using
NOR gates only.

Truth Table

A B C D S
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1

K-MAP

POS
Circuit Diagram

S = (A’+B+C’+D’)(A+B+C)(A+B’+D’)(B’+C+D’)

3. Simplify the following Boolean function F together with the don't care condition d. Construct the
circuit using NOR-NOR, NOR-AND, and OR-AND networks.

A. F(A,B,C,D) = Σ (0,6,8,14)| D = (A,B,C,D) = Σ(2,4,10)

TRUTH TABLE

A B C D F
0 0 0 0 1
0 0 0 1 0
0 0 1 0 X
0 0 1 1 0
0 1 0 0 X
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 X
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0

K-MAP

POS

F = (B’+C)(D’)

LOGIC CIRCUITS

A. NOR-NOR
B. NOR-AND

C. OR – AND
B. F(w,x,y,z) = Σ (0,1,2,3,7,8,10) | D = (w,x,y,z) = Σ(5,6,11,15)

Truth Table

W X Y Z F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 X
0 1 1 0 X
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 X
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 X

K-MAP

POS

F = (W’+Z’)(X’+Z)
LOGIC CIRCUITS

1. NOR-NOR

2. NOR-AND
3. OR-AND

4. Simplify the following Boolean function F together with the don’t care condition d. Construct the
circuit using AND-OR, NAND-OR, and NAND-NAND networks.

a. F(A, B, C, D) = Σ(1, 3, 5, 7, 9, 15); d(A, B, C, D) = Σ(4, 6, 13)

Truth Table

A B C D F
0 0 0 0 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 1
0 1 0 0 X
0 1 0 1 1
0 1 1 0 X
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 X
1 1 1 0 0
1 1 1 1 1
K-MAP

F = A’D + C’D + BD

LOGIC CIRCUIT

A. NAND-NAND

F
A. AND-OR

B. NAND-OR

F
b. F(A, B, C, D) = Σ(3, 4, 13, 15)

Truth Table

A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

K-MAP

F = A’BC’D’ + A’B’CD + ABD


Logic Circuits
A. NAND - NAND

B. AND-OR

F
C. NAND-OR

You might also like