Simulation of GM - Id Design Method in CMOS Integrated Circuit Design and Simulation of Related Parameter Curves With Cadence Virtuoso IC617
Simulation of GM - Id Design Method in CMOS Integrated Circuit Design and Simulation of Related Parameter Curves With Cadence Virtuoso IC617
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foreword
This article is my own study notes, which belong to the advanced part of the Cadence Virtuoso series. The
software version used is Cadence Virtuoso IC617. For other articles, please click above to see the content of
the Cadence Virtuoso column I produced.
In the previous article, the process of designing an op amp using process parameters was documented.
Generally, the relevant parameters of the current process library are simulated first, and then substituted into
each transistor for calculation. The data is more complicated and the calculation amount is huge. When there
are more transistors in a design, modifying one of the parameters results in more data to be recalculated. At the
same time, in short-channel devices, the empirical formula for MOS gradually fails. Therefore, the introduction of
the
principle
MOS working state in amplifier
Assuming the device is N-MOS, the following circuit topology is the simplest for it to work properly.
Before further understanding of other principles, the overdrive voltage VOV is defined as follows.
2 ID
VO V = VG S − VT N =
μn Co x ( W )
L n
When MOS is used in amplifier applications, it is often made to work in the saturation region (the area on the
right in the figure below), after ignoring the effect of channel length modulation, that is, the current Id is only
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transconductance gm
For MOS devices used in amplifiers, the input signal is voltage and the output signal is current, so a parameter
can be defined to represent the ability of the device to convert voltage into current, that is, transconductance
gm, which can be regarded as a quality factor.
Dividing the output current by the input voltage gives the following equation. As for why the coefficient is 2, it can
be obtained according to the VI characteristic formula.
2 ID
gm =
VO V
From this formula, the following curve can be obtained. where the slope is gm. When the overdrive voltage
increases, the output current also increases. But in fact, it is not a strict linear relationship, but has a certain
quadratic coefficient.
gm/id
If there are two transistors with different parameters, we draw their Vov-ID curves and get the following figure.
Looking at the horizontal dotted line, for transistors with different gm values, to achieve the same ID, different
overdrive voltages Vov are required. Similarly, observe the vertical dotted lines, under the same overdrive
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voltage, have different IDs. That is, they have different "efficiencies".
Now, introduce a brand new parameter: gm/id, its value is related to the inverse of the overdrive voltage.
gm 2
=
ID VO V
The first , consider it, is introduced to replace the parameter of the overdrive voltage Vov.
The second , gm under unit current, that is "gm efficiency", when the same ID is put in, when the gm efficiency
is higher, the more gm you get.
So, with this definition, how should we reasonably choose the gm/id value of a transistor? From the contents of
the following three subtitles, we need to choose the gm/id size of a transistor to achieve a compromise between
gain and bandwidth (it can be seen that the bandwidth-gain product GBW is a fixed value), and the gain is larger
than the bandwidth. If the bandwidth is large, the gain will be small, and at the same time, the influence of noise
must be taken into account.
gain gian
In the design of op amps, gain is one of the important parameters to be considered. For a transistor with a fixed
process and fixed parameters, the greater the value of gm/id, the greater the gain it can provide. Meanwhile,
under the same process, the larger the gate length L, the larger the gain.
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Bandwidth fT
Bandwidth fT is also one of the important parameters. Under the same process, when the value of gm/id is
smaller, the bandwidth is larger. Meanwhile, under the same process, the smaller the gate length L, the larger
the bandwidth.
Noise Vn
Only the thermal noise, the largest noise source of the transistor itself, is considered here, and the flicker noise
related to the frequency f is temporarily ignored.
4kT¶ _ _ _
Vn2 , i n =
gm
Vn2 , o u t = 4k T | g _m ro2
MOS is used as an amplifier , the noise is at the input end, and the design should make the gm slightly
larger (gm/id is slightly larger) .
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MOS is used as a current mirror , the noise is at the output end, and the design should make the gm
slightly smaller (gm/id is slightly smaller) .
current density
So much has been laid before, but in fact, they are all talking about some basic theories. When we design an op
amp, it is nothing more than the size of the design transistor, namely W and L. So, how do we map gm/id values
to dimensions?
A new concept is introduced here, current density, represented by id/W. Meaning, the current per unit dimension
W. Under different gm/id values, there are different current densities id/W. At the same time, the gate length L of
the transistor also has a certain influence on it.
At this point, we can fully design the size of the transistor. In the above figure, we selected the value of gm/id,
and at the same time selected the value of L, in the curve, we can get the value of id/W, and the corresponding
value of W will come out.
calculation steps
Using gm/id for transistor design is essentially a table look-up method (polling), which requires little calculation.
After determining the gm/id value, you only need to find the required value in the corresponding curve or table. .
At the beginning, it is necessary to start with the given target parameter bandwidth gain product GBW and the
required load capacitance CL to obtain the value of gm (usually an input tube).
Suggestion: CL needs to consider the parasitic parameters of the circuit itself, so take 1.2 times CL in the
calculation, that is, the design CL is 10pF, and the load capacitance is designed to be 10pF in the
simulation, but the value of CL in the GBW formula is 12pF.
gm
G B W = AV fT =
2 π CL
1. get gm
2. After the bandwidth and gain are compromised, select gm/id and L to get id
4. get W
When the current id of the branch is known, you can directly skip to steps 3 and 4.
Curve simulation
In the above theoretical part, we found that the current density id/W curve is more important, we need to
simulate the transistor to get this curve, in order to carry out the above design. In the meantime, let's take a look
at the gain.
N-MOS Simulation
Schematic
It is consistent with the VI characteristic curve of the previous test. At the same time, the body effect is not
considered for the time being, and the B terminal is directly grounded.
A piece of
Since
chicken…
the final W willon
focus be very large, it is 34 31 111 Column Directory
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3/16/22, 10:43 PM Simulation of gm/id design method in CMOS integrated circuit design and simulation of related parameter curves with Cadence Virtuoso IC617 - Programmer Sought
necessary to set the Multiplier or Fingers of the transistor, divide the large transistors into small blocks, and
connect them in parallel or in series to reduce parasitic parameters. Here set Multiplier as a variable.
Simulation settings
Open ADE-L and make simulation settings.
Assign an initial value to a variable. Among them, W has a slight influence on the simulation results. In the later
stage, according to the actual W, the simulation is re-simulated after fine-tuning.
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Search in Find, and finally find waveVsWave, which is used to draw waveforms.
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Similarly, add "self_gain" to the Y axis. There is no need to click the transistor again here, just select it directly in
the list in the small window.
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Some craft libraries do not have self_gain, so manually input gm/gds. code is below
1 OS("/NM0","gm")/OS("/NM0","gds")
Click Apply.
The value of id is also needed. After adding it, manually enter it and divide it by the variable W, which is the
current density mentioned earlier.
1 OS("/NM0","id")/VAR("W")
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Of course, we can also generate output parameters directly with code. The reason why this paragraph is not
written in the front is to let us use this calculator proficiently. When doing other simulations in the future, the
calculator is a tool that must be used.
When you are proficient, you can directly add the following code in the output settings. Note that the name of the
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transistor here is NM0. If it is another name, remember to modify the corresponding part of the code.
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In addition, we can also scan out the overdrive voltage Vov and the channel length modulation factor λ, and the
following code can be used directly. The use of VGS parameters is also mentioned in some documents, and it is
also released in the last line.
parameter sweep
Set parameter sweep
Scan the gate length L from 200n to 2200n (in fact, it can be less, 1000n is enough, and the general design
does not use such a large L).
Simulation results
After clicking Simulate, two sets of curves are generated. Left is id/W, right is gain.
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When designing, adding a Marker can get the corresponding id/W and gain values under a certain gm/id.
save results
We can choose to save the results so that we don't have to do the simulation settings next time.
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The next time you open the emulator, just load it directly.
P-MOS Simulation
Schematic
Design schematic diagram, for the P tube, the body effect is not considered for the time being, and the B
terminal is directly connected to VDD.
Simulation settings
Like the N tube, set the initial value of the variable, set the dc simulation, and finally set the output.
Attach the two codes for the output parameters. Note that the result of id/W is a negative value, so the absolute
value function of abs is added.
There are also three parameters, pay attention to the abs absolute value function among them
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After setting the emulator, you can compare it with your own.
Simulation results
After setting the parameter sweep, the simulation result is obtained, and then the Y axis of the id/W curve is set
as the log coordinate.
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content
transconductance gm
gm/id
gain gian
Bandwidth fT
Noise Vn
current density
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calculation steps
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Curve simulation
N-MOS Simulation
Schematic
Simulation settings
parameter sweep
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