1

8-bit Addition

8-bit Subtraction

8-bit Multiplication

8-bit Division

Increment

Decrement

Decimal Adjust

2
Function: Addition
Description:
ADD adds the byte variable indicated to the Accumulator, leaving the result in
the Accumulator.
The carry and auxiliary-carry flags are set, respectively, if there is a carry-out
from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the
carry flag indicates an overflow occurred.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit
7 but not bit 6; otherwise OV is cleared. When adding signed integers, OV
indicates a negative number produced as the sum of two positive operands, or
a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-
indirect, or immediate.

3
Example:
The Accumulator holds 0C3H (11000011B) and register R0 holds 0AAH
(10101010B). The instruction,
ADD A , R0
will leave 6DH (01101101B) in the Accumulator with the AC flag cleared
and both the Carry flag and OV set to 1.

ADD A , Rn
Bytes: 1
Cycles: 1
Encoding: 0 0 1 0 1 r r r
Operation: (A)  (A) + (Rn)

4
ADD A , direct
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 0 1 0 1 direct address
Operation: (A)  (A) + (direct)
ADD A , @Ri
Bytes: 1
Cycles: 1
Encoding: 0 0 1 0 0 1 1 i
Operation: (A)  (A) + ((Ri))
ADD A , #data
Bytes: 2
Cycles: 1
Encoding: 0 0 1 0 0 1 0 0 immediate data
Operation: (A)  (A) + #data

5
Function:
Add with Carry
Description:
ADDC simultaneously adds the byte variable indicated, the carry flag and the
Accumulator contents, leaving the result in the Accumulator.
The carry and auxiliary-carry flags are set, respectively, if there is a carry-out
from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the
carry flag indicates an overflow occurred.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit
7 but not out of bit 6; otherwise OV is cleared. When adding signed integers,
OV indicates a negative number produced as the sum of two positive operands,
or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-
indirect, or immediate.

6
Example:
The Accumulator holds 0C3H (11000011B) and register R0 holds
0AAH (10101010B) with the carry flag set. The instruction,
ADDC A , R0
will leave 6EH (01101110B) in the Accumulator with AC cleared and
both the Carry flag and OV set to 1.
ADDC A , Rn
Bytes: 1
Cycles: 1
Encoding: 0 0 1 1 1 r r r
Operation: (A)  (A) + (C) + (Rn)

7
ADDC A , direct
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 0 1 0 1 direct address
Operation: (A)  (A) + (C) + (direct)
ADDC A , @Ri
Bytes: 1
Cycles: 1
Encoding: 0 0 1 1 0 1 1 i
Operation: (A)  (A) + (C) + ((Ri))
ADDC A , #data
Bytes: 2
Cycles: 1
Encoding: 0 0 1 1 0 1 0 0 immediate data
Operation: (A)  (A) + (C) + #data

8
Function:

Subtract with borrow

Description:

SUBB subtracts the indicated variable and the carry flag together
from the Accumulator, leaving the result in the Acc.

SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and
clears C otherwise. (If C was set before executing a SUBB instruction,
this indicates that a borrow was needed for the previous step in a
multiple precision subtraction, so the carry is subtracted from the
Acc. along with the source.)

9
AC is set if a borrow is needed for bit 3, and cleared otherwise.
OV is set if a borrow is needed into bit 6, but not into bit 7, or
into bit 7, but not bit 6.
When subtracting signed integers OV indicates a negative
number produced when a negative value is subtracted from a
positive value, or a positive result when a positive number is
subtracted from a negative number.

The source operand allows four addressing modes: register,

direct, register-indirect, or immediate.
10
Example:
The Accumulator holds 0C9H (11001001B), register 2 holds 54H
(01010100B), and the carry flag is set. The instruction
SUBB A , R2
will leave the value 74H (01110100B) in the Accumulator, with the
carry flag and AC cleared but OV set.
Notice that 0C9H minus 54H is 75H The difference between this and
the above result is due to the carry (borrow) flag being set before
the operation. If the state of the carry is not known before starting a
single or multiple-precision subtraction, it should be explicitly
cleared by a CLR C instruction

11
SUBB A , Rn
Bytes: 1
Cycles: 1
Encoding: 1 0 0 1 1 r r r
Operation: SUBB
(A)  (A) – (C) – (Rn)
SUBB A , direct
Bytes: 2
Cycles: 1
Encoding: 1 0 0 1 0 1 0 1 direct address
Operation: SUBB
(A)  (A) – (C) – (direct)

12
SUBB A , @Ri
Bytes: 1
Cycles: 1
Encoding: 1 0 0 1 0 1 1 i
Operation: SUBB
(A)  (A) – (C) – ((Ri))
SUBB A , #data
Bytes: 2
Cycles: 1
Encoding: 1 0 0 1 0 1 0 0 immediate data
Operation: SUBB
(A)  (A) – (C) – (#data)

13
Function:

Increment

Description:

INC increments the indicated variable by 1. An original value of

0FFH will overflow to 00H. No flags are affected. Three
addressing modes are allowed: register, direct, or register-
indirect. Note: When this instruction is used to modify an
output port, the value used as the original port data will be
read from the output data latch, not the input pins.

14
Example:
Register 0 contains 7EH (01111110B). Internal RAM locations
7EH and 7FH contain 0FFH and 40H, respectively. The
instruction sequence,
INC @R0
INC R0
INC @R0
will leave register 0 set to 7FH and internal RAM locations 7EH
and 7FH holding (respectively) 00H and 41H.

15
INC A
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 1 0 0
Operation: INC
(A)  (A) + 1
INC Rn
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 1 r r r
Operation: INC
(Rn)  (Rn) + 1

16
INC direct
Bytes: 2
Cycles: 1
Encoding: 0 0 0 0 0 1 0 1 direct address
Operation: INC
(direct)  (direct) + 1
INC @Ri
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 1 1 i
Operation: INC
((Ri))  ((Ri)) + 1

17
Function:
Increment Data Pointer
Description:
Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 216) is
performed; an overflow of the low-order byte of the data pointer (DPL)
from 0FFH to 00H will increment the high-order byte (DPH). No flags are
affected.
This is the only 16-bit register which can be incremented.
Example:
Registers DPH and DPL contain 12H and 0FEH, respectively. The instruction
sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and 01H.

18
INC DPTR
Bytes: 1
Cycles: 2
Encoding: 1 0 1 0 0 0 1 1
Operation: INC
(DPTR)  (DPTR) + 1

19
Function:

Decrement

Description:

The variable indicated is decremented by 1. An original value

of 00H will underflow to 0FFH. No flags are affected. Four
operand addressing modes are allowed: accumulator, register,
direct, or register-indirect. Note: When this instruction is used
to modify an output port, the value used as the original data
will be read from the output data latch, not the input pin.

20
Example:
Register R0 contains 7FH (01111111B). Internal RAM locations
7EH and 7FH contain 00H and 40H, respectively. The
instruction sequence,
DEC @R0
DEC R0
DEC @R0
will leave register 0 set to 7EH and internal RAM locations 7EH
and 7FH set to 0FFH and 3FH.

21
DEC A
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 0 1 0 0
Operation: DEC
(A)  (A) – 1
DEC Rn
Bytes: 1
Cycles: 1
Encoding: 0 0 0 1 1 r r r
Operation: DEC
(Rn)  (Rn) – 1

22
DEC direct
Bytes: 2
Cycles: 1
Encoding: 0 0 0 1 0 1 0 1 direct address
Operation: DEC
(direct)  (direct) – 1
DEC @Ri
Bytes: 1 There is no
Cycles: 1 instruction to
Encoding: 0 0 0 1 0 1 1 i Decrement DPTR
Operation: DEC
((Ri))  ((Ri)) – 1

23
Function:

Multiply

Description:

MUL AB multiplies the unsigned eight-bit integers in the

Accumulator and register B. The low-order byte of the sixteen-
bit product is left in the Accumulator, and the high-order byte
in B. If the product is greater than 255 (0FFH) the overflow flag
is set; otherwise it is cleared. The carry flag is always cleared.

24
Example:

Originally the Accumulator holds the value 80 (50H). Register B

holds the value 160 (0A0H).The instruction,

MUL AB

will give the product 12,800 (3200H), so B is changed to 32H

(00110010B) and the Accumulator is cleared. The overflow
flag is set, carry is cleared.

25
MUL AB
Bytes: 1
Cycles: 4
Encoding: 1 0 1 0 0 1 0 0
Operation: MUL
(A)7-0  (A) x (B)
(B)15-8

26
Function:
Divide

Description:
DIV AB divides the unsigned eight-bit integer in the Acc. by the
unsigned 8-bit integer in register B. The Acc. receives the
integer part of the quotient; register B receives the integer
remainder. The carry and OV flags will be cleared. Exception: if
B had originally contained 00H, the values returned in the Acc.
and B will be undefined and the overflow flag will be set. The
carry flag is cleared in any case.

27
Example:

The Accumulator contains 251 (0FBH or 11111011B) and B

contains 18 (12H or 00010010B). The instruction,

DIV AB

will leave 13 in the Accumulator (0DH or 00001101B) and the

value 17 (11H or 00010001B) in B, since 251 = (13 x 18) + 17.
Carry and OV will both be cleared.

28
DIV AB
Bytes: 1
Cycles: 4
Encoding: 1 0 0 0 0 1 0 0
Operation: DIV
(A)15-8  (A)/(B)
(B)7-0

29
Function:
Decimal-adjust Accumulator for Addition

Description:
DA A adjusts the 8-bit value in the Acc. resulting from the
earlier addition of two variable (each in packed-BCD format),
producing two 4-bit digits. Any ADD or ADDC instruction may
have been used to perform the addition.

30
If Acc. bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC = 1,
then 6 (0110) is added to the Acc., producing the proper BCD digit in the
low-order nibble. This internal addition would set the carry flag if a carry-
out of the low-order four-bit field propagated through all high-order bits,
but it would not clear the carry flag otherwise.

If the carry flag is now set, or if the four high-order bits now exceed nine
(1010xxx-111xxxx), these high-order bits are incremented by six, producing
the proper BCD digit in the high-order nibble. Again, this would set the
carry flag if there was a carry-out of the high-order bits, but wouldn’t clear
the carry. The carry flag thus indicates if the sum of the original two BCD
variables is greater than 100, allowing multiple precision decimal addition.
OV is not affected.

31
 All of this occurs during the one instruction cycle. Essentially,
this instruction performs the decimal conversion by adding
00H, 06H, 60H, or 66H to the Accumulator, depending on
initial Accumulator and PSW conditions.

Note:
DA A cannot simply convert a hexadecimal number in the
Accumulator to BCD notation, nor does DA A apply to decimal
subtraction.

32
Example:
The Acc. holds the value 56H (01010110B) representing the packed BCD
digits of the decimal number 56. Register 3 contains the value 67H
(01100111B) representing the packed BCD digits of the decimal number
67. The carry flag is set.. The instruction sequence,
ADDC A,R3
DA A
0101 0110 = A
0110 0111 = R3
0000 0001 = CY
1011 1110
will first perform a standard two’s-complement binary addition, resulting in
the value 0BEH (10111110B) in the Acc. The carry and auxiliary carry flags
will be cleared.

33
The Decimal Adjust instruction will then alter the Accumulator
to the value 24H (00100100B), indicating the packed BCD
digits of the decimal number 24, the low-order two digits of
the decimal sum of 56, 67, and the carry-in.

The carry flag will be set by the Decimal Adjust instruction,

indicating that a decimal overflow occurred. The true sum 56,
67, and 1 is 124.

34
DA A
Bytes: 1
Cycles: 1
Encoding: 1 1 0 1 0 1 0 0
Operation: DA
–contents of Accumulator are BCD
IF [[(A3-0) > 9] or [(AC) = 1]]
– THEN (A3-0)  (A3-0) + 6
– ELSE (A3-0)  (A3-0)
AND
IF [[(A7-4) > 9] or [(C) = 1]]
– THEN (A7-4)  (A7-4) + 6
– ELSE (A7-4)  (A7-4)

35
36
AND

OR

Ex-OR

NOT

Compare

Rotate

37
Function:
Logical-AND for byte variables

Description:
ANL performs the bit wise logical-AND operation between the variables
indicated and stores the results in the destination variable. No flags are
affected. The two operands allow six addressing mode combinations.
When the destination is the Accumulator, the source can use register,
direct, register-indirect, or immediate addressing; when the destination is
a direct address, the source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value
used as the original port data will be read from the output data latch, not
the input pins.
38
Example:
If the Accumulator holds 0C3H (11000011B) and register 0 holds 55H
(01010101B) then the instruction,
ANL A,R0

will leave 41H (01000001B) in the Accumulator.

When the destination is a directly addressed byte, this instruction will clear
combinations of bits in any RAM location or hardware register. The mask
byte determining the pattern of bits to be cleared would either be a
constant contained in the instruction or a value computed in the
Accumulator at run-time. The instruction,
ANL P1,#01110011B

will clear bits 7, 3, and 2 of output port 1.

39
ANL A,Rn
Bytes: 1
Cycles: 1
Encoding: 0 1 0 1 1 r r r
Operation: (A)  (A) ~ (Rn)
ANL A,direct
Bytes: 2
Cycles: 1
Encoding: 0 1 0 1 0 1 0 1 direct address
Operation: (A)  (A) ~ (direct)
ANL A,@Ri
Bytes: 1
Cycles: 1
Encoding: 0 1 0 1 0 1 1 i
Operation: (A)  (A) ~ ((Ri))

40
ANL A,#data
Bytes: 2
Cycles: 1
Encoding: 0 1 0 1 0 1 0 0 immediate data
Operation: (A)  (A) ~ #data
ANL direct,A
Bytes: 2
Cycles: 1
Encoding: 0 1 0 1 0 0 1 0 direct address
Operation: (A)  (direct) ~ (A)
ANL direct,#data
Bytes: 3
Cycles: 2
Encoding: 0 1 0 1 0 0 1 1 direct address immediate data
Operation: (direct)  (direct) ~ #data

41
Function:
Logical-OR for byte variables

Description:
ORL performs the bit wise logical-OR operation between the indicated
variables, storing the results in the destination byte. No flags are affected.
The two operands allow six addressing mode combinations. When the
destination is the Accumulator, the source can use register, direct, register-
indirect, or immediate addressing; when the destination is a direct
address, the source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value
used as the original port data will be read from the output data latch, not
the input pins.
42
Example:
If the Accumulator holds 0C3H (11000011B) and R0 holds 55H
(01010101B) then the instruction,
ORL A,R0

will leave the Accumulator holding the value 0D7H (11010111B). When the
destination is a directly addressed byte, the instruction can set
combinations of bits in any RAM location or hardware register. The pattern
of bits to be set is determined by a mask byte, which may be either a
constant data value in the instruction or a variable computed in the
Accumulator at run-time. The instruction,
ORL P1,#00110010B

will set bits 5, 4, and 1 of output Port 1.

43
ORL A,Rn
Bytes: 1
Cycles: 1
Encoding: 0 1 0 0 1 r r r
Operation: (A)  (A) ! (Rn)
ORL A,direct
Bytes: 2
Cycles: 1
Encoding: 0 1 0 0 0 1 0 1 direct address
Operation: (A)  (A) ! (direct)
ORL A,@Ri
Bytes: 1
Cycles: 1
Encoding: 0 1 0 0 0 1 1 i
Operation: (A)  (A) ! ((Ri))

44
ORL A,#data
Bytes: 2
Cycles: 1
Encoding: 0 1 0 0 0 1 0 0 immediate data
Operation: (A)  (A) ! #data
ORL direct,A
Bytes: 2
Cycles: 1
Encoding: 0 1 0 0 0 0 1 0 direct address
Operation: (direct)  (direct) ! (A)
ORL direct,#data
Bytes: 3
Cycles: 2
Encoding: 0 1 0 0 0 0 1 1 direct address immediate data
Operation: (direct)  (direct) ! #data

45
Function:
Logical Exclusive-OR for byte variables

Description:
XRL performs the bitwise logical Exclusive-OR operation between the
indicated variables, storing the results in the destination. No flags are
affected. The two operands allow six addressing mode combinations.
When the destination is the Accumulator, the source can use register,
direct, register-indirect, or immediate addressing; when the destination is
a direct address, the source can be the Accumulator or immediate data.
Note: When this instruction is used to modify an output port, the value
used as the original port data will be read from the output data latch, not
the input pins.
46
Example:
If the Accumulator holds 0C3H (11000011B) and register 0 holds 0AAH
(10101010B) then the instruction,
XRL A,R0

will leave the Accumulator holding the value 69H (01101001B).

When the destination is a directly addressed byte, this instruction can
complement combinations of bits in any RAM location or hardware
register. The pattern of bits to be complemented is then determined by a
mask byte, either a constant contained in the instruction or a variable
computed in the Accumulator at run-time. The instruction,
XRL P1,#00110001B

will complement bits 5, 4, and 0 of output Port 1.

47
XRL A,Rn
Bytes: 1
Cycles: 1
Encoding: 0 1 1 0 1 r r r
Operation: (A)  (A) xor (Rn)
XRL A,direct
Bytes: 2
Cycles: 1
Encoding: 0 1 1 0 0 1 0 1 direct address
Operation: (A)  (A) xor (direct)
XRL A,@Ri
Bytes: 1
Cycles: 1
Encoding: 0 1 1 0 0 1 1 i
Operation: (A)  (A) xor (Ri)

48
XRL A,#data
Bytes: 2
Cycles: 1
Encoding: 0 1 1 0 0 1 0 0 immediate data
Operation: (A)  (A) xor #data
XRL direct,A
Bytes: 2
Cycles: 1
Encoding: 0 1 1 0 0 0 1 0 direct address
Operation: (direct)  (direct) xor (A)
XRL direct,#data
Bytes: 3
Cycles: 2
Encoding: 0 1 1 0 0 0 1 1 direct address immediate data
Operation: XRL (direct)  (direct) xor #data

49
Function:
Clear Accumulator
Description:
The Accumulator is cleared (all bits reset to zero). No flags are affected.
Example:
The Accumulator contains 5CH (01011100B). The instruction,
CLR A
will leave the Accumulator set to 00H (00000000B).

Bytes: 1
Cycles: 1
Encoding: 1 1 1 0 0 1 0 0
Operation: CLR
(A)  0

50
Function:
Complement Accumulator
Description:
Each bit of the Accumulator is logically complemented (one’s
complement). Bits which previously contained a one are changed to a zero
and vice-versa. No flags are affected.
Example:
The Accumulator contains 5CH (01011100B). The instruction,
CPL A
will leave the Accumulator set to 0A3H (10100011B).
Bytes: 1
Cycles: 1
Encoding: 1 1 1 1 0 1 0 0
Operation: CPL
(A)  /(A)

51
Function: Rotate Accumulator Left
Description:
The eight bits in the Acc. are rotated one bit to the left. Bit 7 is rotated into the
bit 0 position. No flags are affected.
Example:
The Acc. holds the 0C5H (11000101B). The instruction,
RL A
leaves the Accumulator holding the value 8BH (10001011B) with the carry
unaffected.
Bytes: 1
Cycles: 1
Encoding: 0 0 1 0 0 0 1 1 7 6 5 4 3 2 1 0

Operation: RL
(An+1)  (An), n = 0 – 6
(A0)  (A7)

52
Function:
Rotate Accumulator Left through the Carry flag
Description:
The eight bits in the Accumulator and the carry flag are together rotated
one bit to the left. Bit 7 moves into the carry flag; the original state of the
carry flag moves into the bit 0 position. No other flags are affected.
Example:
The Accumulator holds the value 0C5H (11000101B), and the carry is zero.
The instruction,
RLC A
leaves the Acc. holding the value 8AH (10001010B) with the carry set.

53
RLC A
Bytes: 1

Cycles: 1

Encoding: 0 0 1 1 0 0 1 1

Operation: RLC
CY
(An+1)  (An), n = 0 – 6

(A0)  (C) 7 6 5 4 3 2 1 0

(C)  (A7)

54
Function: Rotate Accumulator Right
Description:
The eight bits in the Acc. are rotated one bit to the right. Bit 0 is rotated
into the bit 7 position. No flags are affected.
Example:
The Acc. holds the 0C5H (11000101B). The instruction,
RR A
leaves Acc. holding the value 0E2H (11100010B) with the carry unaffected.
Bytes: 1
Cycles: 1
Encoding: 0 0 0 0 0 0 1 1 7 6 5 4 3 2 1 0

Operation: RR
(An)  (An+1), n = 0 – 6
(A7)  (A0)
55
Function:
Rotate Accumulator Right through the Carry flag
Description:
The eight bits in the Accumulator and the carry flag are together rotated
one bit to the right. Bit 0 moves into the carry flag; the original state of the
carry flag moves into the bit 7 position. No other flags are affected.
Example:
The Accumulator holds the value 0C5H (11000101B), and the carry is zero.
The instruction,
RRC A
leaves the Acc. holding the value 62 (01100010B) with the carry set.

56
RRC A
Bytes: 1

Cycles: 1

Encoding: 0 0 0 1 0 0 1 1

Operation: RRC
CY
(An)  (An+1), n = 0 – 6

(A7)  (C) 7 6 5 4 3 2 1 0

(C)  (A0)

57
Function: Swap nibbles within the Accumulator
Description:
SWAP A interchanges the low- and high-order nibbles (four-bit fields) of
the Accumulator (bits 3-0 and bits 7-4). The operation can also be thought
of as a four-bit rotate instruction. No flags are affected.
Example:
The Accumulator holds the value 0C5H (11000101B). The instruction,
SWAP A
leaves the Accumulator holding the value 5CH (01011100B).
Bytes: 1
Cycles: 1
Encoding: 1 1 0 0 0 1 0 0
Operation: SWAP
(A3-0)  (A7-4)
58
Decrement the Contents of DPTR register.
Add byte in external RAM location 02CDh to internal RAM location 19h; put
the result in to external RAM location 00C0h(LSB) and 00C1h(MSB).
Increment the content of internal RAM location 13h, 14h and 15h.
Square the contents of R5 and store the result in 36h (LSB) and 37h (MSB).
Invert the data on Port 0 (P0) and write data to Port 1 (P1).
Swap the nibble of R0 and R1 so that the low nibble of R0 swaps with the high
nibble of R1 and high nibble of R0 swaps with low nibble of R1.
XOR the number with whatever is in an Accumulator so that the result is 0FFh.
Treat R0 and R1 as 16-bit register, and rotate them one place to the left; bit 7
of R0 become bit 0 of R1, bit 7 of R1 become bit 0 of R0.
Complement the low nibble of internal RAM location 2Ah.