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8255

The document discusses interfacing concepts and the 8255 programmable peripheral interface chip. It describes how the 8255 allows data transfer between a microprocessor and external devices using either memory-mapped or I/O-mapped interfacing. The 8255 has 3 8-bit ports that can be configured as inputs or outputs. It operates in either bit set/reset or I/O mode, with I/O mode having sub-modes 0, 1, and 2 that determine handshake capabilities and direction of individual ports.

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0% found this document useful (0 votes)
165 views

8255

The document discusses interfacing concepts and the 8255 programmable peripheral interface chip. It describes how the 8255 allows data transfer between a microprocessor and external devices using either memory-mapped or I/O-mapped interfacing. The 8255 has 3 8-bit ports that can be configured as inputs or outputs. It operates in either bit set/reset or I/O mode, with I/O mode having sub-modes 0, 1, and 2 that determine handshake capabilities and direction of individual ports.

Uploaded by

satyanarayana12
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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8255A

Basic Interfacing Concept

• Any application of Microprocessor Based system


Requires the transfer of data between external circuitry
to the Microprocessor and Microprocessor to the
External circuitry. User can give information (i.e. input)
to the Microprocessor using keyboard and user can see
the result or output information from the
Microprocessor with the help of display.

• Hence interfacing is used to exchange information


between two different applications/devices.
Memory Mapped I/O

• Device address is of 16 Bit. means A0 to A15 lines are


used to generate device address.
• MEMR and MEMW control signals are used to control
read and write I/O operations.
• Data transfer is between Any register and I/O device.
• Maximum number of I/O devices are 65536.
• Decoding 16 bit address may requires more hardware.
• For e.g. MOV R M, ADD M,CMP M etc.
INTERFACING IN MEMORY MAPPED I/O
A15
A14 D0 D0
D7
A13 D7 PA0
A12 A0 A0 PA7
A1
A11
A10
A1
8255
MEMR PB0
RD
A9
MEMW WR PB7
A8
A7 RESET OUT RESET
PC0
A6
A5 PC7
CS
A4
A3
A2
I/O Mapped I/O

• Device address is of 8 Bit. means A0 to A7 or A8 to A15


lines are used to generate device address.
• IOR and IOW control signals are used to control read
and write I/O operations.
• Data transfer is between Accumulator and I/O device.
• Maximum number of I/O devices are 256.
• Decoding 16 bit address may requires less hardware.
• For e.g. IN, OUT etc.
INTERFACING IN I/O MAPPED I/O

D0 D0
D7
D7 PA0
A7
A0 A0 PA7
A1
A6 A1
8255
IOR RD PB0
A5
IOW WR PB7
A4
RESET OUT RESET PC0
A3
PC7
A2
CS
8255 PPI
• The INTEL 8255 is a 40 pin IC having total 24 I/O pins.
consisting of 3 numbers of 8 –bit parallel I/O ports
(i.e. PORT A, PORT B,PORT C). The ports can be
programmed to function either as a input port or as
a output port in different operating modes. It
requires 4 internal addresses and has one logic LOW
chip select pin. Its main functions are to interface
peripheral devices to the microprocessor. Basically
used for parallel data transfer. operates in mainly
two modes.
• (1) Bit Set Reset Mode (BSR Mode).
• (2) I/O Mode.
Block Diagram of 8255 PPI
POWER +5V PA
SUPPLIES Ground GROUP A
GROUP A
PORT A (8)
CONTROL PA7-PA0
Bidirectional
Data Bus
D7- D0 GROUP A PCU
DATA BUS
BUFFER PORT C
8 Bit UPPER (4) PC7-PC4
Internal
Data Bus
GROUP B PCL
PORT C
LOWER (4) PC3-PC0
READ/
RD
WR WRITE
GROUP B PB
A0 CONTROL GROUP B
A1
LOGIC CONTROL
RESET PORT B (8)
PB7-PB0
cs
Function of Blocks
BLOCK FUNCTION OF BLOCK

It is used to interface the internal data bus of 8255 to the system data bus by
Data Bus Buffer reading and writing operations.

It accepts the input from the address bus and issues commands to the individual
Read/write group blocks. also issues appropriate enabling signals to access the required
Control logic data/control words/status words.

It can be programmed in three modes Mode0, Mode1 and Mode2.


Port A

It can be programmed in three modes Mode0 and Mode1.


Port B

It can be programmed for Bit Set/reset operation.


Port C
Pin Diagram of 8255 PPI

8255 Pin
Diagram
Function of Pins
PIN FUNCTION OF PIN

These are bidirectional, tri-state data bus lines are connected to the system data bus. They
are used to transfer data and control word from microprocessor (8085) to 8255 or receive
D0-D7 (Data Bus) data or status word from 8255 to the 8085.

These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data
from input device. It functions as an 8 Bit data output latch/buffer when used in output
PA0-PA7 (Port A) mode and as an 8 Bit data input latch/buffer when used in input mode.

These are 8 Bit bidirectional I/O pins used to send data to output device and to receive data
from input device. It functions as an 8 Bit data output latch/buffer when used in output
PB0-PB7 (Port B) mode and as an 8 Bit data input latch/buffer when used in input mode.
Function of Pins
PIN FUNCTION OF PIN

These are 8 bit bidirectional I/O pins divided into two groups PCL (PC3-PC) and PCU (PC7-
PC4).these groups can individually transfer data in or out when programmed for simple I/O,
PC0-PC7 and used as handshake signals when programmed for handshake or
(Port C) bidirectional modes.

When this pin is low, the CPU can read data in the ports or the status word through the data
RD bus buffer.

When this pin is low, the CPU can write data on the ports or in the control register through
WR the data bus buffer.

This pin can be enabled for data transfer operation between the CPU and 8255.
CS

This pin is used to reset 8255.i.e control register gets cleared and all the ports are set to the
RESET input mode.
Function of Pins
PIN FUNCTION OF PIN

A0-A1 The selection of input port and control word register is done by using A0 and A1 pins In
conjunction with RD and WR pins.

A1 A0 RD WR CS Operations

0 0 0 1 0 PORT A TO DATA BUS

0 1 0 1 0 PORT B TO DATA BUS

1 0 0 1 0 PORT C TO DATA BUS

0 0 1 0 0 DATA BUS TO PORT A

0 1 1 0 0 DATA BUS TO PORT B

1 0 1 0 0 DATA BUS TO PORT C

1 1 1 0 0 DATA BUS TO CONTROL REGISTER

x x x x 1 DATA BUS TRI STATED

1 1 0 1 0 ILLEGAL CONDITION

x x 1 1 0 DATA BUS TRI STATED


Operating Modes Of 8255
• There are two main operational modes of 8255:
(1) Input/output mode,
(2) Bit set/reset mode (BSR Mode).

I/O mode again classified into three types


• (1) Mode 0,
• (2) Mode 1,
• (3) Mode 2.
MODE 0
• In this mode, the ports can be used for simple input/output operations
without handshaking.
• If both port A and B are initialized in mode 0, the two halves of port C can
be either used together as an additional 8-bit port, or they can be used as
individual 4-bit ports.
• Since the two halves of port C are independent, they may be used such that
one-half is initialized as an input port while the other half is initialized as an
output port.

The mode 0 has following features:

• O/p are latched.


• I/p are buffered not latched.
• Port do not have handshake or interrupt capability.
MODE 1
• When we wish to use port A or port B for handshake (strobed) input or
output operation, we initialize that port in mode 1.
• For port B in this mode (irrespective of whether is acting as an input port
or output port), PC0, PC1 and PC2 pins function as handshake lines.

The mode 1 has following features:


• Two ports i.e. port A and B can be use as 8-bit i/o port.
• Each port uses three lines of port c as handshake signal and remaining two
signals can be function as i/o port.
• Interrupt logic is supported.
• Input and Output data are latched.
MODE 2
• Only group A can be initialized in this mode.
• Port A can be used for bidirectional handshake data
transfer. This means that data can be input or output on
the same eight lines (PA0 - PA7).
• Pins PC3 - PC7 are used as handshake lines for port A.
• The remaining pins of port C (PC0 - PC2) can be used as
input/output lines if group B is initialized in mode 0.
• In this mode, the 8255 may be used to extend the system
bus to a slave microprocessor.
Control Word Format in I/O Mode
0 D6 D5 D4 D3 D2 D1 D0 GROUP B
PORT C (LOWER) 1=I/P,
0=O/P

PORT B
1=I/P, 0=O/P

MODE SELECTION
0 = MODE 0
1 = MODE 1

GROUP A
PORT C (UPPER) 1=I/P,
0=O/P
PORT A
1=I/P, 0=O/P
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X = MODE 2
MODE SET FLAG
1 = ACTIVE
Control Word Format in BSR Mode
0 D6 D5 D4 D3 D2 D1 D0
BIT SET/RESET
1 = SET
2 = RESET

DON’T CARE

BIT SELECT

0 1 2 3 4 5 6 7

0 1 0 1 0 1 0 1 B0

0 0 1 1 0 0 1 1 B1

0 0 0 0 1 1 1 1 B2

BIT SET/RESET FLAG


0 = ACTIVE
Write a program to initialize 8255 in the configuration
below.(assume address of the CW register as 83H).
(1) Port A: simple input (2) Port B: simple output
(3) Port CL: output (4)Port CU: input

• Solution:

1 0 0 1 1 0 0 0
= 98H
Program:
MVI A,98H ; LOAD CONTROL WORD

OUT 83H ; SEND CONTROL WORD


Write a program to initialize 8255 in the configuration
below.(assume address of the CW register as 23H).
(1) Port A: output with handshake
(2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input

• Solution:

1 0 1 0 1 1 1 0

= AEH
Program:
MVI A,AEH ; LOAD CONTROL WORD

OUT 23H ; SEND CONTROL WORD


Find the control word for the register arrangement
of the ports of intel 8255 for mode 0 operation.
• Port A: Output, Port B: Output,
• Port CU: Output, Port CL: Output

Solution:

1 0 0 0 0 0 0 0
= 80H

The control word register for the above ports of intel


8255 is 80H.
Find the control word for the register arrangement
of the ports of intel 8255 for mode 0 operation.
• Port A: Input, Port B: Input,
• Port CU: Input, Port CL: Input

Solution:

1 0 0 1 1 0 1 1
= 9BH

The control word register for the above ports of intel


8255 is 9BH.

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