PART - B

DIGITAL DESIGN
VLSI LAB MANUAL (18ECL77) 2021-22

PART B: ASIC – Digital Design Flow

PROCEDURE FOR CREATING DIGITAL SIMULATION USING VERILOG AND CADENCE
DIGITAL TOOL

Open Terminal Window and use the following commands

Procedure for Simulation:

1. Change directory to Cadence_Digital_labs/Workarea/Inverter using commands:

>csh
>source /home/install/cshrc

2. Type the programs design code and testbench code using editor in workarea folder and save

Create the design file (Verilog module) using editor gedit

>gedit filename.v
The file name can be changed with respect to the experiments.

Create the testbench file (Verilog module) using editor gedit

>gedit tb_filename.v
The testbench file name can be changed with respect to the design file.

3. Compile the source Descriptions: (i) Compile the Inverter description with the -messages
option:
>ncvlog –mess (name of the file) (name of the testbench file)

Example: >ncvlog -mess inv.v tb_inv.v

Note: Check out for error and warnings. If any, then go back to text editor and edit and the compile

4. Elaborate the top level Design using the command:

>ncelab -mess -access +rwc (name of the testbench file without file type)

Example: >ncelab -mess –access +rwc tb_inv //Do not include file type (.v) for testbench
file

5. Simulate the Top-Level Design in Non GUI mode

>ncsim -mess -gui (name of the testbench file)

Example:>ncsim -mess -gui tb_inv

Now a console and Design Browser windows of Simvision are opened and click on the
waveform button in the toolbar to send the selected objects to waveform window.

Waveform Window opens and Press run to run the simulation for a time period specified in
the time field.

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Procedure for Synthesis using Cadence Tool

The Verilog code, technology library and the constraint files are input to the logical synthesis.
The tool will generate the gate level netlist and gives the output as: gatelevel schematic and the
report of area, power and timing.

6. Create a file named Contraints_sdc.sdc

The timing constraints are defined in this file. Example of one such file is as shown –

create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]

set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "A"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "B"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "sum"] -clock [get_clocks "clk"]
There are three different parts in the constraint file:

a. Clock definition and clock constraints –

Clock definition
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clock"]
Clock rise time
set_clock_transition -rise 0.1 [get_clocks " clk "]
Clock fall time
set_clock_transition -fall 0.1 [get_clocks " clk "]
Uncertainties of Clock
set_clock_uncertainty 1.0 [get_ports " clk "]
b. Input port timing constraints –
set_input_delay -max 1.0 [get_ports " A"] -clock [get_clocks " clk "]
Input port delay
set_input_delay -max 1.0 [get_ports " B"] -clock [get_clocks " clk "]
Input port delay
c. Output port timing constraints –
Output port delay
set_output_delay -max 1.0 [get_ports " sum "] -clock [get_clocks " clk "]

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The port names that are used in the constraint file (bolded) must match with the names
that are used in the Verilog program of the main design module. The constraints are
defined for all the ports in the design.

7. Synthesis the top level design

The verilog file to be synthesized must be copied into this directory.

Copy genus.tcl file that created for simulation in desktop into user directory

genus.tcl file contains

read_lib
read_hdl counter_8bit.v (example)
elaborate
read_sdc top.sdc
syn_generic
write_hdl
syn_map
write_hdl

write_hdl>syn_netlist.v
write_sdc>syn_sdc.sdc

gui_show
report area>area_rep
report gates>gates_rep
report timing>timing_rep

Synthesize the top level design

Open the genus.tcl file in gedit

>gedit genus.tcl

Change the filename in read_hdl

read_hdl {filename.v} // filename.v is the Design code file

{inv.v} // for example inv.v as filename.v

Then invoke genus command

>genus -f genus.tcl

Script file contains the Verilog RTL code, standard library file for a particular technology,

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Introduction to Constraints and Synthesis Commands

SDC
Synopsys Design Constraint (SDC) format is used to specify the design intent, including the timing and
area constraints of the design.
1. create_clock
Usage
create_clock [-add] [-name <clock_name>] -period <value> [-waveform <edge_list>]
<targets>
Options
-add: Adds clock to a node with an existing clock
-name <clock_name>: Clock name of the created clock
-period <value>: Speed of the clock in terms of clock period
-waveform <edge_list>: List of edge values
<targets>: List or collection of targets

Description
Defines a clock. If the -name option is not used; the clock name is the same as the first target in the list
or collection. The clock name is used to refer to the clock in other commands.

The -period option specifies the clock period. It is also possible to use this option to specify a frequency
to define the clock period. This can be done by using -period option followed by either
<frequency>MHz or "<frequency> MHz".

The -waveform option specifies the rising and falling edges (duty cycle) of the clock, and is specified as
a list of two time values: the first rising edge and the next falling edge. The rising edge must be within
the range [0, period]. The falling edge must be within one clock period of the rising edge. The waveform
defaults to (0, period/2).

If a clock with the same name is already assigned to a given target, the create_clock command will
overwrite the existing clock. If a clock with a different name exists on the given target, the create_clock
command will be ignored unless the -add option is used. The -add option can be used to assign multiple
clocks to a pin or port.

If the target of the clock is internal (i.e. not an input port), the source latency is zero by default. If a clock
is on a path after another clock, then it blocks or overwrites the previous clock from that point forward.

Example
# Create a simple 10ns with clock with a 60% duty cycle
create_clock -period 10 -waveform {0 6} -name clk [get_ports clk]

# Create a clock with a falling edge at 2ns, rising edge at 8ns,

# falling at 12ns, etc.
create_clock -period 10 -waveform {8 12} -name clk [get_ports clk]
1. get_clocks
Usage
get_clocks [-nocase] [-nowarn] <filter>
Options
-nocase: Specifies the matching of node names to be case-insensitive
-nowarn: Do not issue warnings messages about unmatched patterns
<filter>: Valid destinations (string patterns are matched using Tcl string matching)

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Description
Returns a collection of clocks in the design. When used as an argument to another command, such as the
-from or -to options of set_multicycle_path, each node in the clock represents all nodes driven by the
clocks in the collection.

2. get_ports
Usage
get_ports [-nocase] [-nowarn] <filter>
Options
-nocase: Specifies case-insensitive node name matching
-nowarn: Do not issue warnings messages about unmatched patterns
<filter>: Valid destinations (string patterns are matched using Tcl string matching)

Description
Returns a collection of ports (design inputs and outputs) in the design.
The filter for the collection is a Tcl list of wildcards, and must follow standard Tcl

3. set_clock_uncertainty
Usage
set_clock_uncertainty [-add] [-fall_from <fall_from_clock>] [-fall_to <fall_to_clock>] [-from
<from_clock>] [-hold] [-rise_from <rise_from_clock>] [-rise_to <rise_to_clock>] [-setup] [-to
<to_clock>] <uncertainty>

Options
-add: Specifies that this assignment is an addition to the clock uncertainty derived by
derive_clock_uncertainty call
-fall_from <fall_from_clock>: Valid destinations (string patterns are matched using Tcl string
matching)
-fall_to <fall_to_clock>: Valid destinations (string patterns are matched using Tcl string matching)
-from <from_clock>: Valid destinations (string patterns are matched using Tcl string matching)
-hold: Specifies the uncertainty value (applies to clock hold or removal checks)
-rise_from <rise_from_clock>: Valid destinations (string patterns are matched using Tcl string
matching)
-rise_to <rise_to_clock>: Valid destinations (string patterns are matched using Tcl string matching)
-setup: Specifies the uncertainty value (applies to clock setup or recovery checks)
(default)
-to <to_clock>: Valid destinations (string patterns are matched using Tcl string matching)
<uncertainty>: Uncertainty

Description
Specifies clock uncertainty or skew for clocks or clock-to-clock transfers. You can specify uncertainty
separately for setup and hold, and can specify separate rising and falling clock transitions. The setup
uncertainty is subtracted from the data required time for each applicable path, and the hold uncertainty is
added to the data required time for each applicable path.

The values for the -from, -to, and similar options are either collections or a Tcl list of wildcards used to
create collections of appropriate types. The values used must follow standard Tcl

When -add option is used, clock uncertainty assignment is treated as an addition to the value calculted
by derive_clock_uncertainty command for a particular clock transfer.

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Note that when -add option is not used and derive_clock_uncertainty is called, user specified clock
uncertainty assignment will take priority. When derive_clock_uncertainty command is not used,
specifying -add option to set_clock_uncertainty command will not have any effect.
4. set_input_delay
Usage
set_input_delay [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin
<name>] [-rise] [-source_latency_included] <delay> <targets>
Options
-add_delay: Add to existing delays instead of overriding them
-clock <name>: Clock name
-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling input delay at the port
-max: Applies value as maximum data arrival time
-min: Applies value as minimum data arrival time
-reference_pin <name>: Specifies a port in the design to which the input delay is relative
-rise: Specifies the rising input delay at the port
-source_latency_included: Specifies that input delay includes added source latency
<delay>: Time value
<targets>: List of input port type objects

Description
Specifies the data arrival times at the specified input ports relative the clock specified by the -clock
option. The clock must refer to a clock name in the design.
Input delays can be specified relative to the rising edge (default) or falling edge (-clock_fall) of the
clock.

If the input delay is specified relative to a simple generated clock (a generated clock with a single
target), the clock arrival times to the generated clock are added to the data arrival time.

Input delays can be specified relative to a port (-reference_pin) in the clock network. Clock arrival times
to the reference port are added to data arrival times. Non-port reference pins are not supported.

Input delays can already include clock source latency. By default the clock source latency of the related
clock is added to the input delay value, but when the -source_latency_included option is specified, the
clock source latency is not added because it was factored into the input delay value.

The maximum input delay (-max) is used for clock setup checks or recovery checks and the minimum
input delay (-min) is used for clock hold checks or removal checks. If only -min or -max (or neither) is
specified for a given port, the same value is used for both.

Separate rising (-rise) and falling (-fall) arrival times at the port can be specified. If only one of -rise and
-fall are specified for a given port, the same value is used for both.

By default, set_input_delay removes any other input delays to the port except for those with the same -
clock, -clock_fall, and -reference_pin combination. Multiple input delays relative to different clocks,
clock edges, or reference pins can be specified using the -add_delay option.

5. set_input_transition
Usage
set_input_transition [-clock <name>] [-clock_fall] [-fall] [-max] [-min] [-rise]
<transition> <ports>
Options

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-clock <name>: Clock name

-clock_fall: Specifies that input delay is relative to the falling edge of the clock
-fall: Specifies the falling output delay at the port
-max: Applies value as maximum data required time
-min: Applies value as minimum data required time
-rise: Specifies the rising output delay at the port
<transition>: Time value
<ports>: Collection or list of input or bidir ports

Description
It only affects PrimeTime analysis or HardCopy II devices. If you set this constraint in TimeQuest the
constraint is written out to the SDC file when you call write_sdc
6. set_output_delay
Usage
set_output_delay [-add_delay] -clock <name> [-clock_fall] [-fall] [-max] [-min]
[-reference_pin <name>] [-rise] [-source_latency_included] <delay> <targets>
Options
-add_delay: Add to existing delays instead of overriding them
-clock <name>: Clock name
-clock_fall: Specifies output delay relative to the falling edge of the clock
-fall: Specifies the falling output delay at the port
-max: Applies value as maximum data required time
-min: Applies value as minimum data required time
-reference_pin <name>: Specifies a port in the design to which the output delay is relative
-rise: Specifies the rising output delay at the port
-source_latency_included: Specifies input delay already includes added source latency
<delay>: Time value
<targets>: Collection or list of output ports

Description
Specifies the data required times at the specified output ports relative the clock specified by the -clock
option. The clock must refer to a clock name in the design.
Output delays can be specified relative to the rising edge (default) or falling edge (-clock_fall) of the
clock.

If the output delay is specified relative to a simple generated clock (a generated clock with a single
target), the clock arrival times to the generated clock are added to the data required time. Output delays
can be specified relative to a port (-reference_pin) in the clock network. Clock arrival times to the
reference port are added to the data required time. Non-port reference pins are not supported.
Output delays can include clock source latency.

By default the clock source latency of the related clock is added to the output delay value, but when the -
source_latency_included option is specified, the clock
source latency is not added because it was factored into the output delay value.
The maximum output delay (-max) is used for clock setup checks or recovery checks and the minimum
output delay (-min) is used for clock hold checks or removal checks. If only one of -min and -max (or
neither) is specified for a given port, the same value is used for both.

Separate rising (-rise) and falling (-fall) required times at the port can be specified. If only one of -rise
and -fall are specified for a given port, the same value is used for both.

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By default, set_output_delay removes any other output delays to the port except for those with the same
-clock, -clock_fall, and -reference_pin combination. Multiple output delays relative to different clocks,
clock edges, or reference pins can be specified using the -add_delay option.

TCL Command:
read_sdc
Usage
read_sdc [-hdl] <file_name>
Options
-hdl: Read SDC commands embedded in HDL
<file_name>: Name of the SDC file

Description
Reads an SDC file with all current constraints and exceptions. If an SDC file is specified, read_sdc only
reads that SDC file. If the -hdl option is specified, read_sdc only reads SDC commands that were
embedded in HDL.

If no arguments are specified, read_sdc reads the default SDC files along with any SDC commands that
were embedded in HDL. If one or more SDC_FILE assignments exists in the QSF, read_sdc reads all of
them in order. Otherwise, read_sdc reads the file <revision>.sdc if it exists.

Example
project_new test
create_timing_netlist
# Read SDC commands from test_constraints.sdc
read_sdc test_constraints.sdc

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Experiment-1
Title: 4-bit Up/Down Asynchronous Reset Counter
Problem Statement: To write Verilog code for asynchronous counter circuit and its test bench for
verification, observe the waveform and synthesize the code with technological library with given
Constraints.

Objective:
Write Verilog code for 4-bit up/down asynchronous reset counter and carry out the following:
a. Verify the functionality using test bench
b. Synthesize the design by setting area and timing constraint. Obtain the gate level netlist, find the
critical path and maximum frequency of operation. Record the area requirement in terms of number of
cells required and properties of each cell in terms of driving strength, power and area requirement.
c. Perform the above for 32-bit up/down counter and identify the critical path, delay of critical path, and
maximum frequency of operation, total number of cells required and total area.

TOOL REQUIRED: Cadence Tool

THEORY:
Asynchronous counters are those whose output is free from the clock signal. Because the flip flops in
asynchronous counters are supplied with different clock signals, there may be delay in producing output.
The required number of logic gates to design asynchronous counters is very less. So they are simple in
design. Another name for Asynchronous counters is “Ripple counters”.

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external
clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous
counters are also called ripple-counters because of the way the clock pulse ripples it way through the
flip-flops.

4-bit up/down Counter with loadable count

A counter is a sequential circuit which is used to count clock pulses. In other words, a counter is a
sequential machine constructed with the help of flip-flops & changes its state according to state diagram.
A 4-bit Up/Down counter counts the clock pulses in ascending as well as descending order and recycle
again from its initial value.
A graphical schematic for a 4-bit up/down counter is depicted in the given figure.

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Timing diagram of Asynchronous Counter

/*Asynchronous counter program Verilog code for design file name counter-4bit.v*/

`timescale 1ns/1ps //Defining a Timescale for Precision

module counter(clk,rst,m,count); //Defining Module and Port List
input clk,rst,m; //Defining Inputs
output reg [3:0]count; //Defining 4-bit Output as Reg type
always@(posedge clk or negedge rst) //The Block is executed when either of positive edge of
clock
begin // or negedge of rst arrives
if(!rst)
count=0; // Both are independent events
if(m) //i.e., Asynchronous Up counter
count=count+1;
else //i.e., Asynchronous Down counter
count=count-1;
end
endmodule

/*Asynchronous counter program Verilog code for testbench-file name tb_counter-4bit.v*/

`timescale 1ns/1ps //Creating Time Scale as in Source Code
module counter_test; //Defining Module Name without Port List
reg clk, rst,m; //Defining I/P as Registers [to Hold Values]
wire [3:0] count; //Defining O/P as Wires [To Probe Waveforms]
initial begin
clk=0; //Initializing Clock and Reset

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rst=0;#25; //All O/P is 4’b0000 from t=0 to t=25ns.

rst=1; //Up-Down counting is allowed at posedge clk
end
initial begin
m=1; //Condition for Up-Count
#600 m=0; //Condition for Down-Count
rst=0;#25;
rst=1;
#500 m=0;
end

counter counter1(clk,m,rst, count); //Instantiation of Source Code

always #5 clk=~clk; //Inverting clk every 5ns
initial
#1400 $finish; //Finishing Simulation at t=1400ns
Endmodule

Waveform:

b) Synthesize the design using Constraints and Analyze reports, critical path and Max Operating
Frequency.

Step 1: Getting Started

Make sure you close out all the Incisive tool windows first.
Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (System Design Constraint) File (.sdc)

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Step 2 : Creating an SDC File

In your terminal type “gedit counter_top.sdc” to create an SDC File if you do not have one.

The SDC File must contain the following commands;

i. create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]

ii. set_clock_transition -rise 0.1 [get_clocks "clk"]
iii.set_clock_transition -fall 0.1 [get_clocks "clk"]
iv.set_clock_uncertainty 0.01 [get_ports "clk"]
v. set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
vi.set_output_delay -max 1.0 [get_ports "count"] -clock [get_clocks "clk"]
i→ Creates a Clock named “clk” with Time Period 2ns and On Time from t=0 to t=1.
ii, iii → Sets Clock Rise and Fall time to 100ps.
iv → Sets Clock Uncertainty to 10ps.
v, vi → Sets the maximum limit for I/O port delay to 1ps.

Step 3 : Performing Synthesis

The Liberty files are present in the below path,

/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/

Synthesis RTL Schematic

The procedure for Simulation and Synthesis remains same as mentioned earlier

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PROGRAM:
/*32-bit up/down asynchronous reset counter Verilog code-file name counter.v*/
`timescale 1ns/1ps // Defining a Timescale for Precision
module counter(clk,rst,m,count); // Defining Module and Port List
input clk,rst,m; // Defining Inputs
output reg [31:0]count; // Defining 4-bit Output as Reg type
always@(posedge clk or negedge rst) // The Block is executed when begin
// EITHER of positive edge of clock or Neg Edge of Rst arrives
if(!rst) // Both are independent events
count=0;
if(m)
count=count+1;
else count=count-1;
end
endmodule

/* 32-bit up/down asynchronous reset counter for testbench-file name tb_counter.v*/

`timescale 1ns/1ps //Creating Time Scale as in Source Code
module counter_test; //Defining Module Name without Port List
reg clk, rst,m; //Defining I/P as Registers [to Hold Values]
wire [31:0] count; //Defining O/P as Wires [To Probe Waveforms] initial
begin
clk=0; //Initializing Clock and Reset
rst=0;#25; //All O/P is 4’b0000 from t=0 to t=25ns.
rst=1;
end //Up-Down counting is allowed at posedge clk

initial begin
m=1; //Condition for Up-Count
#600 m=0; rst=0;
#25; rst=1;
#500 m=0; //Condition for Down-Count
end
counter counter1(clk,m,rst, count); //Instantiation of Source Code always
#5 clk=~clk; //Inverting Clk every 5ns
initial
#1400 $finish; //Finishing Simulation at t=1400ns
endmodule

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Waveform:

Synthesis RTL Schematic:

RESULT: Verilog code for an Asynchronous 4-bit Counter circuit and its test bench for verification is
written, the waveform is observed and the code is synthesized with the technological library and is
verified.

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Experiment-2
Title: 4-bit Adder
Problem Statement: To develop the source code for 4-bit Adder by using VERILOG and obtain the
simulation and its test bench for verification, observe the waveform, synthesize the code with
technological library with given Constraints to generate into a netlist and place and route and implement
it.

Objectives:
Write Verilog code for 4-bit Adder and verify its functionality using test bench.
Synthesize the design by setting proper constraints and obtain the net list.
From the report generated, identify critical path, maximum delay, total number of cells, power
requirement and total area required. Change the constraints and obtain optimum synthesis results.

TOOL REQUIRED: Cadence Tool

THEORY:
4-bit Adder is a combinatorial circuit (not clocked, does not have any memory and feedback) adding
every bit position of the operands in the same time. Thus it is requiring number of bit-Adders (full
adders + 1 half adder) equal to the number of bits to be added. The 4-bit adder is constructed by
cascading full adders (FA) blocks in series. One full adder is responsible for the addition of two binary
digits at any stage of the ripple carry. The carryout of one stage is fed directly to the carry-in of the next
stage.

PROGRAM:
Three Codes are written for implementation of 4-bit Adder
◦ fa.v → Single Bit 3-input Full Adder [Sub-Module / Function]
◦ fa_4bit.v → Top Module for Adding 4-bit inputs
◦ fa_test.v → Test bench code for testing of 4-bit Adder design

/* fa.v → Single Bit 3-input Full Adder */

module full_adder( A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
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assign COUT = (A&B) | (CIN&(A^B));

endmodule

/* fa_4bit.v → Top Module for Adding 4-bit Inputs */

module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,[3:0] B,C0;
output [3:0] S,C4;
wire C1,C2,C3;

full_adder fa0 (A[0],B[0],C0,S[0],C1);

full_adder fa1 (A[1],B[1],C1,S[1],C2);
full_adder fa2 (A[2],B[2],C2,S[2],C3);
full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

/* Test Bench – fa_test.v */

module test_4_bit;
reg [3:0] A;
reg [3:0] B; reg C0;
wire [3:0] S; wire C4;
four_bit_adder dut(A,B,C0,S,C4);
initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
end
initial
#50 $finish;
Endmodule
Waveform :

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b) Synthesis and Report/Output Analysis

Step 1: Getting Started

Make sure you close out all the Incisive tool windows first.
Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (System Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

As the Full Adder Program does not contain any Clock, SDC can be skipped as an Input if you
wish to, else you could include only Area Constraints in form of commands during synthesis such
as, set_dont_use *XL (Indicating not to use Larger Cells)

Step 3 : Performing Synthesis

The Liberty files are present in the below path,
/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
The Available technology nodes are 180nm ,90nm and 45nm. In the terminal, initialise the tools
with the following commands if a new terminal is being used.
- csh
- source /home/install/cshrc
The tool used for Synthesis is “Genus”. Hence, type “genus -gui” to open the tool.
The Following are commands to proceed,
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {fa.v fa_4bit.v} //Reading multiple Verilog Files
3. elaborate
4. set_top_module four_bit_adder //Differentiating Top & Sub Module
5. set_dont_use *XL //Dont Use Cells with High Driving Strength
6. synthesize -to_mapped -effort medium //Performing Synthesis Mapping and Optimization
7. report_timing -unconstrained > counter_timing.rep
// Generates Timing report for worst datapath and dumps into file
//-Unconstrained is to be given as no timing constraints are given
8. report_area > counter_area.rep //Generates Synthesis Area report and dumps into a file
9. report_power > counter_power.rep
//Generates Power Report [Pre-Layout]

10. write_hdl > counter_netlist.v //Creates readable Netlist File.

11. write_sdc > counter_sdc.sdc //Creates Block Level SDC

Commands 1-5 are intended for Synthesis process while 6-10 for Generating reports and Outputs.
Note 1:-
1. The Cells given in the netlist can be checked in the .lib files for their properties.
2. The Max Operating Frequency does not apply for Purely Combinational Circuit.

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Synthesis RTL Schematic:

Some Common Constraints are given below for

Note-2:-
1. Tabulate Area, Power and Timing Constraints using any of the SDC Constraints as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do not
overwrite the earlier ones.

RESULT: Verilog code for the 4-bit Adder circuit and its test bench for verification is written, the
waveform is observed and the code is synthesized with the technological library and is verified.

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Experiment-3
Title: UART

Problem statement: To develop the source code for UART by using VERILOG and obtain the
simulation and its test bench for verification, observe the waveform, synthesize the code with
technological library with given Constraints to generate into a netlist and place and route and implement
it.

Objective:
a) To Verify the Functionality using test Bench
b) Synthesize Design using constraints
c) Tabulate Reports using various Constraints
d) Identify Critical Path and calculate Max Operating Frequency

Theory:
UART (Universal Asynchronous Receiver and Transmitter) is a serial communication protocol.
Basically this protocol is used to permit short distance, low cost and reliable full duplex communication.
It is used to exchange data between the processor and peripherals. The UART has three main parts-
receiver, transmitter and baud rate generator. Baud rate generator generates the clock frequency for
transmitter and receiver at a specific baud rate. The UART design has used a baud rate of 115200 bps
with 25 MHz Clock.

Creating a Workspace:
Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

a)Functional Verification using Test Bench

// Source code – Transmitter:

// This code contains the UART Transmitter. This transmitter is able to transmit 8 bits of serial data, one
// start bit, one stop bit, and no parity bit.
// When transmit is complete o_Tx_done will be driven high for one clock cycle.
//

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// Set Parameter CLKS_PER_BIT as follows:

// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module uart_tx
#(parameter CLKS_PER_BIT)
(
input i_Clock,
input i_Tx_DV,
input [7:0] i_Tx_Byte,
output o_Tx_Active,
output reg o_Tx_Serial,
output o_Tx_Done
);

parameter s_IDLE = 3'b000;

parameter s_TX_START_BIT = 3'b001;
parameter s_TX_DATA_BITS = 3'b010;
parameter s_TX_STOP_BIT = 3'b011;
parameter s_CLEANUP = 3'b100;

reg [2:0] r_SM_Main = 0;

reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_Tx_Data = 0;
reg r_Tx_Done = 0;
reg r_Tx_Active = 0;

always @(posedge i_Clock)

begin

case (r_SM_Main)
s_IDLE :
begin
o_Tx_Serial <= 1'b1; // Drive Line High for Idle
r_Tx_Done <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;

if (i_Tx_DV == 1'b1)
begin
r_Tx_Active <= 1'b1;
r_Tx_Data <= i_Tx_Byte;
r_SM_Main <= s_TX_START_BIT;
end
else
r_SM_Main <= s_IDLE;
end // case: s_IDLE

// Send out Start Bit. Start bit = 0

s_TX_START_BIT :

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begin
o_Tx_Serial <= 1'b0;

// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= s_TX_DATA_BITS;
end
end // case: s_TX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish

s_TX_DATA_BITS :
begin
o_Tx_Serial <= r_Tx_Data[r_Bit_Index];

if (r_Clock_Count < CLKS_PER_BIT-1)

begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;

// Check if we have sent out all bits

if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_TX_STOP_BIT;
end
end
end // case: s_TX_DATA_BITS

// Send out Stop bit. Stop bit = 1

s_TX_STOP_BIT :
begin
o_Tx_Serial <= 1'b1;

// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)

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begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_STOP_BIT;
end
else
begin
r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
r_Tx_Active <= 1'b0;
end
end // case: s_Tx_STOP_BIT

// Stay here 1 clock

s_CLEANUP :
begin
r_Tx_Done <= 1'b1;
r_SM_Main <= s_IDLE;
end

default :
r_SM_Main <= s_IDLE;

endcase
end

assign o_Tx_Active = r_Tx_Active;

assign o_Tx_Done = r_Tx_Done;

endmodule// Source code – Receiver :

// This file contains the UART Receiver. This receiver is able to receive 8 bits of serial data, one start bit,
// one stop bit, and no parity bit. When receive is complete o_rx_dv will be driven high for one clock cycle.
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module uart_rx
#(parameter CLKS_PER_BIT)
(
input i_Clock,
input i_Rx_Serial,
output o_Rx_DV,
output [7:0] o_Rx_Byte
);
parameter s_IDLE = 3'b000;
parameter s_RX_START_BIT = 3'b001;
parameter s_RX_DATA_BITS = 3'b010;
parameter s_RX_STOP_BIT = 3'b011;

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parameter s_CLEANUP = 3'b100;

reg r_Rx_Data_R = 1'b1;

reg r_Rx_Data = 1'b1;

reg [7:0] r_Clock_Count = 0;

reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_Rx_Byte = 0;
reg r_Rx_DV = 0;
reg [2:0] r_SM_Main = 0;

// Purpose: Double-register the incoming data.

// This allows it to be used in the UART RX Clock Domain.
// (It removes problems caused by metastability)
always @(posedge i_Clock)
begin
r_Rx_Data_R <= i_Rx_Serial;
r_Rx_Data <= r_Rx_Data_R;
end

// Purpose: Control RX state machine

always @(posedge i_Clock)
begin

case (r_SM_Main)
s_IDLE :
begin
r_Rx_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;

if (r_Rx_Data == 1'b0) // Start bit detected

r_SM_Main <= s_RX_START_BIT;
else
r_SM_Main <= s_IDLE;
end

// Check middle of start bit to make sure it's still low

s_RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (r_Rx_Data == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= s_RX_DATA_BITS;
end
else
r_SM_Main <= s_IDLE;
end
else
begin

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r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= s_RX_START_BIT;
end
end // case: s_RX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles to sample serial data

s_RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;

// Check if we have received all bits

if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_RX_STOP_BIT;
end
end
end // case: s_RX_DATA_BITS

// Receive Stop bit. Stop bit = 1

s_RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_STOP_BIT;
end
else
begin
r_Rx_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
end
end // case: s_RX_STOP_BIT

// Stay here 1 clock

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s_CLEANUP :
begin
r_SM_Main <= s_IDLE;
r_Rx_DV <= 1'b0;
end

default :
r_SM_Main <= s_IDLE;

endcase
end

assign o_Rx_DV = r_Rx_DV;

assign o_Rx_Byte = r_Rx_Byte;

endmodule // uart_rx

Test bench:
// This testbench will exercise the UART RX.
// It sends out byte 0x37, and ensures the RX receives it correctly.

`timescale 1ns/10ps

`include "uart_tx.v"
`include "uart_rx.v"

module UART_TB();

// Testbench uses a 25 MHz clock

// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per Bit.

parameter c_CLOCK_PERIOD_NS = 40;

parameter c_CLKS_PER_BIT= 217;
parameter c_BIT_PERIOD = 8600;

reg r_Clock = 0; reg r_TX_DV = 0;

wire w_TX_Active, w_UART_Line;
wire w_TX_Serial;
reg [7:0] r_TX_Byte = 0;
wire [7:0] w_RX_Byte;

UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst

(.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),
.o_RX_Byte(w_RX_Byte)
);

UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst

(.i_Clock(r_Clock),
.i_TX_DV(r_TX_DV),

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.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);

// Keeps the UART Receive input high (default) when UART transmitter is not active
assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;

always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
// Main Testing:
Initial begin
// Tell UART to send a command (exercise TX) @(posedge r_Clock);
@(posedge r_Clock); r_TX_DV <= 1'b1;
r_TX_Byte <= 8'h3F; @(posedge r_Clock); r_TX_DV <= 1'b0;
end
endmodule
Waveform:

b) Synthesize the Design

1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {uart_tx.v / uart_rx.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Reading Top Level SDC
5. synthesize -to_mapped -effort medium //Performing Synthesis Mapping and Optimization
6. report_timing > uart_timing.rep
//Generates Timing report for worst datapath and dumps into file

7. report_area > uart_area.rep //Generates Synthesis Area report and dumps into a file
8. report_power > uart_power.rep //Generates Power Report [Pre-Layout]
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9. write_hdl > uart_netlist.v //Creates readable Netlist File

10. write_sdc > uart_sdc.sdc //Creates Block Level SDC

Synthesis RTL Schematic:

Constraints file for Synthesis:
create_clock -name clk -period 10 -waveform {0 5} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_uncertainty 1.0 [get_ports "clk"]
set_input_delay -max 1.0 [get_ports "rst"] -clock [get_clocks "clk"]
set_input_delay -max 1.0 [get_ports "din"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "q"] -clock [get_clocks "clk"]
set_output_delay -max 1.0 [get_ports "qb"] -clock [get_clocks "clk"]

Synthesis RTL Schematic:

Note:-
1. Tabulate Area, Power and Timing Constraints using any of the SDC Constraints as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do not
overwrite the earlier ones.

RESULT: Verilog code for the UART circuit and its test bench for verification is written, the waveform
is observed and the code is synthesized with the technological library with given constraints and is
verified.

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VLSI LAB MANUAL (18ECL77) 2021-22

Experiment-4
Title: 32-bit ALU

Problem statement: To develop the source code for 32-bit ALU by using VERILOG and obtain the
simulation and its test bench for verification, observe the waveform, synthesize the code with
technological library with given Constraints to generate into a netlist, place and route and implement it.

Objectives:
a) To Verify the Functionality using Test Bench
b) Synthesize and compare the results using if and case statements
c) Identify Critical Path and constraints

Creating a Work space:

Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

Theory:
An Arithmetic Logic Unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It
represents the fundamental building block of the central processing unit (CPU) of a computer. Most of
the operations of a CPU are performed by one or more ALUs, which load data from input registers.

A 32-bit ALU is a combinational circuit taking two 32-bit data words A and B as inputs, and producing
a 32-bit output Y by performing a specified arithmetic or logical function on the A and B inputs.

Arithmetic Logic Unit (ALU) using these simple logic gates AND, OR, NOT, XOR and other
components. The ALU will take in two 32-bit values, and two control lines. Depending on the value of
the control lines, the output will be the addition, subtraction, bitwise AND or bitwise OR of the inputs.
The Fig. 1 shows the block diagram of 32-bit ALU.

Fig-1: 32-bit ALU

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Fig-2: Logic Diagram of 32-bit ALU

Basic components:

a)To Verify the Functionality using Test Bench

Source Code – Using Case Statement:

module alu_32bit_case(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin

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case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b010:y=a+b; //Addition
3'b011:y=a-b; //Subtraction
3'b100:y=a*b; //Multiply
default:y=32'bx;

endcase
end
endmodule

Test Bench:
module alu_32bit_tb_case;

reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f));
initial begin
a=32'h00000000; b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end

initial
#50 $finish;
endmodule

B:Source Code - Using If Statement:

module alu_32bit_if(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f; output reg [31:0]y;
always@(*)
begin
if(f==3'b000)
y=a&b; //AND Operation else if (f==3'b001)
y=a|b; //OR Operation else if (f==3'b010)
y=a+b; /Addition else if (f==3'b011)
y=a-b; /Subtraction else if (f==3'b100)
y=a*b; //Multiply else
y=32'bx;

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end
endmodule

Test bench:
module alu_32bit_tb_if;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;

alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial begin
a=32'h00000000;

b=32'hFFFFFFFF; #10 f=3'b000;

#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end initial
#50 $finish;
endmodule

Waveforms:

b) Synthesize Design
•Run the synthesis Process one time for each code and make sure the output File names are changed
accordingly.

Synthesis Process:

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1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {alu_32bit_if.v (OR) alu_32bit_case.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Optional-Reading Top Level SDC
5. synthesize -to_mapped -effort medium //Performing Synthesis Mapping and Optimization
6. report_timing > alu_timing.rep //Generates Timing report for worst datapath and dumps into file
7. report_area > alu_area.rep //Generates Synthesis Area report and dumps into a file
8. report_power > uart_power.rep //Generates Power Report [Pre-Layout]
9. write_hdl > uart_netlist.v //Creates readable Netlist File
10. write_sdc > uart_sdc.sdc //Creates Block Level SDC

RTL Schematic of 32-bit Floating Point ALU with Pipelining

Note:-
1. Tabulate Area, Power and Timing Constraints using any of the SDC Constraints as instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do not
overwrite the earlier ones.

RESULT: Verilog code for the 32-bit ALU circuit and its test bench for verification is written, the
waveform is observed and the code is synthesized with the technological library and given constraints
and is verified.

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Experiment-5
Title: Latches and Flip Flops
Problem Statement: Write verilog code for D, SR, JK Latch and Flip-flop, Synthesize the design and
compare the synthesis report.

Objectives:
1. Write Verilog code for D, SR, JK Latch
2. Write Verilog code for D, SR, JK Flip Flop
3. Synthesize the designs

5a. i) D flipflop

Theory:
D flip-flop The D flip-flop is widely used. It is also known as a "data" flip-flop. The D flip-flop captures
the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock).
That captured value becomes the Q output. At other times, the output Q does not change. The D flip-flop
can be viewed as a memory cell, a zero-order hold, or a delay line.

Block diagram:

Truth Table:
Reset Clock D Q Qb
0 1 1 0
0 0 0 1
0 0 X X Hold
1 X 0 1

Design Equation/ calculations (if any):

Q(t+1) = D(t)

Verilog Code with Comments:

`timescale 1ns / 10ps
module DFF( Q,Qbar,D,Clk,Reset);
output reg Q;
output Qbar;
input D,Clk,Reset;
always @(posedge Clk)
begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
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assign Qbar = ~Q;

endmodule

Test bench code:

`timescale 1ns / 10ps
module DFF_tb;
reg D, Clk, Reset; // Inputs
wire Q, Qbar; // Outputs
// Instantiate the Unit Under Test (UUT)
DFF uut ( .Q(Q), .Qbar(Qbar), .D(D), .Clk(Clk), .Reset(Reset));
initial begin
D = 1'b0; // Initialize Inputs
Clk = 1'b0;
Reset = 1'b1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
Reset = 1'b0;
#20;
forever #40 D = ~ D;
end
always #10 Clk = ~Clk;
endmodule

Simulation output:

Constraint File:
create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_transition -
set_clock_uncertainty 0.01 [get_clocks "clk"]
set_input_delay -max 1 [get_ports "Reset"] -clock [get_clocks "clk"]
set_input_delay -max 1 [get_ports "D"] -clock [get_clocks "clk"]
set_output_delay -max 1 [get_ports "Q"] -clock [get_clocks "clk"]
set_output_delay -max 1 [get_ports "Qbar"] -clock [get_clocks "clk"]

Synthesis:

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Gatelevel netlist, gate, area, timing, power reports are generated and analysed by the students

Expected Outcomes:
The students will be able to
Write the Verilog code and analyze it with various testcases for the given input and output
Analyse the reports generated with different input clock frequency

Additional Experimental Questions:

Given the test inputs as given in the figure below and verify the outputs

Change the following constraints and analysis the timing, power, area and gate reports
Clock inputs as 2ns, 4ns, 0.5ns in the constraint file and analyze the result and reports
Change the rising time and falling time to max of 0.5 and 1.5ns both at the input and /or output
and analyze the result and reports

5a ii) S R Flip Flop

Theory:
It can be seen that when both inputs S = “1” and R = “1” the outputs Q and Q can be at either logic level
“1” or “0”, depending upon the state of the inputs S or R BEFORE this input condition existed.
Therefore the condition of S = R = “1” does not change the state of the outputs Q and Q. However, the
input state of S = “0” and R = “0” is an undesirable or invalid condition and must be avoided. The
condition of S = R = “0” causes both outputs Q and Q to be HIGH together at logic level “1” when we
would normally want Q to be the inverse of Q. The result is that the flip-flop loses control of Q and Q,
and if the two inputs are now switched “HIGH” again after this condition to logic “1”, the flip-flop
becomes unstable and switches to an unknown data state based upon the unbalance.

Logic diagram:

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Truth Table:

Clock R S Q Qb Comments
0 0 Hold No change
0 1 1 0 Set
0 1 0 0 1 Reset
1 1 z z Indeterminate
0 X X Hold No change

Design Equation/ calculations (if any):

Q(t+1) = R'(t)Q(t) + S(t) ; S(t)R(t) = 0

Verilog Code with Comments:

`timescale 1ns / 10ps
module SR_FF(S,R,clk,Q,Qbar);
input S,R,clk;
output Q,Qbar;
reg M,N;
always @(posedge clk)
begin
M = !(S & clk);
N = !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);
endmodule

Test bench code:

`timescale 1ns / 10ps
module SRFF_tb;
reg S, R; reg clk;
// Outputs
wire Q, Qbar;
// Instantiate the Unit Under Test (UUT)
SR_FF uut ( .S(S), .R(R), .clk(clk), .Q(Q), .Qbar(Qbar) );
initial begin
// Initialize Inputs
clk = 1'b0;
S =1'b0;
R=1'b0;
// Wait 100 ns for global reset to finish
#10;

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// Add stimulus here

S =1'b1;R=1'b0;
#20 S =1'b0; R=1'b1;
#10 S =1'b0; R=1'b0;
#30 S =1'b1; R=1'b1;
#200 $finish;
end
always #10 clk = ~clk;
endmodule

Simulation output:

Constraint File:
create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_transition -
set_clock_uncertainty 0.01 [get_clocks "clk"]
set_input_delay -max 1 [get_ports "S"] -clock [get_clocks "clk"]
set_input_delay -max 1 [get_ports "R"] -clock [get_clocks "clk"]
set_output_delay -max 1 [get_ports "Q"] -clock [get_clocks "clk"]
set_output_delay -max 1 [get_ports "Qbar"] -clock [get_clocks "clk"]

Synthesis:

Gatelevel netlist, gate, area, timing, power reports are generated and analysed by the students

Expected Outcomes:
The students will be able to
Write the Verilog code and analyze it with various testcases for the given input and output
Analyse the reports generated with different input clock frequency

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Additional Experimental Questions:

Given the test inputs as given in the figure below and verify the outputs

Change the following constraints and analysis the timing, power, area and gate reports
Clock inputs as 2ns, 4ns, 0.5ns in the constraint file and analyze the result and reports
Change the rising time and falling time to max of 0.5 and 1.5ns both at the input and /or
output and analyze the result and reports

5a iii) JK Flip Flop

Theory:
Then the JK flip-flop is basically an SR flip-flop with feedback which enables only one of its two input
terminals, either SET or RESET to be active at any one time thereby eliminating the invalid condition
seen previously in the SR flip-flop circuit. Also when both the J and the K inputs are at logic level “1” at
the same time, and the clock input is pulsed either “HIGH”, the circuit will “toggle” from its SET state
to a RESET state, or visa-versa. This result in the JK flip-flop acting more like a T-type toggle flip-flop
when both terminals are “HIGH”
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing problems
called “race” if the output Q changes state before the timing pulse of the clock input has time to go
“OFF”. To avoid this the timing pulse period ( T ) must be kept as short as possible (high frequency). As
this is sometimes not possible with modern TTL IC’s the much improved MasterSlave JK Flip-flop was
developed

Block and Logic diagram:

Truth Table:

Clock J K Q Qm Comments
0 0 Hold No change
0 1 1 0 Set
0 1 0 0 1 Reset
1 1 0 1 Toggle
1 0
0 X X Hold No change

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Design Equation/ calculations (if any):

Q(t+1) = K'(t)Q(t) + J(t)Q'(t)

Verilog Code with Comments:

`timescale 1ns / 10ps
module jkff(J, K, clk, Q, Qm);
input J, K, clk;
output reg Q;
output Qm;
always @(posedge clk)
begin
if(J == 0 && K == 0)
Q <= 0;
else if(J == 1 && K == 0)
Q <= 1;
else if(J == 0 && K == 1)
Q <= 0;
else if(J == 1 && K == 1)
Q <= ~Q;
end
assign Qm = ~Q;
endmodule

Test bench code:

`timescale 1ns / 10ps
module JKFF_tb;
// Inputs
reg J, K,,clk;
// Outputs
wire Q, Qm;
// Instantiate the Unit Under Test (UUT)
jkff uut ( .J(J), .K(K), .clk(clk), .Q(Q), .Qm(Qm) );
initial begin
// Initialize Inputs
clk = 1'b0;
J =1'b0;
K=1'b0;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
J =1'b1; K=1'b0;
#20 J =1'b1; K=1'b1;
#10 J =1'b1; K=1'b0;
#30 J =1'b1; K=1'b1;
#30 J =1'b0; K=1'b0;
#200 $finish;
end
always #10 clk = ~clk;
endmodule

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Simulation output:

Constraint File:
create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]
set_clock_transition -rise 0.1 [get_clocks "clk"]
set_clock_transition -fall 0.1 [get_clocks "clk"]
set_clock_transition -
set_clock_uncertainty 0.01 [get_clocks "clk"]
set_input_delay -max 1 [get_ports "J"] -clock [get_clocks "clk"]
set_input_delay -max 1 [get_ports "K"] -clock [get_clocks "clk"]
set_output_delay -max 1 [get_ports "Q"] -clock [get_clocks "clk"]
set_output_delay -max 1 [get_ports "Qm"] -clock [get_clocks "clk"]

Synthesis:

Gatelevel netlist, gate, area, timing, power reports are generated and analysed by the students

Expected Outcomes:
The students will be able to
Write the Verilog code and analyze it with various testcases for the given input and output
Analyse the reports generated with different input clock frequency

Additional Experimental Questions:

Given the test inputs as given in the figure below and verify the outputs

Change the following constraints and analysis the timing, power, area and gate reports
Clock inputs as 2ns, 4ns, 0.5ns in the constraint file and analyze the result and reports

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Change the rising time and falling time to max of 0.5 and 1.5ns both at the input and /or
output and analyze the result and reports

5b i) D Latch

Theory:

The Gated D Latch is another special type of gated latch having two inputs, i.e., DATA and ENABLE.
When the enable input set to 1, the input is the same as the Data input. Otherwise, there is no change in
output.

We can design the gated D latch by using gated SR latch. The set and reset inputs are connected together
using an inverter. By doing this, the outputs will be opposite to each other. Below is the circuit diagram
of the Gated D latch.

Logic diagram:

Truth Table:

Enable(en) D Q Qbar
0 0 Latch latch
0 1 Latch latch
1 0 0 1
1 1 1 0

Verilog Code with Comments:

`timescale 1ns/10ps
module DFF( Q,Qbar,D,en,Reset);
output reg Q;
output Qbar;
input D,en,Reset;
always @ (en or Reset or D)
if (!Reset)
Q <= 0;
else
if (en)
Q <= D;
assign Qbar = ~Q;
endmodule

Test bench code:

`timescale 1ns / 10ps

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module DFF_tb;
reg D, en, Reset; // Inputs
wire Q, Qbar; // Outputs
// Instantiate the Unit Under Test (UUT)
DFF uut ( .Q(Q), .Qbar(Qbar), .D(D), .en(en), .Reset(Reset) );
initial begin
D = 1'b0; // Initialize Inputs
en =1'b1;
Reset = 1'b1;
#50; // Wait 100 ns for global reset to finish
// Add stimulus here
Reset =1'b0;
#10 D=1'b1;
#20 Reset =1'b1;
#50 en =1'b0;
#10 D=1'b0;
#10 D=1'b1;
#10 D=1'b1;
#50 en =1'b1;
#20 D=1'b1;
#10 D=1'b0;
#20 D=1'b1;
#10 D=1'b0;
#50 D=1'b1;
#400 $finish;
end
endmodule

Simulation output:

Constraint File:
set_input_delay -max 1 [get_ports "D"]
set_input_delay -max 1 [get_ports "en"]
set_output_delay -max 1 [get_ports "Q"]
set_output_delay -max 1 [get_ports "Qbar"]

Synthesis:

Gatelevel netlist, gate, area, timing, power reports are generated and analysed by the students

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Expected Outcomes:
The students will be able to
Write the Verilog code and analyze it with various testcases for the given input and output
Analyse the reports generated with different input clock frequency

Note: Additional variations that can be done from this experiment

(Eg: for flip flops given the waveform, write the test bench and obtained the given output
Possible change of values in the constraint file and analyze the result and reports)

5b ii) SR Latch
Theory:
A Gated SR Latch is a special type of SR Latch having three inputs, i.e., Set, Reset, and Enable. The
enable input must be active for the SET and RESET inputs to be effective. The ENABLE input of gated
SR Latch enables the operation of the SET and RESET inputs. This ENABLE input connects with a
switch. The Set-Reset inputs are enabled when this switch is on. Otherwise, all the changes are ignored
in the set and reset inputs. Below are the circuit diagram and the truth table of the Gated SR latch.

Logic diagram: //using NOR gate

Truth Table:

Enable(en) S R Q Qm
1 0 0 Latch Latch
1 0 1 0 1
1 1 0 1 0
1 1 1 0 0
0 X X Latch

Verilog Code with Comments:

`timescale 1ns / 10ps
module SRLatch (S,R,en,Q,Qm);
input S,R,en;
output Q,Qm;
reg M,N;
always @(en)
begin
M <= !(S & en);
N <= !(R & en);
end
assign Q = !(M & Qm);
assign Qm = !(N & Q);
endmodule

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Test bench code:

`timescale 1ns / 10ps
module SRlatch_tb;
reg S, R, en; // Inputs
wire Q, Qm; // Outputs
// Instantiate the Unit Under Test (UUT)
SRLatch uut (.S(S), .R(R), .en(en), .Q(Q), .Qm(Qm));
initial begin
S = 1'b0; // Initialize Inputs
R = 1'b0;
en =1'b1;
#50; // Wait 100 ns for global reset to finish
// Add stimulus here
#10 S=1'b1; R=1'b0;
#100 en =1'b0;
#50 S=1'b0; R=1'b0;
#50 S=1'b1; R=1'b0;
#50 en =1'b1;
#100 S=1'b0; R=1'b1;
#150 S=1'b0; R=1'b0;
#100 S=1'b1; R=1'b0;
#150 S=1'b1; R=1'b1;
#50 S=1'b0; R=1'b0;
#200 S=1'b0;R=1'b0;
#600 $finish;
end
endmodule

Simulation output:

Constraint File:
set_input_delay -max 1 [get_ports "R"]
set_input_delay -max 1 [get_ports "en"]
set_input_delay -max 1 [get_ports "S"]
set_output_delay -max 1 [get_ports "Q"]
set_output_delay -max 1 [get_ports "Qbar"]

Synthesis:

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VLSI LAB MANUAL (18ECL77) 2021-22

Gatelevel netlist, gate, area, timing, power reports are generated and analysed by the students

Expected Outcomes:
The students will be able to
Write the Verilog code and analyze it with various testcases for the given input and output
Analyse the reports generated with different input clock frequency

Note: Additional variations that can be done from this experiment

(Eg: for flip flops given the waveform, write the test bench and obtained the given output
Possible change of values in the constraint file and analyze the result and reports)

5b iii) JK Latch
Theory:

The JK Latch is the same as the SR Latch. In JK latch, the unclear states are removed, and the output is
toggled when the JK inputs are high. The only difference between SR latch JK latches is that there is no
output feedback towards the inputs in the SR latch, but it is present in the JK latch. The circuit diagram
and truth table of the JK latch are as follows:

Logic diagram:

Truth Table:
Enable J K Q Qm Comments
1 0 0 Q Q No change
1 0 1 1 0 Set
1 1 0 0 1 Reset
1 1 1 Qb Q Toggle
0 X X Latch No change

Verilog Code with Comments:

`timescale 1ns / 10ps
module JKLatch(J, K, en, Q,Qm);
input J, K, en;
output reg Q;
output Qm;
always @(en)
begin
if(J == 0 && K == 0)
Q <= Q;
else if(J == 1 && K == 0)

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Q <= 1;
else if(J == 0 && K == 1)
Q <= 0;
else if(J == 1 && K == 1)
Q <= ~Q;
end
assign Qm=~Q;
endmodule

Test bench code:

`timescale 1ns / 10ps
module JKlatch_tb;
reg J, K, en; // Inputs
wire Q, Qm; // Outputs
// Instantiate the Unit Under Test (UUT)
JKLatch uut (.J(J), .K(K), .en(en), .Q(Q), .Qm(Qm));
initial begin
J = 1'b0; // Initialize Inputs
K = 1'b0;
en =1'b1;
#50; // Wait 100 ns for global reset to finish
// Add stimulus here
#10 J=1'b1; K=1'b0;
#100 en =1'b0;
#50 J=1'b0; K=1'b0;
#50 J=1'b1; K=1'b0;
#50 en =1'b1;
#100 J=1'b0; K=1'b1;
#150 J=1'b0; K=1'b0;
#100 J=1'b1; K=1'b0;
#150 J=1'b1; K=1'b1;
#50 J=1'b0; K=1'b0;
#200 J=1'b0; K=1'b0;
#600 $finish;
end
endmodule

Simulation output:

Constraint File:
set_input_delay -max 1 [get_ports "J"]
set_input_delay -max 1 [get_ports "K"]
set_input_delay -max 1 [get_ports "en"]

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set_output_delay -max 1 [get_ports "Q"]

set_output_delay -max 1 [get_ports "Qm"]

Synthesis:

Gatelevel netlist, gate, area, timing, power reports are generated and analysed by the students

Expected Outcomes:
The students will be able to
Write the Verilog code and analyze it with various testcases for the given input and output
Analyse the reports generated with different input clock frequency

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VLSI LAB MANUAL (18ECL77) 2021-22

Experiment-6
Title: Physical Design

Problem statement: To develop the Physical Design (Floor planning, Placement, Routing in Layout of
any two experiments of 1 to 5

Objective:
For the synthesized netlist carry out the following for any two above experiments:
a. Floor planning (automatic), identify the placement of pads
b. Placement and Routing, record the parameters
c. Physical verification and record the LVS and DRC reports
d. Perform Back annotation and verify the functionality of the design
e. Generate GDSII and record the number of masks and its color composition

Mandatory inputs for PD:

1. Gate Level Netlist [Output of Synthesis]
2. Block Level SDC [Output of Synthesis]
3. Liberty Files (.lib)
4. LEF Files (Layer Exchange Format)

Expected Outputs from PD:

1. GDS II File (Graphical Data Stream for Information Interchange –Feed In for Fabrication Unit).

Make sure the Synthesis for the target design is done and open aterminal from the
corresponding workspace.
Initiate the Cadence tools enters into Innovus command prompt where in the tool commands can be
entered.

Physical Design involves 5 stages as following:

After Importing Design,
→ Floor Planning
→ Power Planning
→ Placement
→ CTS (Clock Tree Synthesis)
→ Routing

Importing Design

To Import Design, all the Mandatory Inputs are to be loaded and this canbe done either using script files
named with .globals and .view/.tcl or through GUI as shown below.

The target design considered here is 4-bit counter.

The procedure shall remain the same for any other design from theabove discussed experiments.
Note:
1.For Synthesis, slow.lib was read as input. Each liberty file contains apre-defined Process, Voltage and
Temperature (PVT) values which impact the ease of charge movement.

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2.Process, Voltage and Temperature individually affect the ease ofcurrents as depicted below.

3. Hence, slow.lib contains PVT combination (corner) with slow charge movement => Maximum Delay
=> Worst Performance
4. Similarly, fast.lib contains PVT Combinationapplicable across its designs to give Fast charge
movement => Minimum Delay => Best Performance.
5. When these corners are collaborated with the sdc, they can be used to analyze timing for setup in the
worst case and hold in the best case.
6. All these analysis views are to be manually created either in the formof script or using the GUI.

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Script under Default. Globals file

Script under Default.view (or) Default.tcl file

Note: Check the paths to properly read in the input files.
Else, if you would like to import your design using GUI, open theInnovus tool and from the GUI, go to
File → Import Design.
A new pop-up window appears.

First load the netlist. You can browse for the file and select “Topcell : Auto Assign”.
Similarly select your lef files from /home/install/FOUNDRY/digital/90nm/dig/lef/ as shown below.

Once both the Netlist and LEF Files are load ed, your import design window is as follows.

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In order to load the Liberty File and SDC, create delay corners and analysis view, select the “Create
Analysis Configuration” option atthe bottom.

An MMMC browser Pops Up.

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The order of adding the MMMC Objects is as follows.
1. Library Sets
2. RC Corners
3. Delay Corners
4. Constraints (SDC)
Once all of them are added, Analysis Views are created and assigned toSetup and Hold.

In order to add any of the objects, make a right click on the correspondinglabel → Select New.

Adding Liberty Files under “Library Sets”

 Similarly, add fast.lib with a label Fast or anyidentifier of your own.

AAdding RC Corners can also be done in a similar process. The temperature value can be found under
the corresponding liberty file. Also, cap table and RC Tech files can be added from Foundry where
available.
 Delay Corners are formed by combining LibrarySets with RC Corners.
An example is shown below.

Similarly, SDC can be read in under the MMMC Object of“Constraints”.

Analysis Views are formed from combinations ofSDC and Delay Corner.

Once “Best” and “Worst” Analysis views are created, assign them toSetup and Hold.
Once all the process is done, Click on “Save&Close” and save the script generated with any name of
yourchoice.
Make sure the file extension remains .view or .tcl
After saving the script, go back to Import Design window and Click“OK” to load your design.
Add Power and Ground Net names (Identifiers) under Import designwindow.

A rectangular or square box appears in your GUI if and only if all theinputs are read properly.
 If the box does not appear, check for errors in your log (Either onterminal or log file from pwd)

The internal area of the box is called “Core Area”.

T
he horizontal lines running along the width of Core are “Standard Cell Rows”. Every alternate of them
are marked indicating alternateVDD and VSS rows.
This setup is called “Flipped Standard Cell Rows”.

→ Floorplan

Steps under Floorplan :

1. Aspect Ratio [Ratio of Vertical Height to Horizontal Width of Core]

2. Core Utilisation [The total Core Area % to be used for FloorPlanning]
3. Channel Spacing between Core Boundary to IO Boundary
 Select Floorplan → Specify Floorplan to modify/add concerned values to the above Factors. On
adding/modifying the concerned values, the core area is also modified.
 The Yellow patch on the Left Bottom are the group of “Unassigned pins” which are to be placed
along the IO Boundary along with theStandard Cells [Gates].

→ Power Planning

Steps under Power Planning :

1. Connect Global Net Connects
2. Adding Power Rings
3. Adding Power Strings
4. Special Route

Under Connect Global Net Connects, we create two pins, one for VDDand one for VSS connecting
them to corresponding Global Nets as mentioned in Globals file / Power and Ground Nets.

1. Select Power → Connect Global Nets.. to create “Pin” and “Connectto Global Net” as shown and use
“Add to list”.
2. Click on “Apply” to direct the tool in enforcing the Pins and Netconnects to Design and then Close the
window.
In order to Tap in Power from a distant Power supply, Wider Nets and Parallel connections improve
efficiency. Moreover, the cells thatwould be placed inside the core area are expected to have shorter
Nets for lower resistance.
Hence Power Rings [Around Core Boundary] and Power Stripes[Across Core Boundary] are added
which satisfies the above conditions.
Select Power → Power Planning → Add Rings to add Power rings‘around Core Boundary’.

Select the Nets from Browse option OR Directly type in the GlobalNet Names separated by a space
being Case and Spelling Sensitive.
Select the Highest Metals marked ‘H’ [Horizontal] for Top and Bottom and Metals marked ‘V’
[Vertical] for Right and Bottom. This is because Highest metals have Highest Widthsand thus Lowest
Resistance.

Click on Update after the selection and “Set Offset : Centre in Channel” in order to get the Minimum
Width and Minimum Spacingof the corresponding Metals and then Click “OK”.
Similarly, Power Stripes are added using similar content to that ofPower Rings.
Factors to be considered under Power Stripes :
→ Nets
→ Metal and It’s Direction
→ Width and Spacing [Updated]
→ Set to Set Distance = ( Minimum Width of Metal + Min. Spacing ) x 2
 On adding Power Stripes, The Power mesh setup is complete as shown. However, There are no Vias that
could connect Metal 9 or Metal 8 directly with Metal 1 [VDD or VSS of Standard Cells are generally made
up of Metal 1].
The connection between the Highest and Lowest Metals is done through Stacking of Vias done using
“Special Route”.
To perform Special Route, Select Route → Special Route → AddNets → OK.
After the Special Route is complete, all the Standard Cell Rows turn to the Color coded for Metal 1 as
shown below.
The complete Power Planning process makes sure Every Standard Cellreceives enough power to
operate smoothly.

→ Pre – Placement :

After Power Planning, a few Physical Cells are added namely, EndCaps and Well Taps.
End Caps : They are Physical Cells which are added to the Left and Right Core Boundaries acting
as blockages to avoid Standard Cells from moving out of boundary.
Well Taps : They act like Shunt Resistance to avoid Latch Upeffects.
To add End Caps, Select Place → Physical Cell → Add End Caps and“Select” the FILL’s from the
available list.
Higher Fills have Higher Widths. As shown Below, The End Capsare added below your
Power Mesh.

To add Well Taps, Select Place → Physical Cell → Add Well Tap →Select →FillX [X →
Strength of Fill = 1,2,4 etc] → Distance Interval [Could be given in range of 30-45u] → OK
→ Placement
1. The Placement stage deals with Placing of Standard Cells as well asPins.
2. Select Place → Place Standard Cell → Run Full Placement → Mode
→ Enable ‘Place I/O Pins’ → OK → OK .
 All the Standard Cells and Pins are placed as per the communicationbetween them, i.e., Two
communicating Cells are placed as close aspossible so that shorter Net lengths can be used for
connections as Shorter Net Lengths enable Better Timing Results.
You can toggle the Layer Visibility from the list on the Right. The List of Layers available are shown
on the right under “Layer” tabwith colour coding.

→ Report Generation and Optimization :

1. Timing Report :
1. To generate Timing Report, Timing → Report Timing → DesignStage –
PreCTS
2. Analysis Type – Setup → OK
3. The Timing report Summary can be seen on the Terminal.
2. Area Report :
1. cmd : report_area
3. Power Report :
1. cmd : report_power
 In case of any Violating paths, the design could be optimized in thefollowing way.
To optimize the Design, Select ECO → Optimize Design → DesignStage [PreCTS] →
Optimization Type – Setup → OK

After you run the optimization, the terminal displays the latest Timing report and updated
area and power reports can be checked.

This step Optimizes your design in terms of Timing, Area and Power.You can Generate
Timing, Area, Power in similar way as above report Post – Optimization to compare the
Reports.

Clock Tree Synthesis

The CTS Stage is meant to build a Clock Distribution Network suchthat every Register (Flip
Flop) acquires Clock at the same time (Atleast Approximately) to keep them in proper
communication.
A Script can be used to Build the Clock Tree as follows :
 Source the Script as shown in the above snapshot through the Terminal and then Select Clock →
CCOpt Clock Tree Debugger →OK to build and view clock tree.
 67

The Red Boxes are the Clock Pins of various Flip Flops in the Design while Yellow
Pentagon on the top represents Clock Source.
The Clock Tree is built with Clock Buffers and Clock Invertersadded to boost up the
Clock Signal.

Report Generation and Design Optimization :

CTS Stage adds real clock into the Design and hence “Hold” Analysis also becomes
prominent. Hence, Optimizations can be done for both Setup & Hold, Timing Reports are to be Generated
for Setupand Hold Individually.
Setup Timing Analysis :

Hold Timing Analysis :

Routing :

1. All the net connections shown in the GUI till CTS are only based onthe Logical connectivity.
2. These connections are to be replaced with real Metals avoiding Opens, Shorts, Signal Integrity
[Cross Talks], Antenna Violations etc.
3. To run Routing, Select Route → Nano Route → Route and enableTiming Driven and SI
Driven for Design Physical Efficiency and Reliability.
Area and Power Reports :
Use the commands report_area and report_power for Area and PowerReports respectively.
As an alternate to the setAnalysisMode command, you can use the GUI at Tools → Set Mode
→ Set Analysis Mode → Select On-Chip-Variation and CPPR.

The Report generation is same as shown prior to DesignOptimization.

It is recommended to save Netlist and Design at every stage.

To restore a Design Data Base, type source <DesignName>.enc in theterminal.

GDS File Generation

Physical Verification – Capturing DRC and LVS :

After saving the routed Database, you can proceed for PhysicalVerification and capture
the DRC and LVS reports.
Inputs Required – DRC :
◦ Technology Library and Rule Set
◦ GDS format giles of all Standard Cells (Given by Cadence at
/home/install/FOUNDRY/90nm/dig/gds for 90nm Tech node)
Outputs – DRC :
◦ DRC Violation Report
◦ Physical Netlist (Optional)

From the Innovus GUI, select PVS → Run DRC to open the “DRCSubmission Form”.
The DRC Run Submission Form begins with mentioning the Run Directory. The Run Directory is the
location where all the logs, reports andother files concerned with PVS are saved.

The technology Library is to be loaded under “Rules tab”.

 The Technology Library is specific for PVS Tool and technologynode on which the design is created.
On reading the tech lib, the rule set is loaded and the correspondingfabrication rules are read in to be
checked against the design.

The GDS format files of all standard cells available with the corresponding technology node are also
provided by the vendor.Select all of them to add.
The output report can be named and saved as shown.

Hit “Submit” to run the DRC and the following windows appear.
All the list of DRC Errors can be seen in the above window of whichthe location of the DRC
Violation occuring can be highlighted dealing one to one.
For example, in the above shown snapshot, the errors associated withN-Implant can be seen.
(Select a error occurrence and click on the right arrow below to highlight/zoom in the location.)
You can save the DRC Run as a “Preset” file to rerun the DRC ifrequired at a later point
of time.
Saving/loading the Preset File is shown below.

Loading a Preset file is shown below.

Note : A Physical Netlist can be saved after the DRC Run as shown below.

Inputs Required – LVS :

◦ Technology Library
◦ Standard Cell GDS Files
◦ Spice Netlist of all Standard Cells (Provided by Library Vendor)
Outputs – LVS :
◦ LVS Match/Mismatch Report
From the Innovus GUI, Select PVS → Run LVS to open the LVS runsubmission form.

Provide the Run directory and log file name (Along with path –Optional)
Load the Tech Lib, GDS Files and Spice Netlist of all Standard Cellsunder the
corresponding technology node.
On successful completion of LVS Run, the following windowsappear.
VLSI LAB MANUAL (18ECL77) 2021-22

You can create a GDS file along with Stream out file either using theGUI as File → Save →
GDS/Oasis or use the following command.
Cmd : streamOut <GDSFileName>.gds -streamOut
<streamOut>.map

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