Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

Correction TD 2
Conception de circuits numériques

Octobre 2016

1 Correction exercice 1 :
1.1 Buffer Unidirectionnel
1.1.1 Entité

1 --Appel des bibliotheques

2 library IEEE;
3 use IEEE.std_logic_1164.all;
4

5 -- Definition Entite
6 entity Three_State_Unidir is
7 port ( E,Cde : in std_logic;
8 S : out std_logic);
9 end entity Three_State_Unidir;

1.1.2 Architecture 1

1 -- definition Architecture 1
2 architecture a1 of TriState_Unidir is
3 begin
4 S <= E when cde = ’1’ else ’Z’;
5 end architecture a1;

Correction TD 2 R.Hertelli : [email protected] 1/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

1.1.3 Architecture 2

1 -- definition Architecture 2
2 architecture a2 of Thrree_State_Unidir is
3 begin
4 process (E,Cde)
5 begin
6 if (Cde = ’1’) then
7 S <= E ;
8 else
9 S<= ’Z’;
10 end if ;
11 end process;
12 end architecture a2;

1.2 Buffer bidirectionnel

1.2.1 Entité

1 --Appel des bibliotheques

2 library IEEE;
3 use IEEE.std_logic_1164.all;
4

5 --Entite Definition
6 entity Three_State_bidir is
7 port ( E,Cde : in std_logic;
8 S : out std_logic;
9 IO : inout std_logic);
10 end entity Three_State_bidir;

1.2.2 Architecture

1 -- definition Architecture Comportementale

2 architecture comport of Three_State_bidir is
3 begin
4 IO <= E when cde = ’1’ else ’Z’;

Correction TD 2 R.Hertelli : [email protected] 2/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

5 S <= IO;
6 end architecture comport;

2 Correction exercice 2 :

Figure 1 – Multiplexeur Mux4

2.1 Équation

Q = A · B · I0 + A · B · I1 + A · B · I2 + A · B · I3

2.2 Entité

1 Library IEEE;
2 use IEEE.std_logic_1164.all;
3

4 entity Mux4 is
5 port ( I0,I1,I2,I3,A,B : in std_logic;
6 Q : out std_logic);
7 end entity Mux4;

Correction TD 2 R.Hertelli : [email protected] 3/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

2.3 Architectures
2.3.1 Description comportementale 1

1 architecture arch_comb1 of Mux4 is

2 begin
3

4 process(I0,I1,I2,I3,A,B)
5 variable sel : std_logic_vector(1 downto 0);
6

7 begin
8 sel := (A,B);
9 case sel is
10 when "00" => Q <= I0;
11 when "01" => Q <= I1;
12 when "10" => Q <= I2;
13 when "11" => Q <= I3;
14 when others => Q <= ’X’;
15 end case;
16 end process;
17 end architecture arch_comb1;

2.3.2 Description comportementale 2

1 architecture arch_comb2 of Mux4 is

2 begin
3

4 process (I0,I1,I2,I3,A,B)
5 begin
6 if ( A = ’0’ and B= ’0’) then Q<= I0;
7 elsif ( A = ’0’ and B= ’1’) then Q<= I1;
8 elsif ( A = ’1’ and B= ’0’) then Q<= I2;
9 elsif ( A = ’1’ and B= ’1’) then Q<= I3;
10 end if;
11 end process;
12 end architecture arch_comb2;

Correction TD 2 R.Hertelli : [email protected] 4/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

2.3.3 Description float de données 1

1 architecture arch_flotData1 of Mux4 is

2 begin
3 Q <= (not(A) and not (B) and I0) or (not(A) and B and I1)
4 or (A and not (B) and I2) or (A and B and I3) ;
5 end arch_flotData1;

2.3.4 Description float de données 2

1 architecture arch_flotData2 of Mux4 is

2 signal sel : std_logic_vector(1 downto 0);
3 begin
4 sel <= (A,B);
5

6 with sel select

7 Q <= I0 when "00",
8 I1 when "01",
9 I2 when "10",
10 I3 when "11",
11 ’X’ when others;
12 end architecture arch_flotData2;

2.3.5 Description structurelle

AND3
La figure suivante représente le composant logique AND3

Figure 2 – AND3

Correction TD 2 R.Hertelli : [email protected] 5/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3

4 entity AND3 is
5 Port (e0,e1,e2 : in std_logic ;
6 s : out std_logic);
7 end AND3;
8

9 architecture arch_DataFloat of AND3 is

10 begin
11 s <= e0 and e1 and e2 ;
12 end arch_DataFloat;

OR4
La figure suivante représente le composant logique OR4

Figure 3 – OR4

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3

4 entity OR4 is
5 Port (e0,e1,e2,e3 : in std_logic ;
6 s : out std_logic);
7 end OR4;
8

9 architecture arch_DataFloat of OR4 is

10 begin
11 s <= e0 or e1 or e2 or e3 ;
12 end arch_DataFloat;

Correction TD 2 R.Hertelli : [email protected] 6/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

Structure interne Mux4

La figure suivante représente la composition interne de Mux4 à l’aide de AND3 et OR4.

Figure 4 – Mux4 vue externe

Figure 5 – Mux4 vue interne

1 architecture arch_struct of Mux4 is

2

3 component AND3 is
4 Port (e0,e1,e2 : in std_logic ;
5 s : out std_logic);
6 end component AND3;

Correction TD 2 R.Hertelli : [email protected] 7/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

8 component OR4 is
9 Port (e0,e1,e2,e3 : in std_logic ;
10 s : out std_logic);
11 end component OR4;
12

13 --signaux internes
14 signal x0,x1,x2,x3 : std_logic ;
15 signal notA, notB : std_logic ;
16

17 begin
18 --Preparation des signaux inversees
19 notA <= not(A);
20 notB <= not(B);
21

22 --Instanciation et port mapping

23 UT0 : AND3 port map (notA,notB,I0,x0);
24 UT1 : AND3 port map (notA,B,I1,x1);
25 UT2 : AND3 port map (A,notB,I2,x2);
26 UT3 : AND3 port map (A,B,I3,x3);
27

28 UTT : OR4 port map (x0,x1,x2,x3,Q);

29 end architecture arch_struct;

2.4 Test et simulation

La figure suivante représente le principe de simulation :

Figure 6 – Simulation Mux4

Correction TD 2 R.Hertelli : [email protected] 8/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3

4 --Entite vide sans Port

5 entity test_mux4 is
6 end entity test_mux4;
7

8 architecture testbench of test_mux4 is

9

10 --Importation de composant a tester

11 component Mux4 is
12 port ( I0,I1,I2,I3,A,B : in std_logic;
13 Q : out std_logic);
14 end component;
15

16 --Signaux interne de test

17 signal t_I0 , t_I1, t_I2,t_I3, t_A, t_B, t_Q :std_logic;
18

19 begin
20 --instatiation et port mapping
21 UT: Mux4 port map (t_I0,t_I1,t_I2,t_I3,t_A,t_B,t_Q);
22

23 --generation des tests

24 stimulus: process
25 begin
26 t_I0 <= ’0’;
27 t_I1 <= ’0’;
28 t_I2 <= ’0’;
29 t_I3 <= ’0’;
30

31 t_A <= ’0’;

32 t_B <= ’0’;
33 wait for 100 ns;
34

35

36 t_I0 <= ’0’;

37 t_I1 <= ’Z’;
38 t_I2 <= ’0’;
39 t_I3 <= ’1’;
40 wait for 50 ns;
41 t_A <= ’0’;
42 t_B <= ’1’;
43 wait for 100 ns;
44

45 t_I3 <= ’1’;

46 wait for 50 ns;

Correction TD 2 R.Hertelli : [email protected] 9/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

47 t_A <= ’1’;

48 t_B <= ’1’;
49 wait for 100 ns;
50 end process;
51 end architecture testbench;
52

53 --selection architecture a tester

54 configuration config1 of test_mux4 is
55 for testbench
56 for UT : Mux4
57 use entity work.Mux4(arch_struct);
58 end for;
59 end for ;
60 end config1;

3 Correction exercice 3 :

Figure 7 – Demux 1 à 8

3.1 Conception Demux

1 library IEEE;
2 use IEEE.std_logic_1164.all;

Correction TD 2 R.Hertelli : [email protected] 10/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

3 use IEEE.std_logic_unsigned.all;
4

6 entity Demux_1_To_8 is
7 port (G : in std_logic;
8 A : in std_logic_vector(2 downto 0);
9 Y : out std_logic_vector(7 downto 0) );
10 end Demux_1_To_8;
11

12 architecture arch1 of Demux_1_To_8 is

13 begin
14 PROCESS (G, A)
15 BEGIN
16 if (G = ’0’) then
17 Y <= (others => ’0’);
18 else
19 case A is
20 when "000" => Y <= "00000001";
21 when "001" => Y <= "00000010";
22 when "010" => Y <= "00000100";
23 when "011" => Y <= "00001000";
24 when "100" => Y <= "00010000";
25 when "101" => Y <= "00100000";
26 when "110" => Y <= "01000000";
27 when "111" => Y <= "10000000";
28 when others => Y <= "ZZZZZZZZ";
29 end case;
30 end if;
31 END PROCESS;
32 end architecture arch1;
33

34 architecture arch2 of Demux_1_To_8 is

35 begin
36 process (A,G)
37 begin
38 Y <= (others =>’0’); -- forcement en premier lieu
39 if (G = ’1’) then
40 Y(CONV_INTEGER(A)) <= ’1’;
41 --Le probleme avec cette description est que indice du bit dans Y
42 -- doit etre de type entier alors que A est de type std_logic_vector.
43 --Il faut donc utiliser une fonction de conversion definie dans le
44 -- package std_logic_unsigned, CONV_INTEGER. La conversion du
45 -- std_logic_vector en entier est obligatoire.
46 end if ;
47 end process;
48 end architecture arch2;

Correction TD 2 R.Hertelli : [email protected] 11/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

3.2 Test et simulation

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4

5 entity Test_Demux is
6 end entity Test_Demux;
7

9 architecture testbench of Test_Demux is

10

11 component Demux_1_To_8 is
12 port (G : in std_logic;
13 A : in std_logic_vector(2 downto 0);
14 Y : out std_logic_vector(7 downto 0) );
15 end component Demux_1_To_8;
16

17 signal t_G : std_logic;

18 signal t_A : std_logic_vector (2 downto 0);
19 signal t_Y : std_logic_vector (7 downto 0);
20

21 signal an : unsigned (2 downto 0):="000";

22

23 begin
24 UU : Demux_1_To_8 port map (t_G,t_A,t_Y);
25

26 process
27 begin
28 t_G<= ’0’;
29 t_A <= (others => ’0’);
30 wait for 100 ns;
31

32 bb : for i in 0 to 8 loop
33 t_A <= std_logic_vector (an);
34 an <= an +1;
35 wait for 50 ns;
36 t_G <=’1’;
37 end loop bb;
38 end process;
39 end architecture testbench;
40

41 --selection architecture a tester

42 configuration conf of Test_Demux is

Correction TD 2 R.Hertelli : [email protected] 12/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

43 for testbench
44 for UU : Demux_1_To_8
45 use entity work.Demux_1_To_8(arch1);
46 end for;
47 end for ;
48 end conf;

4 Correction exercice 4 :

Figure 8 – Encodeur de priorité 8 à 3

4.1 Encodeur de priorité 8 à 3 : Entité et architecture

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_arith.all;
4

5 entity Priority_Encode_8_to_3 is
6 port (E: in std_logic_vector (7 downto 0);
7 S : out std_logic_vector (2 downto 0);
8 GS : out std_logic);
9 end entity Priority_Encode_8_to_3;
10

11 architecture arch1 of Priority_Encode_8_to_3 is

12 begin
13 process (E)
14 begin

Correction TD 2 R.Hertelli : [email protected] 13/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

15 if ( E = "00000000") then
16 GS <= ’1’;
17 else
18 GS <= ’0’;
19 end if ;
20

21 S <= (Others => ’0’); -- Faire sortir 0

22 cherche : for I in E’Range loop -- pour I = 7,6,5,4,3,2,1,0
23 if ( E(I) = ’1’ ) then
24 S <= CONV_STD_LOGIC_VECTOR(I,3) ;
25 -- I est entier , S est un std_logic_vector(2 downto 0)
26 -- La conversion est obligatoire "CONV_STD_LOGIC_VECTOR"
27 exit cherche; -- sortir de la boucle cherche
28 end if;
29 end loop cherche;
30 end process;
31 end architecture arch1;

4.2 Encodeur de priorité 8 à 3 : Test et simulation

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4

5 entity test_Priority_Encoder is
6 end entity test_Priority_Encoder;
7

8 architecture testbench of test_Priority_Encoder is

9

10 --Importation du composant
11 component Priority_Encode_8_to_3 is
12 port (E: in std_logic_vector (7 downto 0);
13 S : out std_logic_vector (2 downto 0);
14 GS : out std_logic);
15 end component Priority_Encode_8_to_3;
16

17 --signaux interne de test

18 signal t_E : std_logic_vector (7 downto 0);
19 signal t_S : std_logic_vector (2 downto 0);
20 signal t_GS: std_logic;
21

22 signal en : unsigned (7 downto 0);

Correction TD 2 R.Hertelli : [email protected] 14/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

23

24 begin
25 --instantiation et port mapping
26 UT : Priority_Encode_8_to_3 port map(t_E,t_S,t_GS);
27

28 process
29 begin
30 en <= (others => ’0’);
31 wait for 100 ns;
32

33 b0 : for i in 0 to 2**8 loop

34 t_E <= std_logic_vector (en);
35 en <= en +1;
36 wait for 100 ns;
37 end loop b0;
38

39 end process;
40 end architecture testbench;

4.3 Encodeur de priorité 2n à n :Entité et architecture

1 library IEEE;
2 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_arith.all;
4

5 entity Priority_Encode is
6 generic (n : positive);
7 port (E: in std_logic_vector ((2**n)-1 downto 0);
8 S : out std_logic_vector (n-1 downto 0);
9 GS : out std_logic);
10 end entity Priority_Encode;
11

12 architecture arch of Priority_Encode is

13 signal nul : std_logic_vector ((2**n)-1 downto 0) ;
14 begin
15 nul <= (others =>’0’);
16 process (E)
17 begin
18 if ( E = nul) then
19 GS <= ’1’;
20 else
21 GS <= ’0’;

Correction TD 2 R.Hertelli : [email protected] 15/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

22 end if ;
23

24 S <= (Others => ’0’); -- Faire sortir 0

25 cherche : for I in E’Range loop
26 if ( E(I) = ’1’ ) then
27 S <= CONV_STD_LOGIC_VECTOR(I,n) ; --
28 exit cherche; -- sortir de la boucle cherche
29 end if;
30 end loop cherche;
31 end process;
32 end architecture arch;

4.4 Encodeur de priorité 2n à n :Test et simulation

1 library ieee;
2 use ieee.std_logic_1164.all;
3 use IEEE.numeric_std.all;
4

5 entity test_Priority_Encoder_Gen is
6 generic (m : positive := 8 );
7 end entity test_Priority_Encoder_Gen;
8

9 architecture testbench of test_Priority_Encoder_Gen is

10

11 component Priority_Encode is
12 generic (n : positive);
13 port (E: in std_logic_vector ((2**n)-1 downto 0);
14 S : out std_logic_vector (n-1 downto 0);
15 GS : out std_logic);
16 end component Priority_Encode;
17

18 signal t_E : std_logic_vector ((2**m)-1 downto 0);

19 signal t_S : std_logic_vector (m-1 downto 0);
20 signal t_GS: std_logic;
21

22 signal en : unsigned ((2**m)-1 downto 0);

23

24 begin
25 UT : Priority_Encode generic map (m) port map(t_E,t_S,t_GS);
26

27 process
28 begin

Correction TD 2 R.Hertelli : [email protected] 16/17

 Conception de circuits numériques (FPGA) : 2016 / 2017 Iset Béja

29 en <= (others => ’0’);

30 wait for 100 ns;
31

32 b0 : for i in 0 to 2**m loop

33 t_E <= std_logic_vector (en);
34 en <= en +1;
35 wait for 100 ns;
36 end loop b0;
37

38 end process;
39 end architecture testbench;

Correction TD 2 R.Hertelli : [email protected] 17/17