Department of Information Technology IT - Regulations 2017

b) 1 byte
EC8691 c) 3 bytes
d) 4 bytes
MICROPROCESSORS

M
AND Answer: b
Explanation: This format is only one byte
MICROCONTROLLERS long.

O
4. The instruction format ‘register to register’
IT - 5th SEMESTER has a length of

C
a) 2 bytes
b) 1 byte

T.
c) 3 bytes
d) 4 bytes

UNIT I THE 8086

O
Answer: a
Explanation: This format is 2 bytes long.
MICROPROCESSOR

SP
5. The R/M field in a machine instruction
TOPIC 1.1 INTRODUCTION TO format specifies
a) another register
8086 MICROPROCESSOR b) another memory location
G
ARCHITECTURE c) other operands
d) all of the mentioned
LO

1. Operation code field is present in :

a) programming language instruction Answer: d
b) assembly language instruction Explanation: The LSBs(least significant bits)
c) machine language instruction from 0 to 3 represent R/M field that specifies
d) none of the mentioned another register or memory location i.e. the
.B

other operand.
Answer: c
Explanation: Machine language instruction 6. In a machine instruction format, S-bit is the
17

format has one or more fields. The first one is a) status bit
the operation code field. b) sign bit
c) sign extension bit
2. A machine language instruction format d) none of the mentioned
-R

consists of
a) Operand field Answer: c
b) Operation code field Explanation: The S-bit known as sign
c) Operation code field & operand field extension bit is used along with W-bit to
SE

d) none of the mentioned show the type of operation.

Answer: c 7. The bit which is used by the ‘REP’

Explanation: Machine language instruction instruction is
a) W-bit
C

format has both the fields.

b) S-bit
3. The length of the one-byte instruction is c) V-bit
a) 2 bytes d) Z-bit

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 Department of Information Technology IT - Regulations 2017

Answer: d c) branch instructions

Explanation: The Z-bit is used by the REP d) control transfer & branch instructions
instruction to control the loop.
Answer: d
8. If a W-bit value is ‘1’ then the operand is Explanation: The JUMP instruction transfers

M
of the control to the address located in the
a) 8 bits instruction.
b) 4 bits

O
c) 16 bits
d) 2 bits
TOPIC 1.2 ADDRESSING
MODES

C
Answer: c

T.
Explanation: If W-bit is ‘1’ then the operand 1. The instruction, Add #45,R1 does _______
is of 16-bits, and if it is ‘0’ then the operand a) Adds the value of 45 to the address of R1
is of 8-bits. and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in

O
9. The instructions which after execution R1
transfer control to the next instruction in the c) Finds the memory location 45 and adds

SP
sequence are called that content to that of R1
a) Sequential control flow instructions d) None of the mentioned
b) control transfer instructions
c) Sequential control flow & control transfer Answer: b
G
instructions Explanation: The instruction is using
d) none of the mentioned immediate addressing mode hence the value
is stored in the location 45 is added.
LO

Answer: a
Explanation: The sequential control flow 2. In the case of, Zero-address instruction
instructions follow sequence order in their method the operands are stored in _____
execution. a) Registers
.B

b) Accumulators
10. The instructions that transfer the control c) Push down stack
to some predefined address or the address d) Cache
specified in the instruction are called as
17

a) sequential control flow instructions Answer: c

b) control transfer instructions Explanation: In this case, the operands are
c) sequential control flow & control transfer implicitly loaded onto the ALU.
instructions
-R

d) none of the mentioned 3. Add #45, when this instruction is executed

the following happen/s _______
Answer: b a) The processor raises an error and requests
Explanation: The control transfer
SE

for one more operand

instructions transfer control to the specified b) The value stored in memory location 45 is
address. retrieved and one more operand is requested
c) The value 45 gets added to the value on the
11. The instruction “JUMP” belongs to stack and is pushed onto the stack
C

a) sequential control flow instructions d) None of the mentioned

b) control transfer instructions

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 Department of Information Technology IT - Regulations 2017

Answer: b purpose registers as well as memory locations

Explanation: None. a) 1, 2, 3
b) 2
4. The addressing mode which makes use of c) 1, 3
in-direction pointers is ______ d) 2, 3

M
a) Indirect addressing mode
b) Index addressing mode Answer: d
c) Relative addressing mode Explanation: In the case of, auto increment

O
d) Offset addressing mode the increment is done afterward and in auto
decrement the decrement is done first.

C
Answer: a
Explanation: In this addressing mode, the 8. The addressing mode, where you directly

T.
value of the register serves as another specify the operand value is _______
memory location and hence we use pointers a) Immediate
to get the data. b) Direct
c) Definite

O
5. In the following indexed addressing mode d) Relative
instruction, MOV 5(R1), LOC the effective

SP
address is ______ Answer: a
a) EA = 5+R1 Explanation: None.
b) EA = R1
c) EA = [R1] 9. The effective address of the following
instruction is MUL 5(R1,R2).
G
d) EA = 5+[R1]
a) 5+R1+R2
Answer: d b) 5+(R1*R2)
LO

Explanation: This instruction is in Base with c) 5+[R1]+[R2]

offset addressing mode. d) 5*([R1]+[R2])

6. The addressing mode/s, which uses the PC Answer: c

instead of a general purpose register is Explanation: The addressing mode used is
.B

______ base with offset and index.

a) Indexed with offset
b) Relative 10. _____ addressing mode is most suitable to
17

c) Direct change the normal sequence of execution of

d) Both Indexed with offset and direct instructions.
a) Relative
Answer: b b) Indirect
-R

Explanation: In this, the contents of the PC c) Index with Offset

are directly incremented. d) Immediate

7. When we use auto increment or auto Answer: a

SE

decrements, which of the following is/are Explanation: The relative addressing mode is
true? used for this since it directly updates the PC.
1) In both, the address is used to retrieve the
operand and then the address gets altered
TOPIC 1.3 INSTRUCTION SET
C

2) In auto increment, the operand is retrieved

first and then the address altered AND ASSEMBLER DIRECTIVES
3) Both of them can be used on general

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 Department of Information Technology IT - Regulations 2017

1. The assembler directives which are the allocating memory locations in the available
hints using some predefined alphabetical memory.
strings are given to
a) processor 4. The directive that marks the end of an
b) memory assembly language program is

M
c) assembler a) ENDS
d) processor & assembler b) END
c) ENDS & END

O
Answer: c d) None of the mentioned
Explanation: These directives help the

C
assembler to correctly understand the Answer: b
assembly language programs to prepare the Explanation: The directive END is used to

T.
codes. denote the completion of the program.

2. The directive used to inform the assembler, 5. The directive that marks the end of a
the names of the logical segments to be logical segment is

O
assumed for different segments used in the a) ENDS
program is b) END

SP
a) ASSUME c) ENDS & END
b) SEGMENT d) None of the mentioned
c) SHORT
d) DB Answer: a
Explanation: The directive ENDS is used to
G
Answer: a end a segment where as the directive END is
Explanation: In ALP, each segment is given used to end the program.
LO

a name by using the directive ASSUME

SYNTAX: ASSUME segment:segment_name 6. The directive that updates the location
Eg: ASSUME CS:Code counter to the next even address while
here CS is the Code segment and code is the executing a series of instructions is
a) EVN
.B

name assumed to the segment.

b) EVEN
3. Match the following c) EVNE
d) EQU
17

a) DB 1) used to direct the a

ssembler to reserve only 10-bytes Answer: b
b) DT 2) used to direct the a Explanation: The directive updates location
ssembler to reserve only 4 words
c) DW 3) used to direct the a counter to next even address if the current
-R

ssembler to reserve byte or bytes location counter contents are not even.
d) DQ 4) used to direct the a
ssembler to reserve words 7. The directive that directs the assembler to
start the memory allotment for a particular
SE

a) a-3, b-2, c-4, d-1 segment/block/code from the declared

b) a-2, b-3, c-1, d-4 address is
c) a-3, b-1, c-2, d-4 a) OFFSET
d) a-3, b-1, c-4, d-2 b) LABEL
C

c) ORG
Answer: d d) GROUP
Explanation: These directives are used for

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 Department of Information Technology IT - Regulations 2017

Answer: c 1. __________ converts the programs written

Explanation: If an ORG is written then the in assembly language into machine
assembler initiates the location counter to instructions.
keep the track of allotted address for the a) Machine compiler
module as mentioned in the directive. b) Interpreter

M
If the directive is not present, then the c) Assembler
location counter is initialized to 0000H. d) Converter

O
8. The directive that marks the starting of the Answer: c
logical segment is Explanation: An assembler is a software

C
a) SEG used to convert the programs into machine
b) SEGMENT instructions.

T.
c) SEG & SEGMENT
d) PROC 2. The instructions like MOV or ADD are
called as ______
Answer: b a) OP-Code

O
Explanation: The directive SEGMENT b) Operators
indicates the beginning of the segment. c) Commands

SP
d) None of the mentioned
9. The recurrence of the numerical values or
constants in a program code is reduced by Answer: a
a) ASSUME Explanation: This OP – codes tell the system
G
b) LOCAL what operation to perform on the operands.
c) LABEL
d) EQU 3. The alternate way of writing the
LO

instruction, ADD #5,R1 is ______

Answer: d a) ADD [5],[R1];
Explanation: In this, the recurring/repeating b) ADDI 5,R1;
value is assigned with a label. The label is c) ADDIME 5,[R1];
.B

placed instead of the numerical value in the d) There is no other way

entire program code.
Answer: b
10. The labels or constants that can be used Explanation: The ADDI instruction, means
17

by any module in the program is possible the addition is in immediate addressing mode.
when they are declared as
a) PUBLIC 4. Instructions which won’t appear in the
b) LOCAL object program are called as _____
-R

c) GLOBAL a) Redundant instructions

d) Either PUBLIC or GLOBAL b) Exceptions
c) Comments
Answer: c d) Assembler Directives
SE

Explanation: The labels, constants, variables,

procedures declared as GLOBAL can be used Answer: d
by any module in the program. Explanation: The directives help the program
in getting compiled and hence won’t be there
C

in the object code.

TOPIC 1.4 ASSEMBLY
LANGUAGE PROGRAMMING

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 Department of Information Technology IT - Regulations 2017

5. The assembler directive EQU, when used Answer: d

in the instruction: Sum EQU 200 does Explanation: This instruction is used to
________ allocate a block of memory and to store the
a) Finds the first occurrence of Sum and object code of the program there.
assigns value 200 to it

M
b) Replaces every occurrence of Sum with 9. _____ directive specifies the end of
200 execution of a program.
a) End

O
c) Re-assigns the address of Sum by adding
200 to its original address b) Return
d) Assigns 200 bytes of memory starting the c) Stop

C
location of Sum d) Terminate

T.
Answer: b Answer: b
Explanation: This basically is used to replace Explanation: This instruction directive is
the variable with a constant value. used to terminate the program execution.

O
6. The purpose of the ORIGIN directive is 10. The last statement of the source program
__________ should be _______

SP
a) To indicate the starting position in memory, a) Stop
where the program block is to be stored b) Return
b) To indicate the starting of the computation c) OP
code d) End
G
c) To indicate the purpose of the code
d) To list the locations of all the registers used Answer: d
Explanation: This enables the processor to
LO

Answer: a load some other process.

Explanation: This does the function similar
to the main statement. 11. When dealing with the branching code the
assembler ___________
a) Replaces the target with its address
.B

7. The directive used to perform initialization

before the execution of the code is ______ b) Does not replace until the test condition is
a) Reserve satisfied
b) Store c) Finds the Branch offset and replaces the
17

c) Dataword Branch target with it

d) EQU d) Replaces the target with the value specified
by the DATAWORD directive
Answer: c
-R

Explanation: None. Answer: c

Explanation: When the assembler comes
8. _____ directive is used to specify and across the branch code, it immediately finds
assign the memory required for the block of the branch offset and replaces it with it.
SE

code.
a) Allocate 12. The assembler stores all the names and
b) Assign their corresponding values in ______
c) Set a) Special purpose Register
C

d) Reserve b) Symbol Table

c) Value map Set
d) None of the mentioned

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 Department of Information Technology IT - Regulations 2017

Answer: b a) Modularity principles

Explanation: The table where the assembler b) Implementary principles
stores the variable names along with their c) Aesthetic principles
corresponding memory locations and values. d) All of the mentioned

M
13. The assembler stores the object code in Answer: d
______ Explanation: All of the mentioned principles
a) Main memory are known as constructive design principles.

O
b) Cache
c) RAM 2. What is the Aesthetic principle among the

C
d) Magnetic disk following?
a) High quality programs can be constructed

T.
Answer: d from self contained, understandable parts or
Explanation: After compiling the object modules
code, the assembler stores it in the magnetic b) A design will be more or less easy to be
disk and waits for further execution. build

O
c) Beauty is one of the important factor to be
14. The utility program used to bring the acknowledged as design principle

SP
object code into memory for execution is d) None of the mentioned
______
a) Loader Answer: c
b) Fetcher Explanation: Aesthetic principle states
G
c) Extractor Beauty as one of the most important factor to
d) Linker be acknowledged.
LO

Answer: a 3. Which of these distinctions of modular

Explanation: The program is used to load the programs over non modular are true?
program into memory. a) They are not that easier to understand and
explain
15. To overcome the problems of the
.B

b) They are not easier to document

assembler in dealing with branching code we c) They are easier to change
use _____ d) Testing and Debugging is complex
a) Interpreter comparatively
17

b) Debugger
c) Op-Assembler Answer: c
d) Two-pass assembler Explanation: Modular programs are easier to
explain and understand, easier to document,
-R

Answer: d easier to change and also easier to test and

Explanation: This creates entries into the debug.
symbol table first and then creates the object
code. 4. Which of these comes under the
SE

Modularity principle?
a) Small modules
TOPIC 1.5 MODULAR b) Coupling
PROGRAMMING c) Cohesion
C

d) All of the mentioned

1. Which of the following fall under
constructive design principles?

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 Department of Information Technology IT - Regulations 2017

Answer: d 8. Which of the following violates principle

Explanation: All the mentioned follows the of least privilege?
modularity principle. a) Modules that import packages
b) Modules with unneeded access to files
5. What does Coupling mean? c) Classes with reference to Objects

M
a) Coupling is the degree of connection d) All of the mentioned
between pair of module
b) Coupling is the degree to which a module’s Answer: d

O
part are related to one another Explanation: All of the mentioned statements
c) All of the mentioned violated principle of least privilege.

C
d) None of the mentioned
9. Which of these is correct with context to

T.
Answer: a coupling?
Explanation: Coupling is the degree of a) Failure to hide information leads to loose
connection between pair of module. coupling and cannot be avoided
b) Modules that communicate using special

O
6. Which of the following is true? data types and structures are less tightly
a) Module coupling should be maximized coupled than modules with simple values

SP
b) Module cohesion should be minimized c) When modules communicate only through
c) Modules should not have access to public module interface, their coupling
unneeded resources strength is proportional to the number of
d) Design with small modules are not better messages and number of data passed in
G
between
Answer: c d) All of the mentioned
Explanation: Module coupling should be
LO

minimized, module cohesion should be Answer: c

maximized, design with small modules are Explanation: Failure to hide information
always better, modules should not access leads to tight coupling, Modules with special
unneeded resources( principle of least data types are more tightly coupled.
.B

privilege).
10. Which of these is correct with the context
7. Which of the following information should of cohesion?
be kept hidden? a) Cohesion is least in modules that have a
17

a) Internal data representation such as data single clear, logically independent

types and structures responsibility or role
b) Volatile design decisions such as size, b) Cohesion can not be achieved by forming
capacities, waiting time etc modules that implement data types
-R

c) Names, parameters, return types of c) One way to increase cohesion is to build a

operations provided by module module hierarchy reflecting the level of
d) Internal data representation and volatile abstraction in a program
SE

design decisions should be kept hidden d) All of the mentioned

Answer: d Answer: c
Explanation: Names, parameters, return type Explanation: Cohesion is highest in modules
are public information need not be hidden that have a single clear, logically independent
C

whereas internal data representation and responsibility or role, Cohesion can be easily
volatile design decisions should be kept achieved by forming modules that implement
hidden. data types are the correct statements.

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 Department of Information Technology IT - Regulations 2017

TOPIC 1.6 LINKING AND Answer: d

Explanation: A macro can be defined
RELOCATION - STACKS - anywhere in a program.
PROCEDURES - MACROS
5. A macro can be used as ________

M
1. If a number of instructions are repeating a) in data segment
through the main program, then to reduce the b) to represent directives
c) to represent statements

O
length of the program, __________ is used.
a) procedure d) all of the mentioned
b) subroutine

C
Answer: d
c) macro
Explanation: A macro may be used in data
d) none of the mentioned

T.
segment and can also be used to represent
Answer: c statements and directives.
Explanation: For a certain number of
6. The end of a macro can be represented by

O
instructions that are repeated in the main
the directive.
program, when macro is defined then the
a) END
code of a program is reduced by placing the

SP
b) ENDS
name of the macro at which the set of
c) ENDM
instructions are needed to be repeated.
d) ENDD
2. The process of assigning a label or
Answer: c
G
macroname to the string is called
Explanation: The ENDM directive marks the
a) initialising macro
end of the instructions or statements sequence
LO

b) initialising string macro

assigned with the macro name.
c) defining a string macro
d) defining a macro 7. Inserting the statements and instructions
represented by macro, directly at the place of
Answer: d
the macroname, in the program, is known as
.B

Explanation: The process of assigning a label

a) calling a macro
to the string is called defining a macro.
b) inserting a macro
c) initializing a macro
17

3. A macro within a macro is called

a) macro-within-macro d) none of the mentioned
b) nested macro
Answer: a
c) macro-in-macro
Explanation: Inserting the statements and
d) none of the mentioned
-R

instructions at the place of macroname, in the

Answer: b program, is known as calling a macro.
Explanation: A macro may be called from
8. The time required for execution of a macro
SE

inside a macro. This type of macro is called

is ________ that of the procedure.
nested macro.
a) greater than
4. A macro can be defined as b) less than
a) beginning of a program c) equal to
C

b) end of a program d) none of the mentioned

c) after initialisation of program
d) anywhere in a program

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 Department of Information Technology IT - Regulations 2017

Answer: b Answer: c
Explanation: The time required for execution Explanation: An interrupt function is to
of a macro is less than that of procedure as it break the sequence of operation.
does not contain CALL and RET instructions
as the procedures do. 2. An interrupt breaks the execution of

M
instructions and diverts its execution to
9. Which of the following statements is a) Interrupt service routine
incorrect? b) Counter word register

O
a) complete code of instruction string is c) Execution unit
inserted at each place, wherever the d) control unit

C
macroname appears
b) macro requires less time of execution than Answer: a

T.
that of procedure Explanation: An interrupt transfers the
c) macro uses stack memory control to interrupt service routine (ISR).
d) macroname can be anything except After executing ISR, the control is transferred
registers and mnemonics back again to the main program.

O
Answer: c 3. While executing the main program, if two

SP
Explanation: Macro does not require stack or more interrupts occur, then the sequence of
memory and hence has less time for appearance of interrupts is called
execution. a) multi-interrupt
b) nested interrupt
G
10. The beginning of the macro can be c) interrupt within interrupt
represented as d) nested interrupt and interrupt within
a) START interrupt
LO

b) BEGIN
c) MACRO Answer: d
d) None of the mentioned Explanation: If an interrupt occurs while
executing a program, and the processor is
.B

Answer: c executing the interrupt, if one more interrupt

Explanation: The beginning of the macro is occurs again, then it is called a nested
represented as macroname followed by the interrupt.
directive MACRO.
17

SYNTAX: macroname MACRO 4. Whenever a number of devices interrupt a

EXAMPLE: STRINGS MACRO. CPU at a time, and if the processor is able to
handle them properly, it is said to have
a) interrupt handling ability
-R

TOPIC 1.7 INTERRUPTS AND b) interrupt processing ability

INTERRUPT SERVICE c) multiple interrupt processing ability
ROUTINES d) multiple interrupt executing ability
SE

Answer: c
1. While CPU is executing a program, an
Explanation: The processor if handles more
interrupt exists then it
devices as interrupts then it has multiple
a) follows the next instruction in the program
interrupt processing ability.
C

b) jumps to instruction in other registers

c) breaks the normal sequence of execution of 5. NMI stands for
instructions a) nonmaskable interrupt
d) stops executing the program

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 Department of Information Technology IT - Regulations 2017

b) nonmultiple interrupt 10. The INTR interrupt may be masked using

c) nonmovable interrupt the flag
d) none of the mentioned a) direction flag
b) overflow flag
Answer: a c) interrupt flag

M
Explanation: NMI is the acronym for d) sign flag
nonmaskable interrupt.
Answer: c

O
7. If any interrupt request given to an input Explanation: If a microprocessor wants to
pin cannot be disabled by any means then the serve any interrupt then interrupt flag, IF=1.

C
input pin is called If interrupt flag, IF=0, then the processor
a) maskable interrupt ignores the service.

T.
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable
interrupt TOPIC 1.8 BYTE AND STRING
d) none of the mentioned MANIPULATION.

O
Answer: b 1. Which of these methods of Byte wrapper

SP
Explanation: A nonmaskable interrupt input can be used to obtain Byte object from a
pin is one which means that any interrupt string?
request at NMI (nonmaskable interrupt) input a) toString()
cannot be masked or disabled by any means. b) getString()
G
c) decode()
8. The INTR interrupt may be d) encode()
a) maskable
LO

b) nonmaskable Answer: c
c) maskable and nonmaskable Explanation: decode() methods returns a
d) none of the mentioned Byte object that contains the value specified
by string.
Answer: a
.B

Explanation: the INTR (interrupt request) is 2. Which of the following methods Byte
maskable or can be disabled. wrapper return the value as a double?
a) doubleValue()
17

9. The Programmable interrupt controller is b) converDouble()

required to c) getDouble()
a) handle one interrupt request d) getDoubleValue()
b) handle one or more interrupt requests at a
-R

time Answer: a
c) handle one or more interrupt requests with Explanation: doubleValue() returns the value
a delay of invoking object as double.
d) handle no interrupt request
SE

3. Which of these is a super class of wrappers

Answer: b Byte and short wrappers?
Explanation: If more than one interrupt a) Long
request (INTR) occurs at a time, then an b) Digits
C

external chip called programmable interrupt c) Float

controller is required to handle them. d) Number

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 Department of Information Technology IT - Regulations 2017

Answer: d MAX_VALUE is 1.7976931348623157E308.

Explanation: Number is an abstract class Output:
containing subclasses Double, Float, Byte,
$ javac Output.java
Short, Integer and Long. $ java Output

M
1.7976931348623157E308
4. Which of these methods is not defined in
both Byte and Short wrappers? 6. What will be the output of the following
a) intValue()

O
Java program?
b) isInfinite()
c) toString() 1. class Output

C
d) hashCode()
2. {

T.
Answer: b
Explanation: isInfinite() methods is defined 3. public static void main(Str
ing args[])
in Integer and Long Wrappers, returns true if
specified value is an infinite value otherwise 4.

O
{
it returns false.
5. Double i = new Double(2

SP
5. What will be the output of the following 57.5);
Java code?
6. Double x = i.MIN_VALUE;
1. class Output
7. System.out.print(x);
G
2. {
8. }
3.
LO

public static void main(Str

9. }
ing args[])

4. { a) 0
b) 4.9E-324
5. Double i = new Double(2 c) 1.7976931348623157E308
.B

57.5); d) None of the mentioned

6. Double x = i.MAX_VALUE;
Answer: b
17

7. System.out.print(x); Explanation: The super class of Byte class

defines a constant MIN_VALUE below
8. } which a number is considered to be negative
infinity. MIN_VALUE is 4.9E-324.
-R

9. } Output:
a) 0 $ javac Output.java
b) 1.7976931348623157E308 $ java Output
SE

4.9E-324
c) 1.7976931348623157E30
d) None of the mentioned
7. What will be the output of the following
Java program?
Answer: b
C

Explanation: The super class of Double class 1. class Output

defines a constant MAX_VALUE above
which a number is considered to be infinity. 2. {

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 Department of Information Technology IT - Regulations 2017

3. public static void main(Str 1. The mnemonic that is placed before the
ing args[]) arithmetic operation is performed is
a) AAA
4. {
b) AAS
c) AAM

M
5. Double i = new Double(2
57.578123456789); d) AAD

6. float x = i.floatValue( Answer: d

O
); Explanation: The AAD instruction converts
two unpacked BCD digits in AH and AL to
7.

C
System.out.print(x);
the equivalent binary number in AL.
8. }

T.
2. The Carry flag is undefined after
9. } performing the operation
a) AAA
a) 0 b) ADC

O
b) 257.0 c) AAM
c) 257.57812 d) AAD

SP
d) 257.578123456789
Answer: d
Answer: c Explanation: Since the operation, AAD is
Explanation: floatValue() converts the value performed before division operation is
G
of wrapper i into float, since float can performed, the carry flag, auxiliary flag and
measure till 5 places after decimal hence overflow flag are undefined.
257.57812 is stored in floating point variable
LO

x. 3. The instruction that performs logical AND

Output: operation and the result of the operation is not
available is
$ javac Output.java a) AAA
$ java Output
.B

257.57812 b) AND
c) TEST
d) XOR
Java Mock Tests & Certification Test | 1000
17

Java MCQs | 1000 Java Programs | 1000 Java Answer: c

Algorithms | Best Java Books Explanation: In the TEST instruction, the
logical AND operation is performed and the
result is not stored but flags are affected.
-R

4. In the RCL instruction, the contents of the

UNIT II 8086 SYSTEM destination operand undergo function as
a) carry flag is pushed into LSB & MSB is
SE

BUS STRUCTURE pushed into the carry flag

b) carry flag is pushed into MSB & LSB is
TOPIC 2.1 8086 SIGNALS - pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB
C

BASIC CONFIGURATIONS is pushed into the carry flag

d) parity flag is pushed into MSB & LSB is
pushed into the carry flag

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 Department of Information Technology IT - Regulations 2017

Answer: a Answer: c
Explanation: In RCL(Rotate right through Explanation: At each CALL instruction, the
carry), for each operation, the carry flag is IP and CS of the next instruction are pushed
pushed into LSB and the MSB of the operand onto the stack, before the control is
is pushed into carry flag. transferred to the procedure. At the end of the

M
procedure, the RET instruction must be
5. The instruction that is used as prefix to an executed to retrieve the stored contents of IP
instruction to execute it repeatedly until the

O
& CS registers from a stack.
CX register becomes zero is
a) SCAS 8. The instruction that unconditionally

C
b) REP transfers the control of execution to the
c) CMPS specified address is

T.
d) STOS a) CALL
b) JMP
Answer: b c) RET
Explanation: The instruction to which the d) IRET

O
REP is prefix, is executed repeatedly until CX
register becomes zero. When CX becomes Answer: b

SP
zero, the execution proceeds to the next Explanation: In this the control transfers to
instruction in sequence. the address specified in the instruction and
flags are not affected by this instruction.
6. Match the following
G
9. Which instruction cannot force the 8086
A) MOvSB/SW 1) loads AL/AX register processor out of ‘halt’ state?
by content of a string
a) Interrupt request
LO

B) CMPS 2) moves a string of by

tes stored in source to destination b) Reset
C) SCAS 3) compares two strings c) Both interrupt request and reset
of bytes or words whose length is stored d) Hold
in CX register
D) LODS 4) scans a string of by
.B

Answer: d
tes or words
Explanation: Only an interrupt request or
a) A-3,B-4,C-2,D-1 Reset will force the 8086 processor to come
out of the ‘halt’ state.
17

b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
10. NOP instruction introduces
d) A-2,B-3,C-4,D-1
a) Address
Answer: d b) Delay
-R

Explanation: By using the string instructions, c) Memory location

the operations on strings can be performed. d) None of the mentioned

Answer: b
SE

7. The instructions that are used to call a

subroutine from the main program and return Explanation: NOP is the No operation. It
to the main program after execution of called means that the processor performs no
function are operation for the clock cycle and thus there
exists a delay.
C

a) CALL, JMP
b) JMP, IRET
11. Which of the following is not a machine
c) CALL, RET
controlled instruction?
d) JMP, RET

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 Department of Information Technology IT - Regulations 2017

a) HLT read operation and the output activity is

b) CLC similar to write operation.
c) LOCK
d) ESC 4. The operation, IOWR (active low)
performs

M
Answer: b a) write operation on input data
Explanation: Since CLC is a flag b) write operation on output data
manipulation instruction where CLC stands c) read operation on input data

O
for Clear Carry Flag. d) read operation on output data

C
Answer: b
TOPIC 2.2 SYSTEM BUS Explanation: IOWR (active low) operation
TIMING - SYSTEM DESIGN

T.
means writing data to an output device and
USING 8086 - I/O not an input device.
PROGRAMMING
5. The latch or IC 74LS373 acts as

O
a) good input port
1. The device that enables the microprocessor b) bad input port
to read data from the external devices is

SP
c) good output port
a) printer d) bad output port
b) joystick
c) display Answer: c
d) reader Explanation: If the output port is to source
G
large currents, the port lines must be buffered.
Answer: b So, the latch is used as it acts as a good output
LO

Explanation: Since joystick is an input port.

device, it reads data from the external
devices. 6. While performing read operation, one must
take care that much current should not be
2. The example of output device is a) sourced from data lines
.B

a) CRT display b) sinked from data lines

b) 7-segment display c) sourced or sinked from data lines
c) Printer d) sinked from address lines
17

d) All of the mentioned

Answer: c
Answer: d Explanation: More current should not be
Explanation: The output device transfers sourced or sinked from data lines while
-R

data from the microprocessor to the external reading to avoid loading.

devices.
7. To avoid loading during read operation, the
3. The input and output operations are device used is
SE

respectively similar to the operations, a) latch

a) read, read b) flipflop
b) write, write c) buffer
c) read, write d) tristate buffer
C

d) write, read
Answer: d
Answer: c Explanation: A tristate buffer is used as an
Explanation: The input activity is similar to

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 Department of Information Technology IT - Regulations 2017

input device to overcome loading. attaching peripheral devices

d) None of the mentioned
8. The chip 74LS245 is
a) bidirectional buffer Answer: c
b) 8-bit input port Explanation: By using a single BUS

M
c) one that has 8 buffers structure we can minimize the amount of
d) all of the mentioned hardware (wire) required and thereby
reducing the cost.

O
Answer: d
Explanation: The chip 74LS245 is a 2. ______ are used to overcome the

C
bidirectional buffer that contains 8 buffers difference in data transfer speeds of various
and may be used as an 8-bit input port. But devices.

T.
while using as an input device, only one a) Speed enhancing circuitory
direction is useful. b) Bridge circuits
c) Multiple Buses
9. In 74LS245, if DIR is 1, then the direction d) Buffer registers

O
is from
a) inputs to outputs Answer: d

SP
b) outputs to inputs Explanation: By using Buffer registers, the
c) source to sink processor sends the data to the I/O device at
d) sink to source the processor speed and the data gets stored in
the buffer. After that the data gets sent to or
Answer: a
G
from the buffer to the devices at the device
Explanation: If DIR is 1, then the direction is speed.
from A(inputs) to B(outputs).
LO

3. To extend the connectivity of the processor

10. In memory-mapped scheme, the devices bus we use ________
are viewed as a) PCI bus
a) distinct I/O devices b) SCSI bus
b) memory locations
.B

c) Controllers
c) only input devices d) Multiple bus
d) only output devices
Answer: a
17

Answer: b Explanation: PCI BUS is used to connect

Explanation: In memory-mapped scheme, other peripheral devices that require a direct
the devices are viewed as memory locations connection with the processor.
and are addressed likewise.
-R

4. IBM developed a bus standard for their line

of computers ‘PC AT’ called _____
TOPIC 2.3 INTRODUCTION TO a) IB bus
MULTIPROGRAMMING - b) M-bus
SE

SYSTEM BUS STRUCTURE c) ISA

d) None of the mentioned
1. The main virtue for using single Bus
structure is ____________ Answer: c
C

a) Fast data transfers Explanation: None.

b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of

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 Department of Information Technology IT - Regulations 2017

5. The bus used to connect the monitor to the c) Better Connectivity

CPU is ______ d) None of the mentioned
a) PCI bus
b) SCSI bus Answer: a
c) Memory bus Explanation: None.

M
d) Rambus
10. The ISA standard Buses are used to
Answer: b connect ___________

O
Explanation: SCSI BUS is usually used to a) RAM and processor
connect video devices to the processor. b) GPU and processor

C
c) Harddisk and Processor
6. ANSI stands for __________ d) CD/DVD drives and Processor

T.
a) American National Standards Institute
b) American National Standard Interface Answer: c
c) American Network Standard Interfacing Explanation: None.
d) American Network Security Interrupt

O
Answer: a
TOPIC 2.4 MULTIPROCESSOR
CONFIGURATIONS -

SP
Explanation: None.
COPROCESSOR, CLOSELY
7. _____ register Connected to the Processor COUPLED AND LOOSELY
bus is a single-way transfer capable.
a) PC
COUPLED CONFIGURATIONS
G
b) IR
c) Temp 1. The processors used in the multi-
LO

d) Z microprocessor are
a) coprocessors
Answer: d b) independent processors
Explanation: The Z register is a special c) coprocessors or independent processors
register which can interact with the processor d) none of the mentioned
.B

BUS only.
Answer: c
8. In multiple Bus organisation, the registers Explanation: The processors used in the
17

are collectively placed and referred as ______ multi-microprocessor are either coprocessors
a) Set registers or independent processors.
b) Register file
c) Register Block 2. The processor that executes the instructions
-R

d) Map registers fetched for it by the host processor is

a) microprocessor
Answer: b b) coprocessor
Explanation: None. c) independent processor
SE

d) coprocessor and independent processor

9. The main advantage of multiple bus
organisation over a single bus is _____ Answer: b
a) Reduction in the number of cycles for Explanation: The coprocessor executes the
C

execution instructions fetched for it by the host

b) Increase in size of the registers processor.

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 Department of Information Technology IT - Regulations 2017

3. The processor that asks for bus access or its own bus control logic. The bus arbitration
may itself fetch the instructions and execute is handled by an external circuit, common to
them is all the processors.
a) microprocessor
b) coprocessor 7. The loosely coupled system has an

M
c) independent processor advantage of
d) coprocessor and independent processor a) more number of CPUs can be added
b) system structure is modular

O
Answer: c c) more fault-tolerant and suitable for parallel
Explanation: The independent processor may applications

C
ask for bus access, may fetch the instructions d) all of the mentioned
itself, and execute them independently.

T.
Answer: d
4. In tightly coupled systems, the Explanation: The loosely coupled system is
microprocessors share advantageous than the tightly coupled system
a) common clock as it has advantages of more number of CPUs

O
b) bus control logic can be added to improve the system
c) common clock and bus control logic performance. A fault in a single module does

SP
d) none of the mentioned not lead to a complete system breakdown.

Answer: c 8. In a tightly coupled system, when a

Explanation: The microprocessors share a processor is using the bus then the local bus
G
common clock and bus control logic, in a of other processors is in
tightly coupled system. a) hold state
b) high impedance state
LO

5. Communication between processors using c) halt state

a common system bus and common memory d) low impedance state
takes place in
a) loosely coupled system Answer: b
.B

b) tightly coupled system Explanation: When a processor is using the

c) tightly and loosely coupled system bus then the other processors maintain their
d) none of the mentioned local buses in high impedance state.
17

Answer: b 9. The disadvantage of the loosely coupled

Explanation: In tightly coupled systems, the system is
two processors may communicate using a a) complex due to additional hardware
common system bus or common memory. b) less portable
-R

c) more expensive
6. The bus arbitration is handled by an d) all of the mentioned
external circuit in
a) loosely coupled system Answer: d
SE

b) tightly coupled system Explanation: The loosely coupled systems

c) tightly and loosely coupled system are more complicated due to the required
d) none of the mentioned additional communication hardware. They are
less portable and more expensive due to
C

Answer: a additional hardware.

Explanation: In a loosely coupled
multiprocessor system, each CPU may have

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 Department of Information Technology IT - Regulations 2017

10. To indicate the completion of task c) privilege level

allocated in a closely (tightly) coupled d) all of the mentioned
system, the microprocessor uses
a) status bit in memory Answer: d
b) interrupts the host Explanation: The gate descriptor contains the

M
c) status bit in memory or interrupts the host information regarding the destination of
d) clock pulse control transfer, required stack manipulations,
privilege level and its type.

O
Answer: c
Explanation: The microprocessor in a closely 4. The gate that is used to alter the privilege

C
coupled system either uses a status bit in levels is
memory or interrupts the host to inform it a) call gate

T.
about the completion of task allotted to it. b) task gate
c) interrupt gate
d) trap gate
TOPIC 2.5 INTRODUCTION TO

O
ADVANCED PROCESSORS. Answer: a
Explanation: Call gates are used to alter the

SP
1. Which of the following is a type of system privilege levels.
segment descriptor?
a) system descriptor 5. The gate that is used to specify a
b) gate descriptor corresponding service routine is
a) call gate and trap gate
G
c) system descriptor and gate descriptor
d) none of the mentioned b) task gate and interrupt gate
c) interrupt gate and trap gate
LO

Answer: c d) task gate and trap gate

Explanation: The system segment descriptors
are of seven types. The types 1 to 3 are called Answer: c
system descriptors and the types 4 to 7 are Explanation: Interrupt gates and trap gates
are used to specify corresponding service
.B

called gate descriptors.

routines.
2. Which of the following is a type of gate
descriptor? 6. The gate that is used to switch from one
17

a) call gate task to another is

b) task gate a) trap gate
c) interrupt gate b) task gate
d) all of the mentioned c) task gate and trap gate
-R

d) none of the mentioned

Answer: d
Explanation: The gate descriptors are of four Answer: b
Explanation: Task gate is used to switch
SE

types namely, call gate, task gate, interrupt

gate and trap gate. from one task to another.

3. The gate descriptor contains the 7. The gate that uses word count field is
information of a) trap gate
C

a) destination of control transfer b) task gate

b) stack manipulations c) interrupt gate
d) call gate

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 Department of Information Technology IT - Regulations 2017

Answer: d a) LDT
Explanation: The word count field is only b) LGDT and LLDT
used by a call gate descriptor, to indicate the c) GDT
number of bytes to be transferred from the d) None of the mentioned
stack of the calling routine to the stack of the

M
called routine. Answer: b
Explanation: The LGDT and LLDT
8. The memory that maintains the most instructions are privileged, and may be

O
frequently required data for execution, in a executed only at privilege level 0.
high speed memory is called

C
a) virtual memory 12. The instruction that loads a selector which
b) physical memory refers to a local descriptor table, containing

T.
c) cache memory the base address and limit for LDT is
d) ROM (read only memory) a) LGT
b) GDT
Answer: c c) LGDT

O
Explanation: To minimize the time required d) LLDT
for fetching the frequently required descriptor

SP
information, from the main memory, cache Answer: d
memory is used in which the most frequently Explanation: The LLDT instruction loads a
required data for execution is stored. selector, which refers to a local descriptor
table, containing the base address, and limit
G
9. The selector field consists of for LDT.
a) requested privilege level (RPL)
b) table indicator 13. The descriptor that is used to store task
LO

c) index gates, interrupt gates and trap gates is

d) all of the mentioned a) system descriptor table
b) gate descriptor table
Answer: d c) interrupt descriptor table
.B

Explanation: In the protected mode, the d) none of the mentioned

contents of the segment registers are known
as selectors. The selector field consists of Answer: c
three fields namely, RPL, table indicator (TI) Explanation: The 80286 has a third type of
17

and index. descriptor table known as interrupt descriptor

table, which is used to store task gates,
10. If table indicator, TI=0, then the interrupt gates and trap gates.
descriptor table selected is
-R

a) local descriptor table 14. The number of interrupt descriptors that

b) global descriptor table the interrupt descriptor table (IDT) handles is
c) local and global descriptor table a) 16
b) 64
SE

d) none of the mentioned

c) 128
Answer: b d) 256
Explanation: The type of descriptor table is
global if TI=0 and local if TI=1. Answer: d
C

Explanation: The IDT is able to handle upto

11. The instruction that is executed at 256 interrupt descriptors.
privilege level zero (0) is

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 Department of Information Technology IT - Regulations 2017

15. The number of bytes required for an data from the microprocessor to the external
interrupt in an IDT is devices.
a) 2
b) 4 3. The input and output operations are
c) 6 respectively similar to the operations,

M
d) 8 a) read, read
b) write, write
Answer: c c) read, write

O
Explanation: Six bytes are required for each d) write, read
interrupt in an interrupt descriptor table.

C
Answer: c
Explanation: The input activity is similar to

T.
read operation and the output activity is
similar to write operation.
UNIT III I/O
4. The operation, IOWR (active low)
INTERFACING

O
performs
a) write operation on input data

SP
TOPIC 3.1 MEMORY b) write operation on output data
c) read operation on input data
INTERFACING AND I/O d) read operation on output data
INTERFACING - PARALLEL
COMMUNICATION INTERFACE Answer: b
G
- SERIAL COMMUNICATION Explanation: IOWR (active low) operation
means writing data to an output device and
INTERFACE
LO

not an input device.

1. The device that enables the microprocessor 5. The latch or IC 74LS373 acts as
to read data from the external devices is a) good input port
b) bad input port
.B

a) printer
b) joystick c) good output port
c) display d) bad output port
d) reader
17

Answer: c
Answer: b Explanation: If the output port is to source
Explanation: Since joystick is an input large currents, the port lines must be buffered.
device, it reads data from the external So, the latch is used as it acts as a good output
-R

devices. port.

2. The example of output device is 6. While performing read operation, one must
a) CRT display take care that much current should not be
SE

b) 7-segment display a) sourced from data lines

c) Printer b) sinked from data lines
d) All of the mentioned c) sourced or sinked from data lines
d) sinked from address lines
C

Answer: d
Explanation: The output device transfers Answer: c
Explanation: More current should not be

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 Department of Information Technology IT - Regulations 2017

sourced or sinked from data lines while the devices are viewed as memory locations
reading to avoid loading. and are addressed likewise.

7. To avoid loading during read operation, the

device used is TOPIC 3.2 D/A AND A/D

M
a) latch INTERFACE - TIMER
b) flipflop
c) buffer

O
1. How many control lines are present in
d) tristate buffer analog to digital converter in addition to
reference voltage?

C
Answer: d a) Three
Explanation: A tristate buffer is used as an b) Two

T.
input device to overcome loading. c) One
d) None of the mentioned
8. The chip 74LS245 is
a) bidirectional buffer Answer: b

O
b) 8-bit input port Explanation: ADC usually has two
c) one that has 8 buffers additional control lines

SP
d) all of the mentioned 1. Start input-tell ADC when to start
conversion.
Answer: d 2. EOC- end of conversion.
Explanation: The chip 74LS245 is a
bidirectional buffer that contains 8 buffers
G
2. Find out the integrating type analog to
and may be used as an 8-bit input port. But digital converter?
while using as an input device, only one a) Flash type converter
LO

direction is useful. b) Tracking converter

c) Counter type converter
9. In 74LS245, if DIR is 1, then the direction d) Dual slope ADC
is from
a) inputs to outputs
.B

Answer: d
b) outputs to inputs Explanation: Other than dual slope ADC the
c) source to sink rest belongs to direct type ADCs.
d) sink to source
17

3. Which type of ADC follow the conversion

Answer: a technique of changing the analog input signal
Explanation: If DIR is 1, then the direction is to a linear function of frequency?
from A(inputs) to B(outputs). a) Direct type ADC
-R

b) Integrating type ADC

10. In memory-mapped scheme, the devices c) Both integrating and direct type ADC
are viewed as d) None of the mentioned
a) distinct I/O devices
SE

b) memory locations Answer: b

c) only input devices Explanation: Integrating type ADC performs
d) only output devices conversion in an indirect manner by first
changing the analog input signal to a linear
C

Answer: b function of time or frequency and then to a

Explanation: In memory-mapped scheme, digital code.

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 Department of Information Technology IT - Regulations 2017

4. Which A/D converter is considered to be required almost doubles for each added bit.
simplest, fastest and most expensive? For example – 2 -bit ADC requires three
a) Servo converter comparators, 3 -bit ADC needs seven
b) Counter type ADC comparators and a 4 -bit ADC requires fifteen
c) Flash type ADC comparators.

M
d) All of the mentioned
8. Drawback of counter type A/D converter
Answer: c a) Counter clears automatically

O
Explanation: The simplest possible A/D b) More complex
converter is flash type converter and is c) High conversion time

C
expensive for high degree of accuracy. d) Low speed

T.
5. The flash type A/D converters are called as Answer: d
a) Parallel non-inverting A/D converter Explanation: In counter type ADC counter
b) Parallel counter A/D converter frequency is kept low enough to give
c) Parallel inverting A/D converter sufficient time for DAC to settle and for the

O
d) Parallel comparator A/D converter comparator for respond. So, low speed is the
most serious drawback.

SP
Answer: d
Explanation: The flash type A/D converter 9. Calculate the conversion time of a 12-bit
are also called as parallel comparator A/D counter type ADC with 1MHz clock frequent
converter because the purpose of the circuit is to convert a full scale input?
G
to compare the analog input voltage with each a) 4.095 µs
node voltage. b) 4.095ms
c) 4.095s
LO

6. What is the advantage of using flash type d) None of the mentioned

A/D converter?
a) High speed conversion Answer: b
b) Low speed conversion Explanation: conversion time = 2n -1 clock
.B

c) Nominal speed conversion

periods = (12n-1) = 4.095ms.
d) None of the mentioned
10. In a servo tracking A/D converter, the
Answer: a
17

input voltage is greater than the DAC output

Explanation: Flash type ADC has the signal at this condition
advantage of high speed as the conversion a) The counter count up
takes place simultaneously rather than b) The counter count down
sequentially. Typical conversion time is
-R

c) The counter back and forth

100nanosecond or less.
d) None of the mentioned
7. The number of comparator required for Answer: a
flash type A/D converter
SE

Explanation: In servo converter, the circuit

a) Triples for each added bit consist of an up/down counter with
b) Reduce by half for each added bit comparator controlling direction of the count.
c) Double for each added bit So, if the input voltage is greater than DAC
d) Doubles exponentially for each added bit
C

output signal, the output of comparator goes

Answer: c high and counter is caused to count up.
Explanation: The number of comparator

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 Department of Information Technology IT - Regulations 2017

11. At what condition error occurs in the a) keyboard mode

servo tracking A/D Converter? b) strobed input mode
a) Slow change input c) keyboard and strobed input mode
b) Rapid change in input d) scanned sensor matrix mode
c) No change in input

M
d) All of the mentioned Answer: c
Explanation: In this mode, each key code of
Answer: b the pressed key is entered in the order of the

O
Explanation: As long as the analog input entry, and in the meantime, read by the CPU,
changes slowly, the tracking A/D converter till the RAM becomes empty.

C
will be within one LSB of the corrected
value. When the input changes rapidly, the 3. The registers that hold the address of the

T.
tracking A/D converter cannot keep up with word currently being written by the CPU
change and error occurs. from the display RAM are
a) control and timing register
12. How many clock pulses do a successive b) control and timing register and timing

O
approximation converter requires for control
obtaining a digital output. c) display RAM

SP
a) Twelve d) display address registers
b) Six
c) Eight Answer: d
d) None of the mentioned Explanation: The display address registers
G
holds the address of the word currently being
Answer: d written or read by the CPU to or from the
Explanation: The successive approximation display RAM.
LO

technique uses a very efficient code search

strategy to compute n-bit conversion in just n- 4. When a key is pressed, a debounce logic
clock period. comes into operation in
a) scanned keyboard special error mode
.B

b) scanned keyboard with N-key rollover

TOPIC 3.3 KEYBOARD c) scanned keyboard mode with 2 key lockout
/DISPLAY CONTROLLER d) sensor matrix mode
17

1. The registers that store the keyboard and Answer: c

display modes and operations programmed by Explanation: In scanned keyboard mode with
CPU are 2 key lockout mode of operation, when a key
a) I/O control and data buffers is pressed, a debounce logic comes into
-R

b) Control and timing registers operation. During the next two scans, other
c) Return buffers keys are checked for closure and if no other
d) Display address registers key is pressed then the first pressed key is
SE

identified.
Answer: b
Explanation: The control and timing register 5. The mode that is programmed using “end
to store the keyboard and display modes and interrupt/error mode set command” is
other operations programmed by CPU. a) scanned keyboard special error mode
C

b) scanned keyboard with N-key rollover

2. The sensor RAM acts as 8-byte first-in- c) scanned keyboard mode with 2 key lockout
first-out RAM in d) sensor matrix mode

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 Department of Information Technology IT - Regulations 2017

Answer: a 9. The flag that increments automatically

Explanation: The scanned keyboard special after each read or write operation to the
error mode is programmed using end display RAM is
interrupt/error mode set command. This mode a) IF
is valid only under the N-key rollover mode. b) RF

M
c) AI
6. When a key is pressed, the debounce d) WF
circuit waits for 2 keyboard scans and then

O
checks whether the key is still depressed in Answer: c
a) scanned keyboard special error mode Explanation: AI refers to auto increment

C
b) scanned keyboard with N-key rollover flag.
c) scanned keyboard mode with 2 key lockout

T.
d) sensor matrix mode 10. If any change in sensor value is detected
at the end of a sensor matrix scan, then the
Answer: b IRQ line
Explanation: In this mode, When a key is a) goes low

O
pressed, the debounce circuit waits for 2 b) goes high
keyboard scans and then checks whether the c) remains unchanged

SP
key is still depressed. If it is still depressed, d) none
the code is entered in FIFO RAM.
Answer: b
7. The data that is entered from the left side Explanation: In sensor matrix mode, the IRQ
G
of the display unit is of line goes high, if any change in sensor value
a) left entry mode is detected at the end of a sensor matrix scan
b) right entry mode or the sensor RAM has a previous entry to be
LO

c) left and right entry modes read by the CPU.

d) none

Answer: a TOPIC 3.4 INTERRUPT

CONTROLLER
.B

Explanation: The data that is entered from

the left side of the display unit is of left entry
mode, as in a type-writer the first character 1. The number of hardware interrupts that the
typed appears at the left-most position, while processor 8085 consists of is
17

the subsequent characters appear successively a) 1

to the right of the first one. b) 3
c) 5
8. The FIFO status word is used to indicate d) 7
-R

the error in
a) keyboard mode Answer: c
b) strobed input mode Explanation: The processor 8085 has five
SE

c) keyboard and strobed input mode hardware interrupt pins. Out of these five,
d) scanned sensor matrix mode four pins were alloted fixed vector addresses
but the pin INTR was not alloted by vector
Answer: c address, rather an external device was
Explanation: Overrun error occurs when an supposed to hand over the type of the
C

already full FIFO has attempted an entry. interrupt to the microprocessor.

Underrun error occurs when an empty FIFO
read is attempted.

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 Department of Information Technology IT - Regulations 2017

2. The register that stores all the interrupt vectored interrupts. In cascade mode, 64
requests in it in order to serve them one by vectored interrupts can be provided.
one on a priority basis is
a) Interrupt Request Register 6. When the PS(active low)/EN(active low)
b) In-Service Register pin of 8259A used in buffered mode, then it

M
c) Priority resolver can be used as a
d) Interrupt Mask Register a) input to designate chip is master or slave
b) buffer enable

O
Answer: a c) buffer disable
Explanation: The interrupts at IRQ input d) none

C
lines are handled by Interrupt Request
Register internally. Answer: b

T.
Explanation: When the pin is used in
3. The register that stores the bits required to buffered mode, then it can be used as a buffer
mask the interrupt inputs is enable to control buffer transreceivers. If it is
a) In-service register not used in buffered mode, then the pin is

O
b) Priority resolver used as input to designate whether the chip is
c) Interrupt Mask register used as a master or a slave.

SP
d) None
7. Once the ICW1 is loaded, then the
Answer: c initialization procedure involves
Explanation: Also, Interrupt Mask Register a) edge sense circuit is reset
G
operates on IRR(Interrupt Request Register) b) IMR is cleared
at the direction of the Priority Resolver. c) slave mode address is set to 7
d) all of the mentioned
LO

4. The interrupt control logic

a) manages interrupts Answer: d
b) manages interrupt acknowledge signals Explanation: The initialization procedure
c) accepts interrupt acknowledge signal involves
.B

d) all of the mentioned i) edge sense circuit is reset.

ii) IMR is cleared.
Answer: d iii) IR7 input is assigned the lowest priority.
Explanation: The interrupt control logic iv) slave mode address is set to 7
17

performs all the operations that are involved v) special mask mode is cleared and the status
within the interrupts like accepting and read is set to IRR.
managing interrupt acknowledge signals,
interrupts. 8. When non-specific EOI command is issued
-R

to 8259A it will automatically

5. In a cascaded mode, the number of a) set the ISR
vectored interrupts provided by 8259A is b) reset the ISR
a) 4
SE

c) set the INTR

b) 8 d) reset the INTR
c) 16
d) 64 Answer: b
Explanation: When non-specific EOI
C

Answer: d command is issued to 8259A it will

Explanation: A single 8259A provides 8 automatically reset the highest ISR.

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 Department of Information Technology IT - Regulations 2017

9. In the application where all the interrupting c) DMA controllers

devices are of equal priority, the mode used is d) The program itself
a) Automatic rotation
b) Automatic EOI mode Answer: c
c) Specific rotation Explanation: The DMA controller acts as a

M
d) EOI processor for DMA transfers and overlooks
the entire process.
Answer: a

O
Explanation: The automatic rotation is used 4. After the completion of the DMA transfer,
in the applications where all the interrupting the processor is notified by __________

C
devices are of equal priority. a) Acknowledge signal
b) Interrupt signal

T.
c) WMFC signal
TOPIC 3.5 DMA (DIRECT d) None of the mentioned
MEMORY
ACCESS)CONTROLLER Answer: b

O
Explanation: The controller raises an
interrupt signal to notify the processor that
1. The DMA differs from the interrupt mode

SP
the transfer was complete.
by __________
a) The involvement of the processor for the 5. The DMA controller has _______ registers.
operation a) 4
b) The method of accessing the I/O devices b) 2
G
c) The amount of data transfer possible c) 3
d) None of the mentioned d) 1
LO

Answer: d Answer: c
Explanation: DMA is an approach of Explanation: The Controller uses the
performing data transfers in bulk between registers to store the starting address, word
memory and the external device without the count and the status of the operation.
.B

intervention of the processor.

6. When the R/W bit of the status register of
2. The DMA transfers are performed by a the DMA controller is set to 1.
17

control circuit called as __________ a) Read operation is performed

a) Device interface b) Write operation is performed
b) DMA controller c) Read & Write operation is performed
c) Data controller d) None of the mentioned
-R

d) Overlooker
Answer: a
Answer: b Explanation: None.
Explanation: The Controller performs the
SE

functions that would normally be carried out 7. The controller is connected to the ____
by the processor. a) Processor BUS
b) System BUS
3. In DMA transfers, the required signals and c) External BUS
C

addresses are given by the __________ d) None of the mentioned

a) Processor
b) Device drivers Answer: b
Explanation: The controller is directly

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 Department of Information Technology IT - Regulations 2017

connected to the system BUS to provide Answer: a

faster transfer of data. Explanation: The controller stores the data to
transfer in the buffer and then transfers it.
8. Can a single DMA controller perform
operations on two different disks 12. To overcome the conflict over the

M
simultaneously? possession of the BUS we use ______
a) True a) Optimizers
b) False b) BUS arbitrators

O
c) Multiple BUS structure
Answer: a d) None of the mentioned

C
Explanation: The DMA controller can
perform operations on two different disks if Answer: b

T.
the appropriate details are known. Explanation: The BUS arbitrator is used to
overcome the contention over the BUS
9. The technique whereby the DMA possession.
controller steals the access cycles of the

O
processor to operate is called __________ 13. The registers of the controller are ______
a) Fast conning a) 64 bits

SP
b) Memory Con b) 24 bits
c) Cycle stealing c) 32 bits
d) Memory stealing d) 16 bits

Answer: c Answer: c
G
Explanation: The controller takes over the Explanation: None.
processor’s access cycles and performs
LO

memory operations. 14. When the process requests for a DMA

transfer?
10. The technique where the controller is a) Then the process is temporarily suspended
given complete access to main memory is b) The process continues execution
__________ c) Another process gets executed
.B

a) Cycle stealing d) process is temporarily suspended &

b) Memory stealing Another process gets executed
c) Memory Con
17

d) Burst mode Answer: d

Explanation: The process requesting the
Answer: d transfer is paused and the operation is
Explanation: The controller is given full performed, meanwhile another process is run
-R

control of the memory access cycles and can on the processor.

transfer blocks at a faster rate.
15. The DMA transfer is initiated by _____
11. The controller uses _____ to help with the a) Processor
SE

transfers when handling network interfaces. b) The process being executed

a) Input Buffer storage c) I/O devices
b) Signal enhancers d) OS
c) Bridge circuits
C

d) All of the mentioned Answer: c

Explanation: The transfer can only be

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 Department of Information Technology IT - Regulations 2017

initiated by an instruction of a program being a) set

executed. b) reset
c) set & reset
d) none of the mentioned
TOPIC 3.6 PROGRAMMING

M
AND APPLICATIONS CASE Answer: b
STUDIES: TRAFFIC LIGHT Explanation: For writing commands on an
LCD, RS pin is reset.

O
CONTROL, LED DISPLAY , LCD
DISPLAY, KEYBOARD DISPLAY 5. Which command of an LCD is used to shift
INTERFACE AND ALARM

C
the entire display to the right?
CONTROLLER. a) 0x1C

T.
b) 0x18
1. How many rows and columns are present c) 0x05
in a 16*2 alphanumeric LCD? d) 0x07

O
a) rows=2, columns=32
Answer: a
b) rows=16, columns=2
Explanation: 0x1C is used to shift the entire
c) rows=16, columns=16

SP
display to the right.
d) rows=2, columns=16
6. Which command is used to select the 2
Answer: d
lines and 5*7 matrix of an LCD?
Explanation: 16*2 alphanumeric LCD has 2
a) 0x01
G
rows and 16 columns.
b) 0x06
2. How many data lines are there in a 16*2 c) 0x0e
LO

alphanumeric LCD? d) 0x38

a) 16
Answer: d
b) 8
Explanation: 0x38 is used to select the 2
c) 1
lines and 5*7 matrix of an LCD.
.B

d) 0
7. Which of the following step/s is/are correct
Answer: b
for sending data to an LCD?
17

Explanation: There are eight data lines from

a) set the R/W bit
pin no 7 to pin no 14 in an LCD.
b) set the E bit
3. Which pin of the LCD is used for adjusting c) set the RS bit
its contrast? d) all of the mentioned
-R

a) pin no 1
Answer: d
b) pin no 2
Explanation: To send data to an LCD, RS pin
c) pin no 3
should be set so that LCD will come to know
SE

d) pin no 4
that it will receive data which has to display
Answer: c on the screen. R/W pin should be reset as data
Explanation: Pin no 3 is used for controlling has to be displayed (i.e. write to the LCD).
the contrast of the LCD. High to low pulse must be applied to the E
C

pin when data is supplied to data pins of the

4. For writing commands on an LCD, RS bit LCD.
is

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 Department of Information Technology IT - Regulations 2017

8. Which of the following step/s is/are correct INSTRUCTION SET -

to perform reading operation from an LCD? ADDRESSING MODES
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set 1. To initialize any port as an output port what

M
high value is to be given to it?
d) none of the mentioned a) 0xFF
b) 0x00

O
Answer: c c) 0x01
Explanation: For reading operations, R/W d) A port is by default an output port

C
pin should be made high and added to it, a
low to high pulse is also generated at the E Answer: d
Explanation: In 8051, a port is initialized by

T.
pin.
default in its output mode no need to pass any
9. Which instruction is used to select the first value to it.
row first column of an LCD?

O
a) 0x08 2. Which out of the four ports of 8051 needs a
b) 0x0c pull-up resistor for using it is as an input or an

SP
c) 0x80 output port?
d) 0xc0 a) PORT 0
b) PORT 1
Answer: c c) PORT 2
d) PORT 3
G
Explanation: 0x80 is used to select the first
row first column of an LCD.
Answer: a
LO

10. The RS pin is _________ for an LCD. Explanation: These pins are the open drain
a) input pins of the controller which means it needs a
b) output pull-up resistor for using it as an input or an
c) input & output output ports.
.B

d) none of the mentioned

3. Which of the ports act as the 16 bit address
Answer: a lines for transferring data through it?
Explanation: The RS pin is an input pin for a) PORT 0 and PORT 1
17

an LCD. b) PORT 1 and PORT 2

c) PORT 0 and PORT 2
d) PORT 1 and PORT 3
-R

Answer: c
UNIT IV Explanation: PORT 0 and PORT 2 are used
as the 16 bit address lines where PORT0 act
MICROCONTROLLER as lower bit address lines and PORT 2 as
SE

higher bit address lines.

TOPIC 4.1 ARCHITECTURE OF
4. Which of the following registers are not bit
8051 - SPECIAL FUNCTION addressable?
C

REGISTERS(SFRS) - I/O PINS a) SCON

PORTS AND CIRCUITS - b) PCON

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 Department of Information Technology IT - Regulations 2017

c) A a) it makes use of registers R0 and R1

d) PSW b) it uses the data dynamically
c) it makes use of operator @
Answer: b d) it is easy
Explanation: PCON register is not a bit

M
addressable register. Answer: b
Explanation: Register indirect addressing
5. Which instruction is used to check the mode is useful if a series of data is to be

O
status of a single bit? assigned to that address, with the help of this
a) MOV A,P0 quality the number of instructions decreases

C
b) ADD A,#05H as a result of which performance increases.
c) JNB PO.0, label

T.
d) CLR P0.05H 9. Which of the following comes under the
indexed addressing mode?
Answer: c a) MOVX A, @DPTR
Explanation: JNB which stands for Jump if b) MOVC @A+DPTR,A

O
no bit checks the status of the bit P0.0 and c) MOV A,R0
jumps if the bit is 0. d) MOV @R0,A

SP
6. Which addressing mode is used in pushing Answer: b
or popping any element on or from the stack? Explanation: Indexed addressing mode
a) immediate stands for that instruction where the bits of
b) direct
G
the accumulator is also indexed with the 16
c) indirect bit registers.
d) register
LO

10. Is this a valid statement?

Answer: b SETB A
Explanation: If we want to push or pop any a) yes
element on or from the stack then direct b) no
addressing mode has to be used in it, as the
.B

c) cant be determined
other way is not accepted. d) none of the mentioned

7. Which operator is the most important while Answer: b

17

assigning any instruction as register indirect Explanation: SETB is used to set a bit of a
instruction? register. A stands for accumulator which is an
a) $ 8 bit register, so it is an invalid instruction.
b) #
-R

c) @
d) & TOPIC 4.2 ASSEMBLY
LANGUAGE PROGRAMMING.
Answer: c
SE

Explanation: In register, indirect mode data 1. __________ converts the programs written
is copied at that location where R0 or R1 are in assembly language into machine
present, so @ operator is used ex. MOV instructions.
@R0,A a) Machine compiler
C

b) Interpreter
8. What is the advantage of register indirect c) Assembler
addressing mode? d) Converter

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 Department of Information Technology IT - Regulations 2017

Answer: c d) Assigns 200 bytes of memory starting the

Explanation: An assembler is a software location of Sum
used to convert the programs into machine
instructions. Answer: b
Explanation: This basically is used to replace

M
2. The instructions like MOV or ADD are the variable with a constant value.
called as ______
a) OP-Code 6. The purpose of the ORIGIN directive is

O
b) Operators __________
c) Commands a) To indicate the starting position in memory,

C
d) None of the mentioned where the program block is to be stored
b) To indicate the starting of the computation

T.
Answer: a code
Explanation: This OP – codes tell the system c) To indicate the purpose of the code
what operation to perform on the operands. d) To list the locations of all the registers used

O
3. The alternate way of writing the Answer: a
instruction, ADD #5,R1 is ______ Explanation: This does the function similar

SP
a) ADD [5],[R1]; to the main statement.
b) ADDI 5,R1;
c) ADDIME 5,[R1]; 7. The directive used to perform initialization
d) There is no other way before the execution of the code is ______
a) Reserve
G
Answer: b b) Store
Explanation: The ADDI instruction, means c) Dataword
LO

the addition is in immediate addressing mode. d) EQU

4. Instructions which won’t appear in the Answer: c

object program are called as _____ Explanation: None.
a) Redundant instructions
.B

b) Exceptions 8. _____ directive is used to specify and

c) Comments assign the memory required for the block of
d) Assembler Directives code.
17

a) Allocate
Answer: d b) Assign
Explanation: The directives help the program c) Set
in getting compiled and hence won’t be there d) Reserve
-R

in the object code.

Answer: d
5. The assembler directive EQU, when used Explanation: This instruction is used to
in the instruction: Sum EQU 200 does allocate a block of memory and to store the
SE

________ object code of the program there.

a) Finds the first occurrence of Sum and
assigns value 200 to it 9. _____ directive specifies the end of
b) Replaces every occurrence of Sum with execution of a program.
C

200 a) End
c) Re-assigns the address of Sum by adding b) Return
200 to its original address

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 Department of Information Technology IT - Regulations 2017

c) Stop b) Cache
d) Terminate c) RAM
d) Magnetic disk
Answer: b
Explanation: This instruction directive is Answer: d

M
used to terminate the program execution. Explanation: After compiling the object
code, the assembler stores it in the magnetic
10. The last statement of the source program disk and waits for further execution.

O
should be _______
a) Stop 14. The utility program used to bring the

C
b) Return object code into memory for execution is
c) OP ______

T.
d) End a) Loader
b) Fetcher
Answer: d c) Extractor
Explanation: This enables the processor to d) Linker

O
load some other process.
Answer: a

SP
11. When dealing with the branching code the Explanation: The program is used to load the
assembler ___________ program into memory.
a) Replaces the target with its address
b) Does not replace until the test condition is 15. To overcome the problems of the
satisfied assembler in dealing with branching code we
G
c) Finds the Branch offset and replaces the use _____
Branch target with it a) Interpreter
LO

d) Replaces the target with the value specified b) Debugger

by the DATAWORD directive c) Op-Assembler
d) Two-pass assembler
Answer: c
Explanation: When the assembler comes Answer: d
.B

across the branch code, it immediately finds Explanation: This creates entries into the
the branch offset and replaces it with it. symbol table first and then creates the object
code.
17

12. The assembler stores all the names and

their corresponding values in ______
a) Special purpose Register
b) Symbol Table
-R

c) Value map Set UNIT V INTERFACING

d) None of the mentioned
MICROCONTROLLER
Answer: b
SE

Explanation: The table where the assembler TOPIC 5.1 PROGRAMMING 8051
stores the variable names along with their
corresponding memory locations and values.
TIMERS - SERIAL PORT
PROGRAMMING
C

13. The assembler stores the object code in

______ 1. Which devices are specifically being used
a) Main memory for converting serial to parallel and from

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 Department of Information Technology IT - Regulations 2017

parallel to serial respectively? computer about the start and the end of the
a) timers data.
b) counters
c) registers 4. Which of the following signal control the
d) serial communication flow of data?

M
a) RTS
Answer: c b) DTR
Explanation: Some registers like the parallel c) RTS & DTR

O
in serial out and serial in parallel out are used d) None of the mentioned
to convert serial data into parallel and vice

C
versa respectively. Answer: a
Explanation: RTS is a request to send control

T.
2. What is the difference between UART and signal which is a control for the flow of data.
USART communication? On the other hand DTR is a Data Terminal
a) they are the names of the same particular Ready control signal which tells about the
thing, just the difference of A and S is there current status of the DTE.

O
in it
b) one uses asynchronous means of 5. Which of the following is the logic level

SP
communication and the other uses understood by the micro-controller/micro-
synchronous means of communication processor?
c) one uses asynchronous means of a) TTL logic level
communication and the other uses b) RS232 logic level
G
asynchronous and synchronous means of c) None of the mentioned
communication d) TTL & RS232 logic level
d) one uses angular means of the
LO

communication and the other uses linear Answer: a

means of communication Explanation: TTL logic or the transistor
logic level is the logic that is understood by
Answer: c the micro-controllers/microprocessors.
.B

Explanation: UART stands for Universal

Asynchronous receiver-transmitter and 6. What is a null modem connection?
USART stands for Universal Synchronous a) no data transmission
and Asynchronous receiver-transmitter. b) no MAX232
17

c) the RxD of one is the TxD for the other

3. Which of the following best describes the d) no serial communication
use of framing in asynchronous means of
communication? Answer: c
-R

a) it binds the data properly Explanation: In null modem connection the

b) it tells us about the start and stops of the RxD of one is the TxD for the other.
data to be transmitted or received
7. Which of the following best states the
SE

c) it is used for error checking

d) it is used for flow control reason that why baud rate is mentioned in
serial communication?
Answer: b a) to know about the no of bits being
Explanation: In data framing in transmitted per second
C

asynchronous means of communication, the b) to make the two devices compatible with
data is packed between the start and the stop each other, so that the transmission becomes
bit. This is done so as to tell the other easy and error free

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 Department of Information Technology IT - Regulations 2017

c) to use Timer 1 KEYBOARD

d) for wasting memory

Answer: b 1. The method of defining the interrupt

Explanation: To make two devices service routine for software is

M
compatible with each other baud rate is a) same as that of hardware
mentioned in the serial communication so that b) difficult than hardware
the transmission becomes easy and error free. c) easier than software

O
d) none of the mentioned
8. With what frequency UART operates(
Answer: a

C
where f denoted the crystal frequency )?
a) f/12 Explanation: For both software and
hardware, the method of defining the

T.
b) f/32
c) f/144 interrupt service routine is the same.
d) f/384
2. While programming for any type of

O
Answer: d interrupt, the interrupt vector table is set
Explanation: UART frequency is the crystal a) externally
b) through a program

SP
frequency f/12 divided by 32, that comes out
to be f/384. c) either externally or through the program
d) externally and through the program
9. What is the function of the SCON register?
a) to control SBUF and SMOD registers Answer: c
G
b) to program the start bit, stop bit, and data Explanation: The programmer must, either
bits of framing externally or through the program, set the
LO

c) to control SMOD registers interrupt vector table for that type preferably
d) none of the mentioned with the CS and IP addresses of the interrupt
service routine.
Answer: b
Explanation: SCON register is mainly used 3. To execute a program one should
.B

for programming the start bits, stop bits and a) assemble the program
data bits of framing. As it consists of bits like b) link the program
RB8, TB8, SM0, SM1, SM2 etc. c) apply external pulse
17

d) all of the mentioned

10. What should be done if we want to double
the baud rate? Answer: d
a) change a bit of the TMOD register Explanation: To execute a program, first
-R

b) change a bit of the PCON register assemble it, link it and then execute it. After
c) change a bit of the SCON register execution, a new file RESULT is created in
d) change a bit of the SBUF register the directory. Then external pulse is applied
to IRQ2 pin, and this will again cause the
SE

Answer: b execution of ISR into the file.

Explanation: PCON register consists of
SMOD bit as its D7 bit, so if we set this bit 4. Procedures are also known as
then the baud rate gets doubled. a) macros
C

b) segment
c) subroutines
TOPIC 5.2 INTERRUPTS d) none
PROGRAMMING - LCD &

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 Department of Information Technology IT - Regulations 2017

Answer: c c) main routine

Explanation: Procedures are also known as d) main routine and subroutine
subroutines.
Answer: c
5. Procedures, for their execution, require Explanation: For passing the parameters to

M
a) input data procedures, it must be declared PUBLIC in
b) output data the main routine and the same should be
c) constants declared EXTRN in the procedure.

O
d) input data or constants
9. The technique to estimate the size of an

C
Answer: d executable program, before it is assembled
Explanation: Procedures require input data and linked is

T.
or constants for their execution. Their data or a) memory location technique
constants may be passed to the subroutine by b) global variable technique
the main program. c) stack
d) none

O
6. The technique that is used to pass the data
or parameter to procedures in assembly Answer: d

SP
language program is by using Explanation: There is no technique to
a) global declared variable estimate the size of an executable program
b) registers before it is assembled and linked.
c) stack
10. To estimate the size of an executable
G
d) all of the mentioned
program before it is assembled and linked, the
Answer: d programming methodology concerned is by
LO

Explanation: The techniques that are used to writing

pass the data or parameter to procedures are a) programs with more than one segment for
by using global declared variable, registers of data and code
CPU, memory locations, stack, PUBLIC & b) programs with FAR subroutines each of
.B

EXTRN. size up to 64KB

c) programs with more than one segment for
7. If a procedure is interactive, then stack
a) it accepts inputs directly from input d) all of the mentioned
17

devices
b) it uses global declared variable technique Answer: d
c) it uses stack Explanation: By writing programs with more
d) it uses memory locations than one segment for data, code or stack or by
-R

writing programs with FAR subroutines each

Answer: a of size 64KB, the size of an executable
Explanation: If a procedure is interactive, program can be estimated.
then it accepts the inputs directly from input
SE

devices.
TOPIC 5.3.1 INTERFACING -
8. For passing the parameters to procedures DAC & SENSOR INTERFACING
using the PUBLIC & EXTRN directives, it
C

must be declared PUBLIC in the 1. DAC (Digital to Analog Converter) finds

a) subroutine application in
b) procedure a) digitally controlled gains

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 Department of Information Technology IT - Regulations 2017

b) motor speed controls terms of steps is

c) programmable gain amplifiers a) DC motor
d) all of the mentioned b) AC motor
c) Stepper motor
Answer: d d) Servo motor

M
Explanation: DAC is used in digitally
controlled gains, motor speed controls and Answer: c
programmable gain amplifiers. Explanation: Stepper motor employs rotation

O
of its shaft in terms of steps, rather than
2. To save the DAC from negative transients continuous rotation as in case of AC or DC

C
the device connected between OUT1 and motors.
OUT2 of AD 7523 is

T.
a) p-n junction diode 6. The internal schematic of a typical stepper
b) Zener motor has
c) FET a) 1 winding
d) BJT (Bipolar Junction transistor) b) 2 windings

O
c) 3 windings
Answer: b d) 4 windings

SP
Explanation: Zener is connected between
OUT1 and OUT2 pins of AD7523 to save Answer: d
from negative transients. Explanation: The internal schematic of a
typical stepper motor has 4 windings.
3. An operational amplifier connected to the
G
output of AD 7523 is used 7. The number of pulses required for one
a) to convert current output to output voltage complete rotation of the shaft of the stepper
LO

b) to provide additional driving capability motor is equal to the

c) as current-to-voltage converter a) number of internal teeth on a rotor
d) all of the mentioned b) number of internal teeth on a stator
c) number of internal teeth on a rotor and
Answer: d
.B

stator
Explanation: An operational amplifier is d) number of external teeth on a stator
used as a current-to-voltage converter to
convert the current output to output voltage Answer: a
17

and also provides additional driving Explanation: The number of pulses required
capability to the DAC. for one complete rotation of the shaft of the
stepper motor is equal to the number of
4. The DAC 0800 has a settling time of internal teeth on its rotor.
-R

a) 100 milliseconds
b) 100 microseconds 8. A simple scheme for rotating the shaft of a
c) 50 milliseconds stepper motor is called
d) 50 microseconds a) rotating scheme
SE

b) shaft scheme
Answer: a c) wave scheme
Explanation: DAC 0800 has a settling time d) none
of 100 milliseconds.
C

Answer: c
5. The device that is used to obtain an Explanation: In this scheme, the windings
accurate position control of rotating shafts in

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 Department of Information Technology IT - Regulations 2017

are applied with the required voltage pulses, moment of the start of conversion is called
in a cyclic fashion. conversion delay.

9. The firing angles of thyristors are 2. The popular technique that is used in the
controlled by integration of ADC chips is

M
a) pulse generating circuits a) successive approximation
b) relaxation oscillators b) dual slope integration
c) microprocessor c) successive approximation and dual slope

O
d) all of the mentioned integration
d) none

C
Answer: d
Explanation: In early days, the firing angles Answer: c

T.
were controlled by a pulse generating circuits Explanation: Successive approximation and
like relaxation oscillators and now, they are dual slope integration are the most popular
accurately fired using a microprocessor. techniques that are used in the integrated
ADC chips.

O
10. The Isolation transformers are generally
used for 3. The procedure of algorithm for interfacing

SP
a) protecting low power circuit ADC contain
b) isolation a) ensuring stability of analog input
c) protecting low power circuit and isolation b) issuing start of conversion pulse to ADC
d) none c) reading digital data output of ADC as
G
equivalent digital output
Answer: c d) all of the mentioned
Explanation: Any switching component of a
LO

high power circuit may be sufficient to Answer: d

damage the microprocessor system. So, to Explanation: The general algorithm for
protect the low power circuit isolation interfacing ADC contains ensuring the
transformers are used. They are also used if stability of analog input, issuing start of
.B

isolation is necessary. conversion pulse to ADC, reading end of

conversion signal to mark the end of a
conversion process, reading digital data
TOPIC 5.3.2 ADC output of ADC as equivalent digital output.
17

1. The time taken by the ADC from the active 4. Which is the ADC among the following?
edge of SOC(start of conversion) pulse till the a) AD 7523
active edge of EOC(end of conversion) signal b) 74373
-R

is called c) 74245
a) edge time d) ICL7109
b) conversion time
c) conversion delay Answer: d
SE

d) time delay Explanation: AD 7523 is a DAC(Digital to

analog converter), 74373 is a latch, 74245 is
Answer: c transceiver and ICL7109 is an ADC.
Explanation: Broadly speaking, the time
C

taken by the converter to calculate the 5. The conversion delay in a successive

equivalent digital data output from the approximation of an ADC 0808/0809 is
a) 100 milliseconds

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 Department of Information Technology IT - Regulations 2017

b) 100 microseconds 9. Which of the following phase contain

c) 50 milliseconds feedback loop in it?
d) 50 milliseconds a) autozero phase
b) signal integrate phase
Answer: b c) disintegrate phase

M
Explanation: The conversion delay is d) none
100microseconds which is low as compared
to other converters. Answer: a

O
Explanation: A feedback loop is closed
6. The number of inputs that can be around the system to charge the autozero

C
connected at a time to an ADC that is capacitor to compensate for the offset
integrated with successive approximation is voltages in the buffer amplifier, integrator and

T.
a) 4 comparator.
b) 2
c) 8 10. In the signal integrate phase, the
d) 16 differential input voltage between IN

O
LO(input low) and IN HI(input high) pins is
Answer: c integrated by the internal integrator for a

SP
Explanation: As these converters internally fixed period of
have 3:8 analog multiplexer, at a time 8 a) 256 clock cycles
different analog inputs can be connected to b) 1024 clock cycles
the chip. c) 2048 clock cycles
G
d) 4096 clock cycles
7. ADC 7109 integrated by Dual slope
integration technique is used for Answer: c
LO

a) low cost option Explanation: The internal integrator needs

b) slow practical applications 2048 clock cycles to integrate voltage
c) low complexity difference between input low and input high.
d) all of the mentioned
.B

Answer: d TOPIC 5.4 EXTERNAL

Explanation: Compared to other 12-bit MEMORY INTERFACE
ADCs, it is of very low cost and useful for
17

slow practical applications. 1. The device that enables the microprocessor

to read data from the external devices is
8. Which of the following is not one of the a) printer
phases of the total conversion cycle? b) joystick
-R

a) autozero phase c) display

b) conversion phase d) reader
c) signal integrate phase
d) disintegrate phase
SE

Answer: b
Explanation: Since joystick is an input
Answer: b device, it reads data from the external
Explanation: Autozero phase, signal devices.
integrate phase and disintegrate phase are the
C

three phases of total conversion cycle. 2. The example of output device is

a) CRT display
b) 7-segment display

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 Department of Information Technology IT - Regulations 2017

c) Printer c) sourced or sinked from data lines

d) All of the mentioned d) sinked from address lines

Answer: d Answer: c
Explanation: The output device transfers Explanation: More current should not be

M
data from the microprocessor to the external sourced or sinked from data lines while
devices. reading to avoid loading.

O
3. The input and output operations are 7. To avoid loading during read operation, the
respectively similar to the operations, device used is

C
a) read, read a) latch
b) write, write b) flipflop

T.
c) read, write c) buffer
d) write, read d) tristate buffer

Answer: c Answer: d

O
Explanation: The input activity is similar to Explanation: A tristate buffer is used as an
read operation and the output activity is input device to overcome loading.

SP
similar to write operation.
8. The chip 74LS245 is
4. The operation, IOWR (active low) a) bidirectional buffer
performs b) 8-bit input port
a) write operation on input data c) one that has 8 buffers
G
b) write operation on output data d) all of the mentioned
c) read operation on input data
LO

d) read operation on output data Answer: d

Explanation: The chip 74LS245 is a
Answer: b bidirectional buffer that contains 8 buffers
Explanation: IOWR (active low) operation and may be used as an 8-bit input port. But
means writing data to an output device and while using as an input device, only one
.B

not an input device. direction is useful.

5. The latch or IC 74LS373 acts as 9. In 74LS245, if DIR is 1, then the direction

17

a) good input port is from

b) bad input port a) inputs to outputs
c) good output port b) outputs to inputs
d) bad output port c) source to sink
-R

d) sink to source
Answer: c
Explanation: If the output port is to source Answer: a
large currents, the port lines must be buffered. Explanation: If DIR is 1, then the direction is
SE

So, the latch is used as it acts as a good output from A(inputs) to B(outputs).
port.
10. In memory-mapped scheme, the devices
6. While performing read operation, one must are viewed as
C

take care that much current should not be a) distinct I/O devices
a) sourced from data lines b) memory locations
b) sinked from data lines

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 Department of Information Technology IT - Regulations 2017

c) only input devices Answer: c

d) only output devices Explanation: Pulse per second is
mathematically given as PPS = (Rpm/60)*
Answer: b (number of steps per minute).
Explanation: In memory-mapped scheme,

M
the devices are viewed as memory locations 4. If a hybrid stepper motor has a rotor pitch
and are addressed likewise. of 36º and a step angle of 9º, the number of
its phases must be

O
a) 4
TOPIC 5.5 STEPPER MOTOR b) 2
AND WAVEFORM

C
c) 3
GENERATION d) 6

T.
1. A variable reluctance stepper motor is Answer: a
constructed of ______________ material with Explanation: Step angle is defined as =(Ns-
Nr)/(Ns+Nr)*360.

O
salient poles.
a) Paramagnetic
b) Ferromagnetic 5. The rotor of a stepper motor has no

SP
c) Diamagnetic a) Windings
d) Non-magnetic b) Commutator
c) Brushes
Answer: b d) All of the mentioned
G
Explanation: A variable reluctance stepper
motor is the motor that has motion in steps Answer: d
Explanation: The rotor is the rotatory part of
LO

with respect to increase in time and

constructed of ferromagnetic material with the motor of a stepper motor and has no
salient poles. windings, commutator and brushes.

2. In a three-stack 12/8-pole VR motor, the 6. A stepping motor is a ____________

.B

rotor pole pitch is device.

a) 15º a) Mechanical
b) 30º b) Electrical
17

c) 45º c) Analogue
d) 60º d) Incremental

Answer: c Answer: d
Explanation: Pole pitch is defined as the Explanation: A stepping motor is a motor in
-R

number of armature slots to the pole pitch and which the motion in the form of steps and is a
here this has been converted into degrees. incremental device i which as the time
increases the steps are increased.
SE

3. A stepper motor having a resolution of 300

steps/rev and running at 2400 rpm has a pulse 7. The rotational speed of a given stepper
rate of- pps. motor is determined solely by the
a) 4000 a) Shaft load
b) Step pulse frequency
C

b) 8000
c) 6000 c) Polarity of stator current
d) 10,000 d) Magnitude of stator current.

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 Department of Information Technology IT - Regulations 2017

Answer: b TOPIC 5.6 COMPARISON OF

Explanation: The stator part of a motor is the
stationary part of the motor and rotational MICROPROCESSOR,
speed of a given stepper motor is given by the MICROCONTROLLER, PIC
step pulse frequency. AND ARM PROCESSORS

M
8. Which of the following phase switching
sequence represents half-step operation of a 1. A microcontroller at-least should consist

O
VR stepper motor ? of:
a) A, B, C,A…….. a) RAM, ROM, I/O ports and timers

C
b) A, C, B,A……. b) CPU, RAM, I/O ports and timers
c) AB, BC, CA, AB…….. c) CPU, RAM, ROM, I/O ports and timers
d) CPU, ROM, I/O ports and timers

T.
d) A, AB, B, BC……..

Answer: d Answer: c
Explanation: In the half step operation of a Explanation: A microcontroller at-least

O
Variable reluctance motor physical step consists of a processor as its CPU with RAM,
resolution is multiplied by 2 and control ROM, I/O ports and timers. It may contain
some additional peripherals like ADC, PWM,

SP
signals appear to be digital rather than analog.
etc.
9. A stepper motor may be considered as a
____________ converter. 2. Unlike microprocessors, microcontrollers
make use of batteries because they have:
G
a) Dc to dc
b) Ac to ac a) high power dissipation
c) Dc to ac b) low power consumption
LO

d) Digital-to-analogue c) low voltage consumption

d) low current consumption
Answer: d
Explanation: A stepper motor is a motor in Answer: b
Explanation: Micro Controllers are made by
.B

which the motion is in steps and it is an

increemental device and may be considered using the concept of VLSI technology. So
as a digital to analog converter. here, CMOS based logic gates are coupled
together by this technique that consumes low
17

10. What is the step angle of a permanent- power.

magnet stepper motor having 8 stator poles
and 4 rotor poles? 3. What is the order decided by a processor or
a) 60º the CPU of a controller to execute an
-R

b) 45º instruction?
c) 30º a) decode,fetch,execute
d) 15º b) execute,fetch,decode
c) fetch,execute,decode
SE

Answer: b d) fetch,decode,execute
Explanation: Step angle is defined as =(Ns-
Nr)/(Ns+Nr)*360 where Ns is the number of Answer: d
stator poles and Nr is the number of rotor Explanation: First instruction is fetched from
C

poles. Program Memory. After fetching, instruction

is decoded to generate control signals to
perform the intended task. After decoding,

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 Department of Information Technology IT - Regulations 2017

instruction is executed and the complete Answer: b

intended task of that particular instruction. Explanation: CISC means Complete
Instruction Set Computer because in this a
4. If we say microcontroller is 8-bit then here microcontroller has an instruction set that
8-bit denotes size of: supports many addressing modes for the

M
a) Data Bus arithmetic and logical instructions, data
b) ALU transfer and memory accesses instructions.
c) Control Bus

O
RISC means Reduced Instruction Set
d) Address Bus Computer because here a microcontroller has
an instruction set that supports fewer

C
Answer: b addressing modes for the arithmetic and
Explanation: If we say a microcontroller is logical instructions and for data transfer

T.
8-bit it means that it is capable of processing instructions.
8-bit data at a time. Data processing is the
task of ALU and if ALU is able to process 8- 7. Give the names of the buses present in a
bit data then the data bus should be 8-bit controller for transferring data from one place

O
wide. In most books it tells that size of data to another?
bus but to be precise it is the size of ALU a) data bus, address bus

SP
because in Harvard Architecture there are two b) data bus
sets of data bus which can be of same size but c) data bus, address bus, control bus
it is not mandatory. d) address bus
G
5. How are the performance and the computer Answer: c
capability affected by increasing its internal Explanation: There are 3 buses present in a
bus width? microcontroller they are data bus (for
LO

a) it increases and turns better carrying data from one place to another),
b) it decreases address bus (for carrying the address to which
c) remains the same the data will flow) and the control bus (which
d) internal bus width doesn’t affect the tells the controller to execute which type of
.B

performance in any way work at that address may be it read or write

operation).
Answer: a
Explanation: As the bus width increases, the 8. What is the file extension that is loaded in
17

number of bits carried by bus at a time a microcontroller for executing any

increases as a result of which the total instruction?
performance and computer capability a) .doc
increases. b) .c
-R

c) .txt
6. Abbreviate CISC and RISC. d) .hex
a) Complete Instruction Set Computer,
SE

Reduced Instruction Set Computer Answer: d

b) Complex Instruction Set Computer, Explanation: Microcontrollers are loaded
Reduced Instruction Set Computer with .hex extension as they understand the
c) Complex Instruction Set Computer, language of 0’s and 1’s only.
Reliable Instruction Set Computer
C

d) Complete Instruction Set Computer, 9. What is the most appropriate criterion for
Reliable Instruction Set Computer choosing the right microcontroller of our
choice?

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 Department of Information Technology IT - Regulations 2017

a) speed 10. Why microcontrollers are not called

b) availability general purpose computers?
c) ease with the product a) because they have built in RAM and ROM
d) all of the mentioned b) because they design to perform dedicated
task

M
Answer: d c) because they are cheap
Explanation: For choosing the right d) because they consume low power
microcontroller for our product we must

O
consider its speed so that the instructions may Answer: b
be executed in the least possible time. It also Explanation: Microcontrollers are designed

C
depends on the availability so that the to perform dedicated tasks. While designing
particular product may be available in our general purpose computers end use is not

T.
neighboring regions or market in our need. It known to designers.
also depends on the compatibility with the
product so that the best results may be
obtained.

O
SP
G
LO
.B
17
-R
SE
C

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