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Ruby Resume

The document provides a summary of Ruby Krishna's qualifications and experience. It includes details of her educational background including a M.E. in Applied Electronics and a B.E. in Electrical and Electronics Engineering. It lists her areas of technical proficiency including Verilog, MATLAB, and programming languages. It also outlines the academic projects she has worked on, including the design of a current steering DAC and operational amplifier. Her objective is seeking a career in analog/mixed signal VLSI design.

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Rubykrishna Sankaran
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131 views

Ruby Resume

The document provides a summary of Ruby Krishna's qualifications and experience. It includes details of her educational background including a M.E. in Applied Electronics and a B.E. in Electrical and Electronics Engineering. It lists her areas of technical proficiency including Verilog, MATLAB, and programming languages. It also outlines the academic projects she has worked on, including the design of a current steering DAC and operational amplifier. Her objective is seeking a career in analog/mixed signal VLSI design.

Uploaded by

Rubykrishna Sankaran
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Ruby Krishna.

No. 29/10,4th Street,


Rajaji Nagar, Villlivakkam,
+91- 9444663336
Chennai - 600049
[email protected]

Objective
Looking for a challenging career in the field of analog/mixed signal VLSI, which
enhances my competency in System development & design and allows me to
contribute to the growth of our organization.

Educational Qualification

Course Institution Batch % Of


Marks/CGPA

M.E. in SSN College of June ’09–’11 7.8*(CGPA)


Applied Engineering, Chennai.
Electronics

B.E. in St.Peters Engineering June ’04-’08 81%


Electrical and College
Electronics

H.S.C. St.Johns Hr Sec School, June ’03-’04 89.92%


Chennai.

St.Johns Hr Sec School,


S.S.L.C. 85%
Chennai. June ’01 –’02

* Only till second semester

Areas of Interest

 VLSI-Analog& Mixed Signal


 Electronic Circuits,PLL,OP-Amps
 Control Systems
 Digital Electronics

Technical Proficiency

Hardware Languages : Verilog


Simulator : MATLAB, AGILENT ADS (Advance Design System)
Back-End tools : PSPICE, TANNER EDA, HSPICE(Synopsys)
Programming Languages :C

Paper presented in Symposium

o Presented Paper on “Rural Electrification-A Simulative Analysis of


SPV System”And got first prize in a National level Technical Symposium
“Ultra Zone-2007”.

o Presented Paper on “Improving the efficiency solar collectors by


using nanotechnology” And got second prize in a National level
Technical Symposium “Ecognition-2006”.

Academic Projects Handled (Reverse chronology)

1) Design of Current Steering Digital to Analog converter for UWB


receiver
Duration six months project
Simulation Matlab, Tanner, H spice
Guide: 1) Dr.C.Premanand, Professor
SSN College of Engineering
2) Mr.Vaithianathan.V,Asst
Professor
SSN College of Engineering
Tasks accomplished:
• Schematic version of the Self referenced beta multiplier and Wide
swing biasing circuit for the short channel process were designed.
• Comparative analysis is done for the various existing architectures.
• Schematic of the current steering DAC was developed by using
Tanner(S edit)

• Tanner EDA (SEDIT) was used for net list generation and simulated
outputs are obtained using HSPICE(Synopsys)

• Process -TSMC-0.18um (Models are extracted from latest mosis runs).


• A novel 2GS/s current steering DAC was designed using pseudo
segmentation technique which is very less prone to non-linearity.
• The designed current steering provides excellent figure of merit when
compared to the conventional current steering DAC.

2) Design of Three stage operational amplifier using reverse nested


miller hybrid indirect feedback compensation
Duration six month project
Simulation Matlab, Tanner, spice
Guide: 1) Dr.C.Premanand, Professor
SSN College of Engineering

Tasks accomplished:
• Schematic version of the Self referenced beta multiplier and Wide
swing biasing circuit for the short channel process were designed.
• Designed a High defined a Three Stage Operational Amplifier using
Indirect Feedback Reverse Nested Miller Compensation.

• We have developed a Op-Amp with 100MHz unity gain frequency and


a gain of 82DB and a phase margin of 600.

• Tanner EDA (SEDIT) was used for net list generation and simulated
outputs are obtained using HSPICE(Synopsys)

• A Hybrid compensation technique was used in order to facilitate the


application of operational amplifiers in high speed data converter architectures.

3) Design of Successive approximation ADC for UWB receiver


Duration one year project
Simulation Matlab, Tanner, spice
Guide: 1) Dr.C.Premanand, Professor
SSN College of Engineering
2) Mr.Vaithianathan.V,Asst
Professor
SSN College of Engineering
Tasks accomplished as on date:

• Conventional SAR ADC is too slow which make it as a delimiting factor


for high speed applications.

• High Speed switching drivers were designed using Precharge-


evaluation logic with a minimum delay in the order of 60pS.
• Inorder to reduce the rise and fall time issues, differential cascade
pass transistor logic flip flops were used in shift registers.

• Ultra high speed latched comparator was used which has a delay in
the order of 300pS

• Tanner EDA (SEDIT) was used for net list generation and simulated
outputs are obtained using HSPICE(Synopsys)
• A 4 bit 200MS/s successive approximation ADC was designed and we
are currently tuning the Analog to digital converter using time
interleaving topology inorder to enhance the speed of the ADC towards
1GS/s.

Design of Digital Phase Locked Loop using 0.18um Technology


Duration feb ’10 till May ‘10
Simulation Orcad-Pspice
Guide: Mr.Vaithianathan.V, Asst.
Professor
SSN Engineering College
Project details:

• PLL was able to achieve lock for frequency range from 30MHz to 110
MHz using PSPICE(A/D)

• PLL will only be in lock for a short amount of time this is referred to as
the ‘hold time. After the hold time has expired, the PLL tends to leave
lock to approach the free running frequency of the VCO. The
phenomenon will continue indefinitely. Our ‘hold time’ turned out to
be about 2us.

Extra Curricular Activities:

 Played for our school in a Ball Badminton Tournament and


Secured First Place.

 Active member of Youth Red Cross Association.


Strength:
 Hard working nature and Strong reasoning skills.

 Ability to get along with others.

Personal Profile:

Name : Ruby Krishna.S


Date of Birth : 15-4-1987.
Age : 22 Years.
Father’s Name : S.Sankaran
Father’s Occupation : Junior Engineer in Chennai Port Trust.
Mother’s Name : S.Vetriselvi
Sex : Male
Nationality : Indian
Languages Known : Tamil, English.
Hobbies : Playing Ball Badminton, Cricket
Chatting, Listening To Music

Declaration:

I hereby declare that the above-mentioned information is correct up


to my knowledge and I bear the responsibility for the correctness of the above-
mentioned particulars.

Place: Chennai.
(Ruby Krishna.S)

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