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Suresh.M Mobile: 9491450550: Career Objective

This document contains a resume for Suresh M. It includes details about his education, skills, experience, projects, publications, and workshops. The resume provides information on his qualifications and experience in areas like VLSI, digital logic design, and electronics.

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26 views

Suresh.M Mobile: 9491450550: Career Objective

This document contains a resume for Suresh M. It includes details about his education, skills, experience, projects, publications, and workshops. The resume provides information on his qualifications and experience in areas like VLSI, digital logic design, and electronics.

Uploaded by

suresh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Suresh.

M
Email:[email protected]
Mobile: 9491450550

CAREER OBJECTIVE:

Seeking a challenging and creative career environment where I can apply my


knowledge for my career growth and contribute towards the goals of organization.

ACADEMIC QUALIFICATION:

 M.Tech (VLSI.S.D) from Annamacharya institute of technology &Science (JNTU


ananthapur), Rajampet in 2013 with Aggregate of 75.5%
B.Tech (ECE) from Priyadarshni College Of Engineering(JNTU ananthapur), sullurpet
in 2011 with Aggregate of 68.11%
Intermediate (M.P.C) from Vikram Junior College, Sri kalahasti in 2007 with
Aggregate of 73.4%
S.S.C from Z.P. High School, Thondamanadu in 2005 with Aggregate of 66.6%

AREA OF INTEREST:

 VLSI
 Switching theory and logic design
 Linear IC Applications
 Electronic instrumentation
 Antennas and wave propagation

TECHNICAL SKILLS:

Operating systems Windows Family

Designing Tools Modelsim6.4a, Xilinx 10.1

Languages Verilog HDL, VHDL,C

EXPERIENCE:

1.I worked as Academic Consultant in School of Engineering & Technology, SPMVV,


Tirupati from 23rd June 2014 to 20th May 2016.
2.I worked as Assistant professor in Priyadarshni College Of Engineering ,PDCS, Sullurpet
from 9 Aug 2014 to 20th May 2019.
3.I worked as EC LAB Tutor in Indian Institute Of Information Technology , Sricity,IIIT from
9 Oct 2019 to 31st Dec 2020.

My STRENGTHS:

1 Good Communication skills.


2 Ability to work in a team.
3 Adaptive to the new environment quickly.

ACADEMIC PROJECTS:

DESIGN AND DEVELOPMENT OF A GSM BASED VEHICLE THEFT


TRACKING SYSTEM
Description:
The process of working of this project is explained as follows, this total
equipment of this project placed in a vehicle. The authorized person details with mobile
number and some predefined parameters are stored in the Microcontroller. Whenever we
find that our vehicle is missing then simply send a SMS or a Missed-Call to GSM Modem
from the authorized mobile after registering with the GSM modem. Then we can send a SMS
to the modem to block the vehicle such that the vehicle will not move forward anymore. The
message includes the location at which the vehicle is present at that particular instant of
time.

JOURNALS:

1. “A New Efficient Algorithm for Removal of High Density Salt and Pepper Noise Using
Modified DBUF Median Filter for Video Restoration” ( ISSN: 2320-9801, Vol. 3, Issue
5, May 2015)
2. “3G Design For ATM Banking using SIM” (ISSN: 2347-2812,Vol. 1 Issue 3,August
2013)

CONFERENCES:

1. “Distance Analysis and secure Smart Banking using Central FPGA”,presented at


ICEEE in IRD INDIA, Hyderabad on August-2013
2. “Automatic Detection of Diabetic Mellitus Using Image segmentation”, presented at
NCACT-2K15 in AITS,Tirupati on 18th April -2015
3. “Distance Analysis and secure Smart Banking using Central FPGA” ,presented at
ICSS in JBIT,Hyderabad on 8th Oct 2013)
4. National Conference on Modern Trends in Computers,Electronics,Civil&Power
Engineering, Presented at ASCT on sep.2013
5. A two Day National Conference on Advanced Communication Systems & Applications,
Presented at MITS on June 2013

WORKSHOPS:

1. NIDAYS 2014-11th Annual conference, NI India, Nimhans Convention


Center,Bangalore,18th September 2014
2. Two-week STTP workshop on Design of Algorithms -IIT Kharagpur , May
2015
3. Two-week ISTE workshop on Control Systems –IIT Kharagpur, June 2014
4. National level faculty development program on Embedded Systems,TEQIP-II
in SVEC,10th Oct. 2014
5. Two Day Workshop on “VLSI Circuit Design using CADENCE DESIGN
TOOLS,ASCET,9th May 2013

DECLARATION:

I hereby declare that the information furnished above is true to best of my Knowledge.

Place: Signature
Date: (M.Suresh)

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