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MSP430i204x, MSP430i203x, MSP430i202x Mixed-Signal Microcontrollers

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MSP430I2041, MSP430I2040

MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021

MSP430i204x, MSP430i203x, MSP430i202x Mixed-Signal Microcontrollers

– Brownout detector
1 Features
– Built-in voltage reference
• Supply voltage range: 2.2 V to 3.6 V – Temperature sensor
• High-performance analog • Clock system
– MSP430i204x: Four 24-bit sigma-delta analog- – 16.384-MHz internal digitally controlled
to-digital converters (ADCs) with differential oscillator (DCO)
PGA inputs
– DCO operation with internal or external resistor
– MSP430I203x: Three 24-bit sigma-delta
– External digital clock source
analog-to-digital converters (ADCs) with
differential PGA inputs • Development tools and software (also see Tools
and Software)
– MSP430I202x: Two 24-bit sigma-delta analog-
to-digital converters (ADCs) with differential – EVM430-I2040S evaluation module (EVM) for
PGA inputs metering
• Ultra-low power consumption – MSP-TS430RHB32A 100-pin target
development board
– Active mode (AM):
All system clocks active – MSP430Ware™ code examples
275 µA/MHz at 16.384-MHz, 3.0 V, flash • Wake up from standby mode in 1 µs
program execution (typical) • 16-bit RISC architecture, up to 16.384-MHz
– Standby mode (LPM3): system clock
Watchdog timer active, full RAM retention • Serial onboard programming, no external
210 µA at 3.0 V (typical) programming voltage needed
– Off mode (LPM4): • Available in 28-pin TSSOP (PW) and 32-pin VQFN
Full RAM retention (RHB) packages
70 µA at 3.0 V (typical) • Device Comparison summarizes the available
– Shutdown mode (LPM4.5): family members
75 nA at 3.0 V (typical) • Featured software and reference designs
• Intelligent digital peripherals – Energy Measurement Design Center for
– Two 16-bit timers with three capture/compare MSP430 MCUs application software and
registers each frameworks
– Hardware multiplier supports 16-bit operations – Digital Signal Processing (DSP) Library for
• Enhanced universal serial communication MSP430 Microcontrollers software libraries
interfaces (eUSCIs) – Single Phase and DC Embedded Metering
– eUSCI_A0 reference design
• Enhanced UART with automatic baud-rate – Three Output Smart Power Strip reference
detection design
• IrDA encoder and decoder 2 Applications
• Synchronous SPI
• Metering
– eUSCI_B0
• Submetering
• Synchronous SPI
• Power monitoring and control
• I2C
• Industrial sensors
• Flexible power management system
• 1-phase AC and DC power monitoring
– Integrated LDO with 1.8-V regulated core
• 2-phase electronic meters
supply voltage
• Smart plugs
– Supply voltage monitor with programmable
level detection • Smart power strips
• Medical – multiple-parameter patient monitoring

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021 www.ti.com

3 Description
The Texas Instruments MSP430i204x, MSP430I203x and MSP430I202x microcontrollers (MCUs) are part of
the MSP430™ Metrology and Monitoring portfolio. The architecture and integrated peripherals, combined with
five extensive low-power modes, are optimized to achieve extended battery life in portable and battery-powered
measurement applications. The devices feature a powerful 16-bit RISC CPU, 16-bit registers, and constant
generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the
devices to wake up from low-power modes to active mode in less than 5 µs.
The MSP430i204x MCUs include four high-performance 24-bit sigma-delta ADCs, two eUSCIs (one eUSCI_A
module and one eUSCI_B module), two 16-bit timers, a hardware multiplier, and up to 16 I/O pins.
The MSP430I203x MCUs include three high-performance 24-bit sigma-delta ADCs, two eUSCIs (one eUSCI_A
module and one eUSCI_B module), two 16-bit timers, a hardware multiplier, and up to 16 I/O pins.
The MSP430I202x MCUs include two high-performance 24-bit sigma-delta ADCs, two eUSCIs (one eUSCI_A
module and one eUSCI_B module), two 16-bit timers, a hardware multiplier, and up to 16 I/O pins.
Typical applications for these devices include energy measurement, analog and digital sensor systems, LED
lighting, digital power supplies, motor controls, remote controls, thermostats, digital timers, and hand-held
meters.
The MSP430i204x, MSP430I203x and MSP430I202x MCUs are supported by an extensive hardware and
software ecosystem with reference designs and code examples to get your design started quickly. Development
kits include the EVM430-I2040S evaluation module (EVM) for metering and the MSP-TS430RHB32A 100-pin
target development board. The Energy Measurement Design Center for MSP430 MCUs is provided as a rapid
development tool that enables energy measurement on these devices. TI also provides free MSP430Ware™
software, which is available as a component of Code Composer Studio™ IDE desktop and cloud versions within
TI Resource Explorer. The MSP430 MCUs are also supported by extensive online collateral, training, and online
support through the TI E2E™ support forums.
For complete module descriptions, see the MSP430i2xx Family User's Guide.
Device Information
(1)PART NUMBER PACKAGE BODY SIZE(2)
MSP430i2041TPW TSSOP (28) 9.7 mm × 4.4 mm
MSP430i2041TRHB VQFN (32) 5 mm × 5 mm

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
www.ti.com SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021

4 Functional Block Diagram

Figure 4-1 shows the functional block diagram for the MSP430i204x devices in the RHB package. For the
functional block diagrams of all device variants and packages, see Section 9.2.
ROSC VCC DVSS AVSS VCORE RST/NMI P1.x P2.x
8 8

ACLK
Clock TA0 TA1 Port P1 Port P2
System Flash RAM
SMCLK Timer_A Timer_A 8 I/Os, 8 I/Os,
32KB 2KB
3 CC 3 CC Interrupt Interrupt
16KB 1KB
MCLK Registers Registers capability capability

16.384-MHz MAB
CPU
with 16 MDB
registers

Emulation
2BP
Hardware
Power SD24 Multiplier
JTAG Management Watchdog (16x16) eUSCI_A0
Interface 4 eUSCI_B0
WDT
LDO Sigma-Delta MPY, UART, 2
REF Analog-to- 15 or 16 bit SPI, I C
MPYS, IrDA, SPI
Spy-Bi- VMON Digital MAC,
Wire Brownout Converters MACS

Figure 4-1. Functional Block Diagram – RHB Package – MSP430i204x

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020
MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021 www.ti.com

Table of Contents
1 Features............................................................................1 9.2 Functional Block Diagrams....................................... 32
2 Applications..................................................................... 1 9.3 CPU.......................................................................... 38
3 Description.......................................................................2 9.4 Instruction Set........................................................... 39
4 Functional Block Diagram.............................................. 3 9.5 Operating Modes...................................................... 40
5 Revision History.............................................................. 5 9.6 Interrupt Vector Addresses....................................... 41
6 Device Comparison......................................................... 6 9.7 Special Function Registers....................................... 42
6.1 Related Products........................................................ 6 9.8 Flash Memory........................................................... 42
7 Terminal Configuration and Functions..........................7 9.9 JTAG Operation........................................................ 43
7.1 Pin Diagrams.............................................................. 7 9.10 Peripherals..............................................................45
7.2 Signal Descriptions................................................... 10 9.11 Input/Output Diagrams............................................ 49
7.3 Pin Multiplexing.........................................................12 9.12 Device Descriptor....................................................56
7.4 Connection of Unused Pins...................................... 12 9.13 Memory................................................................... 57
8 Specifications................................................................ 13 9.14 Identification............................................................60
8.1 Absolute Maximum Ratings...................................... 13 10 Applications, Implementation, and Layout............... 61
8.2 ESD Ratings............................................................. 13 11 Device and Documentation Support..........................62
8.3 Recommended Operating Conditions.......................13 11.1 Getting Started and Next Steps.............................. 62
8.4 Active Mode Supply Current (Into VCC) 11.2 Device Nomenclature..............................................62
Excluding External Current .........................................14 11.3 Tools and Software..................................................63
8.5 Low-Power Mode Supply Currents (Into VCC) 11.4 Documentation Support.......................................... 64
Excluding External Current .........................................15 11.5 Support Resources................................................. 65
8.6 Thermal Resistance Characteristics......................... 15 11.7 Electrostatic Discharge Caution.............................. 65
8.7 Timing and Switching Characteristics....................... 16 11.8 Glossary.................................................................. 66
9 Detailed Description......................................................32 12 Mechanical, Packaging, and Orderable
9.1 Overview................................................................... 32 Information.................................................................... 67

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
www.ti.com SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from revision B to revision C
Changes from March 4, 2020 to March 16, 2021 Page
• Updated the numbering format for tables, figures, and cross references throughout the document..................1
• Updated "Featured software and reference designs" in Section 1, Features .................................................... 1

Changes from revision A to revision B

Changes from May 3, 2018 to March 3, 2020 Page
• Updated Section 1, Features ............................................................................................................................. 1
• Updated Section 3, Description ......................................................................................................................... 2
• Added 2 and 4 to the SD24GAINx options in the test conditions of the "Gain error" parameter in Section
8.7.7.5, SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256) ...................................23
• Added 2 and 4 to the SD24GAINx options in the test conditions of the "Gain error" parameter in Section
8.7.7.6, SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256) ..................................24
• Changed the MIN values for the tHD,STA, tSU,STA, tHD,DAT, tSU,DAT, and tSU,STO parameters in Section 8.7.8.6,
eUSCI (I2C Mode) Timing ................................................................................................................................ 30
• Updated descriptions and links in Section 10, Applications, Implementation, and Layout .............................. 61

Changes from the initial release to revision A

Changes from August 31, 2014 to May 2, 2018 Page
• Changed the list of applications in Section 2, Applications ................................................................................1
• Added Section 6.1, Related Products ................................................................................................................6
• Added typical conditions statements at the beginning of Section 8, Specifications .........................................13
• Added SD24 input pins and AUXVCCx pins to exception list on "Voltage applied to pins" parameter, and
added SD24 input pin limits in "Diode current at pins" parameter in Section 8.1, Absolute Maximum Ratings ..
13
• Added Section 8.2, ESD Ratings .....................................................................................................................13
• Added Section 8.6, Thermal Resistance Characteristics .................................................................................15
• Changed the MAX value of the tWAKE-UP-LPM4 parameter from 35 µs to 45 µs in Section 8.7.3.1, Wake-up
Times From Low Power Modes ....................................................................................................................... 17
• Added the CAUTION that begins "The CPU will lock up if..." in Section 9.3, CPU ..........................................38

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5

6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Comparison
eUSCI_A:
FLASH SRAM SD24 eUSCI_B:
DEVICE(1) MULTIPLIER Timer_A(2) UART, IrDA, I/O PACKAGE
(KB) (KB) CONVERTERS SPI, I2C
SPI
16 32 RHB
MSP430i2041 32 2 4 1 3, 3 1 1
12 28 PW
16 32 RHB
MSP430i2040 16 1 4 1 3, 3 1 1
12 28 PW
16 32 RHB
MSP430i2031 32 2 3 1 3, 3 1 1
12 28 PW
16 32 RHB
MSP430i2030 16 1 3 1 3, 3 1 1
12 28 PW
16 32 RHB
MSP430i2021 32 2 2 1 3, 3 1 1
12 28 PW
16 32 RHB
MSP430i2020 16 1 2 1 3, 3 1 1
12 28 PW

(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section
12, or see the TI website at www.ti.com.
(2) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and
PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

6.1 Related Products

For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
MSP430 ultra-low-power sensing and measurement microcontrollers
One platform. One ecosystem. Endless possibilities.
Reference designs for MSP430i2041
Find reference designs leveraging the best in TI technology to solve your system-level challenges. All designs
include a schematic, test data and design files.

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
www.ti.com SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021

7 Terminal Configuration and Functions

7.1 Pin Diagrams
Figure 7-1 shows the pin assignments for the MSP430i2041 and MSP430i2040 devices in the RHB package.

P2.0/TA1.0/CLKIN
P2.3/VMONIN
P2.7/TA0.2
P2.6/TA0.1
P2.5/TA0.0
P2.4/TA1.0

P2.2/TA1.2
P2.1/TA1.1
32 31 30 29 28 27 26 25
A0.0+ 1 24 P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A0.0- 2 23 P1.6/UCB0SCL/UCB0SOMI/TA0.2
A1.0+ 3 22 P1.5/UCB0CLK/TA0.1
A1.0- 4 MSP430i2041TRHB 21 P1.4/UCB0STE/TA0.0
MSP430i2040TRHB
A2.0+ 5 20 P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
A2.0- 6 19 P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
A3.0+ 7 18 P1.1/UCA0CLK/SMCLK/TMS
A3.0- 8 17 P1.0/UCA0STE/MCLK/TCK
9 10 11 12 13 14 15 16
VCORE
AVSS

DVSS
VREF

RST/NMI/SBWTDIO
ROSC

VCC

TEST/SBWTCK

NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.

Figure 7-1. 32-Pin RHB Package (Top View) – MSP430i2041, MSP430i2040

Figure 7-2 shows the pin assignments for the MSP430i2041 and MSP430i2040 devices in the PW package.

A0.0+ 1 28 P2.3/VMONIN
A0.0- 2 27 P2.2/TA1.2
A1.0+ 3 26 P2.1/TA1.1
A1.0- 4 25 P2.0/TA1.0/CLKIN
A2.0+ 5 24 P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A2.0- 6 23 P1.6/UCB0SCL/UCB0SOMI/TA0.2
MSP430i2041TPW
A3.0+ 7 22 P1.5/UCB0CLK/TA0.1
MSP430i2040TPW
A3.0- 8 21 P1.4/UCB0STE/TA0.0
VREF 9 20 P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
AVSS 10 19 P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
ROSC 11 18 P1.1/UCA0CLK/SMCLK/TMS
DVSS 12 17 P1.0/UCA0STE/MCLK/TCK
VCC 13 16 TEST/SBWTCK
VCORE 14 15 RST/NMI/SBWTDIO

Figure 7-2. 28-Pin PW Package (Top View) – MSP430i2041, MSP430i2040

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7

Figure 7-3 shows the pin assignments for the MSP430i2031 and MSP430i2030 devices in the RHB package.

P2.0/TA1.0/CLKIN
P2.3/VMONIN
P2.7/TA0.2
P2.6/TA0.1
P2.5/TA0.0
P2.4/TA1.0

P2.2/TA1.2
P2.1/TA1.1
32 31 30 29 28 27 26 25
A0.0+ 1 24 P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A0.0- 2 23 P1.6/UCB0SCL/UCB0SOMI/TA0.2
A1.0+ 3 22 P1.5/UCB0CLK/TA0.1
A1.0- 4 MSP430i2031TRHB 21 P1.4/UCB0STE/TA0.0
MSP430i2030TRHB
A2.0+ 5 20 P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
A2.0- 6 19 P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
NC 7 18 P1.1/UCA0CLK/SMCLK/TMS
NC 8 17 P1.0/UCA0STE/MCLK/TCK
9 10 11 12 13 14 15 16
VCORE
AVSS

DVSS
VREF

RST/NMI/SBWTDIO
ROSC

VCC

TEST/SBWTCK

NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.
NOTE: TI recommends connecting NC pins to AVSS.

Figure 7-3. 32-Pin RHB Package (Top View) – MSP430i2031, MSP430i2030

Figure 7-4 shows the pin assignments for the MSP430i2031 and MSP430i2030 devices in the PW package.

A0.0+ 1 28 P2.3/VMONIN
A0.0- 2 27 P2.2/TA1.2
A1.0+ 3 26 P2.1/TA1.1
A1.0- 4 25 P2.0/TA1.0/CLKIN
A2.0+ 5 24 P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A2.0- 6 23 P1.6/UCB0SCL/UCB0SOMI/TA0.2
MSP430i2031TPW
NC 7 22 P1.5/UCB0CLK/TA0.1
MSP430i2030TPW
NC 8 21 P1.4/UCB0STE/TA0.0
VREF 9 20 P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
AVSS 10 19 P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
ROSC 11 18 P1.1/UCA0CLK/SMCLK/TMS
DVSS 12 17 P1.0/UCA0STE/MCLK/TCK
VCC 13 16 TEST/SBWTCK
VCORE 14 15 RST/NMI/SBWTDIO

NOTE: TI recommends connecting NC pins to AVSS.

Figure 7-4. 28-Pin PW Package (Top View) – MSP430i2031, MSP430i2030

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
www.ti.com SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021

Figure 7-5 shows the pin assignments for the MSP430i2021 and MSP430i2020 devices in the RHB package.

P2.0/TA1.0/CLKIN
P2.3/VMONIN
P2.7/TA0.2
P2.6/TA0.1
P2.5/TA0.0
P2.4/TA1.0

P2.2/TA1.2
P2.1/TA1.1
32 31 30 29 28 27 26 25
A0.0+ 1 24 P1.7/UCB0SDA/UCB0SIMO/TA1CLK
A0.0- 2 23 P1.6/UCB0SCL/UCB0SOMI/TA0.2
A1.0+ 3 22 P1.5/UCB0CLK/TA0.1
A1.0- 4 MSP430i2021TRHB 21 P1.4/UCB0STE/TA0.0
NC 5 MSP430i2020TRHB 20 P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
NC 6 19 P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
NC 7 18 P1.1/UCA0CLK/SMCLK/TMS
NC 8 17 P1.0/UCA0STE/MCLK/TCK
9 10 11 12 13 14 15 16
VCORE
AVSS

DVSS
VREF

RST/NMI/SBWTDIO
ROSC

VCC

TEST/SBWTCK

NOTE: TI recommends connecting the thermal pad on the RHB package to DVSS.
TI recommends connecting NC pins to AVSS.

Figure 7-5. 32-Pin RHB Package (Top View) – MSP430i2021, MSP430i2020

Figure 7-6 shows the pin assignments for the MSP430i2021 and MSP430i2020 devices in the PW package.

A0.0+ 1 28 P2.3/VMONIN
A0.0- 2 27 P2.2/TA1.2
A1.0+ 3 26 P2.1/TA1.1
A1.0- 4 25 P2.0/TA1.0/CLKIN
NC 5 24 P1.7/UCB0SDA/UCB0SIMO/TA1CLK
NC 6 23 P1.6/UCB0SCL/UCB0SOMI/TA0.2
NC 7 MSP430i2021TPW 22 P1.5/UCB0CLK/TA0.1
NC 8 MSP430i2020TPW 21 P1.4/UCB0STE/TA0.0
VREF 9 20 P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI
AVSS 10 19 P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK
ROSC 11 18 P1.1/UCA0CLK/SMCLK/TMS
DVSS 12 17 P1.0/UCA0STE/MCLK/TCK
VCC 13 16 TEST/SBWTCK
VCORE 14 15 RST/NMI/SBWTDIO

TI recommends connecting NC pins to AVSS.

Figure 7-6. 28-Pin PW Package (Top View) – MSP430i2021, MSP430i2020

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9

7.2 Signal Descriptions

Section 7.2 describes the signals for all device variants and package options.
Table 7-1. Signal Descriptions
TERMINAL
NO.(2) I/O(1) DESCRIPTION
NAME
PW RHB
A0.0+ 1 1 I SD24 positive analog input A0.0(3)
A0.0- 2 2 I SD24 negative analog input A0.0(3)
A1.0+ 3 3 I SD24 positive analog input A1.0(3)
A1.0- 4 4 I SD24 negative analog input A1.0(3)
A2.0+ 5 5 I SD24 positive analog input A2.0(3) (4)
A2.0- 6 6 I SD24 negative analog input A2.0(3) (4)
A3.0+ 7 7 I SD24 positive analog input A3.0 (3) (4) (5)
A3.0- 8 8 I SD24 negative analog input A3.0 (3) (4) (5)
VREF(6) 9 9 I SD24 external reference voltage input
AVSS 10 10 Analog supply voltage, negative terminal
External resistor pin for DCO.
Connect recommended resistor between ROSC and AVSS for DCO operation
ROSC 11 11
in external resistor mode. Connect ROSC to AVSS while operating DCO in
internal resistor mode.
DVSS 12 12 Digital supply voltage, negative terminal
VCC 13 13 Analog and digital supply voltage, positive terminal
VCORE (7) 14 14 Regulated core power supply (internal use only, no external current loading)
Reset or nonmaskable interrupt input.
RST/NMI/SBWTDIO 15 15 I/O
Spy-Bi-Wire test data input/output for device programming and test.
Selects test mode for JTAG pins on P1.0 to P1.3.
TEST/SBWTCK 16 16 I
Spy-Bi-Wire test clock input for device programming and test.
General-purpose digital I/O pin.
eUSCI_A0 SPI slave transmit enable (direction controlled by eUSCI).
P1.0/UCA0STE/MCLK/TCK 17 17 I/O
MCLK output.
JTAG test clock. TCK is the clock input port for device programming and test.
General-purpose digital I/O pin.
eUSCI_A0 clock input/output (direction controlled by eUSCI).
P1.1/UCA0CLK/SMCLK/TMS 18 18 I/O SMCLK output.
JTAG test mode select. TMS is used as an input port for device programming
and test.
General-purpose digital I/O pin.
eUSCI_A0 UART receive data or eUSCI_A0 SPI slave out/master in (direction
P1.2/UCA0RXD/UCA0SOMI/ controlled by eUSCI).
19 19 I/O
ACLK/TDI/TCLK
ACLK output.
JTAG test data input or test clock input for device programming and test.
General-purpose digital I/O pin.
eUSCI_A0 UART transmit data or eUSCI_A0 SPI slave in/master out (direction
P1.3/UCA0TXD/UCA0SIMO/ controlled by eUSCI).
20 20 I/O
TA0CLK/TDO/TDI Timer external clock input TACLK for TA0.
JTAG test data output port. TDO/TDI data output or programming data input
terminal.
General-purpose digital I/O pin.
P1.4/UCB0STE/TA0.0 21 21 I/O eUSCI_B0 SPI slave transmit enable (direction controlled by eUSCI).
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output.

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Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020

MSP430I2041, MSP430I2040
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Table 7-1. Signal Descriptions (continued)

TERMINAL
NO.(2) I/O(1) DESCRIPTION
NAME
PW RHB
General-purpose digital I/O pin.
P1.5/UCB0CLK/TA0.1 22 22 I/O eUSCI_B0 clock input/output (direction controlled by eUSCI).
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output.
General-purpose digital I/O pin.
P1.6/UCB0SCL/UCB0SOMI/ eUSCI_B0 I2C clock or eUSCI_B0 SPI slave out/master in (direction controlled
23 23 I/O
TA0.2 by eUSCI).
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output.
General-purpose digital I/O pin.
P1.7/UCB0SDA/UCB0SIMO/ eUSCI_B0 I2C data or eUSCI_B0 slave input/master output (direction
24 24 I/O
TA1CLK controlled by eUSCI).
Timer external clock input TACLK for TA1.
General-purpose digital I/O pin.
P2.0/TA1.0/CLKIN 25 25 I/O Timer TA1 CCR0 capture: CCI0A input, compare: Out0 output.
DCO bypass clock input.
General-purpose digital I/O pin.
P2.1/TA1.1 26 26 I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 output.
General-purpose digital I/O pin.
P2.2/TA1.2 27 27 I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 output.
General-purpose digital I/O pin.
P2.3/VMONIN 28 28 I/O
Voltage monitor input.
General-purpose digital I/O pin.
P2.4/TA1.0(8) N/A 29 I/O
Timer TA1 CCR0 capture: CCI0B input, compare: Out0 output.
General-purpose digital I/O pin.
P2.5/TA0.0(8) N/A 30 I/O
Timer TA0 CCR0 capture: CCI0B input, compare: Out0 output.
General-purpose digital I/O pin.
P2.6/TA0.1(8) N/A 31 I/O
Timer TA0 CCR1 compare: Out1 output.
General-purpose digital I/O pin.
P2.7/TA0.2(8) N/A 32 I/O
Timer TA0 CCR2 compare: Out2 output.

(1) I = input, O = output

(2) N/A = not available
(3) Short unused analog input pairs and connect them to analog ground (see Section 7.4 for recommendations on all unused pins).
(4) Not available on MSP430i2021 and MSP430i2020 devices.
(5) Not available on MSP430i2031 and MSP430i2030 devices.
(6) When the SD24 operates with the internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Connect only the
recommended capacitor value (CVREF) from the VREF pin to AVSS (see Section 8.7.7.2).
(7) VCORE is for internal use only. No external current loading is possible. Connect VCORE to only the recommended capacitor value
(CVCORE) (see Section 8.3).
(8) These pins are not available on the 28-pin PW package. Program these four pins to output direction and drive value 0 in software.

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7.3 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if
the device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see
Section 9.11.
7.4 Connection of Unused Pins
Table 7-2 lists the correct termination of all unused pins.
Table 7-2. Connection of Unused Pins
PIN(1) POTENTIAL COMMENT
AVCC DVCC
AVSS DVSS
VREF Open
ROSC AVSS Connect the ROSC pin to AVSS when the DCO is used in internal resistor mode.
Px.0 to Px.7 Open Set to port function, output direction.
Ax.0+ and Ax.0- AVSS Short unused analog input pairs and connect them to analog ground.
RST/NMI DVCC or VCC 47-kΩ pullup with 10 nF (or 2.2 nF(2)) pulldown
TEST Open This pin always has an internal pulldown enabled.
P1.3/TDO
The JTAG pins are shared with general-purpose I/O function (P1.x). If these pins are not
P1.2/TDI
Open used, set them to port function and output direction. When used as JTAG pins, leave these
P1.1/TMS
pins open.
P1.0/TCK

(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 unused
pin connection.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools like FET interfaces or GANG programmers.

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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
Supply voltage applied at VCC –0.3 4.1 V
All pins except VCORE(3), ROSC(4), and SD24 input pins
Voltage applied to pins –0.3 VCC + 0.3 V
(A0.0+, A0.0-, A1.0+, A1.0-, A2.0+, A2.0-, A3.0+, A3.0-)(5)
All pins except SD24 input pins (A0.0+, A0.0-, A1.0+, A1.0-,
±2
Diode current at pins A2.0+, A2.0-, A3.0+, A3.0-) mA
A0.0+, A0.0-, A1.0+, A1.0-, A2.0+, A2.0-, A3.0+, A3.0-(6) 2
Maximum junction temperature, TJ,MAX 115 °C
Storage temperature, Tstg (7) –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are referenced to VSS.
(3) VCORE is for internal device use only. Do not apply external DC loading or voltage at VCORE.
(4) Do not apply external DC loading or voltage at ROSC. Connect the recommended resistor at ROSC using the DCO in external resistor
mode. Connect ROSC to AVSS when operating the DCO in internal resistor mode.
(5) See Section 8.7.7.1 for SD24 specifications.
(6) A protection diode is connected to VCC for the SD24 input pins. No protection diode is connected to VSS.
(7) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.

8.2 ESD Ratings

over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.

8.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage during program execution and flash programming or erase (VCC = VCC) 2.2 3.6 V
VSS Supply voltage (AVSS = DVSS = VSS) 0 V
TA Operating free-air temperature T temperature range –40 105 °C
TJ Operating junction temperature T temperature range –40 105 °C
CVCORE Recommended capacitor at VCORE 470 nF
CVCC/
Capacitor ratio of VCC to VCORE 10
CVCORE
fSYSTEM Processor frequency (maximum MCLK frequency) (1) (2) 0 16.384 MHz

(1) The MSP430i CPU is clocked directly with MCLK.

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(2) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

16.384

System Frequency (MHz)

0
2.2 3.6
Supply Voltage (V)

Figure 8-1. Maximum System Frequency

8.4 Active Mode Supply Current (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fDCO = 16.384 MHz, fMCLK = fSMCLK = 1.024 MHz,
Active mode
fACLK = 32 kHz,
IAM, 1.024MHz current at 3V 1.6 mA
Program executes from flash,
1.024 MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fDCO = 16.384 MHz, fMCLK = fSMCLK = 8.192 MHz,
Active mode
fACLK = 32 kHz,
IAM, 8.192MHz current at 3V 3.0 mA
Program executes from flash,
8.192 MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
fDCO = fMCLK = fSMCLK = 16.384 MHz,
Active mode
fACLK = 32 kHz,
IAM, 16.384MHz current at 3V 4.5 mA
Program executes from flash,
16.384 MHz
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
(2) All peripherals are inactive.

4.5 4.5

4
4
IAM - Active Mode Current (mA)

IAM - Active Mode Current (mA)

3.5
3.5
3

2.5 3

2
2.5
1.5
2
1 TA = 25°C, VCC = 2.2 V
fMCLK = 1.024 MHz fMCLK = 8.192 MHz TA = 25°C, VCC = 3 V
0.5 fMCLK = 2.048 MHz fMCLK = 16.348 MHz 1.5 TA = 105°C, VCC = 2.2 V
fMCLK = 4.096 MHz TA = 105°C, VCC = 3 V
0 1
2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 0 2 4 6 8 10 12 14 16 18
VCC - Supply Voltage (V) D007 fMCLK - Frequency (MHz) D008
Figure 8-2. Active Mode Current vs Supply Voltage Figure 8-3. Active Mode Current vs MCLK
Frequency

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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT
fDCO = 16.384 MHz, fMCLK = fSMCLK = 0 MHz,
Low-power mode 3
ILPM3 fACLK = 32 kHz, 25°C 3V 210 µA
(LPM3) current (2)
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0
Low-power mode 4 fDCO = fMCLK = fSMCLK = fACLK = 0 MHz,
ILPM4 25°C 3V 70 µA
(LPM4) current (3) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1
fDCO = fMCLK = fSMCLK = fACLK = 0 MHz, 25°C 75 nA
Low-power mode 4.5
ILPM4.5 REGOFF = 1, CPUOFF = 1, SCG0 = 1, SCG1 = 1, 3V
(LPM4.5) current (3) 105°C 325 nA
OSCOFF = 1

(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by ACLK included. All other peripherals are inactive.
(3) All peripherals are inactive.

8.6 Thermal Resistance Characteristics

THERMAL METRIC(1) PACKAGE VALUE(2) (3) UNIT
RθJA Junction-to-ambient thermal resistance, still air 35.9 °C/W
RθJC(TOP) Junction-to-case (top) thermal resistance 25.5 °C/W
RθJB Junction-to-board thermal resistance 8.6 °C/W
QFN-32 (RHB)
ΨJB Junction-to-board thermal characterization parameter 8.6 °C/W
ΨJT Junction-to-top thermal characterization parameter 0.3 °C/W
RθJC(BOTTOM) Junction-to-case (bottom) thermal resistance 1.4 °C/W
RθJA Junction-to-ambient thermal resistance, still air 77.5 °C/W
RθJC(TOP) Junction-to-case (top) thermal resistance 18.2 °C/W
RθJB Junction-to-board thermal resistance 35.5 °C/W
TSSOP-28 (PW)
ΨJB Junction-to-board thermal characterization parameter 35.0 °C/W
ΨJT Junction-to-top thermal characterization parameter 0.5 °C/W
RθJC(BOTTOM) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC package thermal metrics.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) N/A = Not applicable

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8.7 Timing and Switching Characteristics

8.7.1 Reset Timing
8.7.1.1 Reset Timing
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN MAX UNIT
tRESET Pulse duration required at the RST/NMI pin to accept a reset 4 µs

8.7.2 Clock Specifications

8.7.2.1 DCO in External Resistor Mode
recommended resistor at ROSC pin: 20 kΩ, 0.1%, ±50 ppm/°C)(1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDCO DCO current consumption 85 µA
DCO frequency calibrated 16.384 MHz
fDCO
DCO absolute tolerance calibrated VCC = 3 V, TA = 25°C ±0.25%
dfDCO/dT DCO frequency temperature drift ±20 ppm/°C
dfDCO/dVCC DCO frequency supply voltage drift 200 600 ppm/V
DCDCO Duty cycle 50%
Tdcoon DCO start-up time 40 µs

(1) The maximum parasitic capacitance at ROSC pin should not exceed 5 pF to ensure the specified DCO start-up time.

8.7.2.2 DCO in Internal Resistor Mode

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDCO DCO current consumption 85 µA
DCO frequency calibrated 16.384 MHz
fDCO
DCO absolute tolerance calibrated VCC = 3 V, TA = 25°C ±0.9%
dfDCO/dT DCO frequency temperature drift ±200 ppm/°C
dfDCO/dVCC DCO frequency supply voltage drift 200 600 ppm/V
DCDCO Duty cycle 50%
Tdcoon DCO start-up time 40 µs

8.7.2.3 DCO Overall Tolerance Table

over operating free-air temperature range (unless otherwise noted)
OVERALL
TEMPERATURE TEMPERATURE VOLTAGE VOLTAGE OVERALL
RESISTOR OPTION ACCURACY
CHANGE DRIFT (%) CHANGE DRIFT (%) DRIFT (%)
(%)
–40°C to 105 °C ±2.9 2.2 V to 3.6 V ±0.084 ±2.984 ±3.884
Internal resistor 0°C 0 2.2 V to 3.6 V ±0.084 ±0.084 ±0.984
–40°C to 105 °C ±2.9 0V 0 ±2.9 ±3.8
–40°C to 105 °C ±0.29 2.2 V to 3.6 V ±0.084 ±0.374 ±0.624
External resistor with
0°C 0 2.2 V to 3.6 V ±0.084 ±0.084 ±0.334
50-ppm TCR
–40°C to 105 °C ±0.29 0V 0 ±0.29 ±0.54

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8.7.2.4 DCO in Bypass Mode Recommended Operating Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN MAX UNIT
fDCOBYP Frequency in DCO bypass mode(1) 0 16.384 MHz

(1) External digital clock frequency in DCO bypass mode must be 16.384 MHz for the SD24 module to meet the specified performance.

8.7.3 Wake-up Characteristics

8.7.3.1 Wake-up Times From Low Power Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tWAKE-UP-LPM3 Wake-up time from LPM3 to active mode MCLK = SMCLK = 1.024 MHz 1 µs
tWAKE-UP-LPM4 Wake-up time from LPM4 to active mode MCLK = SMCLK = 1.024 MHz 45 µs
Wake-up time from LPM4.5 to active
tWAKE-UP-LPM4.5-IO CVCORE = 470 nF 0.45 ms
mode upon I/O event(1)
tWAKE-UP-LPM4.5- Wake-up time from LPM4.5 to active
CVCORE = 470 nF 0.45 ms
RESET mode upon external reset ( RST)(1)

(1) This value represents the time from the wake-up event to the reset vector execution by CPU.

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8.7.4 I/O Ports

8.7.4.1 Schmitt-Trigger Inputs – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
0.5 VCC 0.7 VCC
VIT+ Positive-going input threshold voltage V
3V 1.50 2.10
0.25 VCC 0.55 VCC
VIT- Negative-going input threshold voltage V
3V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ – VIT-) 3V 0.4 1.1 V
CI Input capacitance VIN = VSS or VCC 5 pF

8.7.4.2 Inputs – Ports P1 and P2

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Port P1, P2: P1.x to P2.x, External trigger pulse
t(int) External interrupt timing(1) 3V 20 ns
duration to set interrupt flag

(1) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int).

8.7.4.3 Leakage Current – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Py.x) High-impedance leakage current See (1) (2) 3V ±50 nA

(1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input.

8.7.4.4 Outputs – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage I(OHmax) = –6 mA(1) 3.0 V VCC – 0.60 VCC V
VOL Low-level output voltage I(OLmax) = 6 mA(1) 3.0 V VSS VSS + 0.60 V

(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.

8.7.4.5 Output Frequency – General-Purpose I/O

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC TYP UNIT
fPy.x Port output frequency (with load) Py.x, CL = 20 pF, RL = 3.2 kΩ (1) (2) 3V 16.384 MHz
fPort_CLK Clock output frequency Py.x, CL = 20 pF(2) 3V 16.384 MHz

(1) A resistive divider with two times 1.6 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
(2) The output voltage reaches at least 10% and 90% of VCC at the specified toggle frequency.

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8.7.4.6 Typical Characteristics – Outputs

One output loaded at a time.

14 22
20
IOL - Low-Level Output Current (mA)

12
18

IOL - Low Output Current (mA)

10 16
14
8
12
6 10
8
4
6
2 4
2
0 TA = 25°C TA = 25°C
TA = 105°C 0 TA = 105°C
-2 -2
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
VOL - Low-Level Output Voltage (V) D004
VOL - Low Output Voltage (V) D003

VCC = 2.2 V Measured at P1.3 VCC = 3 V Measured at P1.3

Figure 8-4. Typical Low-Level Output Current vs Figure 8-5. Typical Low-Level Output Current vs
Low-Level Output Voltage Low-Level Output Voltage
0 0
TA = 25°C TA = 25°C
-2
IOH - High-Level Output Current (mA)

IOH - High-Level Output Current (mA)

TA = 105°C TA = 105°C
-2 -4
-6
-4
-8
-10
-6
-12
-14
-8
-16

-10 -18
-20
-12 -22
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3
VOH - High-Level Output Voltage (V) D006
VOH - High-Level Output Voltage (V) D005

VCC = 2.2 V Measured at P1.3 VCC = 3 V Measured at P1.3

Figure 8-6. Typical High-Level Output Current vs Figure 8-7. Typical High-Level Output Current vs
High-Level Output Voltage High-Level Output Voltage

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8.7.5 Power Management Module

8.7.5.1 PMM, High-Side Brownout Reset (BORH)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(VCC_BOR_IT–) BORH on voltage, VCC falling level | dVCC/dt | < 3 V/s 1.08 V
V(VCC_BOR_IT+) BORH off voltage, VCC rising level | dVCC/dt | < 3 V/s 1.18 V
V(VCC_BOR_hys) BORH hysteresis 100 mV
tPOWERUP (1) Cold power-up time 0.75 ms

(1) This is the time duration between application of VCC and execution of reset vector by CPU.

8.7.5.2 PMM, Low-Side SVS (SVSL)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
V(SVSL) SVSL trip voltage on VCORE 1.70 V
V(SVSL_hys) SVSL hysteresis 14 mV
I(SVSL) SVSL current consumption 3 µA

8.7.5.3 PMM, Core Voltage

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
VCORE Core voltage 1.83 V

8.7.5.4 PMM, Voltage Monitor (VMON)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VMONIN trip level VMONLVLx = 111b 1.17
VCC trip level – 1 VMONLVLx = 001b 2.32
VMONtrip_level V
VCC trip level – 2 VMONLVLx = 010b 2.62
VCC trip level – 3 VMONLVLx = 011b 2.82
IVMON VMON current consumption 6 µA
tVMON VMON settling time 0.5 µs

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8.7.6 Reference Module

8.7.6.1 Voltage Reference (REF)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC Supply voltage range 2.2 3.6 V
VBG Bandgap output voltage calibrated VCC = 3 V 1.146 1.158 1.17 V
PSRR_DC Power supply rejection ratio (DC) VCC = 2.2 V to 3.6 V 50 µV/V
VCC = 2.2 V to 3.6 V, f = 1 kHz,
PSRR_AC Power supply rejection ratio (AC) 0.35 mV/V
ΔVpp = 100 mV
dVBG/dT Bandgap reference temperature coefficient VCC = 3 V 10 50 ppm/°C

8.7.6.2 Temperature Sensor

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 3 V, TA = 30°C 610 650 690
Vsensor Temperature sensor output voltage mV
VCC = 3 V, TA = 105°C 765 805 845
Isensor Temperature sensor quiescent current consumption 3 µA
TCsensor Temperature coefficient of sensor 1.96 2.07 2.17 mV/°C

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8.7.7 SD24
8.7.7.1 SD24 Power Supply and Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VCC Supply voltage range AVSS = DVSS = 0 V 2.2 3.6 V

Analog plus digital supply current per GAIN: 1, 2, 4, 8, 16 3V 190

ISD24 SD24OSRx = 256 µA
converter (reference current not included) GAIN: 1, 16 3V 250

8.7.7.2 SD24 Internal Voltage Reference

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VSD24REF SD24 internal reference voltage SD24REFS = 1 3V 1.146 1.158 1.17 V
CVREF Recommended capacitor at VREF 100 nF
tSD24REF_settle SD24 reference buffer settling time SD24REFS = 0 → 1, CVREF = 100 nF 200 µs

(1) When SD24 operates with internal reference (SD24REFS = 1), the VREF pin must not be loaded externally. Only the recommended
capacitor value, CVREF must be connected at the VREF pin to AVSS.

8.7.7.3 SD24 External Voltage Reference

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VREF(I) Input voltage range SD24REFS = 0 3V 1.0 1.2 1.5 V
IREF(I) Input current SD24REFS = 0 3V 50 nA

8.7.7.4 SD24 Input Range

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Differential full-scale input voltage –VREF/ +VREF/
VID,FSR VID = VI,A+ – VI,A– V
range GAIN GAIN
SD24GAINx = 1 ±928
SD24GAINx = 2 ±464
Differential input voltage range for
VID SD24REFS = 1 SD24GAINx = 4 ±232 mV
specified performance(2)
SD24GAINx = 8 ±116
SD24GAINx = 16 ±58
Input impedance
ZI SD24GAINx = 1, 16 3V 200 kΩ
(pin A+ or A- to AVSS)(3)
Differential input impedance (pin A+
ZID SD24GAINx = 1, 16 3V 300 400 kΩ
to pin A-)(3)
VI Absolute input voltage range AVSS – 1 VCC V
VIC Common-mode input voltage range AVSS – 1 VCC V

(1) All parameters pertain to each SD24 channel.

(2) The full-scale range is defined by VFSR+ = +VREF/GAIN and VFSR– = –VREF/GAIN; FSR = VFSR+ – VFSR– = 2xVREF/GAIN. If VREF is
sourced externally, the analog input range should not exceed 80% of VFSR+ or VFSR–; that is, VID = 0.8 VFSR– to 0.8 VFSR+. If VREF is
sourced internally, the given VID ranges apply.
(3) Applicable for SD24 modulator OFF as well as ON conditions.

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8.7.7.5 SD24 Performance, Internal Reference (SD24REFS = 1, SD24OSRx = 256)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAINx = 1 84 89
SD24GAINx = 2 89
Signal-to-noise +
SINAD SD24GAINx = 4 fIN = 50 Hz(1) 3V 87 dB
distortion ratio
SD24GAINx = 8 83
SD24GAINx = 16 77
SD24GAINx = 1 100
THD Total harmonic distortion SD24GAINx = 8 fIN = 50 Hz(1) 3V 95 dB
SD24GAINx = 16 90
SD24GAINx = 1 100
Spurious-free dynamic
SFDR SD24GAINx = 8 fIN = 50 Hz(1) 3V 95 dB
range
SD24GAINx = 16 90
Integral nonlinearity,
INL SD24GAINx: 1, 8, 16 3V –0.003 0.003 % FSR
end-point fit
SD24GAINx = 1 1
SD24GAINx = 2 2
G Nominal gain SD24GAINx = 4 3V 4
SD24GAINx = 8 8
SD24GAINx = 16 16
EG Gain error SD24GAINx: 1, 2, 4, 8, 16 3V –2% 2%
Gain error temperature
ΔEG/ ΔT SD24GAINx: 1, 8, 16 3V 50 ppm/°C
coefficient
SD24GAINx = 1 4
EOS Offset error 3V mV
SD24GAINx = 16 2

Offset error temperature SD24GAINx = 1 ±5 ±25 ppm

ΔEOS/ΔT 3V
coefficient SD24GAINx = 16 ±3 ±10 FSR/°C
SD24GAINx = 1, Common-mode input signal:
–55
Common-mode rejection VID = 928 mV, fIN = 50 Hz
CMRR,50Hz 3V dB
ratio at 50 Hz SD24GAINx = 16, Common-mode input signal:
–60
VID = 58 mV, fIN = 50 Hz
SD24GAINx: 1, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =
3V –90
50 Hz, Inputs grounded (no analog signal applied)
AC power supply SD24GAINx: 8, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =
AC PSRR 3V –95 dB
rejection ratio 50 Hz, Inputs grounded (no analog signal applied)
SD24GAINx: 16, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =
3V –95
50 Hz, Inputs grounded (no analog signal applied)
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: –120
SD24GAINx = 1
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
Crosstalk between
XT possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: 3V –110 dB
converters
SD24GAINx = 8
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: –110
SD24GAINx = 16

(1) The following voltages are applied to the SD24 inputs:

VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) – VIN,A–(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to SD24 input range).

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23

8.7.7.6 SD24 Performance, External Reference (SD24REFS = 0, SD24OSRx = 256)

external reference voltage is 1.2 V., over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
SD24GAINx = 1 91
SD24GAINx = 2 90
Signal-to-noise + distortion
SINAD SD24GAINx = 4 fIN = 50 Hz(1) 3V 88 dB
ratio
SD24GAINx = 8 83
SD24GAINx = 16 77
SD24GAINx = 1 100
THD Total harmonic distortion SD24GAINx = 8 fIN = 50 Hz(1) 3V 95 dB
SD24GAINx = 16 90
SD24GAINx = 1 100
Spurious-free dynamic
SFDR SD24GAINx = 8 fIN = 50 Hz(1) 3V 95 dB
range
SD24GAINx = 16 90
Integral nonlinearity, end-
INL SD24GAINx: 1, 8, 16 3V –0.003 0.003 % FSR
point fit
SD24GAINx = 1 1
SD24GAINx = 2 2
G Nominal gain SD24GAINx = 4 3V 4
SD24GAINx = 8 8
SD24GAINx = 16 16
EG Gain error SD24GAINx: 1, 2, 4, 8, 16 3V –1% +1%
Gain error temperature
ΔEG/ ΔT SD24GAINx: 1, 8, 16 3V 10 ppm/°C
coefficient
SD24GAINx = 1 4
EOS Offset error 3V mV
SD24GAINx = 16 2

Offset error temperature SD24GAINx = 1 ±5 ±25 ppm

ΔEOS/ΔT 3V
coefficient SD24GAINx = 16 ±3 ±10 FSR/°C
SD24GAINx = 1, Common-mode input signal:
–55
Common-mode rejection VID = 928 mV, fIN = 50 Hz
CMRR,50Hz 3V dB
ratio at 50 Hz SD24GAINx = 16, Common-mode input signal:
–60
VID = 58 mV, fIN = 50 Hz
SD24GAINx: 1, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =
3V –90
50 Hz, Inputs grounded (no analog signal applied)
AC power supply rejection SD24GAINx: 8, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC =
AC PSRR 3V –95 dB
ratio 50 Hz, Inputs grounded (no analog signal applied)
SD24GAINx: 16, VCC = 3 V ±50 mV × sin(2π × fVCC × t), fVCC
3V –95
= 50 Hz, Inputs grounded (no analog signal applied)
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: –120
SD24GAINx = 1
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
Crosstalk between
XT possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: 3V –110 dB
converters
SD24GAINx = 8
Crosstalk source: SD24GAINx = 1, Sine-wave with maximum
possible VPP, fIN = 50 Hz or 100 Hz, Converter under test: –110
SD24GAINx = 16

(1) The following voltages are applied to the SD24 inputs:

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8.7.7.7 Typical Characteristics

90 90
87
85
84
81 80
78

SINAD (dB)
SINAD (dB)

75
75
72 70
69
66 65

63
60
60
57 55
25 50 75 100 125 150 175 200 225 250 275 0 0.2 0.4 0.6 0.8 1 1.2
OSR VPP (V) D002
D001

A. fSD24 = 1.024 MHz SD24REFS = 1 SD24GAINx = 1 A. fSD24 = 1.024 MHz SD24REFS = 1

OSR = 256 SD24GAINx = 1

Figure 8-8. SINAD vs OSR
Figure 8-9. SINAD vs VPP

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8.7.8 eUSCI
8.7.8.1 eUSCI (UART Mode) Clock Frequency
PARAMETER TEST CONDITIONS MIN MAX UNIT
Internal: SMCLK or ACLK,
feUSCI eUSCI input clock frequency External: UCLK fSYSTEM MHz
Duty cycle = 50% ±10%
BITCLK clock frequency
fBITCLK 4 MHz
(equals baud rate in MBaud)

8.7.8.2 eUSCI (UART Mode) Deglitch Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
UCGLITx = 0 8 15 20
UCGLITx = 1 30 50 60
tt UART receive deglitch time(1) 2.2 V, 3 V ns
UCGLITx = 2 50 70 100
UCGLITx = 3 70 100 150

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.

8.7.8.3 eUSCI (SPI Master Mode) Clock Frequency

PARAMETER TEST CONDITIONS MIN MAX UNIT
Internal: SMCLK or ACLK,
feUSCI eUSCI input clock frequency fSYSTEM MHz
Duty cycle = 50% ±10%

8.7.8.4 eUSCI (SPI Master Mode) Timing

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
tSTE,LEAD STE lead time, STE active to clock UCSTEM = 1, UCMODEx = 01 or 10 2.2 V, 3 V 150 ns
tSTE,LAG STE lag time, Last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10 2.2 V, 3 V 200 ns

STE access time, STE active to SIMO 2.2 V 40

tSTE,ACC UCSTEM = 0, UCMODEx = 01 or 10 ns
data out 3V 30

STE disable time, STE inactive to SIMO 2.2 V 40

tSTE,DIS UCSTEM = 0, UCMODEx = 01 or 10 ns
high impedance 3V 30
2.2 V 50
tSU,MI SOMI input data setup time ns
3V 30
tHD,MI SOMI input data hold time 2.2 V, 3 V 0 ns
2.2 V 7
tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid, CL = 20 pF ns
3V 5
tHD,MO SIMO output data hold time(3) CL = 20 pF 2.2 V, 3 V 0 ns

(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))

For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 8-10 and Figure 8-11.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 8-10 and Figure 8-11.

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UCMODEx = 01
STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0

UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH
tSU,MI
tHD,MI

SOMI

tHD,MO
tSTE,ACC tVALID,MO tSTE,DIS

SIMO

Figure 8-10. SPI Master Mode, CKPH = 0

UCMODEx = 01

STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0

UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH
tHD,MI
tSU,MI

SOMI

tHD,MO
tSTE,ACC tVALID,MO tSTE,DIS

SIMO

Figure 8-11. SPI Master Mode, CKPH = 1

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8.7.8.5 eUSCI (SPI Slave Mode) Timing

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
tSTE,LEAD STE lead time, STE active to clock 2.2 V, 3 V 3 ns
tSTE,LAG STE lag time, Last clock to STE inactive 2.2 V, 3 V 0 ns
2.2 V 35
tSTE,ACC STE access time, STE active to SOMI data out ns
3V 25
STE disable time, STE inactive to SOMI high
tSTE,DIS 2.2 V, 3 V 35 ns
impedance
tSU,SI SIMO input data setup time 2.2 V, 3 V 1 ns
tHD,SI SIMO input data hold time 2.2 V, 3 V 5 ns

UCLK edge to SOMI valid, 2.2 V 35

tVALID,SO SOMI output data valid time(2) ns
CL = 20 pF 3V 25
2.2 V 35
tHD,SO SOMI output data hold time(3) CL = 20 pF ns
3V 25

(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))

For the master parameters tSU,MI(Master) and tVALID,MO(Master), refer to the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 8-12 and Figure 8-13.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in Figure
8-12 and Figure 8-13.

UCMODEx = 01
STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0
UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH tSU,SI

tHD,SI

SIMO

tHD,SO
tSTE,ACC tVALID,SO tSTE,DIS

SOMI

Figure 8-12. SPI Slave Mode, CKPH = 0

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UCMODEx = 01
STE tSTE,LEAD tSTE,LAG

UCMODEx = 10

1/fUCxCLK

CKPL = 0
UCLK
CKPL = 1

tLOW/HIGH tLOW/HIGH
tHD,SI
tSU,SI
SIMO

tHD,SO
tSTE,ACC tVALID,SO tSTE,DIS

SOMI

Figure 8-13. SPI Slave Mode, CKPH = 1

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8.7.8.6 eUSCI (I2C Mode) Timing

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 8-14)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK or ACLK,
feUSCI eUSCI input clock frequency External: UCLK, fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL SCL clock frequency 2.2 V, 3 V 0 400 kHz
fSCL = 100 kHz 4.8
tHD,STA Hold time (repeated) START 2.2 V, 3 V µs
fSCL > 100 kHz 1.2
fSCL = 100 kHz 4.9
tSU,STA Setup time for a repeated START 2.2 V, 3 V µs
fSCL > 100 kHz 1.26
tHD,DAT Data hold time 2.2 V, 3 V 0.12 µs
fSCL = 100 kHz 4.7
tSU,DAT Data setup time 2.2 V, 3 V µs
fSCL > 100 kHz 1.08
fSCL = 100 kHz 4.9
tSU,STO Setup time for STOP 2.2 V, 3 V µs
fSCL > 100 kHz 1.18
UCGLITx = 0 75 110 160

Pulse duration of spikes suppressed UCGLITx = 1 35 50 80

tSP 2.2 V, 3 V ns
by input filter UCGLITx = 2 15 25 40
UCGLITx = 3 10 15 20
UCCLTOx = 1 33
tTIMEOUT Clock low timeout UCCLTOx = 2 2.2 V, 3 V 37 ms
UCCLTOx = 3 41

tHD,STA tSU,STA tHD,STA tBUF

SDA

tLOW tHIGH tSP

SCL

tSU,DAT tSU,STO
tHD,DAT

Figure 8-14. I2C Mode Timing

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8.7.9 Timer_A
8.7.9.1 Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Internal: SMCLK
fTA Timer_A input clock frequency 3.0 V 16.384 MHz
External: TACLK
All capture inputs, Minimum pulse
tTA,cap Timer_A capture timing 3.0 V 20 ns
duration required for capture

8.7.10 Flash
8.7.10.1 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST
VCC MIN TYP MAX UNIT
CONDITIONS
VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V
fFTG Flash timing generator frequency 257 476 kHz
IPGM Supply current from VCC during program 2.2 V, 3.6 V 8 mA
IERASE Supply current from VCC during erase 2.2 V, 3.6 V 13 mA
tCPT Cumulative program time(1) 2.2 V, 3.6 V 8 ms
Program and erase endurance 20000 cycles
tRetention Data retention duration TJ = 25°C 100 years
tWord Word or byte program time (2) 25
tBlock, 0 Block program time for first byte or word (2) 20
Block program time for each additional byte or (2)
tBlock, 1-63 11
word tFTG
tBlock, End Block program end-sequence wait time (2) 6
tMass Erase Mass erase time (2) 10593
tSeg Erase Segment erase time (2) 9628

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word-write mode, individual byte-write mode, and block-write mode.
(2) These values are hardwired into the state machine of the flash controller (tFTG = 1/fFTG).

8.7.11 Emulation and Debug

8.7.11.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER VCC MIN TYP MAX UNIT
fSBW Spy-Bi-Wire input frequency 3.0 V 0 20 MHz
tSBW,Low Spy-Bi-Wire low clock pulse duration 3.0 V 0.025 15 μs
tSBW, En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1) 3.0 V 1 μs
tSBW,Rst Spy-Bi-Wire return to normal operation time 3.0 V 15 100 μs
fTCK TCK input frequency, 4-wire JTAG(2) 3.0 V 0 10 MHz
Rinternal Internal pulldown resistance on TEST 3.0 V 45 60 80 kΩ

(1) Tools that access the Spy-Bi-Wire interface must wait for the minimum tSBW,En time after pulling the TEST/SBWTCK pin high before
applying the first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.

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9 Detailed Description
9.1 Overview
The MSP430i204x, MSP430i203x, MSP430i202x devices consist of a powerful 16-bit RISC CPU, a DCO-based
clock system that generates system clocks, a power-management module (PMM) with built-in voltage reference
and voltage monitor, two to four 24-bit sigma-delta analog-to-digital converters (ADCs), a temperature sensor, a
16-bit hardware multiplier, two 16-bit timers, one eUSCI-A module and one eUSCI-B module, a watchdog timer
(WDT), and up to 16 I/O pins.
9.2 Functional Block Diagrams
Figure 9-1 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the RHB package.
ROSC VCC DVSS AVSS VCORE RST/NMI P1.x P2.x
8 8

ACLK
Clock TA0 TA1 Port P1 Port P2
System Flash RAM
SMCLK Timer_A Timer_A 8 I/Os, 8 I/Os,
32KB 2KB
3 CC 3 CC Interrupt Interrupt
16KB 1KB
MCLK Registers Registers capability capability

16.384-MHz MAB
CPU
with 16 MDB
registers

Figure 9-1. Functional Block Diagram – RHB Package – MSP430i2041, MSP430i2040

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Figure 9-2 shows the functional block diagram for the MSP430i2041 and MSP430i2040 in the PW package.
ROSC VCC DVSS AVSS VCORE RST/NMI P1.x P2.x
8 4

ACLK
Clock
TA0 TA1 Port P1 Port P2
System Flash RAM
Timer_A Timer_A 8 I/Os, 4 I/Os,
SMCLK 32KB 2KB 3 CC 3 CC Interrupt Interrupt
16KB 1KB Registers Registers capability capability
MCLK

16.384-MHz MAB
CPU

with 16 MDB
registers

Emulation
2BP
Hardware
Power SD24
Multiplier
JTAG Management eUSCI_A0
Watchdog (16x16) eUSCI_B0
Interface 4
Sigma-Delta WDT
LDO UART,
MPY, 2
SPI, I C
REF Analog-to- IrDA, SPI
15 or 16 bit MPYS,
VMON Digital
Spy-Bi- MAC,
Brownout Converters
Wire MACS

Figure 9-2. Functional Block Diagram – PW Package – MSP430i2041, MSP430i2040

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 33

Figure 9-3 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the RHB package.
ROSC VCC DVSS AVSS VCORE RST/NMI P1.x P2.x
8 8

ACLK
Clock
TA0 TA1 Port P1 Port P2
System Flash RAM
Timer_A Timer_A 8 I/Os, 8 I/Os,
SMCLK 32KB 2KB 3 CC 3 CC Interrupt Interrupt
16KB 1KB Registers Registers capability capability
MCLK

16.384-MHz MAB
CPU

with 16 MDB
registers

Emulation
2BP
Hardware
Power SD24
Multiplier
JTAG Management eUSCI_A0
Watchdog (16x16) eUSCI_B0
Interface 3
Sigma-Delta WDT
LDO UART,
MPY, 2
SPI, I C
REF Analog-to- IrDA, SPI
15 or 16 bit MPYS,
VMON Digital
Spy-Bi- MAC,
Brownout Converters
Wire MACS

Figure 9-3. Functional Block Diagram – RHB Package – MSP430i2031, MSP430i2030

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Figure 9-4 shows the functional block diagram for the MSP430i2031 and MSP430i2030 in the PW package.
ROSC VCC DVSS AVSS VCORE RST/NMI P1.x P2.x
8 4

ACLK
Clock
TA0 TA1 Port P1 Port P2
System Flash RAM
Timer_A Timer_A 8 I/Os, 4 I/Os,
SMCLK 32KB 2KB 3 CC 3 CC Interrupt Interrupt
16KB 1KB Registers Registers capability capability
MCLK

16.384-MHz MAB
CPU

with 16 MDB
registers

Figure 9-4. Functional Block Diagram – PW Package – MSP430i2031, MSP430i2030

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35

Figure 9-5 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the RHB package.
ROSC VCC DVSS AVSS VCORE RST/NMI P1.x P2.x
8 8

ACLK
Clock
TA0 TA1 Port P1 Port P2
System Flash RAM
Timer_A Timer_A 8 I/Os, 8 I/Os,
SMCLK 32KB 2KB 3 CC 3 CC Interrupt Interrupt
16KB 1KB Registers Registers capability capability
MCLK

16.384-MHz MAB
CPU

with 16 MDB
registers

Emulation
2BP
Hardware
Power SD24
Multiplier
JTAG Management eUSCI_A0
Watchdog (16x16) eUSCI_B0
Interface 2
Sigma-Delta WDT
LDO UART,
MPY, 2
SPI, I C
REF Analog-to- IrDA, SPI
15 or 16 bit MPYS,
VMON Digital
Spy-Bi- MAC,
Brownout Converters
Wire MACS

Figure 9-5. Functional Block Diagram – RHB Package – MSP430i2021, MSP430i2020

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Figure 9-6 shows the functional block diagram for the MSP430i2021 and MSP430i2020 in the PW package.
ROSC VCC DVSS AVSS VCORE RST/NMI P1.x P2.x
8 4

ACLK
Clock
TA0 TA1 Port P1 Port P2
System Flash RAM
Timer_A Timer_A 8 I/Os, 4 I/Os,
SMCLK 32KB 2KB 3 CC 3 CC Interrupt Interrupt
16KB 1KB Registers Registers capability capability
MCLK

16.384-MHz MAB
CPU

with 16 MDB
registers

Figure 9-6. Functional Block Diagram – PW Package – MSP430i2021, MSP430i2020

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9.3 CPU
The MSP430i CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant
generator respectively. The remaining registers are general-purpose registers (see Figure 9-7).
Peripherals are connected to the CPU using data, address, and control buses and can be handled with all
instructions.

Program Counter PC/R0

Stack Pointer SP/R1

Status Register SR/CG1/R2

Constant Generator CG2/R3

General-Purpose Register R4

General-Purpose Register R5

General-Purpose Register R6

General-Purpose Register R7

General-Purpose Register R8

General-Purpose Register R9

General-Purpose Register R10

General-Purpose Register R11

General-Purpose Register R12

General-Purpose Register R13

General-Purpose Register R14

General-Purpose Register R15

Figure 9-7. CPU Registers

CAUTION
The CPU will lock up if the device enters a low-power mode (CPU off) within 64 cycles after reset.

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9.4 Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can
operate on word and byte data. Table 9-1 gives examples of the three types of instruction formats; Table 9-2 lists
the address modes.
Table 9-1. Instruction Word Formats
INSTRUCTION FORMAT EXAMPLE OPERATION
Dual operands, source and destination ADD R4,R5 R4 + R5 → R5
Single operands, destination only CALL R8 PC → (TOS), R8 → PC
Relative jump, unconditional or conditional JNE Jump-on-equal bit = 0

Table 9-2. Address Mode Descriptions

ADDRESS MODE S (1) D (2) SYNTAX EXAMPLE OPERATION
Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) → M(TONI)
Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) → M(TCDAT)
Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)
M(R10) → R11
Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11
R10 + 2 → R10
Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI)

(1) S = source
(2) D = destination

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9.5 Operating Modes

MSP430i204x, MSP430i203x, MSP430i202x devices have one active mode and four software-selectable low-
power modes. An interrupt event can wake up the device from the low-power modes LPM0 to LPM4, service the
request, and restore back to the low-power mode on return from the interrupt program.
The following five operating modes can be configured by software:
• Active mode (AM)
– All clocks are active.
• Low-power mode 0 or low-power mode 1 (LPM0 = LPM1)
– CPU is disabled
– Internal regulator remains enabled
– DCO remains enabled
– MCLK is disabled
– ACLK and SMCLK remain active
• Low-power mode 2 or low-power mode 3 (LPM2 = LPM3)
– CPU is disabled
– Internal regulator remains enabled
– DCO remains enabled
– MCLK and SMCLK are disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– Internal regulator remains enabled
– DCO is disabled
– MCLK, SMCLK, and ACLK are disabled
• Low-power mode 4.5 (LPM4.5)
– Internal regulator is disabled
– No RAM retention
– I/O pad state retention
– Wake from RST/NMI, ports pins P2.1 or P2.2

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9.6 Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are in the address range 0FFFFh to 0FFE0h. The vector
contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the
CPU goes into LPM4 immediately after power up.
Table 9-3. Interrupt Vector Addresses
INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY
Power up BORIFG
External reset RSTIFG
Watchdog WDTIFG Reset 0FFFEh 15, highest
Flash key violation KEYV
PC out-of-range (1) (2)

NMI NMIIFG (Non)maskable,

Oscillator fault OFIFG (Non)maskable, 0FFFCh 14
Flash memory access violation ACCVIFG (2) (4) (Non)maskable
Timer TA1 TA1CCR0 CCIFG (3) Maskable 0FFFAh 13
TA1CCR1 CCIFG,
Timer TA1 TA1CCR2 CCIFG, Maskable 0FFF8h 12
TA1CTL TAIFG (2) (3)
Voltage monitor VMONIFG Maskable 0FFF6h 11
Watchdog timer WDTIFG Maskable 0FFF4h 10
eUSCI_A0 receive or transmit UCA0RXIFG, UCA0TXIFG Maskable 0FFF2h 9
eUSCI_B0 receive or transmit UCB0RXIFG, UCB0TXIFG Maskable 0FFF0h 8
SD24CCTLx SD24OVIFG,
SD24 Maskable 0FFEEh 7
SD24CCTLx SD24IFG(2) (3)
Timer TA0 TA0CCR0 CCIFG (3) Maskable 0FFECh 6
TA0CCR1 CCIFG,
Timer TA0 TA0CCR2 CCIFG, Maskable 0FFEAh 5
TA0CTL TAIFG (2) (3)
I/O port P1 P1IFG.0 to P1IFG.7 (2) (3) Maskable 0FFE8h 4
0FFE6h 3
0FFE4h 2
I/O port P2 P2IFG.0 to P2IFG.7 (2) (3) Maskable 0FFE2h 1
0FFE0h 0, lowest

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from
within unused address range.
(2) Multiple source flags
(3) Interrupt flags are in the module.
(4) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

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9.7 Special Function Registers

Some interrupt enable and interrupt flag bits are collected into the lowest address space. Special function
register bits not allocated to a functional purpose are not physically present in the device. Simple software
access is provided with this arrangement.
Legend
rw Bit can be read and written.
rw-0, rw-1 Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-(1) Bit can be read and written. It is Reset or Set by POR.
rw-[0], rw-[1] Bit can be read and written. It is Reset or Set by BOR.
SFR bit is not present in device.

Table 9-4. Interrupt Enable 1 (Address = 00h)

7 6 5 4 3 2 1 0
ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval timer
mode.
OFIE Oscillator fault interrupt enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable

Table 9-5. Interrupt Flag Register 1 (Address = 02h)

7 6 5 4 3 2 1 0
NMIIFG RSTIFG BORIFG OFIFG WDTIFG
rw-0 rw-[0] rw-[1] rw-0 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG Flag set on oscillator fault. This flag can be cleared by software when the oscillator runs free of fault.
BORIFG Brown out reset flag. This bit is set after VCC power up and can be cleared by software.
RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power up.
NMIIFG Set by the RST/NMI pin in NMI configuration.

9.8 Flash Memory

The flash memory can be programmed through the Spy-Bi-Wire or JTAG port, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory:
• Flash memory has n segments of main memory and one segment of information memory.
• Segment size is 1KB for both main memory and information memory.
• Segments 0 to n in main memory can be erased in one step, or each segment may be individually erased.
• Information memory segment can be erased separately or as a group with main memory segments 0 to n.
• Information memory segment contains calibration data. After reset, information memory segment is protected
against programming and erasing. It can be unlocked but care should be taken not to erase this segment if
the device-specific calibration data is required.

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9.9 JTAG Operation

9.9.1 JTAG Standard Interface
The MSP430i family supports the standard JTAG interface which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430i
development tools and device programmers. Table 9-6 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide.
Table 9-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
P1.0/UCA0STE/MCLK/TCK IN JTAG clock input
P1.1/UCA0CLK/SMCLK/TMS IN JTAG state control
P1.2/UCA0RXD/UCA0SOMI/ACLK/TDI/TCLK IN JTAG data input/TCLK input
P1.3/UCA0TXD/UCA0SIMO/TA0CLK/TDO/TDI OUT JTAG data output
TEST/SBWTCK IN Enable JTAG pins
RST/NMI/SBWTDIO IN External reset
VCC Power supply
DVSS Ground supply

9.9.2 Spy-Bi-Wire Interface

In addition to the standard JTAG interface, the MSP430i family supports the 2-wire Spy-Bi-Wire interface.
Spy-Bi-Wire can be used to interface with MSP430i development tools and device programmers. Table 9-7 lists
the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide.
Table 9-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL DIRECTION FUNCTION
TEST/SBWTCK IN Spy-Bi-Wire clock input
RST/NMI/SBWTDIO IN, OUT Spy-Bi-Wire data input/output
VCC Power supply
DVSS Ground supply

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9.9.3 JTAG Disable Register

The SYSJTAGDIS register can disable the JTAG port to provide code protection and device security. JTAG
is disabled when software writes the value 0xA5A5 to this register within 64 MCLK clock cycles after a BOR
or POR reset; otherwise, the JTAG port is enabled. Any writes to this register after the first 64 MCLK clock
cycles are ignored. Reads from this register at any time return the JTAG enable or disable status. The value
0xA5A5 indicates that JTAG is disabled, and 0x9696 indicates that JTAG is enabled. The SYSJTAGDIS register
is mapped to address 01FEh.

Note
Application programming the device to any of the low power modes within first 64 MCLK clock cycles
after a BOR or POR reset will lock the device for any JTAG/SBW access.

Table 9-8. SYSJTAGDIS Register

15 14 13 12 11 10 9 8
JTAGKEY
rw-[1] rw-[0] rw-[1] rw-[0] rw-[0] rw-[1] rw-[0] rw-[1]

7 6 5 4 3 2 1 0
JTAGKEY
rw-[1] rw-[0] rw-[1] rw-[0] rw-[0] rw-[1] rw-[0] rw-[1]

JTAGKEY 0xA5A5 indicates JTAG is disabled and 0x9696 indicates JTAG is enabled.

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9.10 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430i2xx Family User's Guide.
9.10.1 Clock System
The clock system consists of a fixed 16.384-MHz frequency internal DCO. The DCO can operate in internal
resistor mode or external resistor mode. The DCO clock accuracy is higher when operating in external resistor
mode especially upon variation in operating temperature. This feature can be useful in applications like utility
metering in which accurate clock is necessary under varying operating temperature. When external resistor
mode is selected by application, the resistor of recommended value must be connected to ROSC pin of the
device. Refer to Section 8.7.2.1 for the recommended value of the resistor at the ROSC pin. TI recommends
connecting the ROSC pin to AVSS when operating the DCO in internal resistor mode. When a resistor fault
is detected in the external resistor mode, the DCO automatically switches to the internal resistor mode as a
fail-safe mechanism to keep the system clocks active.
The DCO can be completely bypassed and the system clocks can be sourced by an external digital clock. The
clock system generates MCLK, SMCLK, and ACLK. MCLK is used by the CPU, while SMCLK and ACLK are
used by the peripheral modules. There are programmable clock dividers for MCLK and SMCLK. ACLK runs at a
fixed 32-kHz frequency. The clock system supports active mode and four low-power modes.
9.10.2 Power-Management Module (PMM)
The PMM consists of voltage regulator that generates 1.8-V regulated core voltage. There is a brownout reset
(BOR) circuit on the high-voltage domain, and a supply voltage supervisor (SVS) module on the low-voltage
domain. The BOR and SVS provide the proper internal reset signal to the device during power on and power off.
A built-in voltage reference is used by submodules of the PMM and by the analog modules on the device. A
temperature sensor is also available in the built-in voltage reference.
The voltage monitor (VMON) on the high-voltage domain can monitor external voltage on the VMONIN pin
against the internal reference voltage or by comparing the on-chip VCC to one of three programmable threshold
voltages. During the LPM4.5 mode, the reference, voltage regulator, temperature sensor, and voltage monitor
are turned off, and only the high-side brownout circuit is active.

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9.10.3 Digital I/O

Two 8-bit I/O ports (P1 and P2) are implemented on the MSP430i204x, MSP430i203x, MSP430i202x devices.
On 32-pin RHB devices, ports P1 and P2 are complete, and 16 I/Os are available. On 28-pin PW devices, port
P2 is reduced to 4 bits, and 12 I/Os are available. On 28-pin PW devices, the unavailable pins (P2.4 to P2.7)
must be programmed to port function, output direction, and be driven with value 0.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt condition is possible.
• Edge-selectable interrupt input capability for all 8 bits of port P1 and P2
• LPM4.5 wake-up capability for Port pins P2.1 and P2.2
• Read and write access to port-control registers is supported by all instructions.
9.10.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be disabled or configured as an interval timer and can generate interrupts at
selected time intervals.
9.10.5 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA0 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 9-9). TA0 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-9. TA0 Signal Connections
DEVICE INPUT MODULE INPUT MODULE DEVICE OUTPUT OUTPUT PORT
INPUT PORT PIN MODULE BLOCK
SIGNAL SIGNAL OUTPUT SIGNAL SIGNAL PIN
P1.3 TA0CLK TACLK
ACLK (internal) ACLK
Timer NA NA
SMCLK (internal) SMCLK
P1.3 TA0CLK INCLK
P1.4 TA0.0 CCI0A P1.4
P2.5 TA0.0 CCI0B P2.5
CCR0 TA0 TA0.0
DVSS GND
VCC VCC
P1.5 TA0.1 CCI1A P1.5
ACLK (internal) CCI1B P2.6
CCR1 TA1 TA0.1
DVSS GND
VCC VCC
P1.6 TA0.2 CCI2A P1.6
TA1 CCR2 output TA0.2
CCI2B P2.7
(internal) CCR2 TA2
DVSS GND
TA1 CCI2B input
VCC VCC

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9.10.6 Timer TA1

Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support
multiple capture/compares, PWM outputs, and interval timing (see Table 9-10). TA1 also has extensive interrupt
capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/
compare registers.
Table 9-10. TA1 Signal Connections
DEVICE INPUT MODULE INPUT MODULE DEVICE OUTPUT OUTPUT PORT
INPUT PORT PIN MODULE BLOCK
SIGNAL SIGNAL OUTPUT SIGNAL SIGNAL PIN
P1.7 TA1CLK TACLK
ACLK (internal) ACLK
Timer NA NA
SMCLK (internal) SMCLK
P1.7 TA1CLK INCLK
P2.0 TA1.0 CCI0A P2.0
P2.4 TA1.0 CCI0B P2.4
CCR0 TA0 TA1.0
DVSS GND
VCC VCC
P2.1 TA1.1 CCI1A P2.1
ACLK (internal) CCI1B
CCR1 TA1 TA1.1
DVSS GND
VCC VCC
P2.2 TA1.2 CCI2A P2.2
TA0 CCR2 output TA1.2
CCI2B
(internal) CCR2 TA2
DVSS GND
TA0 CCI2B input
VCC VCC

9.10.7 Enhanced Universal Serial Communication Interface (eUSCI)

The eUSCI module is used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocols
such as UART, enhanced UART with automatic baudrate detection, and IrDA.
The eUSCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3-pin or 4-pin) and I2C.
One eUSCI_A and one eUSCI_B module are implemented on MSP430i20xx devices.
9.10.8 Hardware Multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16-bit,
16×8-bit, 8×16-bit, and 8×8-bit operations. The module supports signed and unsigned multiplication as well
as signed and unsigned multiply-and-accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.

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9.10.9 SD24
There are up to four independent 24-bit sigma-delta ADCs. Each converter is designed with a fully differential
analog input pair and programmable gain amplifier input stage. Also the converters are based on second-order
oversampling sigma-delta modulators and digital decimation filters. The decimation filters are comb-type filters
with selectable oversampling ratios of up to 256.
The SD24 converters can operate with internal reference (SD24REFS = 1) or with external reference
(SD24REFS = 0). When SD24 operates with internal reference the VREF pin must not be loaded externally.
Connect only the recommended capacitor value (CVREF) at VREF pin to AVSS (see Section 8.7.7.2).

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9.11 Input/Output Diagrams

9.11.1 Port P1, P1.0 to P1.3, Input/Output With Schmitt Trigger
Figure 9-8 shows the pin diagram. Table 9-11 summarizes the selection of the pin function.
JTAG enable
From JTAG
From JTAG

Direction Pad Logic

PyDIR.x 00 0: Input
1 1: Output
From module 1 01
0
10
11

PyOUT.x 00
From module 1 01 1
From module 2 10 0
DVSS 11 Py.x/Mod1/Mod2/JTAG

PySEL1.x
PySEL0.x
PyIN.x

To modules D
and JTAG

Functional representation only.

Figure 9-8. Py.x/Mod1/Mod2/JTAG Pin Diagram

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Table 9-11. Port P1 (P1.0 to P1.3) Pin Functions

CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL1.x P1SEL0.x JTAG Enable
P1.0/UCA0STE/MCLK/TCK 0 P1.0 (I/O)(2) I: 0; O: 1 0 0 0
UCA0STE X(3) 0 1 0
N/A 0
1 0 0
MCLK 1
N/A 0
1 1 0
DVSS 1
TCK(4) X X X 1
P1.1/UCA0CLK/SMCLK/TMS 1 P1.1 (I/O)(2) I: 0; O: 1 0 0 0
UCA0CLK X(3) 0 1 0
N/A 0
1 0 0
SMCLK 1
N/A 0
1 1 0
DVSS 1
TMS(4) X X X 1
P1.2/UCA0RXD/UCA0SOMI/ 2 P1.2 (I/O)(2) I: 0; O: 1 0 0 0
ACLK/TDI/TCLK
UCA0RXD/UCA0SOMI X(3) 0 1 0
N/A 0
1 0 0
ACLK 1
N/A 0
1 1 0
DVSS 1
TDI/TCLK(4) X X X 1
P1.3/UCA0TXD/UCA0SIMO/ 3 P1.3 (I/O)(2) I: 0; O: 1 0 0 0
TA0CLK/TDO/TDI
UCA0TXD/UCA0SIMO X(3) 0 1 0
TA0CLK 0
1 0 0
DVSS 1
N/A 0
1 1 0
DVSS 1
TDO/TDI(4) X X X 1

(1) X = Don't care

(2) Default condition
(3) Direction is controlled by eUSCI_A0 module.
(4) The pin direction is controlled by the JTAG module. The JTAG mode selection is made through the Spy-Bi-Wire 4-wire entry sequence.
Neither P1SEL0.x and P1SEL1.x nor P1DIR.x have an effect in these cases.

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9.11.2 Port P1, P1.4 to P1.7, Input/Output With Schmitt Trigger

Figure 9-9 shows the pin diagram. Table 9-12 summarizes the selection of the pin function.

Pad Logic
Direction
PyDIR.x 00 0: Input
1: Output
From module 1 01
10
11

PyOUT.x 00
From module 1 01
From module 2 10
DVSS 11 Py.x/Mod1/Mod2

PySEL1.x
PySEL0.x
PyIN.x

To module D

Functional representation only.

Figure 9-9. Py.x/Mod1/Mod2 Pin Schematic

Table 9-12. Port P1 (P1.4 to P1.7) Pin Functions

CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x) x FUNCTION
P1DIR.x P1SEL1.x P1SEL0.x
P1.4/UCB0STE/TA0.0 4 P1.4 (I/O) I: 0; O: 1 0 0
UCB0STE X(2) 0 1
TA0.CCI0A 0
1 0
TA0.0 1
N/A 0
1 1
DVSS 1
P1.5/UCB0CLK/TA0.1 5 P1.5 (I/O) I: 0; O: 1 0 0
UCB0CLK X(2) 0 1
TA0.CCI1A 0
1 0
TA0.1 1
N/A 0
1 1
DVSS 1
P1.6/UCB0SCL/UCB0SOMI/ 6 P1.6 (I/O) I: 0; O: 1 0 0
TA0.2
UCB0SCL/UCB0SOMI X(2) 0 1
TA0.CCI2A 0
1 0
TA0.2 1
N/A 0
1 1
DVSS 1
P1.7/UCB0SDA/UCB0SIMO/ 7 P1.7 (I/O) I: 0; O: 1 0 0
TA1CLK
UCB0SDA/UCB0SIMO X(2) 0 1
TA1CLK 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1

(1) X = Don't care

(2) Direction is controlled by eUSCI_B0 module.

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9.11.3 Port P2, P2.0 to P2.2 and P2.4 to P2.7, Input/Output With Schmitt Trigger
Figure 9-10 shows the pin diagram. Table 9-13 summarizes the selection of the pin function.

Pad Logic
Direction
PyDIR.x 00 0: Input
1: Output
01
10
11

PyOUT.x 00
From module 01
DVSS 10
DVSS 11 Py.x/Mod1/Mod2

PySEL1.x
PySEL0.x
PyIN.x

To module D

Functional representation only.

Figure 9-10. Py.x/Mod1/Mod2 Pin Schematic

Table 9-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (P2.x) x FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
P2.0/TA1.0/CLKIN 0 P2.0 (I/O) I: 0; O: 1 0 0
TA1.CCI0A 0
0 1
TA1.0 1
CLKIN (DCO bypass clock) 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1
P2.1/TA1.1 1 P2.1 (I/O) I: 0; O: 1 0 0
TA1.CCI1A 0
0 1
TA1.1 1
N/A 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1

Table 9-13. Port P2 (P2.0 to P2.2 and P2.4 to P2.7) Pin Functions (continued)
CONTROL BITS OR SIGNALS
PIN NAME (P2.x) x FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
P2.2/TA1.2 2 P2.2 (I/O) I: 0; O: 1 0 0
TA1.CCI2A 0
0 1
TA1.2 1
N/A 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1
P2.4/TA1.0(1) 4 P2.4 (I/O) I: 0; O: 1 0 0
TA1.CCI0B 0
0 1
TA1.0 1
N/A 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1
P2.5/TA0.0(1) 5 P2.5 (I/O) I: 0; O: 1 0 0
TA0.CCI0B 0
0 1
TA0.0 1
N/A 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1
P2.6/TA0.1(1) 6 P2.6 (I/O) I: 0; O: 1 0 0
N/A 0
0 1
TA0.1 1
N/A 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1
P2.7/TA0.2(1) 7 P2.7 (I/O) I: 0; O: 1 0 0
N/A 0
0 1
TA0.2 1
N/A 0
1 0
DVSS 1
N/A 0
1 1
DVSS 1

(1) Available only on 32-pin RHB devices.

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9.11.4 Port P2, P2.3, Input/Output With Schmitt Trigger

Figure 9-11 shows the pin diagram. Table 9-14 summarizes the selection of the pin function.

Pad Logic

To VMON

From VMON

Direction
PyDIR.x 00 0: Input
01 1: Output

10
11

PyOUT.x 00
DVSS 01
DVSS 10
DVSS 11 Py.x/VMONIN

PySEL1.x
PySEL0.x
PyIN.x

EN Bus
Keeper
No connect D

Functional representation only.

Figure 9-11. Py.x/VMONIN Pin Schematic

Table 9-14. Port P2 (P2.3) Pin Functions

CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x) x FUNCTION
P2DIR.x P2SEL1.x P2SEL0.x
P2.3/VMONIN 3 P2.3 (I/O) I: 0; O: 1 0 0
N/A 0
0 1
DVSS 1
N/A 0
1 0
DVSS 1
VMONIN(2) X 1 1

(1) X = Don't care

(2) Setting P2SEL1.3 and P2SEL0.3 disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying voltage at VMONIN pin. To enable the VMONIN function, VMONLVLx bits must be set to 3'b111 in the VMONCTL register.

9.12 Device Descriptor

Table 9-15 lists the contents of the tag-length-value (TLV) device descriptor structure for the MSP430i204x,
MSP430i203x, and MSP430i202x devices.
Table 9-15. MSP430i204x, MSP430i203x, MSP430i202x TLV
SIZE
DESCRIPTION ADDRESS VALUE
(BYTES)
Checksum TLV checksum 013C0h 2 Per unit
Die Record Tag 013C2h 1 01h
Die Record Length 013C3h 1 0Ah
Lot/Wafer ID 013C4h 4 Per unit
Die Record
Die X position 013C8h 2 Per unit
Die Y position 013CAh 2 Per unit
Test results 013CCh 2 Per unit
REF Calibration Tag 013CEh 1 02h
REF Calibration Length 013CFh 1 02h
REF Calibration
Calibrate REF – for REFCAL1 register 013D0h 1 Per unit
Calibrate REF – for REFCAL0 register 013D1h 1 Per unit
DCO Calibration Tag 013D2h 1 03h
DCO Calibration Length 013D3h 1 04h
Calibrate DCO – for CSIRFCAL register 013D4h 1 Per unit
DCO Calibration
Calibrate DCO – for CSIRTCAL register 013D5h 1 Per unit
Calibrate DCO – for CSERFCAL register 013D6h 1 Per unit
Calibrate DCO – for CSERTCAL register 013D7h 1 Per unit
SD24 Calibration Tag 013D8h 1 04h
SD24 Calibration Length 013D9h 1 02h
SD24 Calibration
Calibrate SD24 – for SD24TRIM register 013DAh 1 Per unit
Empty 013DBh 1 FFh
Tag Empty 013DCh 1 FEh
Empty Empty Length 013DDh 1 22h
Empty 013DEh 34 FFh

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9.13 Memory
Table 9-16 lists the memory organization for the specified devices.
Table 9-16. Memory Organization
MSP430i2040 MSP430i2041
MSP430i2030 MSP430i2031
MSP430i2020 MSP430i2021
Memory Size 16KB 32KB
Main: interrupt vector Flash 0xFFFF to 0xFFE0 0xFFFF to 0xFFE0
Main: code memory Flash 0xFFFF to 0xC000 0xFFFF to 0x8000
Size 1KB 1KB
Information memory
Flash 0x13FFh to 0x1000 0x13FFh to 0x1000
Size 1KB 2KB
RAM
Address 0x05FF to 0x0200 0x09FF to 0x0200
16-bit 0x01FF to 0x0100 0x01FF to 0x0100
Peripherals 8-bit 0x00FF to 0x0010 0x00FF to 0x0010
8-bit SFR 0x000F to 0x0000 0x000F to 0x0000

9.13.1 Peripheral File Map

Table 9-17 lists the peripherals that support word access, and Table 9-18 lists the peripherals that support byte
access. Peripherals that support both access types are listed in both tables.
Table 9-17. Peripherals With Word Access
MODULE REGISTER DESCRIPTION ACRONYM ADDRESS
SYS JTAG disable register SYSJTAGDIS 0x01FE
Capture/compare register 2 TA1CCR2 0x0196
Capture/compare register 1 TA1CCR1 0x0194
Capture/compare register 0 TA1CCR0 0x0192
Timer_A register TA1R 0x0190
Timer TA1 Capture/compare control 2 TA1CCTL2 0x0186
Capture/compare control 1 TA1CCTL1 0x0184
Capture/compare control 0 TA1CCTL0 0x0182
Timer_A control TA1CTL 0x0180
Timer_A interrupt vector TA1IV 0x011E
Capture/compare register 2 TA0CCR2 0x0176
Capture/compare register 1 TA0CCR1 0x0174
Capture/compare register 0 TA0CCR0 0x0172
Timer_A register TA0R 0x0170
Timer TA0 Capture/compare control 2 TA0CCTL2 0x0166
Capture/compare control 1 TA0CCTL1 0x0164
Capture/compare control 0 TA0CCTL0 0x0162
Timer_A control TA0CTL 0x0160
Timer_A interrupt vector TA0IV 0x012E

Table 9-17. Peripherals With Word Access (continued)

MODULE REGISTER DESCRIPTION ACRONYM ADDRESS
USCI_A control word 0 UCA0CTLW0 0x0140
USCI _A control word 1 UCA0CTLW1 0x0142
USCI_A baud rate 0 UCA0BR0 0x0146
USCI_A baud rate 1 UCA0BR1 0x0147
USCI_A modulation control UCA0MCTLW 0x0148
USCI_A status UCA0STAT 0x014A
USCI_A receive buffer UCA0RXBUF 0x014C
eUSCI_A0
USCI_A transmit buffer UCA0TXBUF 0x014E
USCI_A LIN control UCA0ABCTL 0x0150
USCI_A IrDA transmit control UCA0IRTCTL 0x0152
USCI_A IrDA receive control UCA0IRRCTL 0x0153
USCI_A interrupt enable UCA0IE 0x015A
USCI_A interrupt flags UCA0IFG 0x015C
USCI_A interrupt vector word UCA0IV 0x015E
USCI_B control word 0 UCB0CTLW0 0x01C0
USCI_B control word 1 UCB0CTLW1 0x01C2
USCI_B bit rate 0 UCB0BR0 0x01C6
USCI_B bit rate 1 UCB0BR1 0x01C7
USCI_B status word UCB0STATW 0x01C8
USCI_B byte counter threshold UCB0TBCNT 0x01CA
USCI_B receive buffer UCB0RXBUF 0x01CC
USCI_B transmit buffer UCB0TXBUF 0x01CE
USCI_B I2C own address 0 UCB0I2COA0 0x01D4
eUSCI_B0
USCI_B I2C own address 1 UCB0I2COA1 0x01D6
USCI_B I2C own address 2 UCB0I2COA2 0x01D8
USCI_B I2C own address 3 UCB0I2COA3 0x01DA
USCI_B received address UCB0ADDRX 0x01DC
USCI_B address mask UCB0ADDMASK 0x01DE
USCI I2C slave address UCB0I2CSA 0x01E0
USCI interrupt enable UCB0IE 0x01EA
USCI interrupt flags UCB0IFG 0x01EC
USCI interrupt vector word UCB0IV 0x01EE
Sum extend SUMEXT 0x013E
Result high word RESHI 0x013C
Result low word RESLO 0x013A
Second operand OP2 0x0138
Hardware Multiplier
Multiply signed + accumulate/operand 1 MACS 0x0136
Multiply + accumulate/operand 1 MAC 0x0134
Multiply signed/operand 1 MPYS 0x0132
Multiply unsigned/operand 1 MPY 0x0130
Flash control 3 FCTL3 0x012C
Flash Memory Flash control 2 FCTL2 0x012A
Flash control 1 FCTL1 0x0128
Watchdog Timer Watchdog/timer control WDTCTL 0x0120

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Table 9-17. Peripherals With Word Access (continued)

MODULE REGISTER DESCRIPTION ACRONYM ADDRESS
SD24 interrupt vector word register SD24IV 0x01F0
Channel 3 conversion memory(1) (2) SD24MEM3 0x0116
Channel 2 conversion memory(2) SD24MEM2 0x0114
Channel 1 conversion memory SD24MEM1 0x0112

SD24 Channel 0 conversion memory SD24MEM0 0x0110

(also see Table 9-18) Channel 3 control(1) (2) SD24CCTL3 0x0108
Channel 2 control(2) SD24CCTL2 0x0106
Channel 1 control SD24CCTL1 0x0104
Channel 0 control SD24CCTL0 0x0102
General Control SD24CTL 0x0100

(1) Not available on MSP430i2031 and MSP430i2030 devices.

(2) Not available on MSP430i2021 and MSP430i2020 devices.

Table 9-18. Peripherals With Byte Access

MODULE REGISTER DESCRIPTION REGISTER NAME ADDRESS
SD24 trim SD24TRIM 0x00BF
Channel 3 preload(1) (2) SD24PRE3 0x00BB
Channel 2 preload(2) SD24PRE2 0x00BA
Channel 1 preload SD24PRE1 0x00B9
SD24
Channel 0 preload SD24PRE0 0x00B8
(also see Table 9-17)
Channel 3 input control(1) (2) SD24INCTL3 0x00B3
Channel 2 input control(2) SD24INCTL2 0x00B2
Channel 1 input control SD24INCTL1 0x00B1
Channel 0 input control SD24INCTL0 0x00B0
Reference calibration 1 REFCAL1 0x0063
Reference calibration 0 REFCAL0 0x0062
PMM
Voltage monitor control VMONCTL 0x0061
LPM4.5 control LPM45CTL 0x0060
Clock system external resistor temperature calibration CSERTCAL 0x0055
Clock system external resistor frequency calibration CSERFCAL 0x0054
Clock system internal resistor temperature calibration CSIRTCAL 0x0053
Clock System
Clock system internal resistor frequency calibration CSIRFCAL 0x0052
Clock system control 1 CSCTL1 0x0051
Clock system control 0 CSCTL0 0x0050
Port P2 interrupt flag P2IFG 0x002D
Port P2 interrupt enable P2IE 0x002B
Port P2 interrupt edge select P2IES 0x0029
Port P2 interrupt vector word P2IV 0x002E
Port P2 Port P2 selection 1 P2SEL1 0x001D
Port P2 selection 0 P2SEL0 0x001B
Port P2 direction P2DIR 0x0015
Port P2 output P2OUT 0x0013
Port P2 input P2IN 0x0011

Table 9-18. Peripherals With Byte Access (continued)

MODULE REGISTER DESCRIPTION REGISTER NAME ADDRESS
Port P1 interrupt flag P1IFG 0x002C
Port P1 interrupt enable P1IE 0x002A
Port P1 interrupt edge select P1IES 0x0028
Port P1 interrupt vector word P1IV 0x001E
Port P1 Port P1 selection 1 P1SEL1 0x001C
Port P1 selection 0 P1SEL0 0x001A
Port P1 direction P1DIR 0x0014
Port P1 output P1OUT 0x0012
Port P1 input P1IN 0x0010
SFR interrupt flag 1 IFG1 0x0002
Special Function
SFR interrupt enable 1 IE1 0x0000

(1) Not available on MSP430i2031 or MSP430i2030 devices.

(2) Not available on MSP430i2021 or MSP430i2020 devices.

9.14 Identification
9.14.1 Device Identification
The device type can be identified from the top-side marking on the device package. See the packaging
information page or the device errata sheets listed in Section 11.4 for help.
9.14.2 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in
the MSP430 Programming With the JTAG Interface.

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10 Applications, Implementation, and Layout

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

The following resources provide application guidelines and best practices when designing with the MSP430i20xx
devices.
Implementation of a One- or Two-Phase Electronic Watt-Hour Meter Using MSP430i20xx application
report
This application report describes the implementation of a low-cost 1- or 2-phase electronic electricity meter that
uses the TI MSP430i20xx metering processor. This application report includes information on metrology software
and hardware procedures for this single-chip implementation.
Single-Phase and DC Embedded Metering Power Using MSP430i2040 application report
This application report describes an EVM that uses the MSP430i2040 microcontroller for embedded metering
(submetering). In this application, the electricity measuring device is embedded in the end application and gives
the user information about the voltage, current, and power consumption of the device. In addition, the EVM can
compensate for line resistance and EMI filter capacitance.
Single Phase and DC Embedded Metering (Server Power Monitor) reference design
This reference design implements a high-accuracy single-phase embedded meter using an MSP430 MCU.
This EVM has built-in support to measure AC voltage, current, active power, reactive power, apparent power,
frequency, power factor, voltage THD, current THD, fundamental voltage, fundamental current, fundamental
power and DC voltage, DC current, DC active power. It can detect the input voltage to work in DC or AC mode.
It can also compensate for the effects of the wire resistance and the EMI filter capacitance so that the reading of
voltage and power matches the reading of an external meter when EMI filter is connected to the input.
Three Output Smart Power Strip reference design
This reference design implements a high-accuracy single-phase embedded metering smart power strip using
an MSP430 MCU. This design supports measurement of AC voltage, current, active power, reactive power,
apparent power, frequency, and power factor with 3 sockets measured individually. Additional hardware is added
to provide futher development like relay control and wired or wireless communication.

11 Device and Documentation Support

11.1 Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to help with
your development, visit the MSP430™ ultra-low-power sensing & measurement MCUs overview.
11.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. Figure 11-1 provides a legend for reading the complete device
name.
MSP 430 i 2 041 T PW R
Processor Family Tape and Reel
MCU Platform Packaging

Device Type Temperature Range

Series Feature Set

Processor Family MSP = Mixed-Signal Processor

XMS = Experimental Silicon
MCU Platform 430 = TI’s MSP430 Microcontroller Platform
Device Type Specialized Application
i = Flash Industrial
Series 2 = Flash 2 series up to 16.384 MHz
Feature Set Various levels of integration within a series
Temperature Range T = –40°C to 105°C
Packaging http://www.ti.com/packaging
Tape and Reel T = Small Reel
R = Large Reel
No markings = Tube or tray

Figure 11-1. Device Nomenclature

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MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
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11.3 Tools and Software

All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools
are available from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Design &
development.
Design Kits and Evaluation Modules
32-pin target development board and MSP-FET programmer bundle for MSP430i2x MCUs
The MSP-FET430U32A is a stand-alone ZIF socket target board used to program and debug the MSP430 MCU
in-system through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG) protocol.
MSP430 LaunchPad™ Value Line Development Kit
The MSP-EXP430G2 LaunchPad development kit is an easy-to-use microcontroller development board for the
low-power and low-cost MSP430G2x MCUs. It has on-board emulation for programming and debugging and
features a 14/20-pin DIP socket, on-board buttons and LEDs and BoosterPack plug-in module pinouts that
support a wide range of modules for added functionality such as wireless, displays, and more.
MSP430i2040 Submetering EVM
This embedded metering (sub-meter or e-meter) EVM is designed based on the MSP430i2040. The EVM can be
connected to the mains (or to DC) and the load directly. The EVM measures the electrical parameters of the load
and the result of measurement can be read from the UART port. This EVM provided with built-in power supply
and isolated serial connect to facilitate user quick start to the evaluation of the MSP430i2040 in embedded
metering application.
Software
MSP430Ware™ Software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 MCU design resources, MSP430Ware software also includes a high-level API called MSP Driver
Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a
component of CCS or as a stand-alone package.
MSP430i20xx Code Examples
C code examples are available for every MSP device that configures each of the integrated peripherals for
various application needs.
Floating Point Math Library for MSP430
Leveraging the intelligent peripherals of TI devices, this floating point math library of scalar functions brings you
up to 26x better performance. Mathlib is easy to integrate into your designs. This library is free and is integrated
in both Code Composer Studio and IAR IDEs.
Fixed Point Math Library for MSP
The TI MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 devices. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.

Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio (CCS) integrated development environment (IDE) supports all MSP microcontroller
devices. CCS comprises a suite of embedded software utilities used to develop and debug embedded
applications. CCS includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features.
MSP Flasher - Command Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) directly to the MSP microcontroller without an IDE.
MSP MCU Programmer and Debugger
The MSP-FET is a powerful emulation development tool – often called a debug probe – which lets users quickly
begin application development on MSP low-power MCUs. Creating MCU software usually requires downloading
the resulting binary program to the MSP device for validation and debugging.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects
to a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
11.4 Documentation Support
The following documents describe the MSP430i20xx MCUs. Copies of these documents are available on the
Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for example, MSP430i2041). In the upper right corner, click the "Alert me" button. This
registers you to receive a weekly digest of product information that has changed (if any). For change details,
check the revision history of any revised document.
Errata
MSP430i2041 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2040 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2031 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2031 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2021 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430i2021 Device Erratasheet
Describes the known exceptions to the functional specifications.

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MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
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User's Guides
MSP430i2xx Family User's Guide
Detailed description of all modules and peripherals available in this device family.
MSP430™ Flash Device Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller
during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)
and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap
loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)
from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module
of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In
addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices.
This document describes device access using both the standard 4-wire JTAG interface and the 2-wire JTAG
interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 Flash Emulation Tool (FET). The FET is the
program development tool for the MSP430 ultra-low-power microcontroller. Both available interface types, the
parallel port interface and the USB interface, are described.
Application Reports
MSP430 32-kHz Crystal Oscillators
Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
different ESD topics to help board designers and OEMs understand and design robust system-level designs.
11.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.6 Trademarks
MSP430Ware™, MSP430™, Code Composer Studio™, TI E2E™, LaunchPad™, are trademarks of Texas
Instruments.
All trademarks are the property of their respective owners.
11.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020

MSP430I2041, MSP430I2040
MSP430I2031, MSP430I2030
MSP430I2021, MSP430I2020
www.ti.com SLAS887C – SEPTEMBER 2014 – REVISED MARCH 2021

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: MSP430I2041 MSP430I2040 MSP430I2031 MSP430I2030 MSP430I2021 MSP430I2020
PACKAGE OPTION ADDENDUM

www.ti.com 8-Mar-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MSP430I2020TPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2020T

MSP430I2020TPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2020T

MSP430I2020TRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2020T

MSP430I2020TRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2020T

MSP430I2021TPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2021T

MSP430I2021TPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2021T

MSP430I2021TRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2021T

MSP430I2021TRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2021T

MSP430I2030TPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2030T

MSP430I2030TPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2030T

MSP430I2030TRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2030T

MSP430I2030TRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2030T

MSP430I2031TPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2031T

MSP430I2031TPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2031T

MSP430I2031TRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2031T

MSP430I2031TRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2031T

MSP430I2040TPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2040T

MSP430I2040TPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2040T

MSP430I2040TRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2040T

MSP430I2040TRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2040T

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 8-Mar-2021

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MSP430I2041TPW ACTIVE TSSOP PW 28 50 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2041T

MSP430I2041TPWR ACTIVE TSSOP PW 28 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2041T

MSP430I2041TRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2041T

MSP430I2041TRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 I2041T

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 8-Mar-2021

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 8-Mar-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430I2020TPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MSP430I2020TRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2020TRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2021TPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MSP430I2021TRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2021TRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2030TPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MSP430I2030TRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2030TRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2031TPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MSP430I2031TRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2031TRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2040TPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MSP430I2040TRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2040TRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2041TPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
MSP430I2041TRHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
MSP430I2041TRHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 8-Mar-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MSP430I2020TPWR TSSOP PW 28 2000 350.0 350.0 43.0
MSP430I2020TRHBR VQFN RHB 32 3000 367.0 367.0 35.0
MSP430I2020TRHBT VQFN RHB 32 250 210.0 185.0 35.0
MSP430I2021TPWR TSSOP PW 28 2000 367.0 367.0 38.0
MSP430I2021TRHBR VQFN RHB 32 3000 367.0 367.0 35.0
MSP430I2021TRHBT VQFN RHB 32 250 210.0 185.0 35.0
MSP430I2030TPWR TSSOP PW 28 2000 350.0 350.0 43.0
MSP430I2030TRHBR VQFN RHB 32 3000 367.0 367.0 35.0
MSP430I2030TRHBT VQFN RHB 32 250 210.0 185.0 35.0
MSP430I2031TPWR TSSOP PW 28 2000 350.0 350.0 43.0
MSP430I2031TRHBR VQFN RHB 32 3000 367.0 367.0 35.0
MSP430I2031TRHBT VQFN RHB 32 250 210.0 185.0 35.0
MSP430I2040TPWR TSSOP PW 28 2000 350.0 350.0 43.0
MSP430I2040TRHBR VQFN RHB 32 3000 367.0 367.0 35.0
MSP430I2040TRHBT VQFN RHB 32 250 210.0 185.0 35.0
MSP430I2041TPWR TSSOP PW 28 2000 350.0 350.0 43.0
MSP430I2041TRHBR VQFN RHB 32 3000 367.0 367.0 35.0
MSP430I2041TRHBT VQFN RHB 32 250 210.0 185.0 35.0

Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32 VQFN - 1 mm max height
5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224745/A

www.ti.com
PACKAGE OUTLINE
RHB0032M VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

5.1 A
B 4.9

5.1
4.9
PIN 1 INDEX AREA

C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP

9 16
28X 0.5
8
17

33 SYMM
2X
3.5

1 24
32X 0.3
0.2
PIN 1 ID 32 25
SYMM 0.1 C A B
(OPTIONAL)
32X 0.5
0.3 0.05 C

4223725/A 08/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032M VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

(4.8)

( 2.1)
32 25
32X (0.6)
32X (0.25)
1
24

28X (0.5)

SYMM 33
(4.8)
2X
(0.8)

VIA TYP

8 17

(R0.05) TYP

9 16
2X (0.8)
SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X
0.07 MAX 0.07 MIN
ALL AROUND ALL AROUND
METAL
SOLDER MASK
SOLDER MASK OPENING
EXPOSED OPENING
METAL EXPOSED
METAL UNDER
METAL
NON SOLDER MASK SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

4223725/A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032M VQFN - 1 mm max height
PLASTIC QUAD FLATPACK-NO LEAD

(4.8)

4X ( 0.94)
32 25
32X (0.6)
32X (0.25)
1
24

28X (0.5) 33

SYMM
(4.8)
2X
(0.57)

METAL
TYP

8 17

(R0.05) TYP

9 16
2X (0.57)
SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
80% PRINTED COVERAGE BY AREA
SCALE: 15X

4223725/A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

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